1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016 MediaTek Inc.
4  */
5 
6 #include <linux/delay.h>
7 #include <linux/err.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/i2c.h>
10 #include <linux/module.h>
11 #include <linux/of_graph.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 
16 #include <drm/display/drm_dp_aux_bus.h>
17 #include <drm/display/drm_dp_helper.h>
18 #include <drm/drm_atomic_state_helper.h>
19 #include <drm/drm_bridge.h>
20 #include <drm/drm_edid.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_of.h>
23 #include <drm/drm_panel.h>
24 #include <drm/drm_print.h>
25 
26 #define PAGE0_AUXCH_CFG3	0x76
27 #define  AUXCH_CFG3_RESET	0xff
28 #define PAGE0_SWAUX_ADDR_7_0	0x7d
29 #define PAGE0_SWAUX_ADDR_15_8	0x7e
30 #define PAGE0_SWAUX_ADDR_23_16	0x7f
31 #define  SWAUX_ADDR_MASK	GENMASK(19, 0)
32 #define PAGE0_SWAUX_LENGTH	0x80
33 #define  SWAUX_LENGTH_MASK	GENMASK(3, 0)
34 #define  SWAUX_NO_PAYLOAD	BIT(7)
35 #define PAGE0_SWAUX_WDATA	0x81
36 #define PAGE0_SWAUX_RDATA	0x82
37 #define PAGE0_SWAUX_CTRL	0x83
38 #define  SWAUX_SEND		BIT(0)
39 #define PAGE0_SWAUX_STATUS	0x84
40 #define  SWAUX_M_MASK		GENMASK(4, 0)
41 #define  SWAUX_STATUS_MASK	GENMASK(7, 5)
42 #define  SWAUX_STATUS_NACK	(0x1 << 5)
43 #define  SWAUX_STATUS_DEFER	(0x2 << 5)
44 #define  SWAUX_STATUS_ACKM	(0x3 << 5)
45 #define  SWAUX_STATUS_INVALID	(0x4 << 5)
46 #define  SWAUX_STATUS_I2C_NACK	(0x5 << 5)
47 #define  SWAUX_STATUS_I2C_DEFER	(0x6 << 5)
48 #define  SWAUX_STATUS_TIMEOUT	(0x7 << 5)
49 
50 #define PAGE2_GPIO_H		0xa7
51 #define  PS_GPIO9		BIT(1)
52 #define PAGE2_I2C_BYPASS	0xea
53 #define  I2C_BYPASS_EN		0xd0
54 #define PAGE2_MCS_EN		0xf3
55 #define  MCS_EN			BIT(0)
56 
57 #define PAGE3_SET_ADD		0xfe
58 #define  VDO_CTL_ADD		0x13
59 #define  VDO_DIS		0x18
60 #define  VDO_EN			0x1c
61 
62 #define NUM_MIPI_LANES		4
63 
64 #define COMMON_PS8640_REGMAP_CONFIG \
65 	.reg_bits = 8, \
66 	.val_bits = 8, \
67 	.cache_type = REGCACHE_NONE
68 
69 /*
70  * PS8640 uses multiple addresses:
71  * page[0]: for DP control
72  * page[1]: for VIDEO Bridge
73  * page[2]: for control top
74  * page[3]: for DSI Link Control1
75  * page[4]: for MIPI Phy
76  * page[5]: for VPLL
77  * page[6]: for DSI Link Control2
78  * page[7]: for SPI ROM mapping
79  */
80 enum page_addr_offset {
81 	PAGE0_DP_CNTL = 0,
82 	PAGE1_VDO_BDG,
83 	PAGE2_TOP_CNTL,
84 	PAGE3_DSI_CNTL1,
85 	PAGE4_MIPI_PHY,
86 	PAGE5_VPLL,
87 	PAGE6_DSI_CNTL2,
88 	PAGE7_SPI_CNTL,
89 	MAX_DEVS
90 };
91 
92 enum ps8640_vdo_control {
93 	DISABLE = VDO_DIS,
94 	ENABLE = VDO_EN,
95 };
96 
97 struct ps8640 {
98 	struct drm_bridge bridge;
99 	struct drm_bridge *panel_bridge;
100 	struct drm_dp_aux aux;
101 	struct mipi_dsi_device *dsi;
102 	struct i2c_client *page[MAX_DEVS];
103 	struct regmap	*regmap[MAX_DEVS];
104 	struct regulator_bulk_data supplies[2];
105 	struct gpio_desc *gpio_reset;
106 	struct gpio_desc *gpio_powerdown;
107 	struct device_link *link;
108 	bool pre_enabled;
109 	bool need_post_hpd_delay;
110 };
111 
112 static const struct regmap_config ps8640_regmap_config[] = {
113 	[PAGE0_DP_CNTL] = {
114 		COMMON_PS8640_REGMAP_CONFIG,
115 		.max_register = 0xbf,
116 	},
117 	[PAGE1_VDO_BDG] = {
118 		COMMON_PS8640_REGMAP_CONFIG,
119 		.max_register = 0xff,
120 	},
121 	[PAGE2_TOP_CNTL] = {
122 		COMMON_PS8640_REGMAP_CONFIG,
123 		.max_register = 0xff,
124 	},
125 	[PAGE3_DSI_CNTL1] = {
126 		COMMON_PS8640_REGMAP_CONFIG,
127 		.max_register = 0xff,
128 	},
129 	[PAGE4_MIPI_PHY] = {
130 		COMMON_PS8640_REGMAP_CONFIG,
131 		.max_register = 0xff,
132 	},
133 	[PAGE5_VPLL] = {
134 		COMMON_PS8640_REGMAP_CONFIG,
135 		.max_register = 0x7f,
136 	},
137 	[PAGE6_DSI_CNTL2] = {
138 		COMMON_PS8640_REGMAP_CONFIG,
139 		.max_register = 0xff,
140 	},
141 	[PAGE7_SPI_CNTL] = {
142 		COMMON_PS8640_REGMAP_CONFIG,
143 		.max_register = 0xff,
144 	},
145 };
146 
147 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
148 {
149 	return container_of(e, struct ps8640, bridge);
150 }
151 
152 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
153 {
154 	return container_of(aux, struct ps8640, aux);
155 }
156 
157 static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us)
158 {
159 	struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
160 	int status;
161 	int ret;
162 
163 	/*
164 	 * Apparently something about the firmware in the chip signals that
165 	 * HPD goes high by reporting GPIO9 as high (even though HPD isn't
166 	 * actually connected to GPIO9).
167 	 */
168 	ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
169 				       status & PS_GPIO9, 20000, wait_us);
170 
171 	/*
172 	 * The first time we see HPD go high after a reset we delay an extra
173 	 * 50 ms. The best guess is that the MCU is doing "stuff" during this
174 	 * time (maybe talking to the panel) and we don't want to interrupt it.
175 	 *
176 	 * No locking is done around "need_post_hpd_delay". If we're here we
177 	 * know we're holding a PM Runtime reference and the only other place
178 	 * that touches this is PM Runtime resume.
179 	 */
180 	if (!ret && ps_bridge->need_post_hpd_delay) {
181 		ps_bridge->need_post_hpd_delay = false;
182 		msleep(50);
183 	}
184 
185 	return ret;
186 }
187 
188 static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
189 {
190 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
191 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
192 	int ret;
193 
194 	/*
195 	 * Note that this function is called by code that has already powered
196 	 * the panel. We have to power ourselves up but we don't need to worry
197 	 * about powering the panel.
198 	 */
199 	pm_runtime_get_sync(dev);
200 	ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us);
201 	pm_runtime_mark_last_busy(dev);
202 	pm_runtime_put_autosuspend(dev);
203 
204 	return ret;
205 }
206 
207 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
208 				       struct drm_dp_aux_msg *msg)
209 {
210 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
211 	struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
212 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
213 	size_t len = msg->size;
214 	unsigned int data;
215 	unsigned int base;
216 	int ret;
217 	u8 request = msg->request &
218 		     ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
219 	u8 *buf = msg->buffer;
220 	u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
221 	u8 i;
222 	bool is_native_aux = false;
223 
224 	if (len > DP_AUX_MAX_PAYLOAD_BYTES)
225 		return -EINVAL;
226 
227 	if (msg->address & ~SWAUX_ADDR_MASK)
228 		return -EINVAL;
229 
230 	switch (request) {
231 	case DP_AUX_NATIVE_WRITE:
232 	case DP_AUX_NATIVE_READ:
233 		is_native_aux = true;
234 		fallthrough;
235 	case DP_AUX_I2C_WRITE:
236 	case DP_AUX_I2C_READ:
237 		break;
238 	default:
239 		return -EINVAL;
240 	}
241 
242 	ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
243 	if (ret) {
244 		DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
245 			      ret);
246 		return ret;
247 	}
248 
249 	/* Assume it's good */
250 	msg->reply = 0;
251 
252 	base = PAGE0_SWAUX_ADDR_7_0;
253 	addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
254 	addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
255 	addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
256 						  (msg->request << 4);
257 	addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
258 					      ((len - 1) & SWAUX_LENGTH_MASK);
259 
260 	regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len,
261 			  ARRAY_SIZE(addr_len));
262 
263 	if (len && (request == DP_AUX_NATIVE_WRITE ||
264 		    request == DP_AUX_I2C_WRITE)) {
265 		/* Write to the internal FIFO buffer */
266 		for (i = 0; i < len; i++) {
267 			ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]);
268 			if (ret) {
269 				DRM_DEV_ERROR(dev,
270 					      "failed to write WDATA: %d\n",
271 					      ret);
272 				return ret;
273 			}
274 		}
275 	}
276 
277 	regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
278 
279 	/* Zero delay loop because i2c transactions are slow already */
280 	regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
281 				 !(data & SWAUX_SEND), 0, 50 * 1000);
282 
283 	regmap_read(map, PAGE0_SWAUX_STATUS, &data);
284 	if (ret) {
285 		DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
286 			      ret);
287 		return ret;
288 	}
289 
290 	switch (data & SWAUX_STATUS_MASK) {
291 	case SWAUX_STATUS_NACK:
292 	case SWAUX_STATUS_I2C_NACK:
293 		/*
294 		 * The programming guide is not clear about whether a I2C NACK
295 		 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
296 		 * we handle both cases together.
297 		 */
298 		if (is_native_aux)
299 			msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
300 		else
301 			msg->reply |= DP_AUX_I2C_REPLY_NACK;
302 
303 		fallthrough;
304 	case SWAUX_STATUS_ACKM:
305 		len = data & SWAUX_M_MASK;
306 		break;
307 	case SWAUX_STATUS_DEFER:
308 	case SWAUX_STATUS_I2C_DEFER:
309 		if (is_native_aux)
310 			msg->reply |= DP_AUX_NATIVE_REPLY_DEFER;
311 		else
312 			msg->reply |= DP_AUX_I2C_REPLY_DEFER;
313 		len = data & SWAUX_M_MASK;
314 		break;
315 	case SWAUX_STATUS_INVALID:
316 		return -EOPNOTSUPP;
317 	case SWAUX_STATUS_TIMEOUT:
318 		return -ETIMEDOUT;
319 	}
320 
321 	if (len && (request == DP_AUX_NATIVE_READ ||
322 		    request == DP_AUX_I2C_READ)) {
323 		/* Read from the internal FIFO buffer */
324 		for (i = 0; i < len; i++) {
325 			ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data);
326 			if (ret) {
327 				DRM_DEV_ERROR(dev,
328 					      "failed to read RDATA: %d\n",
329 					      ret);
330 				return ret;
331 			}
332 
333 			if (i < msg->size)
334 				buf[i] = data;
335 		}
336 	}
337 
338 	return min(len, msg->size);
339 }
340 
341 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
342 				   struct drm_dp_aux_msg *msg)
343 {
344 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
345 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
346 	int ret;
347 
348 	pm_runtime_get_sync(dev);
349 	ret = ps8640_aux_transfer_msg(aux, msg);
350 	pm_runtime_mark_last_busy(dev);
351 	pm_runtime_put_autosuspend(dev);
352 
353 	return ret;
354 }
355 
356 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
357 				      const enum ps8640_vdo_control ctrl)
358 {
359 	struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
360 	struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
361 	u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
362 	int ret;
363 
364 	ret = regmap_bulk_write(map, PAGE3_SET_ADD,
365 				vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
366 
367 	if (ret < 0)
368 		dev_err(dev, "failed to %sable VDO: %d\n",
369 			ctrl == ENABLE ? "en" : "dis", ret);
370 }
371 
372 static int __maybe_unused ps8640_resume(struct device *dev)
373 {
374 	struct ps8640 *ps_bridge = dev_get_drvdata(dev);
375 	int ret;
376 
377 	ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
378 				    ps_bridge->supplies);
379 	if (ret < 0) {
380 		dev_err(dev, "cannot enable regulators %d\n", ret);
381 		return ret;
382 	}
383 
384 	gpiod_set_value(ps_bridge->gpio_powerdown, 0);
385 	gpiod_set_value(ps_bridge->gpio_reset, 1);
386 	usleep_range(2000, 2500);
387 	gpiod_set_value(ps_bridge->gpio_reset, 0);
388 	/* Double reset for T4 and T5 */
389 	msleep(50);
390 	gpiod_set_value(ps_bridge->gpio_reset, 1);
391 	msleep(50);
392 	gpiod_set_value(ps_bridge->gpio_reset, 0);
393 
394 	/* We just reset things, so we need a delay after the first HPD */
395 	ps_bridge->need_post_hpd_delay = true;
396 
397 	/*
398 	 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
399 	 * this is truly necessary since the MCU will already signal that
400 	 * things are "good to go" by signaling HPD on "gpio 9". See
401 	 * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
402 	 * just in case.
403 	 */
404 	msleep(200);
405 
406 	return 0;
407 }
408 
409 static int __maybe_unused ps8640_suspend(struct device *dev)
410 {
411 	struct ps8640 *ps_bridge = dev_get_drvdata(dev);
412 	int ret;
413 
414 	gpiod_set_value(ps_bridge->gpio_reset, 1);
415 	gpiod_set_value(ps_bridge->gpio_powerdown, 1);
416 	ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
417 				     ps_bridge->supplies);
418 	if (ret < 0)
419 		dev_err(dev, "cannot disable regulators %d\n", ret);
420 
421 	return ret;
422 }
423 
424 static const struct dev_pm_ops ps8640_pm_ops = {
425 	SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
426 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
427 				pm_runtime_force_resume)
428 };
429 
430 static void ps8640_atomic_pre_enable(struct drm_bridge *bridge,
431 				     struct drm_bridge_state *old_bridge_state)
432 {
433 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
434 	struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
435 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
436 	int ret;
437 
438 	pm_runtime_get_sync(dev);
439 	ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000);
440 	if (ret < 0)
441 		dev_warn(dev, "HPD didn't go high: %d\n", ret);
442 
443 	/*
444 	 * The Manufacturer Command Set (MCS) is a device dependent interface
445 	 * intended for factory programming of the display module default
446 	 * parameters. Once the display module is configured, the MCS shall be
447 	 * disabled by the manufacturer. Once disabled, all MCS commands are
448 	 * ignored by the display interface.
449 	 */
450 
451 	ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
452 	if (ret < 0)
453 		dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
454 
455 	/* Switch access edp panel's edid through i2c */
456 	ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
457 	if (ret < 0)
458 		dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
459 
460 	ps8640_bridge_vdo_control(ps_bridge, ENABLE);
461 
462 	ps_bridge->pre_enabled = true;
463 }
464 
465 static void ps8640_atomic_post_disable(struct drm_bridge *bridge,
466 				       struct drm_bridge_state *old_bridge_state)
467 {
468 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
469 
470 	ps_bridge->pre_enabled = false;
471 
472 	ps8640_bridge_vdo_control(ps_bridge, DISABLE);
473 	pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev);
474 }
475 
476 static int ps8640_bridge_attach(struct drm_bridge *bridge,
477 				enum drm_bridge_attach_flags flags)
478 {
479 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
480 	struct device *dev = &ps_bridge->page[0]->dev;
481 	int ret;
482 
483 	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
484 		return -EINVAL;
485 
486 	ps_bridge->aux.drm_dev = bridge->dev;
487 	ret = drm_dp_aux_register(&ps_bridge->aux);
488 	if (ret) {
489 		dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
490 		return ret;
491 	}
492 
493 	ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
494 	if (!ps_bridge->link) {
495 		dev_err(dev, "failed to create device link");
496 		ret = -EINVAL;
497 		goto err_devlink;
498 	}
499 
500 	/* Attach the panel-bridge to the dsi bridge */
501 	ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
502 				&ps_bridge->bridge, flags);
503 	if (ret)
504 		goto err_bridge_attach;
505 
506 	return 0;
507 
508 err_bridge_attach:
509 	device_link_del(ps_bridge->link);
510 err_devlink:
511 	drm_dp_aux_unregister(&ps_bridge->aux);
512 
513 	return ret;
514 }
515 
516 static void ps8640_bridge_detach(struct drm_bridge *bridge)
517 {
518 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
519 
520 	drm_dp_aux_unregister(&ps_bridge->aux);
521 	if (ps_bridge->link)
522 		device_link_del(ps_bridge->link);
523 }
524 
525 static void ps8640_runtime_disable(void *data)
526 {
527 	pm_runtime_dont_use_autosuspend(data);
528 	pm_runtime_disable(data);
529 }
530 
531 static const struct drm_bridge_funcs ps8640_bridge_funcs = {
532 	.attach = ps8640_bridge_attach,
533 	.detach = ps8640_bridge_detach,
534 	.atomic_post_disable = ps8640_atomic_post_disable,
535 	.atomic_pre_enable = ps8640_atomic_pre_enable,
536 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
537 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
538 	.atomic_reset = drm_atomic_helper_bridge_reset,
539 };
540 
541 static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge)
542 {
543 	struct device_node *in_ep, *dsi_node;
544 	struct mipi_dsi_device *dsi;
545 	struct mipi_dsi_host *host;
546 	const struct mipi_dsi_device_info info = { .type = "ps8640",
547 						   .channel = 0,
548 						   .node = NULL,
549 						 };
550 
551 	/* port@0 is ps8640 dsi input port */
552 	in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
553 	if (!in_ep)
554 		return -ENODEV;
555 
556 	dsi_node = of_graph_get_remote_port_parent(in_ep);
557 	of_node_put(in_ep);
558 	if (!dsi_node)
559 		return -ENODEV;
560 
561 	host = of_find_mipi_dsi_host_by_node(dsi_node);
562 	of_node_put(dsi_node);
563 	if (!host)
564 		return -EPROBE_DEFER;
565 
566 	dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
567 	if (IS_ERR(dsi)) {
568 		dev_err(dev, "failed to create dsi device\n");
569 		return PTR_ERR(dsi);
570 	}
571 
572 	ps_bridge->dsi = dsi;
573 
574 	dsi->host = host;
575 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
576 			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
577 	dsi->format = MIPI_DSI_FMT_RGB888;
578 	dsi->lanes = NUM_MIPI_LANES;
579 
580 	return 0;
581 }
582 
583 static int ps8640_bridge_link_panel(struct drm_dp_aux *aux)
584 {
585 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
586 	struct device *dev = aux->dev;
587 	struct device_node *np = dev->of_node;
588 	int ret;
589 
590 	/*
591 	 * NOTE about returning -EPROBE_DEFER from this function: if we
592 	 * return an error (most relevant to -EPROBE_DEFER) it will only
593 	 * be passed out to ps8640_probe() if it called this directly (AKA the
594 	 * panel isn't under the "aux-bus" node). That should be fine because
595 	 * if the panel is under "aux-bus" it's guaranteed to have probed by
596 	 * the time this function has been called.
597 	 */
598 
599 	/* port@1 is ps8640 output port */
600 	ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
601 	if (IS_ERR(ps_bridge->panel_bridge))
602 		return PTR_ERR(ps_bridge->panel_bridge);
603 
604 	ret = devm_drm_bridge_add(dev, &ps_bridge->bridge);
605 	if (ret)
606 		return ret;
607 
608 	return devm_mipi_dsi_attach(dev, ps_bridge->dsi);
609 }
610 
611 static int ps8640_probe(struct i2c_client *client)
612 {
613 	struct device *dev = &client->dev;
614 	struct ps8640 *ps_bridge;
615 	int ret;
616 	u32 i;
617 
618 	ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
619 	if (!ps_bridge)
620 		return -ENOMEM;
621 
622 	ps_bridge->supplies[0].supply = "vdd12";
623 	ps_bridge->supplies[1].supply = "vdd33";
624 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
625 				      ps_bridge->supplies);
626 	if (ret)
627 		return ret;
628 
629 	ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
630 						   GPIOD_OUT_HIGH);
631 	if (IS_ERR(ps_bridge->gpio_powerdown))
632 		return PTR_ERR(ps_bridge->gpio_powerdown);
633 
634 	/*
635 	 * Assert the reset to avoid the bridge being initialized prematurely
636 	 */
637 	ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
638 					       GPIOD_OUT_HIGH);
639 	if (IS_ERR(ps_bridge->gpio_reset))
640 		return PTR_ERR(ps_bridge->gpio_reset);
641 
642 	ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
643 	ps_bridge->bridge.of_node = dev->of_node;
644 	ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
645 
646 	/*
647 	 * Get MIPI DSI resources early. These can return -EPROBE_DEFER so
648 	 * we want to get them out of the way sooner.
649 	 */
650 	ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge);
651 	if (ret)
652 		return ret;
653 
654 	ps_bridge->page[PAGE0_DP_CNTL] = client;
655 
656 	ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
657 	if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]))
658 		return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]);
659 
660 	for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
661 		ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
662 							     client->adapter,
663 							     client->addr + i);
664 		if (IS_ERR(ps_bridge->page[i]))
665 			return PTR_ERR(ps_bridge->page[i]);
666 
667 		ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
668 							    ps8640_regmap_config + i);
669 		if (IS_ERR(ps_bridge->regmap[i]))
670 			return PTR_ERR(ps_bridge->regmap[i]);
671 	}
672 
673 	i2c_set_clientdata(client, ps_bridge);
674 
675 	ps_bridge->aux.name = "parade-ps8640-aux";
676 	ps_bridge->aux.dev = dev;
677 	ps_bridge->aux.transfer = ps8640_aux_transfer;
678 	ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted;
679 	drm_dp_aux_init(&ps_bridge->aux);
680 
681 	pm_runtime_enable(dev);
682 	/*
683 	 * Powering on ps8640 takes ~300ms. To avoid wasting time on power
684 	 * cycling ps8640 too often, set autosuspend_delay to 2000ms to ensure
685 	 * the bridge wouldn't suspend in between each _aux_transfer_msg() call
686 	 * during EDID read (~20ms in my experiment) and in between the last
687 	 * _aux_transfer_msg() call during EDID read and the _pre_enable() call
688 	 * (~100ms in my experiment).
689 	 */
690 	pm_runtime_set_autosuspend_delay(dev, 2000);
691 	pm_runtime_use_autosuspend(dev);
692 	pm_suspend_ignore_children(dev, true);
693 	ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
694 	if (ret)
695 		return ret;
696 
697 	ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel);
698 
699 	/*
700 	 * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to
701 	 * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case
702 	 * the function is allowed to -EPROBE_DEFER.
703 	 */
704 	if (ret == -ENODEV)
705 		return ps8640_bridge_link_panel(&ps_bridge->aux);
706 
707 	return ret;
708 }
709 
710 static const struct of_device_id ps8640_match[] = {
711 	{ .compatible = "parade,ps8640" },
712 	{ }
713 };
714 MODULE_DEVICE_TABLE(of, ps8640_match);
715 
716 static struct i2c_driver ps8640_driver = {
717 	.probe = ps8640_probe,
718 	.driver = {
719 		.name = "ps8640",
720 		.of_match_table = ps8640_match,
721 		.pm = &ps8640_pm_ops,
722 	},
723 };
724 module_i2c_driver(ps8640_driver);
725 
726 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
727 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
728 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
729 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
730 MODULE_LICENSE("GPL v2");
731