1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016 MediaTek Inc.
4  */
5 
6 #include <linux/delay.h>
7 #include <linux/err.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/i2c.h>
10 #include <linux/module.h>
11 #include <linux/of_graph.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 
16 #include <drm/display/drm_dp_aux_bus.h>
17 #include <drm/display/drm_dp_helper.h>
18 #include <drm/drm_bridge.h>
19 #include <drm/drm_mipi_dsi.h>
20 #include <drm/drm_of.h>
21 #include <drm/drm_panel.h>
22 #include <drm/drm_print.h>
23 
24 #define PAGE0_AUXCH_CFG3	0x76
25 #define  AUXCH_CFG3_RESET	0xff
26 #define PAGE0_SWAUX_ADDR_7_0	0x7d
27 #define PAGE0_SWAUX_ADDR_15_8	0x7e
28 #define PAGE0_SWAUX_ADDR_23_16	0x7f
29 #define  SWAUX_ADDR_MASK	GENMASK(19, 0)
30 #define PAGE0_SWAUX_LENGTH	0x80
31 #define  SWAUX_LENGTH_MASK	GENMASK(3, 0)
32 #define  SWAUX_NO_PAYLOAD	BIT(7)
33 #define PAGE0_SWAUX_WDATA	0x81
34 #define PAGE0_SWAUX_RDATA	0x82
35 #define PAGE0_SWAUX_CTRL	0x83
36 #define  SWAUX_SEND		BIT(0)
37 #define PAGE0_SWAUX_STATUS	0x84
38 #define  SWAUX_M_MASK		GENMASK(4, 0)
39 #define  SWAUX_STATUS_MASK	GENMASK(7, 5)
40 #define  SWAUX_STATUS_NACK	(0x1 << 5)
41 #define  SWAUX_STATUS_DEFER	(0x2 << 5)
42 #define  SWAUX_STATUS_ACKM	(0x3 << 5)
43 #define  SWAUX_STATUS_INVALID	(0x4 << 5)
44 #define  SWAUX_STATUS_I2C_NACK	(0x5 << 5)
45 #define  SWAUX_STATUS_I2C_DEFER	(0x6 << 5)
46 #define  SWAUX_STATUS_TIMEOUT	(0x7 << 5)
47 
48 #define PAGE2_GPIO_H		0xa7
49 #define  PS_GPIO9		BIT(1)
50 #define PAGE2_I2C_BYPASS	0xea
51 #define  I2C_BYPASS_EN		0xd0
52 #define PAGE2_MCS_EN		0xf3
53 #define  MCS_EN			BIT(0)
54 
55 #define PAGE3_SET_ADD		0xfe
56 #define  VDO_CTL_ADD		0x13
57 #define  VDO_DIS		0x18
58 #define  VDO_EN			0x1c
59 
60 #define NUM_MIPI_LANES		4
61 
62 #define COMMON_PS8640_REGMAP_CONFIG \
63 	.reg_bits = 8, \
64 	.val_bits = 8, \
65 	.cache_type = REGCACHE_NONE
66 
67 /*
68  * PS8640 uses multiple addresses:
69  * page[0]: for DP control
70  * page[1]: for VIDEO Bridge
71  * page[2]: for control top
72  * page[3]: for DSI Link Control1
73  * page[4]: for MIPI Phy
74  * page[5]: for VPLL
75  * page[6]: for DSI Link Control2
76  * page[7]: for SPI ROM mapping
77  */
78 enum page_addr_offset {
79 	PAGE0_DP_CNTL = 0,
80 	PAGE1_VDO_BDG,
81 	PAGE2_TOP_CNTL,
82 	PAGE3_DSI_CNTL1,
83 	PAGE4_MIPI_PHY,
84 	PAGE5_VPLL,
85 	PAGE6_DSI_CNTL2,
86 	PAGE7_SPI_CNTL,
87 	MAX_DEVS
88 };
89 
90 enum ps8640_vdo_control {
91 	DISABLE = VDO_DIS,
92 	ENABLE = VDO_EN,
93 };
94 
95 struct ps8640 {
96 	struct drm_bridge bridge;
97 	struct drm_bridge *panel_bridge;
98 	struct drm_dp_aux aux;
99 	struct mipi_dsi_device *dsi;
100 	struct i2c_client *page[MAX_DEVS];
101 	struct regmap	*regmap[MAX_DEVS];
102 	struct regulator_bulk_data supplies[2];
103 	struct gpio_desc *gpio_reset;
104 	struct gpio_desc *gpio_powerdown;
105 	struct device_link *link;
106 	bool pre_enabled;
107 };
108 
109 static const struct regmap_config ps8640_regmap_config[] = {
110 	[PAGE0_DP_CNTL] = {
111 		COMMON_PS8640_REGMAP_CONFIG,
112 		.max_register = 0xbf,
113 	},
114 	[PAGE1_VDO_BDG] = {
115 		COMMON_PS8640_REGMAP_CONFIG,
116 		.max_register = 0xff,
117 	},
118 	[PAGE2_TOP_CNTL] = {
119 		COMMON_PS8640_REGMAP_CONFIG,
120 		.max_register = 0xff,
121 	},
122 	[PAGE3_DSI_CNTL1] = {
123 		COMMON_PS8640_REGMAP_CONFIG,
124 		.max_register = 0xff,
125 	},
126 	[PAGE4_MIPI_PHY] = {
127 		COMMON_PS8640_REGMAP_CONFIG,
128 		.max_register = 0xff,
129 	},
130 	[PAGE5_VPLL] = {
131 		COMMON_PS8640_REGMAP_CONFIG,
132 		.max_register = 0x7f,
133 	},
134 	[PAGE6_DSI_CNTL2] = {
135 		COMMON_PS8640_REGMAP_CONFIG,
136 		.max_register = 0xff,
137 	},
138 	[PAGE7_SPI_CNTL] = {
139 		COMMON_PS8640_REGMAP_CONFIG,
140 		.max_register = 0xff,
141 	},
142 };
143 
144 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
145 {
146 	return container_of(e, struct ps8640, bridge);
147 }
148 
149 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
150 {
151 	return container_of(aux, struct ps8640, aux);
152 }
153 
154 static bool ps8640_of_panel_on_aux_bus(struct device *dev)
155 {
156 	struct device_node *bus, *panel;
157 
158 	bus = of_get_child_by_name(dev->of_node, "aux-bus");
159 	if (!bus)
160 		return false;
161 
162 	panel = of_get_child_by_name(bus, "panel");
163 	of_node_put(bus);
164 	if (!panel)
165 		return false;
166 	of_node_put(panel);
167 
168 	return true;
169 }
170 
171 static int ps8640_ensure_hpd(struct ps8640 *ps_bridge)
172 {
173 	struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
174 	struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev;
175 	int status;
176 	int ret;
177 
178 	/*
179 	 * Apparently something about the firmware in the chip signals that
180 	 * HPD goes high by reporting GPIO9 as high (even though HPD isn't
181 	 * actually connected to GPIO9).
182 	 */
183 	ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
184 				       status & PS_GPIO9, 20 * 1000, 200 * 1000);
185 
186 	if (ret < 0)
187 		dev_warn(dev, "HPD didn't go high: %d\n", ret);
188 
189 	return ret;
190 }
191 
192 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
193 				       struct drm_dp_aux_msg *msg)
194 {
195 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
196 	struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
197 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
198 	unsigned int len = msg->size;
199 	unsigned int data;
200 	unsigned int base;
201 	int ret;
202 	u8 request = msg->request &
203 		     ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
204 	u8 *buf = msg->buffer;
205 	u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
206 	u8 i;
207 	bool is_native_aux = false;
208 
209 	if (len > DP_AUX_MAX_PAYLOAD_BYTES)
210 		return -EINVAL;
211 
212 	if (msg->address & ~SWAUX_ADDR_MASK)
213 		return -EINVAL;
214 
215 	switch (request) {
216 	case DP_AUX_NATIVE_WRITE:
217 	case DP_AUX_NATIVE_READ:
218 		is_native_aux = true;
219 		fallthrough;
220 	case DP_AUX_I2C_WRITE:
221 	case DP_AUX_I2C_READ:
222 		break;
223 	default:
224 		return -EINVAL;
225 	}
226 
227 	ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
228 	if (ret) {
229 		DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
230 			      ret);
231 		return ret;
232 	}
233 
234 	/* Assume it's good */
235 	msg->reply = 0;
236 
237 	base = PAGE0_SWAUX_ADDR_7_0;
238 	addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
239 	addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
240 	addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
241 						  (msg->request << 4);
242 	addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
243 					      ((len - 1) & SWAUX_LENGTH_MASK);
244 
245 	regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len,
246 			  ARRAY_SIZE(addr_len));
247 
248 	if (len && (request == DP_AUX_NATIVE_WRITE ||
249 		    request == DP_AUX_I2C_WRITE)) {
250 		/* Write to the internal FIFO buffer */
251 		for (i = 0; i < len; i++) {
252 			ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]);
253 			if (ret) {
254 				DRM_DEV_ERROR(dev,
255 					      "failed to write WDATA: %d\n",
256 					      ret);
257 				return ret;
258 			}
259 		}
260 	}
261 
262 	regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
263 
264 	/* Zero delay loop because i2c transactions are slow already */
265 	regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
266 				 !(data & SWAUX_SEND), 0, 50 * 1000);
267 
268 	regmap_read(map, PAGE0_SWAUX_STATUS, &data);
269 	if (ret) {
270 		DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
271 			      ret);
272 		return ret;
273 	}
274 
275 	switch (data & SWAUX_STATUS_MASK) {
276 	/* Ignore the DEFER cases as they are already handled in hardware */
277 	case SWAUX_STATUS_NACK:
278 	case SWAUX_STATUS_I2C_NACK:
279 		/*
280 		 * The programming guide is not clear about whether a I2C NACK
281 		 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
282 		 * we handle both cases together.
283 		 */
284 		if (is_native_aux)
285 			msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
286 		else
287 			msg->reply |= DP_AUX_I2C_REPLY_NACK;
288 
289 		fallthrough;
290 	case SWAUX_STATUS_ACKM:
291 		len = data & SWAUX_M_MASK;
292 		break;
293 	case SWAUX_STATUS_INVALID:
294 		return -EOPNOTSUPP;
295 	case SWAUX_STATUS_TIMEOUT:
296 		return -ETIMEDOUT;
297 	}
298 
299 	if (len && (request == DP_AUX_NATIVE_READ ||
300 		    request == DP_AUX_I2C_READ)) {
301 		/* Read from the internal FIFO buffer */
302 		for (i = 0; i < len; i++) {
303 			ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data);
304 			if (ret) {
305 				DRM_DEV_ERROR(dev,
306 					      "failed to read RDATA: %d\n",
307 					      ret);
308 				return ret;
309 			}
310 
311 			buf[i] = data;
312 		}
313 	}
314 
315 	return len;
316 }
317 
318 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
319 				   struct drm_dp_aux_msg *msg)
320 {
321 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
322 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
323 	int ret;
324 
325 	pm_runtime_get_sync(dev);
326 	ret = ps8640_ensure_hpd(ps_bridge);
327 	if (!ret)
328 		ret = ps8640_aux_transfer_msg(aux, msg);
329 	pm_runtime_mark_last_busy(dev);
330 	pm_runtime_put_autosuspend(dev);
331 
332 	return ret;
333 }
334 
335 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
336 				      const enum ps8640_vdo_control ctrl)
337 {
338 	struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
339 	struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
340 	u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
341 	int ret;
342 
343 	ret = regmap_bulk_write(map, PAGE3_SET_ADD,
344 				vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
345 
346 	if (ret < 0)
347 		dev_err(dev, "failed to %sable VDO: %d\n",
348 			ctrl == ENABLE ? "en" : "dis", ret);
349 }
350 
351 static int __maybe_unused ps8640_resume(struct device *dev)
352 {
353 	struct ps8640 *ps_bridge = dev_get_drvdata(dev);
354 	int ret;
355 
356 	ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
357 				    ps_bridge->supplies);
358 	if (ret < 0) {
359 		dev_err(dev, "cannot enable regulators %d\n", ret);
360 		return ret;
361 	}
362 
363 	gpiod_set_value(ps_bridge->gpio_powerdown, 0);
364 	gpiod_set_value(ps_bridge->gpio_reset, 1);
365 	usleep_range(2000, 2500);
366 	gpiod_set_value(ps_bridge->gpio_reset, 0);
367 
368 	/*
369 	 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
370 	 * this is truly necessary since the MCU will already signal that
371 	 * things are "good to go" by signaling HPD on "gpio 9". See
372 	 * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in
373 	 * case.
374 	 */
375 	msleep(200);
376 
377 	return 0;
378 }
379 
380 static int __maybe_unused ps8640_suspend(struct device *dev)
381 {
382 	struct ps8640 *ps_bridge = dev_get_drvdata(dev);
383 	int ret;
384 
385 	gpiod_set_value(ps_bridge->gpio_reset, 1);
386 	gpiod_set_value(ps_bridge->gpio_powerdown, 1);
387 	ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
388 				     ps_bridge->supplies);
389 	if (ret < 0)
390 		dev_err(dev, "cannot disable regulators %d\n", ret);
391 
392 	return ret;
393 }
394 
395 static const struct dev_pm_ops ps8640_pm_ops = {
396 	SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
397 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
398 				pm_runtime_force_resume)
399 };
400 
401 static void ps8640_pre_enable(struct drm_bridge *bridge)
402 {
403 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
404 	struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
405 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
406 	int ret;
407 
408 	pm_runtime_get_sync(dev);
409 	ps8640_ensure_hpd(ps_bridge);
410 
411 	/*
412 	 * The Manufacturer Command Set (MCS) is a device dependent interface
413 	 * intended for factory programming of the display module default
414 	 * parameters. Once the display module is configured, the MCS shall be
415 	 * disabled by the manufacturer. Once disabled, all MCS commands are
416 	 * ignored by the display interface.
417 	 */
418 
419 	ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
420 	if (ret < 0)
421 		dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
422 
423 	/* Switch access edp panel's edid through i2c */
424 	ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
425 	if (ret < 0)
426 		dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
427 
428 	ps8640_bridge_vdo_control(ps_bridge, ENABLE);
429 
430 	ps_bridge->pre_enabled = true;
431 }
432 
433 static void ps8640_post_disable(struct drm_bridge *bridge)
434 {
435 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
436 
437 	ps_bridge->pre_enabled = false;
438 
439 	ps8640_bridge_vdo_control(ps_bridge, DISABLE);
440 	pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev);
441 }
442 
443 static int ps8640_bridge_attach(struct drm_bridge *bridge,
444 				enum drm_bridge_attach_flags flags)
445 {
446 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
447 	struct device *dev = &ps_bridge->page[0]->dev;
448 	int ret;
449 
450 	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
451 		return -EINVAL;
452 
453 	ps_bridge->aux.drm_dev = bridge->dev;
454 	ret = drm_dp_aux_register(&ps_bridge->aux);
455 	if (ret) {
456 		dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
457 		return ret;
458 	}
459 
460 	ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
461 	if (!ps_bridge->link) {
462 		dev_err(dev, "failed to create device link");
463 		ret = -EINVAL;
464 		goto err_devlink;
465 	}
466 
467 	/* Attach the panel-bridge to the dsi bridge */
468 	ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
469 				&ps_bridge->bridge, flags);
470 	if (ret)
471 		goto err_bridge_attach;
472 
473 	return 0;
474 
475 err_bridge_attach:
476 	device_link_del(ps_bridge->link);
477 err_devlink:
478 	drm_dp_aux_unregister(&ps_bridge->aux);
479 
480 	return ret;
481 }
482 
483 static void ps8640_bridge_detach(struct drm_bridge *bridge)
484 {
485 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
486 
487 	drm_dp_aux_unregister(&ps_bridge->aux);
488 	if (ps_bridge->link)
489 		device_link_del(ps_bridge->link);
490 }
491 
492 static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
493 					   struct drm_connector *connector)
494 {
495 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
496 	bool poweroff = !ps_bridge->pre_enabled;
497 	struct edid *edid;
498 
499 	/*
500 	 * When we end calling get_edid() triggered by an ioctl, i.e
501 	 *
502 	 *   drm_mode_getconnector (ioctl)
503 	 *     -> drm_helper_probe_single_connector_modes
504 	 *        -> drm_bridge_connector_get_modes
505 	 *           -> ps8640_bridge_get_edid
506 	 *
507 	 * We need to make sure that what we need is enabled before reading
508 	 * EDID, for this chip, we need to do a full poweron, otherwise it will
509 	 * fail.
510 	 */
511 	drm_bridge_chain_pre_enable(bridge);
512 
513 	edid = drm_get_edid(connector,
514 			    ps_bridge->page[PAGE0_DP_CNTL]->adapter);
515 
516 	/*
517 	 * If we call the get_edid() function without having enabled the chip
518 	 * before, return the chip to its original power state.
519 	 */
520 	if (poweroff)
521 		drm_bridge_chain_post_disable(bridge);
522 
523 	return edid;
524 }
525 
526 static void ps8640_runtime_disable(void *data)
527 {
528 	pm_runtime_dont_use_autosuspend(data);
529 	pm_runtime_disable(data);
530 }
531 
532 static const struct drm_bridge_funcs ps8640_bridge_funcs = {
533 	.attach = ps8640_bridge_attach,
534 	.detach = ps8640_bridge_detach,
535 	.get_edid = ps8640_bridge_get_edid,
536 	.post_disable = ps8640_post_disable,
537 	.pre_enable = ps8640_pre_enable,
538 };
539 
540 static int ps8640_bridge_host_attach(struct device *dev, struct ps8640 *ps_bridge)
541 {
542 	struct device_node *in_ep, *dsi_node;
543 	struct mipi_dsi_device *dsi;
544 	struct mipi_dsi_host *host;
545 	int ret;
546 	const struct mipi_dsi_device_info info = { .type = "ps8640",
547 						   .channel = 0,
548 						   .node = NULL,
549 						 };
550 
551 	/* port@0 is ps8640 dsi input port */
552 	in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
553 	if (!in_ep)
554 		return -ENODEV;
555 
556 	dsi_node = of_graph_get_remote_port_parent(in_ep);
557 	of_node_put(in_ep);
558 	if (!dsi_node)
559 		return -ENODEV;
560 
561 	host = of_find_mipi_dsi_host_by_node(dsi_node);
562 	of_node_put(dsi_node);
563 	if (!host)
564 		return -EPROBE_DEFER;
565 
566 	dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
567 	if (IS_ERR(dsi)) {
568 		dev_err(dev, "failed to create dsi device\n");
569 		return PTR_ERR(dsi);
570 	}
571 
572 	ps_bridge->dsi = dsi;
573 
574 	dsi->host = host;
575 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
576 			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
577 	dsi->format = MIPI_DSI_FMT_RGB888;
578 	dsi->lanes = NUM_MIPI_LANES;
579 
580 	ret = devm_mipi_dsi_attach(dev, dsi);
581 	if (ret)
582 		return ret;
583 
584 	return 0;
585 }
586 
587 static int ps8640_probe(struct i2c_client *client)
588 {
589 	struct device *dev = &client->dev;
590 	struct device_node *np = dev->of_node;
591 	struct ps8640 *ps_bridge;
592 	int ret;
593 	u32 i;
594 
595 	ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
596 	if (!ps_bridge)
597 		return -ENOMEM;
598 
599 	ps_bridge->supplies[0].supply = "vdd33";
600 	ps_bridge->supplies[1].supply = "vdd12";
601 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
602 				      ps_bridge->supplies);
603 	if (ret)
604 		return ret;
605 
606 	ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
607 						   GPIOD_OUT_HIGH);
608 	if (IS_ERR(ps_bridge->gpio_powerdown))
609 		return PTR_ERR(ps_bridge->gpio_powerdown);
610 
611 	/*
612 	 * Assert the reset to avoid the bridge being initialized prematurely
613 	 */
614 	ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
615 					       GPIOD_OUT_HIGH);
616 	if (IS_ERR(ps_bridge->gpio_reset))
617 		return PTR_ERR(ps_bridge->gpio_reset);
618 
619 	ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
620 	ps_bridge->bridge.of_node = dev->of_node;
621 	ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
622 
623 	/*
624 	 * In the device tree, if panel is listed under aux-bus of the bridge
625 	 * node, panel driver should be able to retrieve EDID by itself using
626 	 * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here.
627 	 */
628 	if (!ps8640_of_panel_on_aux_bus(&client->dev))
629 		ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
630 
631 	ps_bridge->page[PAGE0_DP_CNTL] = client;
632 
633 	ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
634 	if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]))
635 		return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]);
636 
637 	for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
638 		ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
639 							     client->adapter,
640 							     client->addr + i);
641 		if (IS_ERR(ps_bridge->page[i]))
642 			return PTR_ERR(ps_bridge->page[i]);
643 
644 		ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
645 							    ps8640_regmap_config + i);
646 		if (IS_ERR(ps_bridge->regmap[i]))
647 			return PTR_ERR(ps_bridge->regmap[i]);
648 	}
649 
650 	i2c_set_clientdata(client, ps_bridge);
651 
652 	ps_bridge->aux.name = "parade-ps8640-aux";
653 	ps_bridge->aux.dev = dev;
654 	ps_bridge->aux.transfer = ps8640_aux_transfer;
655 	drm_dp_aux_init(&ps_bridge->aux);
656 
657 	pm_runtime_enable(dev);
658 	/*
659 	 * Powering on ps8640 takes ~300ms. To avoid wasting time on power
660 	 * cycling ps8640 too often, set autosuspend_delay to 1000ms to ensure
661 	 * the bridge wouldn't suspend in between each _aux_transfer_msg() call
662 	 * during EDID read (~20ms in my experiment) and in between the last
663 	 * _aux_transfer_msg() call during EDID read and the _pre_enable() call
664 	 * (~100ms in my experiment).
665 	 */
666 	pm_runtime_set_autosuspend_delay(dev, 1000);
667 	pm_runtime_use_autosuspend(dev);
668 	pm_suspend_ignore_children(dev, true);
669 	ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
670 	if (ret)
671 		return ret;
672 
673 	devm_of_dp_aux_populate_ep_devices(&ps_bridge->aux);
674 
675 	/* port@1 is ps8640 output port */
676 	ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
677 	if (IS_ERR(ps_bridge->panel_bridge))
678 		return PTR_ERR(ps_bridge->panel_bridge);
679 
680 	drm_bridge_add(&ps_bridge->bridge);
681 
682 	ret = ps8640_bridge_host_attach(dev, ps_bridge);
683 	if (ret)
684 		goto err_bridge_remove;
685 
686 	return 0;
687 
688 err_bridge_remove:
689 	drm_bridge_remove(&ps_bridge->bridge);
690 	return ret;
691 }
692 
693 static int ps8640_remove(struct i2c_client *client)
694 {
695 	struct ps8640 *ps_bridge = i2c_get_clientdata(client);
696 
697 	drm_bridge_remove(&ps_bridge->bridge);
698 
699 	return 0;
700 }
701 
702 static const struct of_device_id ps8640_match[] = {
703 	{ .compatible = "parade,ps8640" },
704 	{ }
705 };
706 MODULE_DEVICE_TABLE(of, ps8640_match);
707 
708 static struct i2c_driver ps8640_driver = {
709 	.probe_new = ps8640_probe,
710 	.remove = ps8640_remove,
711 	.driver = {
712 		.name = "ps8640",
713 		.of_match_table = ps8640_match,
714 		.pm = &ps8640_pm_ops,
715 	},
716 };
717 module_i2c_driver(ps8640_driver);
718 
719 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
720 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
721 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
722 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
723 MODULE_LICENSE("GPL v2");
724