1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 MediaTek Inc. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/err.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/of_graph.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <drm/display/drm_dp_aux_bus.h> 17 #include <drm/display/drm_dp_helper.h> 18 #include <drm/drm_atomic_state_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_edid.h> 21 #include <drm/drm_mipi_dsi.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_panel.h> 24 #include <drm/drm_print.h> 25 26 #define PAGE0_AUXCH_CFG3 0x76 27 #define AUXCH_CFG3_RESET 0xff 28 #define PAGE0_SWAUX_ADDR_7_0 0x7d 29 #define PAGE0_SWAUX_ADDR_15_8 0x7e 30 #define PAGE0_SWAUX_ADDR_23_16 0x7f 31 #define SWAUX_ADDR_MASK GENMASK(19, 0) 32 #define PAGE0_SWAUX_LENGTH 0x80 33 #define SWAUX_LENGTH_MASK GENMASK(3, 0) 34 #define SWAUX_NO_PAYLOAD BIT(7) 35 #define PAGE0_SWAUX_WDATA 0x81 36 #define PAGE0_SWAUX_RDATA 0x82 37 #define PAGE0_SWAUX_CTRL 0x83 38 #define SWAUX_SEND BIT(0) 39 #define PAGE0_SWAUX_STATUS 0x84 40 #define SWAUX_M_MASK GENMASK(4, 0) 41 #define SWAUX_STATUS_MASK GENMASK(7, 5) 42 #define SWAUX_STATUS_NACK (0x1 << 5) 43 #define SWAUX_STATUS_DEFER (0x2 << 5) 44 #define SWAUX_STATUS_ACKM (0x3 << 5) 45 #define SWAUX_STATUS_INVALID (0x4 << 5) 46 #define SWAUX_STATUS_I2C_NACK (0x5 << 5) 47 #define SWAUX_STATUS_I2C_DEFER (0x6 << 5) 48 #define SWAUX_STATUS_TIMEOUT (0x7 << 5) 49 50 #define PAGE2_GPIO_H 0xa7 51 #define PS_GPIO9 BIT(1) 52 #define PAGE2_I2C_BYPASS 0xea 53 #define I2C_BYPASS_EN 0xd0 54 #define PAGE2_MCS_EN 0xf3 55 #define MCS_EN BIT(0) 56 57 #define PAGE3_SET_ADD 0xfe 58 #define VDO_CTL_ADD 0x13 59 #define VDO_DIS 0x18 60 #define VDO_EN 0x1c 61 62 #define NUM_MIPI_LANES 4 63 64 #define COMMON_PS8640_REGMAP_CONFIG \ 65 .reg_bits = 8, \ 66 .val_bits = 8, \ 67 .cache_type = REGCACHE_NONE 68 69 /* 70 * PS8640 uses multiple addresses: 71 * page[0]: for DP control 72 * page[1]: for VIDEO Bridge 73 * page[2]: for control top 74 * page[3]: for DSI Link Control1 75 * page[4]: for MIPI Phy 76 * page[5]: for VPLL 77 * page[6]: for DSI Link Control2 78 * page[7]: for SPI ROM mapping 79 */ 80 enum page_addr_offset { 81 PAGE0_DP_CNTL = 0, 82 PAGE1_VDO_BDG, 83 PAGE2_TOP_CNTL, 84 PAGE3_DSI_CNTL1, 85 PAGE4_MIPI_PHY, 86 PAGE5_VPLL, 87 PAGE6_DSI_CNTL2, 88 PAGE7_SPI_CNTL, 89 MAX_DEVS 90 }; 91 92 enum ps8640_vdo_control { 93 DISABLE = VDO_DIS, 94 ENABLE = VDO_EN, 95 }; 96 97 struct ps8640 { 98 struct drm_bridge bridge; 99 struct drm_bridge *panel_bridge; 100 struct drm_dp_aux aux; 101 struct mipi_dsi_device *dsi; 102 struct i2c_client *page[MAX_DEVS]; 103 struct regmap *regmap[MAX_DEVS]; 104 struct regulator_bulk_data supplies[2]; 105 struct gpio_desc *gpio_reset; 106 struct gpio_desc *gpio_powerdown; 107 struct device_link *link; 108 struct edid *edid; 109 bool pre_enabled; 110 bool need_post_hpd_delay; 111 }; 112 113 static const struct regmap_config ps8640_regmap_config[] = { 114 [PAGE0_DP_CNTL] = { 115 COMMON_PS8640_REGMAP_CONFIG, 116 .max_register = 0xbf, 117 }, 118 [PAGE1_VDO_BDG] = { 119 COMMON_PS8640_REGMAP_CONFIG, 120 .max_register = 0xff, 121 }, 122 [PAGE2_TOP_CNTL] = { 123 COMMON_PS8640_REGMAP_CONFIG, 124 .max_register = 0xff, 125 }, 126 [PAGE3_DSI_CNTL1] = { 127 COMMON_PS8640_REGMAP_CONFIG, 128 .max_register = 0xff, 129 }, 130 [PAGE4_MIPI_PHY] = { 131 COMMON_PS8640_REGMAP_CONFIG, 132 .max_register = 0xff, 133 }, 134 [PAGE5_VPLL] = { 135 COMMON_PS8640_REGMAP_CONFIG, 136 .max_register = 0x7f, 137 }, 138 [PAGE6_DSI_CNTL2] = { 139 COMMON_PS8640_REGMAP_CONFIG, 140 .max_register = 0xff, 141 }, 142 [PAGE7_SPI_CNTL] = { 143 COMMON_PS8640_REGMAP_CONFIG, 144 .max_register = 0xff, 145 }, 146 }; 147 148 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) 149 { 150 return container_of(e, struct ps8640, bridge); 151 } 152 153 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) 154 { 155 return container_of(aux, struct ps8640, aux); 156 } 157 158 static bool ps8640_of_panel_on_aux_bus(struct device *dev) 159 { 160 struct device_node *bus, *panel; 161 162 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 163 if (!bus) 164 return false; 165 166 panel = of_get_child_by_name(bus, "panel"); 167 of_node_put(bus); 168 if (!panel) 169 return false; 170 of_node_put(panel); 171 172 return true; 173 } 174 175 static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us) 176 { 177 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; 178 int status; 179 int ret; 180 181 /* 182 * Apparently something about the firmware in the chip signals that 183 * HPD goes high by reporting GPIO9 as high (even though HPD isn't 184 * actually connected to GPIO9). 185 */ 186 ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, 187 status & PS_GPIO9, 20000, wait_us); 188 189 /* 190 * The first time we see HPD go high after a reset we delay an extra 191 * 50 ms. The best guess is that the MCU is doing "stuff" during this 192 * time (maybe talking to the panel) and we don't want to interrupt it. 193 * 194 * No locking is done around "need_post_hpd_delay". If we're here we 195 * know we're holding a PM Runtime reference and the only other place 196 * that touches this is PM Runtime resume. 197 */ 198 if (!ret && ps_bridge->need_post_hpd_delay) { 199 ps_bridge->need_post_hpd_delay = false; 200 msleep(50); 201 } 202 203 return ret; 204 } 205 206 static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) 207 { 208 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 209 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 210 int ret; 211 212 /* 213 * Note that this function is called by code that has already powered 214 * the panel. We have to power ourselves up but we don't need to worry 215 * about powering the panel. 216 */ 217 pm_runtime_get_sync(dev); 218 ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us); 219 pm_runtime_mark_last_busy(dev); 220 pm_runtime_put_autosuspend(dev); 221 222 return ret; 223 } 224 225 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, 226 struct drm_dp_aux_msg *msg) 227 { 228 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 229 struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; 230 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 231 unsigned int len = msg->size; 232 unsigned int data; 233 unsigned int base; 234 int ret; 235 u8 request = msg->request & 236 ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 237 u8 *buf = msg->buffer; 238 u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0]; 239 u8 i; 240 bool is_native_aux = false; 241 242 if (len > DP_AUX_MAX_PAYLOAD_BYTES) 243 return -EINVAL; 244 245 if (msg->address & ~SWAUX_ADDR_MASK) 246 return -EINVAL; 247 248 switch (request) { 249 case DP_AUX_NATIVE_WRITE: 250 case DP_AUX_NATIVE_READ: 251 is_native_aux = true; 252 fallthrough; 253 case DP_AUX_I2C_WRITE: 254 case DP_AUX_I2C_READ: 255 break; 256 default: 257 return -EINVAL; 258 } 259 260 ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); 261 if (ret) { 262 DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n", 263 ret); 264 return ret; 265 } 266 267 /* Assume it's good */ 268 msg->reply = 0; 269 270 base = PAGE0_SWAUX_ADDR_7_0; 271 addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address; 272 addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8; 273 addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) | 274 (msg->request << 4); 275 addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD : 276 ((len - 1) & SWAUX_LENGTH_MASK); 277 278 regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len, 279 ARRAY_SIZE(addr_len)); 280 281 if (len && (request == DP_AUX_NATIVE_WRITE || 282 request == DP_AUX_I2C_WRITE)) { 283 /* Write to the internal FIFO buffer */ 284 for (i = 0; i < len; i++) { 285 ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]); 286 if (ret) { 287 DRM_DEV_ERROR(dev, 288 "failed to write WDATA: %d\n", 289 ret); 290 return ret; 291 } 292 } 293 } 294 295 regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND); 296 297 /* Zero delay loop because i2c transactions are slow already */ 298 regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data, 299 !(data & SWAUX_SEND), 0, 50 * 1000); 300 301 regmap_read(map, PAGE0_SWAUX_STATUS, &data); 302 if (ret) { 303 DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n", 304 ret); 305 return ret; 306 } 307 308 switch (data & SWAUX_STATUS_MASK) { 309 case SWAUX_STATUS_NACK: 310 case SWAUX_STATUS_I2C_NACK: 311 /* 312 * The programming guide is not clear about whether a I2C NACK 313 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So 314 * we handle both cases together. 315 */ 316 if (is_native_aux) 317 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 318 else 319 msg->reply |= DP_AUX_I2C_REPLY_NACK; 320 321 fallthrough; 322 case SWAUX_STATUS_ACKM: 323 len = data & SWAUX_M_MASK; 324 break; 325 case SWAUX_STATUS_DEFER: 326 case SWAUX_STATUS_I2C_DEFER: 327 if (is_native_aux) 328 msg->reply |= DP_AUX_NATIVE_REPLY_DEFER; 329 else 330 msg->reply |= DP_AUX_I2C_REPLY_DEFER; 331 len = data & SWAUX_M_MASK; 332 break; 333 case SWAUX_STATUS_INVALID: 334 return -EOPNOTSUPP; 335 case SWAUX_STATUS_TIMEOUT: 336 return -ETIMEDOUT; 337 } 338 339 if (len && (request == DP_AUX_NATIVE_READ || 340 request == DP_AUX_I2C_READ)) { 341 /* Read from the internal FIFO buffer */ 342 for (i = 0; i < len; i++) { 343 ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data); 344 if (ret) { 345 DRM_DEV_ERROR(dev, 346 "failed to read RDATA: %d\n", 347 ret); 348 return ret; 349 } 350 351 buf[i] = data; 352 } 353 } 354 355 return len; 356 } 357 358 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, 359 struct drm_dp_aux_msg *msg) 360 { 361 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 362 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 363 int ret; 364 365 pm_runtime_get_sync(dev); 366 ret = ps8640_aux_transfer_msg(aux, msg); 367 pm_runtime_mark_last_busy(dev); 368 pm_runtime_put_autosuspend(dev); 369 370 return ret; 371 } 372 373 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, 374 const enum ps8640_vdo_control ctrl) 375 { 376 struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; 377 struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; 378 u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; 379 int ret; 380 381 ret = regmap_bulk_write(map, PAGE3_SET_ADD, 382 vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); 383 384 if (ret < 0) 385 dev_err(dev, "failed to %sable VDO: %d\n", 386 ctrl == ENABLE ? "en" : "dis", ret); 387 } 388 389 static int __maybe_unused ps8640_resume(struct device *dev) 390 { 391 struct ps8640 *ps_bridge = dev_get_drvdata(dev); 392 int ret; 393 394 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), 395 ps_bridge->supplies); 396 if (ret < 0) { 397 dev_err(dev, "cannot enable regulators %d\n", ret); 398 return ret; 399 } 400 401 gpiod_set_value(ps_bridge->gpio_powerdown, 0); 402 gpiod_set_value(ps_bridge->gpio_reset, 1); 403 usleep_range(2000, 2500); 404 gpiod_set_value(ps_bridge->gpio_reset, 0); 405 /* Double reset for T4 and T5 */ 406 msleep(50); 407 gpiod_set_value(ps_bridge->gpio_reset, 1); 408 msleep(50); 409 gpiod_set_value(ps_bridge->gpio_reset, 0); 410 411 /* We just reset things, so we need a delay after the first HPD */ 412 ps_bridge->need_post_hpd_delay = true; 413 414 /* 415 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if 416 * this is truly necessary since the MCU will already signal that 417 * things are "good to go" by signaling HPD on "gpio 9". See 418 * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay 419 * just in case. 420 */ 421 msleep(200); 422 423 return 0; 424 } 425 426 static int __maybe_unused ps8640_suspend(struct device *dev) 427 { 428 struct ps8640 *ps_bridge = dev_get_drvdata(dev); 429 int ret; 430 431 gpiod_set_value(ps_bridge->gpio_reset, 1); 432 gpiod_set_value(ps_bridge->gpio_powerdown, 1); 433 ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), 434 ps_bridge->supplies); 435 if (ret < 0) 436 dev_err(dev, "cannot disable regulators %d\n", ret); 437 438 return ret; 439 } 440 441 static const struct dev_pm_ops ps8640_pm_ops = { 442 SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) 443 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 444 pm_runtime_force_resume) 445 }; 446 447 static void ps8640_atomic_pre_enable(struct drm_bridge *bridge, 448 struct drm_bridge_state *old_bridge_state) 449 { 450 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 451 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; 452 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 453 int ret; 454 455 pm_runtime_get_sync(dev); 456 ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000); 457 if (ret < 0) 458 dev_warn(dev, "HPD didn't go high: %d\n", ret); 459 460 /* 461 * The Manufacturer Command Set (MCS) is a device dependent interface 462 * intended for factory programming of the display module default 463 * parameters. Once the display module is configured, the MCS shall be 464 * disabled by the manufacturer. Once disabled, all MCS commands are 465 * ignored by the display interface. 466 */ 467 468 ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); 469 if (ret < 0) 470 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); 471 472 /* Switch access edp panel's edid through i2c */ 473 ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); 474 if (ret < 0) 475 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); 476 477 ps8640_bridge_vdo_control(ps_bridge, ENABLE); 478 479 ps_bridge->pre_enabled = true; 480 } 481 482 static void ps8640_atomic_post_disable(struct drm_bridge *bridge, 483 struct drm_bridge_state *old_bridge_state) 484 { 485 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 486 487 ps_bridge->pre_enabled = false; 488 489 ps8640_bridge_vdo_control(ps_bridge, DISABLE); 490 pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); 491 } 492 493 static int ps8640_bridge_attach(struct drm_bridge *bridge, 494 enum drm_bridge_attach_flags flags) 495 { 496 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 497 struct device *dev = &ps_bridge->page[0]->dev; 498 int ret; 499 500 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 501 return -EINVAL; 502 503 ps_bridge->aux.drm_dev = bridge->dev; 504 ret = drm_dp_aux_register(&ps_bridge->aux); 505 if (ret) { 506 dev_err(dev, "failed to register DP AUX channel: %d\n", ret); 507 return ret; 508 } 509 510 ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS); 511 if (!ps_bridge->link) { 512 dev_err(dev, "failed to create device link"); 513 ret = -EINVAL; 514 goto err_devlink; 515 } 516 517 /* Attach the panel-bridge to the dsi bridge */ 518 ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, 519 &ps_bridge->bridge, flags); 520 if (ret) 521 goto err_bridge_attach; 522 523 return 0; 524 525 err_bridge_attach: 526 device_link_del(ps_bridge->link); 527 err_devlink: 528 drm_dp_aux_unregister(&ps_bridge->aux); 529 530 return ret; 531 } 532 533 static void ps8640_bridge_detach(struct drm_bridge *bridge) 534 { 535 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 536 537 drm_dp_aux_unregister(&ps_bridge->aux); 538 if (ps_bridge->link) 539 device_link_del(ps_bridge->link); 540 } 541 542 static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, 543 struct drm_connector *connector) 544 { 545 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 546 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 547 bool poweroff = !ps_bridge->pre_enabled; 548 549 if (!ps_bridge->edid) { 550 /* 551 * When we end calling get_edid() triggered by an ioctl, i.e 552 * 553 * drm_mode_getconnector (ioctl) 554 * -> drm_helper_probe_single_connector_modes 555 * -> drm_bridge_connector_get_modes 556 * -> ps8640_bridge_get_edid 557 * 558 * We need to make sure that what we need is enabled before 559 * reading EDID, for this chip, we need to do a full poweron, 560 * otherwise it will fail. 561 */ 562 if (poweroff) 563 drm_atomic_bridge_chain_pre_enable(bridge, 564 connector->state->state); 565 566 ps_bridge->edid = drm_get_edid(connector, 567 ps_bridge->page[PAGE0_DP_CNTL]->adapter); 568 569 /* 570 * If we call the get_edid() function without having enabled the 571 * chip before, return the chip to its original power state. 572 */ 573 if (poweroff) 574 drm_atomic_bridge_chain_post_disable(bridge, 575 connector->state->state); 576 } 577 578 if (!ps_bridge->edid) { 579 dev_err(dev, "Failed to get EDID\n"); 580 return NULL; 581 } 582 583 return drm_edid_duplicate(ps_bridge->edid); 584 } 585 586 static void ps8640_runtime_disable(void *data) 587 { 588 pm_runtime_dont_use_autosuspend(data); 589 pm_runtime_disable(data); 590 } 591 592 static const struct drm_bridge_funcs ps8640_bridge_funcs = { 593 .attach = ps8640_bridge_attach, 594 .detach = ps8640_bridge_detach, 595 .get_edid = ps8640_bridge_get_edid, 596 .atomic_post_disable = ps8640_atomic_post_disable, 597 .atomic_pre_enable = ps8640_atomic_pre_enable, 598 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 599 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 600 .atomic_reset = drm_atomic_helper_bridge_reset, 601 }; 602 603 static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge) 604 { 605 struct device_node *in_ep, *dsi_node; 606 struct mipi_dsi_device *dsi; 607 struct mipi_dsi_host *host; 608 const struct mipi_dsi_device_info info = { .type = "ps8640", 609 .channel = 0, 610 .node = NULL, 611 }; 612 613 /* port@0 is ps8640 dsi input port */ 614 in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 615 if (!in_ep) 616 return -ENODEV; 617 618 dsi_node = of_graph_get_remote_port_parent(in_ep); 619 of_node_put(in_ep); 620 if (!dsi_node) 621 return -ENODEV; 622 623 host = of_find_mipi_dsi_host_by_node(dsi_node); 624 of_node_put(dsi_node); 625 if (!host) 626 return -EPROBE_DEFER; 627 628 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 629 if (IS_ERR(dsi)) { 630 dev_err(dev, "failed to create dsi device\n"); 631 return PTR_ERR(dsi); 632 } 633 634 ps_bridge->dsi = dsi; 635 636 dsi->host = host; 637 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 638 MIPI_DSI_MODE_VIDEO_SYNC_PULSE; 639 dsi->format = MIPI_DSI_FMT_RGB888; 640 dsi->lanes = NUM_MIPI_LANES; 641 642 return 0; 643 } 644 645 static int ps8640_bridge_link_panel(struct drm_dp_aux *aux) 646 { 647 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 648 struct device *dev = aux->dev; 649 struct device_node *np = dev->of_node; 650 int ret; 651 652 /* 653 * NOTE about returning -EPROBE_DEFER from this function: if we 654 * return an error (most relevant to -EPROBE_DEFER) it will only 655 * be passed out to ps8640_probe() if it called this directly (AKA the 656 * panel isn't under the "aux-bus" node). That should be fine because 657 * if the panel is under "aux-bus" it's guaranteed to have probed by 658 * the time this function has been called. 659 */ 660 661 /* port@1 is ps8640 output port */ 662 ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); 663 if (IS_ERR(ps_bridge->panel_bridge)) 664 return PTR_ERR(ps_bridge->panel_bridge); 665 666 ret = devm_drm_bridge_add(dev, &ps_bridge->bridge); 667 if (ret) 668 return ret; 669 670 return devm_mipi_dsi_attach(dev, ps_bridge->dsi); 671 } 672 673 static int ps8640_probe(struct i2c_client *client) 674 { 675 struct device *dev = &client->dev; 676 struct ps8640 *ps_bridge; 677 int ret; 678 u32 i; 679 680 ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL); 681 if (!ps_bridge) 682 return -ENOMEM; 683 684 ps_bridge->supplies[0].supply = "vdd12"; 685 ps_bridge->supplies[1].supply = "vdd33"; 686 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies), 687 ps_bridge->supplies); 688 if (ret) 689 return ret; 690 691 ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown", 692 GPIOD_OUT_HIGH); 693 if (IS_ERR(ps_bridge->gpio_powerdown)) 694 return PTR_ERR(ps_bridge->gpio_powerdown); 695 696 /* 697 * Assert the reset to avoid the bridge being initialized prematurely 698 */ 699 ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset", 700 GPIOD_OUT_HIGH); 701 if (IS_ERR(ps_bridge->gpio_reset)) 702 return PTR_ERR(ps_bridge->gpio_reset); 703 704 ps_bridge->bridge.funcs = &ps8640_bridge_funcs; 705 ps_bridge->bridge.of_node = dev->of_node; 706 ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP; 707 708 /* 709 * In the device tree, if panel is listed under aux-bus of the bridge 710 * node, panel driver should be able to retrieve EDID by itself using 711 * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here. 712 */ 713 if (!ps8640_of_panel_on_aux_bus(&client->dev)) 714 ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID; 715 716 /* 717 * Get MIPI DSI resources early. These can return -EPROBE_DEFER so 718 * we want to get them out of the way sooner. 719 */ 720 ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge); 721 if (ret) 722 return ret; 723 724 ps_bridge->page[PAGE0_DP_CNTL] = client; 725 726 ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config); 727 if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL])) 728 return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]); 729 730 for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { 731 ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, 732 client->adapter, 733 client->addr + i); 734 if (IS_ERR(ps_bridge->page[i])) 735 return PTR_ERR(ps_bridge->page[i]); 736 737 ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i], 738 ps8640_regmap_config + i); 739 if (IS_ERR(ps_bridge->regmap[i])) 740 return PTR_ERR(ps_bridge->regmap[i]); 741 } 742 743 i2c_set_clientdata(client, ps_bridge); 744 745 ps_bridge->aux.name = "parade-ps8640-aux"; 746 ps_bridge->aux.dev = dev; 747 ps_bridge->aux.transfer = ps8640_aux_transfer; 748 ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted; 749 drm_dp_aux_init(&ps_bridge->aux); 750 751 pm_runtime_enable(dev); 752 /* 753 * Powering on ps8640 takes ~300ms. To avoid wasting time on power 754 * cycling ps8640 too often, set autosuspend_delay to 2000ms to ensure 755 * the bridge wouldn't suspend in between each _aux_transfer_msg() call 756 * during EDID read (~20ms in my experiment) and in between the last 757 * _aux_transfer_msg() call during EDID read and the _pre_enable() call 758 * (~100ms in my experiment). 759 */ 760 pm_runtime_set_autosuspend_delay(dev, 2000); 761 pm_runtime_use_autosuspend(dev); 762 pm_suspend_ignore_children(dev, true); 763 ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); 764 if (ret) 765 return ret; 766 767 ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel); 768 769 /* 770 * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to 771 * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case 772 * the function is allowed to -EPROBE_DEFER. 773 */ 774 if (ret == -ENODEV) 775 return ps8640_bridge_link_panel(&ps_bridge->aux); 776 777 return ret; 778 } 779 780 static void ps8640_remove(struct i2c_client *client) 781 { 782 struct ps8640 *ps_bridge = i2c_get_clientdata(client); 783 784 kfree(ps_bridge->edid); 785 } 786 787 static const struct of_device_id ps8640_match[] = { 788 { .compatible = "parade,ps8640" }, 789 { } 790 }; 791 MODULE_DEVICE_TABLE(of, ps8640_match); 792 793 static struct i2c_driver ps8640_driver = { 794 .probe_new = ps8640_probe, 795 .remove = ps8640_remove, 796 .driver = { 797 .name = "ps8640", 798 .of_match_table = ps8640_match, 799 .pm = &ps8640_pm_ops, 800 }, 801 }; 802 module_i2c_driver(ps8640_driver); 803 804 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>"); 805 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>"); 806 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>"); 807 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver"); 808 MODULE_LICENSE("GPL v2"); 809