1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016 MediaTek Inc.
4  */
5 
6 #include <linux/delay.h>
7 #include <linux/err.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/i2c.h>
10 #include <linux/module.h>
11 #include <linux/of_graph.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 
16 #include <drm/display/drm_dp_aux_bus.h>
17 #include <drm/display/drm_dp_helper.h>
18 #include <drm/drm_bridge.h>
19 #include <drm/drm_edid.h>
20 #include <drm/drm_mipi_dsi.h>
21 #include <drm/drm_of.h>
22 #include <drm/drm_panel.h>
23 #include <drm/drm_print.h>
24 
25 #define PAGE0_AUXCH_CFG3	0x76
26 #define  AUXCH_CFG3_RESET	0xff
27 #define PAGE0_SWAUX_ADDR_7_0	0x7d
28 #define PAGE0_SWAUX_ADDR_15_8	0x7e
29 #define PAGE0_SWAUX_ADDR_23_16	0x7f
30 #define  SWAUX_ADDR_MASK	GENMASK(19, 0)
31 #define PAGE0_SWAUX_LENGTH	0x80
32 #define  SWAUX_LENGTH_MASK	GENMASK(3, 0)
33 #define  SWAUX_NO_PAYLOAD	BIT(7)
34 #define PAGE0_SWAUX_WDATA	0x81
35 #define PAGE0_SWAUX_RDATA	0x82
36 #define PAGE0_SWAUX_CTRL	0x83
37 #define  SWAUX_SEND		BIT(0)
38 #define PAGE0_SWAUX_STATUS	0x84
39 #define  SWAUX_M_MASK		GENMASK(4, 0)
40 #define  SWAUX_STATUS_MASK	GENMASK(7, 5)
41 #define  SWAUX_STATUS_NACK	(0x1 << 5)
42 #define  SWAUX_STATUS_DEFER	(0x2 << 5)
43 #define  SWAUX_STATUS_ACKM	(0x3 << 5)
44 #define  SWAUX_STATUS_INVALID	(0x4 << 5)
45 #define  SWAUX_STATUS_I2C_NACK	(0x5 << 5)
46 #define  SWAUX_STATUS_I2C_DEFER	(0x6 << 5)
47 #define  SWAUX_STATUS_TIMEOUT	(0x7 << 5)
48 
49 #define PAGE2_GPIO_H		0xa7
50 #define  PS_GPIO9		BIT(1)
51 #define PAGE2_I2C_BYPASS	0xea
52 #define  I2C_BYPASS_EN		0xd0
53 #define PAGE2_MCS_EN		0xf3
54 #define  MCS_EN			BIT(0)
55 
56 #define PAGE3_SET_ADD		0xfe
57 #define  VDO_CTL_ADD		0x13
58 #define  VDO_DIS		0x18
59 #define  VDO_EN			0x1c
60 
61 #define NUM_MIPI_LANES		4
62 
63 #define COMMON_PS8640_REGMAP_CONFIG \
64 	.reg_bits = 8, \
65 	.val_bits = 8, \
66 	.cache_type = REGCACHE_NONE
67 
68 /*
69  * PS8640 uses multiple addresses:
70  * page[0]: for DP control
71  * page[1]: for VIDEO Bridge
72  * page[2]: for control top
73  * page[3]: for DSI Link Control1
74  * page[4]: for MIPI Phy
75  * page[5]: for VPLL
76  * page[6]: for DSI Link Control2
77  * page[7]: for SPI ROM mapping
78  */
79 enum page_addr_offset {
80 	PAGE0_DP_CNTL = 0,
81 	PAGE1_VDO_BDG,
82 	PAGE2_TOP_CNTL,
83 	PAGE3_DSI_CNTL1,
84 	PAGE4_MIPI_PHY,
85 	PAGE5_VPLL,
86 	PAGE6_DSI_CNTL2,
87 	PAGE7_SPI_CNTL,
88 	MAX_DEVS
89 };
90 
91 enum ps8640_vdo_control {
92 	DISABLE = VDO_DIS,
93 	ENABLE = VDO_EN,
94 };
95 
96 struct ps8640 {
97 	struct drm_bridge bridge;
98 	struct drm_bridge *panel_bridge;
99 	struct drm_dp_aux aux;
100 	struct mipi_dsi_device *dsi;
101 	struct i2c_client *page[MAX_DEVS];
102 	struct regmap	*regmap[MAX_DEVS];
103 	struct regulator_bulk_data supplies[2];
104 	struct gpio_desc *gpio_reset;
105 	struct gpio_desc *gpio_powerdown;
106 	struct device_link *link;
107 	bool pre_enabled;
108 	bool need_post_hpd_delay;
109 };
110 
111 static const struct regmap_config ps8640_regmap_config[] = {
112 	[PAGE0_DP_CNTL] = {
113 		COMMON_PS8640_REGMAP_CONFIG,
114 		.max_register = 0xbf,
115 	},
116 	[PAGE1_VDO_BDG] = {
117 		COMMON_PS8640_REGMAP_CONFIG,
118 		.max_register = 0xff,
119 	},
120 	[PAGE2_TOP_CNTL] = {
121 		COMMON_PS8640_REGMAP_CONFIG,
122 		.max_register = 0xff,
123 	},
124 	[PAGE3_DSI_CNTL1] = {
125 		COMMON_PS8640_REGMAP_CONFIG,
126 		.max_register = 0xff,
127 	},
128 	[PAGE4_MIPI_PHY] = {
129 		COMMON_PS8640_REGMAP_CONFIG,
130 		.max_register = 0xff,
131 	},
132 	[PAGE5_VPLL] = {
133 		COMMON_PS8640_REGMAP_CONFIG,
134 		.max_register = 0x7f,
135 	},
136 	[PAGE6_DSI_CNTL2] = {
137 		COMMON_PS8640_REGMAP_CONFIG,
138 		.max_register = 0xff,
139 	},
140 	[PAGE7_SPI_CNTL] = {
141 		COMMON_PS8640_REGMAP_CONFIG,
142 		.max_register = 0xff,
143 	},
144 };
145 
146 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
147 {
148 	return container_of(e, struct ps8640, bridge);
149 }
150 
151 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
152 {
153 	return container_of(aux, struct ps8640, aux);
154 }
155 
156 static bool ps8640_of_panel_on_aux_bus(struct device *dev)
157 {
158 	struct device_node *bus, *panel;
159 
160 	bus = of_get_child_by_name(dev->of_node, "aux-bus");
161 	if (!bus)
162 		return false;
163 
164 	panel = of_get_child_by_name(bus, "panel");
165 	of_node_put(bus);
166 	if (!panel)
167 		return false;
168 	of_node_put(panel);
169 
170 	return true;
171 }
172 
173 static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us)
174 {
175 	struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
176 	int status;
177 	int ret;
178 
179 	/*
180 	 * Apparently something about the firmware in the chip signals that
181 	 * HPD goes high by reporting GPIO9 as high (even though HPD isn't
182 	 * actually connected to GPIO9).
183 	 */
184 	ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
185 				       status & PS_GPIO9, wait_us / 10, wait_us);
186 
187 	/*
188 	 * The first time we see HPD go high after a reset we delay an extra
189 	 * 50 ms. The best guess is that the MCU is doing "stuff" during this
190 	 * time (maybe talking to the panel) and we don't want to interrupt it.
191 	 *
192 	 * No locking is done around "need_post_hpd_delay". If we're here we
193 	 * know we're holding a PM Runtime reference and the only other place
194 	 * that touches this is PM Runtime resume.
195 	 */
196 	if (!ret && ps_bridge->need_post_hpd_delay) {
197 		ps_bridge->need_post_hpd_delay = false;
198 		msleep(50);
199 	}
200 
201 	return ret;
202 }
203 
204 static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
205 {
206 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
207 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
208 	int ret;
209 
210 	/*
211 	 * Note that this function is called by code that has already powered
212 	 * the panel. We have to power ourselves up but we don't need to worry
213 	 * about powering the panel.
214 	 */
215 	pm_runtime_get_sync(dev);
216 	ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us);
217 	pm_runtime_mark_last_busy(dev);
218 	pm_runtime_put_autosuspend(dev);
219 
220 	return ret;
221 }
222 
223 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
224 				       struct drm_dp_aux_msg *msg)
225 {
226 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
227 	struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
228 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
229 	unsigned int len = msg->size;
230 	unsigned int data;
231 	unsigned int base;
232 	int ret;
233 	u8 request = msg->request &
234 		     ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
235 	u8 *buf = msg->buffer;
236 	u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
237 	u8 i;
238 	bool is_native_aux = false;
239 
240 	if (len > DP_AUX_MAX_PAYLOAD_BYTES)
241 		return -EINVAL;
242 
243 	if (msg->address & ~SWAUX_ADDR_MASK)
244 		return -EINVAL;
245 
246 	switch (request) {
247 	case DP_AUX_NATIVE_WRITE:
248 	case DP_AUX_NATIVE_READ:
249 		is_native_aux = true;
250 		fallthrough;
251 	case DP_AUX_I2C_WRITE:
252 	case DP_AUX_I2C_READ:
253 		break;
254 	default:
255 		return -EINVAL;
256 	}
257 
258 	ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
259 	if (ret) {
260 		DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
261 			      ret);
262 		return ret;
263 	}
264 
265 	/* Assume it's good */
266 	msg->reply = 0;
267 
268 	base = PAGE0_SWAUX_ADDR_7_0;
269 	addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
270 	addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
271 	addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
272 						  (msg->request << 4);
273 	addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
274 					      ((len - 1) & SWAUX_LENGTH_MASK);
275 
276 	regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len,
277 			  ARRAY_SIZE(addr_len));
278 
279 	if (len && (request == DP_AUX_NATIVE_WRITE ||
280 		    request == DP_AUX_I2C_WRITE)) {
281 		/* Write to the internal FIFO buffer */
282 		for (i = 0; i < len; i++) {
283 			ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]);
284 			if (ret) {
285 				DRM_DEV_ERROR(dev,
286 					      "failed to write WDATA: %d\n",
287 					      ret);
288 				return ret;
289 			}
290 		}
291 	}
292 
293 	regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
294 
295 	/* Zero delay loop because i2c transactions are slow already */
296 	regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
297 				 !(data & SWAUX_SEND), 0, 50 * 1000);
298 
299 	regmap_read(map, PAGE0_SWAUX_STATUS, &data);
300 	if (ret) {
301 		DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
302 			      ret);
303 		return ret;
304 	}
305 
306 	switch (data & SWAUX_STATUS_MASK) {
307 	/* Ignore the DEFER cases as they are already handled in hardware */
308 	case SWAUX_STATUS_NACK:
309 	case SWAUX_STATUS_I2C_NACK:
310 		/*
311 		 * The programming guide is not clear about whether a I2C NACK
312 		 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
313 		 * we handle both cases together.
314 		 */
315 		if (is_native_aux)
316 			msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
317 		else
318 			msg->reply |= DP_AUX_I2C_REPLY_NACK;
319 
320 		fallthrough;
321 	case SWAUX_STATUS_ACKM:
322 		len = data & SWAUX_M_MASK;
323 		break;
324 	case SWAUX_STATUS_INVALID:
325 		return -EOPNOTSUPP;
326 	case SWAUX_STATUS_TIMEOUT:
327 		return -ETIMEDOUT;
328 	}
329 
330 	if (len && (request == DP_AUX_NATIVE_READ ||
331 		    request == DP_AUX_I2C_READ)) {
332 		/* Read from the internal FIFO buffer */
333 		for (i = 0; i < len; i++) {
334 			ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data);
335 			if (ret) {
336 				DRM_DEV_ERROR(dev,
337 					      "failed to read RDATA: %d\n",
338 					      ret);
339 				return ret;
340 			}
341 
342 			buf[i] = data;
343 		}
344 	}
345 
346 	return len;
347 }
348 
349 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
350 				   struct drm_dp_aux_msg *msg)
351 {
352 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
353 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
354 	int ret;
355 
356 	pm_runtime_get_sync(dev);
357 	ret = ps8640_aux_transfer_msg(aux, msg);
358 	pm_runtime_mark_last_busy(dev);
359 	pm_runtime_put_autosuspend(dev);
360 
361 	return ret;
362 }
363 
364 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
365 				      const enum ps8640_vdo_control ctrl)
366 {
367 	struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
368 	struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
369 	u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
370 	int ret;
371 
372 	ret = regmap_bulk_write(map, PAGE3_SET_ADD,
373 				vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
374 
375 	if (ret < 0)
376 		dev_err(dev, "failed to %sable VDO: %d\n",
377 			ctrl == ENABLE ? "en" : "dis", ret);
378 }
379 
380 static int __maybe_unused ps8640_resume(struct device *dev)
381 {
382 	struct ps8640 *ps_bridge = dev_get_drvdata(dev);
383 	int ret;
384 
385 	ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
386 				    ps_bridge->supplies);
387 	if (ret < 0) {
388 		dev_err(dev, "cannot enable regulators %d\n", ret);
389 		return ret;
390 	}
391 
392 	gpiod_set_value(ps_bridge->gpio_powerdown, 0);
393 	gpiod_set_value(ps_bridge->gpio_reset, 1);
394 	usleep_range(2000, 2500);
395 	gpiod_set_value(ps_bridge->gpio_reset, 0);
396 	/* Double reset for T4 and T5 */
397 	msleep(50);
398 	gpiod_set_value(ps_bridge->gpio_reset, 1);
399 	msleep(50);
400 	gpiod_set_value(ps_bridge->gpio_reset, 0);
401 
402 	/* We just reset things, so we need a delay after the first HPD */
403 	ps_bridge->need_post_hpd_delay = true;
404 
405 	/*
406 	 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
407 	 * this is truly necessary since the MCU will already signal that
408 	 * things are "good to go" by signaling HPD on "gpio 9". See
409 	 * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
410 	 * just in case.
411 	 */
412 	msleep(200);
413 
414 	return 0;
415 }
416 
417 static int __maybe_unused ps8640_suspend(struct device *dev)
418 {
419 	struct ps8640 *ps_bridge = dev_get_drvdata(dev);
420 	int ret;
421 
422 	gpiod_set_value(ps_bridge->gpio_reset, 1);
423 	gpiod_set_value(ps_bridge->gpio_powerdown, 1);
424 	ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
425 				     ps_bridge->supplies);
426 	if (ret < 0)
427 		dev_err(dev, "cannot disable regulators %d\n", ret);
428 
429 	return ret;
430 }
431 
432 static const struct dev_pm_ops ps8640_pm_ops = {
433 	SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
434 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
435 				pm_runtime_force_resume)
436 };
437 
438 static void ps8640_pre_enable(struct drm_bridge *bridge)
439 {
440 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
441 	struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
442 	struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
443 	int ret;
444 
445 	pm_runtime_get_sync(dev);
446 	ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000);
447 	if (ret < 0)
448 		dev_warn(dev, "HPD didn't go high: %d\n", ret);
449 
450 	/*
451 	 * The Manufacturer Command Set (MCS) is a device dependent interface
452 	 * intended for factory programming of the display module default
453 	 * parameters. Once the display module is configured, the MCS shall be
454 	 * disabled by the manufacturer. Once disabled, all MCS commands are
455 	 * ignored by the display interface.
456 	 */
457 
458 	ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
459 	if (ret < 0)
460 		dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
461 
462 	/* Switch access edp panel's edid through i2c */
463 	ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
464 	if (ret < 0)
465 		dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
466 
467 	ps8640_bridge_vdo_control(ps_bridge, ENABLE);
468 
469 	ps_bridge->pre_enabled = true;
470 }
471 
472 static void ps8640_post_disable(struct drm_bridge *bridge)
473 {
474 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
475 
476 	ps_bridge->pre_enabled = false;
477 
478 	ps8640_bridge_vdo_control(ps_bridge, DISABLE);
479 	pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev);
480 }
481 
482 static int ps8640_bridge_attach(struct drm_bridge *bridge,
483 				enum drm_bridge_attach_flags flags)
484 {
485 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
486 	struct device *dev = &ps_bridge->page[0]->dev;
487 	int ret;
488 
489 	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
490 		return -EINVAL;
491 
492 	ps_bridge->aux.drm_dev = bridge->dev;
493 	ret = drm_dp_aux_register(&ps_bridge->aux);
494 	if (ret) {
495 		dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
496 		return ret;
497 	}
498 
499 	ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
500 	if (!ps_bridge->link) {
501 		dev_err(dev, "failed to create device link");
502 		ret = -EINVAL;
503 		goto err_devlink;
504 	}
505 
506 	/* Attach the panel-bridge to the dsi bridge */
507 	ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
508 				&ps_bridge->bridge, flags);
509 	if (ret)
510 		goto err_bridge_attach;
511 
512 	return 0;
513 
514 err_bridge_attach:
515 	device_link_del(ps_bridge->link);
516 err_devlink:
517 	drm_dp_aux_unregister(&ps_bridge->aux);
518 
519 	return ret;
520 }
521 
522 static void ps8640_bridge_detach(struct drm_bridge *bridge)
523 {
524 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
525 
526 	drm_dp_aux_unregister(&ps_bridge->aux);
527 	if (ps_bridge->link)
528 		device_link_del(ps_bridge->link);
529 }
530 
531 static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
532 					   struct drm_connector *connector)
533 {
534 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
535 	bool poweroff = !ps_bridge->pre_enabled;
536 	struct edid *edid;
537 
538 	/*
539 	 * When we end calling get_edid() triggered by an ioctl, i.e
540 	 *
541 	 *   drm_mode_getconnector (ioctl)
542 	 *     -> drm_helper_probe_single_connector_modes
543 	 *        -> drm_bridge_connector_get_modes
544 	 *           -> ps8640_bridge_get_edid
545 	 *
546 	 * We need to make sure that what we need is enabled before reading
547 	 * EDID, for this chip, we need to do a full poweron, otherwise it will
548 	 * fail.
549 	 */
550 	drm_bridge_chain_pre_enable(bridge);
551 
552 	edid = drm_get_edid(connector,
553 			    ps_bridge->page[PAGE0_DP_CNTL]->adapter);
554 
555 	/*
556 	 * If we call the get_edid() function without having enabled the chip
557 	 * before, return the chip to its original power state.
558 	 */
559 	if (poweroff)
560 		drm_bridge_chain_post_disable(bridge);
561 
562 	return edid;
563 }
564 
565 static void ps8640_runtime_disable(void *data)
566 {
567 	pm_runtime_dont_use_autosuspend(data);
568 	pm_runtime_disable(data);
569 }
570 
571 static const struct drm_bridge_funcs ps8640_bridge_funcs = {
572 	.attach = ps8640_bridge_attach,
573 	.detach = ps8640_bridge_detach,
574 	.get_edid = ps8640_bridge_get_edid,
575 	.post_disable = ps8640_post_disable,
576 	.pre_enable = ps8640_pre_enable,
577 };
578 
579 static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge)
580 {
581 	struct device_node *in_ep, *dsi_node;
582 	struct mipi_dsi_device *dsi;
583 	struct mipi_dsi_host *host;
584 	const struct mipi_dsi_device_info info = { .type = "ps8640",
585 						   .channel = 0,
586 						   .node = NULL,
587 						 };
588 
589 	/* port@0 is ps8640 dsi input port */
590 	in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
591 	if (!in_ep)
592 		return -ENODEV;
593 
594 	dsi_node = of_graph_get_remote_port_parent(in_ep);
595 	of_node_put(in_ep);
596 	if (!dsi_node)
597 		return -ENODEV;
598 
599 	host = of_find_mipi_dsi_host_by_node(dsi_node);
600 	of_node_put(dsi_node);
601 	if (!host)
602 		return -EPROBE_DEFER;
603 
604 	dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
605 	if (IS_ERR(dsi)) {
606 		dev_err(dev, "failed to create dsi device\n");
607 		return PTR_ERR(dsi);
608 	}
609 
610 	ps_bridge->dsi = dsi;
611 
612 	dsi->host = host;
613 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
614 			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
615 	dsi->format = MIPI_DSI_FMT_RGB888;
616 	dsi->lanes = NUM_MIPI_LANES;
617 
618 	return 0;
619 }
620 
621 static int ps8640_bridge_link_panel(struct drm_dp_aux *aux)
622 {
623 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);
624 	struct device *dev = aux->dev;
625 	struct device_node *np = dev->of_node;
626 	int ret;
627 
628 	/*
629 	 * NOTE about returning -EPROBE_DEFER from this function: if we
630 	 * return an error (most relevant to -EPROBE_DEFER) it will only
631 	 * be passed out to ps8640_probe() if it called this directly (AKA the
632 	 * panel isn't under the "aux-bus" node). That should be fine because
633 	 * if the panel is under "aux-bus" it's guaranteed to have probed by
634 	 * the time this function has been called.
635 	 */
636 
637 	/* port@1 is ps8640 output port */
638 	ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
639 	if (IS_ERR(ps_bridge->panel_bridge))
640 		return PTR_ERR(ps_bridge->panel_bridge);
641 
642 	ret = devm_drm_bridge_add(dev, &ps_bridge->bridge);
643 	if (ret)
644 		return ret;
645 
646 	return devm_mipi_dsi_attach(dev, ps_bridge->dsi);
647 }
648 
649 static int ps8640_probe(struct i2c_client *client)
650 {
651 	struct device *dev = &client->dev;
652 	struct ps8640 *ps_bridge;
653 	int ret;
654 	u32 i;
655 
656 	ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
657 	if (!ps_bridge)
658 		return -ENOMEM;
659 
660 	ps_bridge->supplies[0].supply = "vdd12";
661 	ps_bridge->supplies[1].supply = "vdd33";
662 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
663 				      ps_bridge->supplies);
664 	if (ret)
665 		return ret;
666 
667 	ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
668 						   GPIOD_OUT_HIGH);
669 	if (IS_ERR(ps_bridge->gpio_powerdown))
670 		return PTR_ERR(ps_bridge->gpio_powerdown);
671 
672 	/*
673 	 * Assert the reset to avoid the bridge being initialized prematurely
674 	 */
675 	ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
676 					       GPIOD_OUT_HIGH);
677 	if (IS_ERR(ps_bridge->gpio_reset))
678 		return PTR_ERR(ps_bridge->gpio_reset);
679 
680 	ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
681 	ps_bridge->bridge.of_node = dev->of_node;
682 	ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
683 
684 	/*
685 	 * In the device tree, if panel is listed under aux-bus of the bridge
686 	 * node, panel driver should be able to retrieve EDID by itself using
687 	 * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here.
688 	 */
689 	if (!ps8640_of_panel_on_aux_bus(&client->dev))
690 		ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
691 
692 	/*
693 	 * Get MIPI DSI resources early. These can return -EPROBE_DEFER so
694 	 * we want to get them out of the way sooner.
695 	 */
696 	ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge);
697 	if (ret)
698 		return ret;
699 
700 	ps_bridge->page[PAGE0_DP_CNTL] = client;
701 
702 	ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
703 	if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]))
704 		return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]);
705 
706 	for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
707 		ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
708 							     client->adapter,
709 							     client->addr + i);
710 		if (IS_ERR(ps_bridge->page[i]))
711 			return PTR_ERR(ps_bridge->page[i]);
712 
713 		ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
714 							    ps8640_regmap_config + i);
715 		if (IS_ERR(ps_bridge->regmap[i]))
716 			return PTR_ERR(ps_bridge->regmap[i]);
717 	}
718 
719 	i2c_set_clientdata(client, ps_bridge);
720 
721 	ps_bridge->aux.name = "parade-ps8640-aux";
722 	ps_bridge->aux.dev = dev;
723 	ps_bridge->aux.transfer = ps8640_aux_transfer;
724 	ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted;
725 	drm_dp_aux_init(&ps_bridge->aux);
726 
727 	pm_runtime_enable(dev);
728 	/*
729 	 * Powering on ps8640 takes ~300ms. To avoid wasting time on power
730 	 * cycling ps8640 too often, set autosuspend_delay to 1000ms to ensure
731 	 * the bridge wouldn't suspend in between each _aux_transfer_msg() call
732 	 * during EDID read (~20ms in my experiment) and in between the last
733 	 * _aux_transfer_msg() call during EDID read and the _pre_enable() call
734 	 * (~100ms in my experiment).
735 	 */
736 	pm_runtime_set_autosuspend_delay(dev, 1000);
737 	pm_runtime_use_autosuspend(dev);
738 	pm_suspend_ignore_children(dev, true);
739 	ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
740 	if (ret)
741 		return ret;
742 
743 	ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel);
744 
745 	/*
746 	 * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to
747 	 * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case
748 	 * the function is allowed to -EPROBE_DEFER.
749 	 */
750 	if (ret == -ENODEV)
751 		return ps8640_bridge_link_panel(&ps_bridge->aux);
752 
753 	return ret;
754 }
755 
756 static const struct of_device_id ps8640_match[] = {
757 	{ .compatible = "parade,ps8640" },
758 	{ }
759 };
760 MODULE_DEVICE_TABLE(of, ps8640_match);
761 
762 static struct i2c_driver ps8640_driver = {
763 	.probe_new = ps8640_probe,
764 	.driver = {
765 		.name = "ps8640",
766 		.of_match_table = ps8640_match,
767 		.pm = &ps8640_pm_ops,
768 	},
769 };
770 module_i2c_driver(ps8640_driver);
771 
772 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
773 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
774 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
775 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
776 MODULE_LICENSE("GPL v2");
777