1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 MediaTek Inc. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/err.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/of_graph.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <drm/drm_bridge.h> 17 #include <drm/drm_dp_aux_bus.h> 18 #include <drm/drm_dp_helper.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_of.h> 21 #include <drm/drm_panel.h> 22 #include <drm/drm_print.h> 23 24 #define PAGE0_AUXCH_CFG3 0x76 25 #define AUXCH_CFG3_RESET 0xff 26 #define PAGE0_SWAUX_ADDR_7_0 0x7d 27 #define PAGE0_SWAUX_ADDR_15_8 0x7e 28 #define PAGE0_SWAUX_ADDR_23_16 0x7f 29 #define SWAUX_ADDR_MASK GENMASK(19, 0) 30 #define PAGE0_SWAUX_LENGTH 0x80 31 #define SWAUX_LENGTH_MASK GENMASK(3, 0) 32 #define SWAUX_NO_PAYLOAD BIT(7) 33 #define PAGE0_SWAUX_WDATA 0x81 34 #define PAGE0_SWAUX_RDATA 0x82 35 #define PAGE0_SWAUX_CTRL 0x83 36 #define SWAUX_SEND BIT(0) 37 #define PAGE0_SWAUX_STATUS 0x84 38 #define SWAUX_M_MASK GENMASK(4, 0) 39 #define SWAUX_STATUS_MASK GENMASK(7, 5) 40 #define SWAUX_STATUS_NACK (0x1 << 5) 41 #define SWAUX_STATUS_DEFER (0x2 << 5) 42 #define SWAUX_STATUS_ACKM (0x3 << 5) 43 #define SWAUX_STATUS_INVALID (0x4 << 5) 44 #define SWAUX_STATUS_I2C_NACK (0x5 << 5) 45 #define SWAUX_STATUS_I2C_DEFER (0x6 << 5) 46 #define SWAUX_STATUS_TIMEOUT (0x7 << 5) 47 48 #define PAGE2_GPIO_H 0xa7 49 #define PS_GPIO9 BIT(1) 50 #define PAGE2_I2C_BYPASS 0xea 51 #define I2C_BYPASS_EN 0xd0 52 #define PAGE2_MCS_EN 0xf3 53 #define MCS_EN BIT(0) 54 55 #define PAGE3_SET_ADD 0xfe 56 #define VDO_CTL_ADD 0x13 57 #define VDO_DIS 0x18 58 #define VDO_EN 0x1c 59 60 #define NUM_MIPI_LANES 4 61 62 #define COMMON_PS8640_REGMAP_CONFIG \ 63 .reg_bits = 8, \ 64 .val_bits = 8, \ 65 .cache_type = REGCACHE_NONE 66 67 /* 68 * PS8640 uses multiple addresses: 69 * page[0]: for DP control 70 * page[1]: for VIDEO Bridge 71 * page[2]: for control top 72 * page[3]: for DSI Link Control1 73 * page[4]: for MIPI Phy 74 * page[5]: for VPLL 75 * page[6]: for DSI Link Control2 76 * page[7]: for SPI ROM mapping 77 */ 78 enum page_addr_offset { 79 PAGE0_DP_CNTL = 0, 80 PAGE1_VDO_BDG, 81 PAGE2_TOP_CNTL, 82 PAGE3_DSI_CNTL1, 83 PAGE4_MIPI_PHY, 84 PAGE5_VPLL, 85 PAGE6_DSI_CNTL2, 86 PAGE7_SPI_CNTL, 87 MAX_DEVS 88 }; 89 90 enum ps8640_vdo_control { 91 DISABLE = VDO_DIS, 92 ENABLE = VDO_EN, 93 }; 94 95 struct ps8640 { 96 struct drm_bridge bridge; 97 struct drm_bridge *panel_bridge; 98 struct drm_dp_aux aux; 99 struct mipi_dsi_device *dsi; 100 struct i2c_client *page[MAX_DEVS]; 101 struct regmap *regmap[MAX_DEVS]; 102 struct regulator_bulk_data supplies[2]; 103 struct gpio_desc *gpio_reset; 104 struct gpio_desc *gpio_powerdown; 105 bool pre_enabled; 106 }; 107 108 static const struct regmap_config ps8640_regmap_config[] = { 109 [PAGE0_DP_CNTL] = { 110 COMMON_PS8640_REGMAP_CONFIG, 111 .max_register = 0xbf, 112 }, 113 [PAGE1_VDO_BDG] = { 114 COMMON_PS8640_REGMAP_CONFIG, 115 .max_register = 0xff, 116 }, 117 [PAGE2_TOP_CNTL] = { 118 COMMON_PS8640_REGMAP_CONFIG, 119 .max_register = 0xff, 120 }, 121 [PAGE3_DSI_CNTL1] = { 122 COMMON_PS8640_REGMAP_CONFIG, 123 .max_register = 0xff, 124 }, 125 [PAGE4_MIPI_PHY] = { 126 COMMON_PS8640_REGMAP_CONFIG, 127 .max_register = 0xff, 128 }, 129 [PAGE5_VPLL] = { 130 COMMON_PS8640_REGMAP_CONFIG, 131 .max_register = 0x7f, 132 }, 133 [PAGE6_DSI_CNTL2] = { 134 COMMON_PS8640_REGMAP_CONFIG, 135 .max_register = 0xff, 136 }, 137 [PAGE7_SPI_CNTL] = { 138 COMMON_PS8640_REGMAP_CONFIG, 139 .max_register = 0xff, 140 }, 141 }; 142 143 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) 144 { 145 return container_of(e, struct ps8640, bridge); 146 } 147 148 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) 149 { 150 return container_of(aux, struct ps8640, aux); 151 } 152 153 static bool ps8640_of_panel_on_aux_bus(struct device *dev) 154 { 155 struct device_node *bus, *panel; 156 157 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 158 if (!bus) 159 return false; 160 161 panel = of_get_child_by_name(bus, "panel"); 162 of_node_put(bus); 163 if (!panel) 164 return false; 165 of_node_put(panel); 166 167 return true; 168 } 169 170 static int ps8640_ensure_hpd(struct ps8640 *ps_bridge) 171 { 172 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; 173 struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev; 174 int status; 175 int ret; 176 177 /* 178 * Apparently something about the firmware in the chip signals that 179 * HPD goes high by reporting GPIO9 as high (even though HPD isn't 180 * actually connected to GPIO9). 181 */ 182 ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, 183 status & PS_GPIO9, 20 * 1000, 200 * 1000); 184 185 if (ret < 0) 186 dev_warn(dev, "HPD didn't go high: %d\n", ret); 187 188 return ret; 189 } 190 191 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, 192 struct drm_dp_aux_msg *msg) 193 { 194 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 195 struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; 196 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 197 unsigned int len = msg->size; 198 unsigned int data; 199 unsigned int base; 200 int ret; 201 u8 request = msg->request & 202 ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 203 u8 *buf = msg->buffer; 204 u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0]; 205 u8 i; 206 bool is_native_aux = false; 207 208 if (len > DP_AUX_MAX_PAYLOAD_BYTES) 209 return -EINVAL; 210 211 if (msg->address & ~SWAUX_ADDR_MASK) 212 return -EINVAL; 213 214 switch (request) { 215 case DP_AUX_NATIVE_WRITE: 216 case DP_AUX_NATIVE_READ: 217 is_native_aux = true; 218 fallthrough; 219 case DP_AUX_I2C_WRITE: 220 case DP_AUX_I2C_READ: 221 break; 222 default: 223 return -EINVAL; 224 } 225 226 ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); 227 if (ret) { 228 DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n", 229 ret); 230 return ret; 231 } 232 233 /* Assume it's good */ 234 msg->reply = 0; 235 236 base = PAGE0_SWAUX_ADDR_7_0; 237 addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address; 238 addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8; 239 addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) | 240 (msg->request << 4); 241 addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD : 242 ((len - 1) & SWAUX_LENGTH_MASK); 243 244 regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len, 245 ARRAY_SIZE(addr_len)); 246 247 if (len && (request == DP_AUX_NATIVE_WRITE || 248 request == DP_AUX_I2C_WRITE)) { 249 /* Write to the internal FIFO buffer */ 250 for (i = 0; i < len; i++) { 251 ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]); 252 if (ret) { 253 DRM_DEV_ERROR(dev, 254 "failed to write WDATA: %d\n", 255 ret); 256 return ret; 257 } 258 } 259 } 260 261 regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND); 262 263 /* Zero delay loop because i2c transactions are slow already */ 264 regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data, 265 !(data & SWAUX_SEND), 0, 50 * 1000); 266 267 regmap_read(map, PAGE0_SWAUX_STATUS, &data); 268 if (ret) { 269 DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n", 270 ret); 271 return ret; 272 } 273 274 switch (data & SWAUX_STATUS_MASK) { 275 /* Ignore the DEFER cases as they are already handled in hardware */ 276 case SWAUX_STATUS_NACK: 277 case SWAUX_STATUS_I2C_NACK: 278 /* 279 * The programming guide is not clear about whether a I2C NACK 280 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So 281 * we handle both cases together. 282 */ 283 if (is_native_aux) 284 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 285 else 286 msg->reply |= DP_AUX_I2C_REPLY_NACK; 287 288 fallthrough; 289 case SWAUX_STATUS_ACKM: 290 len = data & SWAUX_M_MASK; 291 break; 292 case SWAUX_STATUS_INVALID: 293 return -EOPNOTSUPP; 294 case SWAUX_STATUS_TIMEOUT: 295 return -ETIMEDOUT; 296 } 297 298 if (len && (request == DP_AUX_NATIVE_READ || 299 request == DP_AUX_I2C_READ)) { 300 /* Read from the internal FIFO buffer */ 301 for (i = 0; i < len; i++) { 302 ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data); 303 if (ret) { 304 DRM_DEV_ERROR(dev, 305 "failed to read RDATA: %d\n", 306 ret); 307 return ret; 308 } 309 310 buf[i] = data; 311 } 312 } 313 314 return len; 315 } 316 317 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, 318 struct drm_dp_aux_msg *msg) 319 { 320 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 321 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 322 int ret; 323 324 pm_runtime_get_sync(dev); 325 ret = ps8640_ensure_hpd(ps_bridge); 326 if (!ret) 327 ret = ps8640_aux_transfer_msg(aux, msg); 328 pm_runtime_mark_last_busy(dev); 329 pm_runtime_put_autosuspend(dev); 330 331 return ret; 332 } 333 334 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, 335 const enum ps8640_vdo_control ctrl) 336 { 337 struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; 338 struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; 339 u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; 340 int ret; 341 342 ret = regmap_bulk_write(map, PAGE3_SET_ADD, 343 vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); 344 345 if (ret < 0) 346 dev_err(dev, "failed to %sable VDO: %d\n", 347 ctrl == ENABLE ? "en" : "dis", ret); 348 } 349 350 static int __maybe_unused ps8640_resume(struct device *dev) 351 { 352 struct ps8640 *ps_bridge = dev_get_drvdata(dev); 353 int ret; 354 355 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), 356 ps_bridge->supplies); 357 if (ret < 0) { 358 dev_err(dev, "cannot enable regulators %d\n", ret); 359 return ret; 360 } 361 362 gpiod_set_value(ps_bridge->gpio_powerdown, 0); 363 gpiod_set_value(ps_bridge->gpio_reset, 1); 364 usleep_range(2000, 2500); 365 gpiod_set_value(ps_bridge->gpio_reset, 0); 366 367 /* 368 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if 369 * this is truly necessary since the MCU will already signal that 370 * things are "good to go" by signaling HPD on "gpio 9". See 371 * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in 372 * case. 373 */ 374 msleep(200); 375 376 return 0; 377 } 378 379 static int __maybe_unused ps8640_suspend(struct device *dev) 380 { 381 struct ps8640 *ps_bridge = dev_get_drvdata(dev); 382 int ret; 383 384 gpiod_set_value(ps_bridge->gpio_reset, 1); 385 gpiod_set_value(ps_bridge->gpio_powerdown, 1); 386 ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), 387 ps_bridge->supplies); 388 if (ret < 0) 389 dev_err(dev, "cannot disable regulators %d\n", ret); 390 391 return ret; 392 } 393 394 static const struct dev_pm_ops ps8640_pm_ops = { 395 SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) 396 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 397 pm_runtime_force_resume) 398 }; 399 400 static void ps8640_pre_enable(struct drm_bridge *bridge) 401 { 402 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 403 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; 404 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 405 int ret; 406 407 pm_runtime_get_sync(dev); 408 ps8640_ensure_hpd(ps_bridge); 409 410 /* 411 * The Manufacturer Command Set (MCS) is a device dependent interface 412 * intended for factory programming of the display module default 413 * parameters. Once the display module is configured, the MCS shall be 414 * disabled by the manufacturer. Once disabled, all MCS commands are 415 * ignored by the display interface. 416 */ 417 418 ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); 419 if (ret < 0) 420 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); 421 422 /* Switch access edp panel's edid through i2c */ 423 ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); 424 if (ret < 0) 425 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); 426 427 ps8640_bridge_vdo_control(ps_bridge, ENABLE); 428 429 ps_bridge->pre_enabled = true; 430 } 431 432 static void ps8640_post_disable(struct drm_bridge *bridge) 433 { 434 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 435 436 ps_bridge->pre_enabled = false; 437 438 ps8640_bridge_vdo_control(ps_bridge, DISABLE); 439 pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); 440 } 441 442 static int ps8640_bridge_attach(struct drm_bridge *bridge, 443 enum drm_bridge_attach_flags flags) 444 { 445 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 446 struct device *dev = &ps_bridge->page[0]->dev; 447 int ret; 448 449 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 450 return -EINVAL; 451 452 ps_bridge->aux.drm_dev = bridge->dev; 453 ret = drm_dp_aux_register(&ps_bridge->aux); 454 if (ret) { 455 dev_err(dev, "failed to register DP AUX channel: %d\n", ret); 456 return ret; 457 } 458 459 /* Attach the panel-bridge to the dsi bridge */ 460 return drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, 461 &ps_bridge->bridge, flags); 462 } 463 464 static void ps8640_bridge_detach(struct drm_bridge *bridge) 465 { 466 drm_dp_aux_unregister(&bridge_to_ps8640(bridge)->aux); 467 } 468 469 static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, 470 struct drm_connector *connector) 471 { 472 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 473 bool poweroff = !ps_bridge->pre_enabled; 474 struct edid *edid; 475 476 /* 477 * When we end calling get_edid() triggered by an ioctl, i.e 478 * 479 * drm_mode_getconnector (ioctl) 480 * -> drm_helper_probe_single_connector_modes 481 * -> drm_bridge_connector_get_modes 482 * -> ps8640_bridge_get_edid 483 * 484 * We need to make sure that what we need is enabled before reading 485 * EDID, for this chip, we need to do a full poweron, otherwise it will 486 * fail. 487 */ 488 drm_bridge_chain_pre_enable(bridge); 489 490 edid = drm_get_edid(connector, 491 ps_bridge->page[PAGE0_DP_CNTL]->adapter); 492 493 /* 494 * If we call the get_edid() function without having enabled the chip 495 * before, return the chip to its original power state. 496 */ 497 if (poweroff) 498 drm_bridge_chain_post_disable(bridge); 499 500 return edid; 501 } 502 503 static void ps8640_runtime_disable(void *data) 504 { 505 pm_runtime_dont_use_autosuspend(data); 506 pm_runtime_disable(data); 507 } 508 509 static const struct drm_bridge_funcs ps8640_bridge_funcs = { 510 .attach = ps8640_bridge_attach, 511 .detach = ps8640_bridge_detach, 512 .get_edid = ps8640_bridge_get_edid, 513 .post_disable = ps8640_post_disable, 514 .pre_enable = ps8640_pre_enable, 515 }; 516 517 static int ps8640_bridge_host_attach(struct device *dev, struct ps8640 *ps_bridge) 518 { 519 struct device_node *in_ep, *dsi_node; 520 struct mipi_dsi_device *dsi; 521 struct mipi_dsi_host *host; 522 int ret; 523 const struct mipi_dsi_device_info info = { .type = "ps8640", 524 .channel = 0, 525 .node = NULL, 526 }; 527 528 /* port@0 is ps8640 dsi input port */ 529 in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 530 if (!in_ep) 531 return -ENODEV; 532 533 dsi_node = of_graph_get_remote_port_parent(in_ep); 534 of_node_put(in_ep); 535 if (!dsi_node) 536 return -ENODEV; 537 538 host = of_find_mipi_dsi_host_by_node(dsi_node); 539 of_node_put(dsi_node); 540 if (!host) 541 return -EPROBE_DEFER; 542 543 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 544 if (IS_ERR(dsi)) { 545 dev_err(dev, "failed to create dsi device\n"); 546 return PTR_ERR(dsi); 547 } 548 549 ps_bridge->dsi = dsi; 550 551 dsi->host = host; 552 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 553 MIPI_DSI_MODE_VIDEO_SYNC_PULSE; 554 dsi->format = MIPI_DSI_FMT_RGB888; 555 dsi->lanes = NUM_MIPI_LANES; 556 557 ret = devm_mipi_dsi_attach(dev, dsi); 558 if (ret) 559 return ret; 560 561 return 0; 562 } 563 564 static int ps8640_probe(struct i2c_client *client) 565 { 566 struct device *dev = &client->dev; 567 struct device_node *np = dev->of_node; 568 struct ps8640 *ps_bridge; 569 struct drm_panel *panel; 570 int ret; 571 u32 i; 572 573 ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL); 574 if (!ps_bridge) 575 return -ENOMEM; 576 577 ps_bridge->supplies[0].supply = "vdd33"; 578 ps_bridge->supplies[1].supply = "vdd12"; 579 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies), 580 ps_bridge->supplies); 581 if (ret) 582 return ret; 583 584 ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown", 585 GPIOD_OUT_HIGH); 586 if (IS_ERR(ps_bridge->gpio_powerdown)) 587 return PTR_ERR(ps_bridge->gpio_powerdown); 588 589 /* 590 * Assert the reset to avoid the bridge being initialized prematurely 591 */ 592 ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset", 593 GPIOD_OUT_HIGH); 594 if (IS_ERR(ps_bridge->gpio_reset)) 595 return PTR_ERR(ps_bridge->gpio_reset); 596 597 ps_bridge->bridge.funcs = &ps8640_bridge_funcs; 598 ps_bridge->bridge.of_node = dev->of_node; 599 ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP; 600 601 /* 602 * In the device tree, if panel is listed under aux-bus of the bridge 603 * node, panel driver should be able to retrieve EDID by itself using 604 * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here. 605 */ 606 if (!ps8640_of_panel_on_aux_bus(&client->dev)) 607 ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID; 608 609 ps_bridge->page[PAGE0_DP_CNTL] = client; 610 611 ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config); 612 if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL])) 613 return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]); 614 615 for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { 616 ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, 617 client->adapter, 618 client->addr + i); 619 if (IS_ERR(ps_bridge->page[i])) 620 return PTR_ERR(ps_bridge->page[i]); 621 622 ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i], 623 ps8640_regmap_config + i); 624 if (IS_ERR(ps_bridge->regmap[i])) 625 return PTR_ERR(ps_bridge->regmap[i]); 626 } 627 628 i2c_set_clientdata(client, ps_bridge); 629 630 ps_bridge->aux.name = "parade-ps8640-aux"; 631 ps_bridge->aux.dev = dev; 632 ps_bridge->aux.transfer = ps8640_aux_transfer; 633 drm_dp_aux_init(&ps_bridge->aux); 634 635 pm_runtime_enable(dev); 636 /* 637 * Powering on ps8640 takes ~300ms. To avoid wasting time on power 638 * cycling ps8640 too often, set autosuspend_delay to 1000ms to ensure 639 * the bridge wouldn't suspend in between each _aux_transfer_msg() call 640 * during EDID read (~20ms in my experiment) and in between the last 641 * _aux_transfer_msg() call during EDID read and the _pre_enable() call 642 * (~100ms in my experiment). 643 */ 644 pm_runtime_set_autosuspend_delay(dev, 1000); 645 pm_runtime_use_autosuspend(dev); 646 pm_suspend_ignore_children(dev, true); 647 ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); 648 if (ret) 649 return ret; 650 651 devm_of_dp_aux_populate_ep_devices(&ps_bridge->aux); 652 653 /* port@1 is ps8640 output port */ 654 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 655 if (ret < 0) 656 return ret; 657 if (!panel) 658 return -ENODEV; 659 660 ps_bridge->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 661 if (IS_ERR(ps_bridge->panel_bridge)) 662 return PTR_ERR(ps_bridge->panel_bridge); 663 664 drm_bridge_add(&ps_bridge->bridge); 665 666 ret = ps8640_bridge_host_attach(dev, ps_bridge); 667 if (ret) 668 goto err_bridge_remove; 669 670 return 0; 671 672 err_bridge_remove: 673 drm_bridge_remove(&ps_bridge->bridge); 674 return ret; 675 } 676 677 static int ps8640_remove(struct i2c_client *client) 678 { 679 struct ps8640 *ps_bridge = i2c_get_clientdata(client); 680 681 drm_bridge_remove(&ps_bridge->bridge); 682 683 return 0; 684 } 685 686 static const struct of_device_id ps8640_match[] = { 687 { .compatible = "parade,ps8640" }, 688 { } 689 }; 690 MODULE_DEVICE_TABLE(of, ps8640_match); 691 692 static struct i2c_driver ps8640_driver = { 693 .probe_new = ps8640_probe, 694 .remove = ps8640_remove, 695 .driver = { 696 .name = "ps8640", 697 .of_match_table = ps8640_match, 698 .pm = &ps8640_pm_ops, 699 }, 700 }; 701 module_i2c_driver(ps8640_driver); 702 703 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>"); 704 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>"); 705 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>"); 706 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver"); 707 MODULE_LICENSE("GPL v2"); 708