1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 MediaTek Inc. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/err.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/of_graph.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <drm/display/drm_dp_aux_bus.h> 17 #include <drm/display/drm_dp_helper.h> 18 #include <drm/drm_bridge.h> 19 #include <drm/drm_edid.h> 20 #include <drm/drm_mipi_dsi.h> 21 #include <drm/drm_of.h> 22 #include <drm/drm_panel.h> 23 #include <drm/drm_print.h> 24 25 #define PAGE0_AUXCH_CFG3 0x76 26 #define AUXCH_CFG3_RESET 0xff 27 #define PAGE0_SWAUX_ADDR_7_0 0x7d 28 #define PAGE0_SWAUX_ADDR_15_8 0x7e 29 #define PAGE0_SWAUX_ADDR_23_16 0x7f 30 #define SWAUX_ADDR_MASK GENMASK(19, 0) 31 #define PAGE0_SWAUX_LENGTH 0x80 32 #define SWAUX_LENGTH_MASK GENMASK(3, 0) 33 #define SWAUX_NO_PAYLOAD BIT(7) 34 #define PAGE0_SWAUX_WDATA 0x81 35 #define PAGE0_SWAUX_RDATA 0x82 36 #define PAGE0_SWAUX_CTRL 0x83 37 #define SWAUX_SEND BIT(0) 38 #define PAGE0_SWAUX_STATUS 0x84 39 #define SWAUX_M_MASK GENMASK(4, 0) 40 #define SWAUX_STATUS_MASK GENMASK(7, 5) 41 #define SWAUX_STATUS_NACK (0x1 << 5) 42 #define SWAUX_STATUS_DEFER (0x2 << 5) 43 #define SWAUX_STATUS_ACKM (0x3 << 5) 44 #define SWAUX_STATUS_INVALID (0x4 << 5) 45 #define SWAUX_STATUS_I2C_NACK (0x5 << 5) 46 #define SWAUX_STATUS_I2C_DEFER (0x6 << 5) 47 #define SWAUX_STATUS_TIMEOUT (0x7 << 5) 48 49 #define PAGE2_GPIO_H 0xa7 50 #define PS_GPIO9 BIT(1) 51 #define PAGE2_I2C_BYPASS 0xea 52 #define I2C_BYPASS_EN 0xd0 53 #define PAGE2_MCS_EN 0xf3 54 #define MCS_EN BIT(0) 55 56 #define PAGE3_SET_ADD 0xfe 57 #define VDO_CTL_ADD 0x13 58 #define VDO_DIS 0x18 59 #define VDO_EN 0x1c 60 61 #define NUM_MIPI_LANES 4 62 63 #define COMMON_PS8640_REGMAP_CONFIG \ 64 .reg_bits = 8, \ 65 .val_bits = 8, \ 66 .cache_type = REGCACHE_NONE 67 68 /* 69 * PS8640 uses multiple addresses: 70 * page[0]: for DP control 71 * page[1]: for VIDEO Bridge 72 * page[2]: for control top 73 * page[3]: for DSI Link Control1 74 * page[4]: for MIPI Phy 75 * page[5]: for VPLL 76 * page[6]: for DSI Link Control2 77 * page[7]: for SPI ROM mapping 78 */ 79 enum page_addr_offset { 80 PAGE0_DP_CNTL = 0, 81 PAGE1_VDO_BDG, 82 PAGE2_TOP_CNTL, 83 PAGE3_DSI_CNTL1, 84 PAGE4_MIPI_PHY, 85 PAGE5_VPLL, 86 PAGE6_DSI_CNTL2, 87 PAGE7_SPI_CNTL, 88 MAX_DEVS 89 }; 90 91 enum ps8640_vdo_control { 92 DISABLE = VDO_DIS, 93 ENABLE = VDO_EN, 94 }; 95 96 struct ps8640 { 97 struct drm_bridge bridge; 98 struct drm_bridge *panel_bridge; 99 struct drm_dp_aux aux; 100 struct mipi_dsi_device *dsi; 101 struct i2c_client *page[MAX_DEVS]; 102 struct regmap *regmap[MAX_DEVS]; 103 struct regulator_bulk_data supplies[2]; 104 struct gpio_desc *gpio_reset; 105 struct gpio_desc *gpio_powerdown; 106 struct device_link *link; 107 bool pre_enabled; 108 }; 109 110 static const struct regmap_config ps8640_regmap_config[] = { 111 [PAGE0_DP_CNTL] = { 112 COMMON_PS8640_REGMAP_CONFIG, 113 .max_register = 0xbf, 114 }, 115 [PAGE1_VDO_BDG] = { 116 COMMON_PS8640_REGMAP_CONFIG, 117 .max_register = 0xff, 118 }, 119 [PAGE2_TOP_CNTL] = { 120 COMMON_PS8640_REGMAP_CONFIG, 121 .max_register = 0xff, 122 }, 123 [PAGE3_DSI_CNTL1] = { 124 COMMON_PS8640_REGMAP_CONFIG, 125 .max_register = 0xff, 126 }, 127 [PAGE4_MIPI_PHY] = { 128 COMMON_PS8640_REGMAP_CONFIG, 129 .max_register = 0xff, 130 }, 131 [PAGE5_VPLL] = { 132 COMMON_PS8640_REGMAP_CONFIG, 133 .max_register = 0x7f, 134 }, 135 [PAGE6_DSI_CNTL2] = { 136 COMMON_PS8640_REGMAP_CONFIG, 137 .max_register = 0xff, 138 }, 139 [PAGE7_SPI_CNTL] = { 140 COMMON_PS8640_REGMAP_CONFIG, 141 .max_register = 0xff, 142 }, 143 }; 144 145 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) 146 { 147 return container_of(e, struct ps8640, bridge); 148 } 149 150 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) 151 { 152 return container_of(aux, struct ps8640, aux); 153 } 154 155 static bool ps8640_of_panel_on_aux_bus(struct device *dev) 156 { 157 struct device_node *bus, *panel; 158 159 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 160 if (!bus) 161 return false; 162 163 panel = of_get_child_by_name(bus, "panel"); 164 of_node_put(bus); 165 if (!panel) 166 return false; 167 of_node_put(panel); 168 169 return true; 170 } 171 172 static int ps8640_ensure_hpd(struct ps8640 *ps_bridge) 173 { 174 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; 175 struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev; 176 int status; 177 int ret; 178 179 /* 180 * Apparently something about the firmware in the chip signals that 181 * HPD goes high by reporting GPIO9 as high (even though HPD isn't 182 * actually connected to GPIO9). 183 */ 184 ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, 185 status & PS_GPIO9, 20 * 1000, 200 * 1000); 186 187 if (ret < 0) 188 dev_warn(dev, "HPD didn't go high: %d\n", ret); 189 190 return ret; 191 } 192 193 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, 194 struct drm_dp_aux_msg *msg) 195 { 196 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 197 struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; 198 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 199 unsigned int len = msg->size; 200 unsigned int data; 201 unsigned int base; 202 int ret; 203 u8 request = msg->request & 204 ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 205 u8 *buf = msg->buffer; 206 u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0]; 207 u8 i; 208 bool is_native_aux = false; 209 210 if (len > DP_AUX_MAX_PAYLOAD_BYTES) 211 return -EINVAL; 212 213 if (msg->address & ~SWAUX_ADDR_MASK) 214 return -EINVAL; 215 216 switch (request) { 217 case DP_AUX_NATIVE_WRITE: 218 case DP_AUX_NATIVE_READ: 219 is_native_aux = true; 220 fallthrough; 221 case DP_AUX_I2C_WRITE: 222 case DP_AUX_I2C_READ: 223 break; 224 default: 225 return -EINVAL; 226 } 227 228 ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); 229 if (ret) { 230 DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n", 231 ret); 232 return ret; 233 } 234 235 /* Assume it's good */ 236 msg->reply = 0; 237 238 base = PAGE0_SWAUX_ADDR_7_0; 239 addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address; 240 addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8; 241 addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) | 242 (msg->request << 4); 243 addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD : 244 ((len - 1) & SWAUX_LENGTH_MASK); 245 246 regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len, 247 ARRAY_SIZE(addr_len)); 248 249 if (len && (request == DP_AUX_NATIVE_WRITE || 250 request == DP_AUX_I2C_WRITE)) { 251 /* Write to the internal FIFO buffer */ 252 for (i = 0; i < len; i++) { 253 ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]); 254 if (ret) { 255 DRM_DEV_ERROR(dev, 256 "failed to write WDATA: %d\n", 257 ret); 258 return ret; 259 } 260 } 261 } 262 263 regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND); 264 265 /* Zero delay loop because i2c transactions are slow already */ 266 regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data, 267 !(data & SWAUX_SEND), 0, 50 * 1000); 268 269 regmap_read(map, PAGE0_SWAUX_STATUS, &data); 270 if (ret) { 271 DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n", 272 ret); 273 return ret; 274 } 275 276 switch (data & SWAUX_STATUS_MASK) { 277 /* Ignore the DEFER cases as they are already handled in hardware */ 278 case SWAUX_STATUS_NACK: 279 case SWAUX_STATUS_I2C_NACK: 280 /* 281 * The programming guide is not clear about whether a I2C NACK 282 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So 283 * we handle both cases together. 284 */ 285 if (is_native_aux) 286 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 287 else 288 msg->reply |= DP_AUX_I2C_REPLY_NACK; 289 290 fallthrough; 291 case SWAUX_STATUS_ACKM: 292 len = data & SWAUX_M_MASK; 293 break; 294 case SWAUX_STATUS_INVALID: 295 return -EOPNOTSUPP; 296 case SWAUX_STATUS_TIMEOUT: 297 return -ETIMEDOUT; 298 } 299 300 if (len && (request == DP_AUX_NATIVE_READ || 301 request == DP_AUX_I2C_READ)) { 302 /* Read from the internal FIFO buffer */ 303 for (i = 0; i < len; i++) { 304 ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data); 305 if (ret) { 306 DRM_DEV_ERROR(dev, 307 "failed to read RDATA: %d\n", 308 ret); 309 return ret; 310 } 311 312 buf[i] = data; 313 } 314 } 315 316 return len; 317 } 318 319 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, 320 struct drm_dp_aux_msg *msg) 321 { 322 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 323 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 324 int ret; 325 326 pm_runtime_get_sync(dev); 327 ret = ps8640_ensure_hpd(ps_bridge); 328 if (!ret) 329 ret = ps8640_aux_transfer_msg(aux, msg); 330 pm_runtime_mark_last_busy(dev); 331 pm_runtime_put_autosuspend(dev); 332 333 return ret; 334 } 335 336 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, 337 const enum ps8640_vdo_control ctrl) 338 { 339 struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; 340 struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; 341 u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; 342 int ret; 343 344 ret = regmap_bulk_write(map, PAGE3_SET_ADD, 345 vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); 346 347 if (ret < 0) 348 dev_err(dev, "failed to %sable VDO: %d\n", 349 ctrl == ENABLE ? "en" : "dis", ret); 350 } 351 352 static int __maybe_unused ps8640_resume(struct device *dev) 353 { 354 struct ps8640 *ps_bridge = dev_get_drvdata(dev); 355 int ret; 356 357 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), 358 ps_bridge->supplies); 359 if (ret < 0) { 360 dev_err(dev, "cannot enable regulators %d\n", ret); 361 return ret; 362 } 363 364 gpiod_set_value(ps_bridge->gpio_powerdown, 0); 365 gpiod_set_value(ps_bridge->gpio_reset, 1); 366 usleep_range(2000, 2500); 367 gpiod_set_value(ps_bridge->gpio_reset, 0); 368 369 /* 370 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if 371 * this is truly necessary since the MCU will already signal that 372 * things are "good to go" by signaling HPD on "gpio 9". See 373 * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in 374 * case. 375 */ 376 msleep(200); 377 378 return 0; 379 } 380 381 static int __maybe_unused ps8640_suspend(struct device *dev) 382 { 383 struct ps8640 *ps_bridge = dev_get_drvdata(dev); 384 int ret; 385 386 gpiod_set_value(ps_bridge->gpio_reset, 1); 387 gpiod_set_value(ps_bridge->gpio_powerdown, 1); 388 ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), 389 ps_bridge->supplies); 390 if (ret < 0) 391 dev_err(dev, "cannot disable regulators %d\n", ret); 392 393 return ret; 394 } 395 396 static const struct dev_pm_ops ps8640_pm_ops = { 397 SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) 398 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 399 pm_runtime_force_resume) 400 }; 401 402 static void ps8640_pre_enable(struct drm_bridge *bridge) 403 { 404 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 405 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; 406 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; 407 int ret; 408 409 pm_runtime_get_sync(dev); 410 ps8640_ensure_hpd(ps_bridge); 411 412 /* 413 * The Manufacturer Command Set (MCS) is a device dependent interface 414 * intended for factory programming of the display module default 415 * parameters. Once the display module is configured, the MCS shall be 416 * disabled by the manufacturer. Once disabled, all MCS commands are 417 * ignored by the display interface. 418 */ 419 420 ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); 421 if (ret < 0) 422 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); 423 424 /* Switch access edp panel's edid through i2c */ 425 ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); 426 if (ret < 0) 427 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); 428 429 ps8640_bridge_vdo_control(ps_bridge, ENABLE); 430 431 ps_bridge->pre_enabled = true; 432 } 433 434 static void ps8640_post_disable(struct drm_bridge *bridge) 435 { 436 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 437 438 ps_bridge->pre_enabled = false; 439 440 ps8640_bridge_vdo_control(ps_bridge, DISABLE); 441 pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); 442 } 443 444 static int ps8640_bridge_attach(struct drm_bridge *bridge, 445 enum drm_bridge_attach_flags flags) 446 { 447 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 448 struct device *dev = &ps_bridge->page[0]->dev; 449 int ret; 450 451 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 452 return -EINVAL; 453 454 ps_bridge->aux.drm_dev = bridge->dev; 455 ret = drm_dp_aux_register(&ps_bridge->aux); 456 if (ret) { 457 dev_err(dev, "failed to register DP AUX channel: %d\n", ret); 458 return ret; 459 } 460 461 ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS); 462 if (!ps_bridge->link) { 463 dev_err(dev, "failed to create device link"); 464 ret = -EINVAL; 465 goto err_devlink; 466 } 467 468 /* Attach the panel-bridge to the dsi bridge */ 469 ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, 470 &ps_bridge->bridge, flags); 471 if (ret) 472 goto err_bridge_attach; 473 474 return 0; 475 476 err_bridge_attach: 477 device_link_del(ps_bridge->link); 478 err_devlink: 479 drm_dp_aux_unregister(&ps_bridge->aux); 480 481 return ret; 482 } 483 484 static void ps8640_bridge_detach(struct drm_bridge *bridge) 485 { 486 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 487 488 drm_dp_aux_unregister(&ps_bridge->aux); 489 if (ps_bridge->link) 490 device_link_del(ps_bridge->link); 491 } 492 493 static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, 494 struct drm_connector *connector) 495 { 496 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); 497 bool poweroff = !ps_bridge->pre_enabled; 498 struct edid *edid; 499 500 /* 501 * When we end calling get_edid() triggered by an ioctl, i.e 502 * 503 * drm_mode_getconnector (ioctl) 504 * -> drm_helper_probe_single_connector_modes 505 * -> drm_bridge_connector_get_modes 506 * -> ps8640_bridge_get_edid 507 * 508 * We need to make sure that what we need is enabled before reading 509 * EDID, for this chip, we need to do a full poweron, otherwise it will 510 * fail. 511 */ 512 drm_bridge_chain_pre_enable(bridge); 513 514 edid = drm_get_edid(connector, 515 ps_bridge->page[PAGE0_DP_CNTL]->adapter); 516 517 /* 518 * If we call the get_edid() function without having enabled the chip 519 * before, return the chip to its original power state. 520 */ 521 if (poweroff) 522 drm_bridge_chain_post_disable(bridge); 523 524 return edid; 525 } 526 527 static void ps8640_runtime_disable(void *data) 528 { 529 pm_runtime_dont_use_autosuspend(data); 530 pm_runtime_disable(data); 531 } 532 533 static const struct drm_bridge_funcs ps8640_bridge_funcs = { 534 .attach = ps8640_bridge_attach, 535 .detach = ps8640_bridge_detach, 536 .get_edid = ps8640_bridge_get_edid, 537 .post_disable = ps8640_post_disable, 538 .pre_enable = ps8640_pre_enable, 539 }; 540 541 static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge) 542 { 543 struct device_node *in_ep, *dsi_node; 544 struct mipi_dsi_device *dsi; 545 struct mipi_dsi_host *host; 546 const struct mipi_dsi_device_info info = { .type = "ps8640", 547 .channel = 0, 548 .node = NULL, 549 }; 550 551 /* port@0 is ps8640 dsi input port */ 552 in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 553 if (!in_ep) 554 return -ENODEV; 555 556 dsi_node = of_graph_get_remote_port_parent(in_ep); 557 of_node_put(in_ep); 558 if (!dsi_node) 559 return -ENODEV; 560 561 host = of_find_mipi_dsi_host_by_node(dsi_node); 562 of_node_put(dsi_node); 563 if (!host) 564 return -EPROBE_DEFER; 565 566 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 567 if (IS_ERR(dsi)) { 568 dev_err(dev, "failed to create dsi device\n"); 569 return PTR_ERR(dsi); 570 } 571 572 ps_bridge->dsi = dsi; 573 574 dsi->host = host; 575 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 576 MIPI_DSI_MODE_VIDEO_SYNC_PULSE; 577 dsi->format = MIPI_DSI_FMT_RGB888; 578 dsi->lanes = NUM_MIPI_LANES; 579 580 return 0; 581 } 582 583 static int ps8640_bridge_link_panel(struct drm_dp_aux *aux) 584 { 585 struct ps8640 *ps_bridge = aux_to_ps8640(aux); 586 struct device *dev = aux->dev; 587 struct device_node *np = dev->of_node; 588 int ret; 589 590 /* 591 * NOTE about returning -EPROBE_DEFER from this function: if we 592 * return an error (most relevant to -EPROBE_DEFER) it will only 593 * be passed out to ps8640_probe() if it called this directly (AKA the 594 * panel isn't under the "aux-bus" node). That should be fine because 595 * if the panel is under "aux-bus" it's guaranteed to have probed by 596 * the time this function has been called. 597 */ 598 599 /* port@1 is ps8640 output port */ 600 ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); 601 if (IS_ERR(ps_bridge->panel_bridge)) 602 return PTR_ERR(ps_bridge->panel_bridge); 603 604 ret = devm_drm_bridge_add(dev, &ps_bridge->bridge); 605 if (ret) 606 return ret; 607 608 return devm_mipi_dsi_attach(dev, ps_bridge->dsi); 609 } 610 611 static int ps8640_probe(struct i2c_client *client) 612 { 613 struct device *dev = &client->dev; 614 struct ps8640 *ps_bridge; 615 int ret; 616 u32 i; 617 618 ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL); 619 if (!ps_bridge) 620 return -ENOMEM; 621 622 ps_bridge->supplies[0].supply = "vdd33"; 623 ps_bridge->supplies[1].supply = "vdd12"; 624 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies), 625 ps_bridge->supplies); 626 if (ret) 627 return ret; 628 629 ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown", 630 GPIOD_OUT_HIGH); 631 if (IS_ERR(ps_bridge->gpio_powerdown)) 632 return PTR_ERR(ps_bridge->gpio_powerdown); 633 634 /* 635 * Assert the reset to avoid the bridge being initialized prematurely 636 */ 637 ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset", 638 GPIOD_OUT_HIGH); 639 if (IS_ERR(ps_bridge->gpio_reset)) 640 return PTR_ERR(ps_bridge->gpio_reset); 641 642 ps_bridge->bridge.funcs = &ps8640_bridge_funcs; 643 ps_bridge->bridge.of_node = dev->of_node; 644 ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP; 645 646 /* 647 * In the device tree, if panel is listed under aux-bus of the bridge 648 * node, panel driver should be able to retrieve EDID by itself using 649 * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here. 650 */ 651 if (!ps8640_of_panel_on_aux_bus(&client->dev)) 652 ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID; 653 654 /* 655 * Get MIPI DSI resources early. These can return -EPROBE_DEFER so 656 * we want to get them out of the way sooner. 657 */ 658 ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge); 659 if (ret) 660 return ret; 661 662 ps_bridge->page[PAGE0_DP_CNTL] = client; 663 664 ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config); 665 if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL])) 666 return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]); 667 668 for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { 669 ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, 670 client->adapter, 671 client->addr + i); 672 if (IS_ERR(ps_bridge->page[i])) 673 return PTR_ERR(ps_bridge->page[i]); 674 675 ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i], 676 ps8640_regmap_config + i); 677 if (IS_ERR(ps_bridge->regmap[i])) 678 return PTR_ERR(ps_bridge->regmap[i]); 679 } 680 681 i2c_set_clientdata(client, ps_bridge); 682 683 ps_bridge->aux.name = "parade-ps8640-aux"; 684 ps_bridge->aux.dev = dev; 685 ps_bridge->aux.transfer = ps8640_aux_transfer; 686 drm_dp_aux_init(&ps_bridge->aux); 687 688 pm_runtime_enable(dev); 689 /* 690 * Powering on ps8640 takes ~300ms. To avoid wasting time on power 691 * cycling ps8640 too often, set autosuspend_delay to 1000ms to ensure 692 * the bridge wouldn't suspend in between each _aux_transfer_msg() call 693 * during EDID read (~20ms in my experiment) and in between the last 694 * _aux_transfer_msg() call during EDID read and the _pre_enable() call 695 * (~100ms in my experiment). 696 */ 697 pm_runtime_set_autosuspend_delay(dev, 1000); 698 pm_runtime_use_autosuspend(dev); 699 pm_suspend_ignore_children(dev, true); 700 ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); 701 if (ret) 702 return ret; 703 704 ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel); 705 706 /* 707 * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to 708 * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case 709 * the function is allowed to -EPROBE_DEFER. 710 */ 711 if (ret == -ENODEV) 712 return ps8640_bridge_link_panel(&ps_bridge->aux); 713 714 return ret; 715 } 716 717 static const struct of_device_id ps8640_match[] = { 718 { .compatible = "parade,ps8640" }, 719 { } 720 }; 721 MODULE_DEVICE_TABLE(of, ps8640_match); 722 723 static struct i2c_driver ps8640_driver = { 724 .probe_new = ps8640_probe, 725 .driver = { 726 .name = "ps8640", 727 .of_match_table = ps8640_match, 728 .pm = &ps8640_pm_ops, 729 }, 730 }; 731 module_i2c_driver(ps8640_driver); 732 733 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>"); 734 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>"); 735 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>"); 736 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver"); 737 MODULE_LICENSE("GPL v2"); 738