1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * i.MX8 NWL MIPI DSI host driver 4 * 5 * Copyright (C) 2017 NXP 6 * Copyright (C) 2020 Purism SPC 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/irq.h> 13 #include <linux/math64.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/mux/consumer.h> 17 #include <linux/of.h> 18 #include <linux/of_platform.h> 19 #include <linux/phy/phy.h> 20 #include <linux/regmap.h> 21 #include <linux/reset.h> 22 #include <linux/sys_soc.h> 23 #include <linux/time64.h> 24 25 #include <drm/drm_atomic_state_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_mipi_dsi.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_panel.h> 30 #include <drm/drm_print.h> 31 32 #include <video/mipi_display.h> 33 34 #include "nwl-dsi.h" 35 36 #define DRV_NAME "nwl-dsi" 37 38 /* i.MX8 NWL quirks */ 39 /* i.MX8MQ errata E11418 */ 40 #define E11418_HS_MODE_QUIRK BIT(0) 41 42 #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500) 43 44 enum transfer_direction { 45 DSI_PACKET_SEND, 46 DSI_PACKET_RECEIVE, 47 }; 48 49 #define NWL_DSI_ENDPOINT_LCDIF 0 50 #define NWL_DSI_ENDPOINT_DCSS 1 51 52 struct nwl_dsi_transfer { 53 const struct mipi_dsi_msg *msg; 54 struct mipi_dsi_packet packet; 55 struct completion completed; 56 57 int status; /* status of transmission */ 58 enum transfer_direction direction; 59 bool need_bta; 60 u8 cmd; 61 u16 rx_word_count; 62 size_t tx_len; /* in bytes */ 63 size_t rx_len; /* in bytes */ 64 }; 65 66 struct nwl_dsi { 67 struct drm_bridge bridge; 68 struct mipi_dsi_host dsi_host; 69 struct device *dev; 70 struct phy *phy; 71 union phy_configure_opts phy_cfg; 72 unsigned int quirks; 73 74 struct regmap *regmap; 75 int irq; 76 /* 77 * The DSI host controller needs this reset sequence according to NWL: 78 * 1. Deassert pclk reset to get access to DSI regs 79 * 2. Configure DSI Host and DPHY and enable DPHY 80 * 3. Deassert ESC and BYTE resets to allow host TX operations) 81 * 4. Send DSI cmds to configure peripheral (handled by panel drv) 82 * 5. Deassert DPI reset so DPI receives pixels and starts sending 83 * DSI data 84 * 85 * TODO: Since panel_bridges do their DSI setup in enable we 86 * currently have 4. and 5. swapped. 87 */ 88 struct reset_control *rst_byte; 89 struct reset_control *rst_esc; 90 struct reset_control *rst_dpi; 91 struct reset_control *rst_pclk; 92 struct mux_control *mux; 93 94 /* DSI clocks */ 95 struct clk *phy_ref_clk; 96 struct clk *rx_esc_clk; 97 struct clk *tx_esc_clk; 98 struct clk *core_clk; 99 /* 100 * hardware bug: the i.MX8MQ needs this clock on during reset 101 * even when not using LCDIF. 102 */ 103 struct clk *lcdif_clk; 104 105 /* dsi lanes */ 106 u32 lanes; 107 enum mipi_dsi_pixel_format format; 108 struct drm_display_mode mode; 109 unsigned long dsi_mode_flags; 110 int error; 111 112 struct nwl_dsi_transfer *xfer; 113 }; 114 115 static const struct regmap_config nwl_dsi_regmap_config = { 116 .reg_bits = 16, 117 .val_bits = 32, 118 .reg_stride = 4, 119 .max_register = NWL_DSI_IRQ_MASK2, 120 .name = DRV_NAME, 121 }; 122 123 static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge) 124 { 125 return container_of(bridge, struct nwl_dsi, bridge); 126 } 127 128 static int nwl_dsi_clear_error(struct nwl_dsi *dsi) 129 { 130 int ret = dsi->error; 131 132 dsi->error = 0; 133 return ret; 134 } 135 136 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val) 137 { 138 int ret; 139 140 if (dsi->error) 141 return; 142 143 ret = regmap_write(dsi->regmap, reg, val); 144 if (ret < 0) { 145 DRM_DEV_ERROR(dsi->dev, 146 "Failed to write NWL DSI reg 0x%x: %d\n", reg, 147 ret); 148 dsi->error = ret; 149 } 150 } 151 152 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg) 153 { 154 unsigned int val; 155 int ret; 156 157 if (dsi->error) 158 return 0; 159 160 ret = regmap_read(dsi->regmap, reg, &val); 161 if (ret < 0) { 162 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n", 163 reg, ret); 164 dsi->error = ret; 165 } 166 return val; 167 } 168 169 static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format) 170 { 171 switch (format) { 172 case MIPI_DSI_FMT_RGB565: 173 return NWL_DSI_PIXEL_FORMAT_16; 174 case MIPI_DSI_FMT_RGB666: 175 return NWL_DSI_PIXEL_FORMAT_18L; 176 case MIPI_DSI_FMT_RGB666_PACKED: 177 return NWL_DSI_PIXEL_FORMAT_18; 178 case MIPI_DSI_FMT_RGB888: 179 return NWL_DSI_PIXEL_FORMAT_24; 180 default: 181 return -EINVAL; 182 } 183 } 184 185 /* 186 * ps2bc - Picoseconds to byte clock cycles 187 */ 188 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps) 189 { 190 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 191 192 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp, 193 dsi->lanes * 8ULL * NSEC_PER_SEC); 194 } 195 196 /* 197 * ui2bc - UI time periods to byte clock cycles 198 */ 199 static u32 ui2bc(unsigned int ui) 200 { 201 return DIV_ROUND_UP(ui, BITS_PER_BYTE); 202 } 203 204 /* 205 * us2bc - micro seconds to lp clock cycles 206 */ 207 static u32 us2lp(u32 lp_clk_rate, unsigned long us) 208 { 209 return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC); 210 } 211 212 static int nwl_dsi_config_host(struct nwl_dsi *dsi) 213 { 214 u32 cycles; 215 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy; 216 217 if (dsi->lanes < 1 || dsi->lanes > 4) 218 return -EINVAL; 219 220 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes); 221 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1); 222 223 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 224 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01); 225 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01); 226 } else { 227 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00); 228 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00); 229 } 230 231 /* values in byte clock cycles */ 232 cycles = ui2bc(cfg->clk_pre); 233 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); 234 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles); 235 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); 236 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles); 237 cycles += ui2bc(cfg->clk_pre); 238 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); 239 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles); 240 cycles = ps2bc(dsi, cfg->hs_exit); 241 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles); 242 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles); 243 244 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01); 245 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00); 246 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00); 247 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00); 248 /* In LP clock cycles */ 249 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup); 250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles); 251 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles); 252 253 return nwl_dsi_clear_error(dsi); 254 } 255 256 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi) 257 { 258 u32 mode; 259 int color_format; 260 bool burst_mode; 261 int hfront_porch, hback_porch, vfront_porch, vback_porch; 262 int hsync_len, vsync_len; 263 264 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay; 265 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start; 266 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end; 267 268 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay; 269 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start; 270 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end; 271 272 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch); 273 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch); 274 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len); 275 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay); 276 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch); 277 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch); 278 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len); 279 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay); 280 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock); 281 282 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format); 283 if (color_format < 0) { 284 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n", 285 dsi->format); 286 return color_format; 287 } 288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format); 289 290 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT); 291 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format); 292 /* 293 * Adjusting input polarity based on the video mode results in 294 * a black screen so always pick active low: 295 */ 296 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY, 297 NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW); 298 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY, 299 NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW); 300 301 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && 302 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE); 303 304 if (burst_mode) { 305 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE); 306 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256); 307 } else { 308 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ? 309 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES : 310 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS); 311 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode); 312 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 313 dsi->mode.hdisplay); 314 } 315 316 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch); 317 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch); 318 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len); 319 320 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0); 321 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1); 322 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0); 323 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0); 324 325 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay); 326 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1); 327 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch); 328 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch); 329 330 return nwl_dsi_clear_error(dsi); 331 } 332 333 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi) 334 { 335 u32 irq_enable; 336 337 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff); 338 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7); 339 340 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK | 341 NWL_DSI_RX_PKT_HDR_RCVD_MASK | 342 NWL_DSI_TX_FIFO_OVFLW_MASK | 343 NWL_DSI_HS_TX_TIMEOUT_MASK); 344 345 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable); 346 347 return nwl_dsi_clear_error(dsi); 348 } 349 350 static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host, 351 struct mipi_dsi_device *device) 352 { 353 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); 354 struct device *dev = dsi->dev; 355 356 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes, 357 device->format, device->mode_flags); 358 359 if (device->lanes < 1 || device->lanes > 4) 360 return -EINVAL; 361 362 dsi->lanes = device->lanes; 363 dsi->format = device->format; 364 dsi->dsi_mode_flags = device->mode_flags; 365 366 return 0; 367 } 368 369 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status) 370 { 371 struct device *dev = dsi->dev; 372 struct nwl_dsi_transfer *xfer = dsi->xfer; 373 int err; 374 u8 *payload = xfer->msg->rx_buf; 375 u32 val; 376 u16 word_count; 377 u8 channel; 378 u8 data_type; 379 380 xfer->status = 0; 381 382 if (xfer->rx_word_count == 0) { 383 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD)) 384 return false; 385 /* Get the RX header and parse it */ 386 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER); 387 err = nwl_dsi_clear_error(dsi); 388 if (err) 389 xfer->status = err; 390 word_count = NWL_DSI_WC(val); 391 channel = NWL_DSI_RX_VC(val); 392 data_type = NWL_DSI_RX_DT(val); 393 394 if (channel != xfer->msg->channel) { 395 DRM_DEV_ERROR(dev, 396 "[%02X] Channel mismatch (%u != %u)\n", 397 xfer->cmd, channel, xfer->msg->channel); 398 xfer->status = -EINVAL; 399 return true; 400 } 401 402 switch (data_type) { 403 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 404 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 405 if (xfer->msg->rx_len > 1) { 406 /* read second byte */ 407 payload[1] = word_count >> 8; 408 ++xfer->rx_len; 409 } 410 fallthrough; 411 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 412 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 413 if (xfer->msg->rx_len > 0) { 414 /* read first byte */ 415 payload[0] = word_count & 0xff; 416 ++xfer->rx_len; 417 } 418 xfer->status = xfer->rx_len; 419 return true; 420 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 421 word_count &= 0xff; 422 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n", 423 xfer->cmd, word_count); 424 xfer->status = -EPROTO; 425 return true; 426 } 427 428 if (word_count > xfer->msg->rx_len) { 429 DRM_DEV_ERROR(dev, 430 "[%02X] Receive buffer too small: %zu (< %u)\n", 431 xfer->cmd, xfer->msg->rx_len, word_count); 432 xfer->status = -EINVAL; 433 return true; 434 } 435 436 xfer->rx_word_count = word_count; 437 } else { 438 /* Set word_count from previous header read */ 439 word_count = xfer->rx_word_count; 440 } 441 442 /* If RX payload is not yet received, wait for it */ 443 if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)) 444 return false; 445 446 /* Read the RX payload */ 447 while (word_count >= 4) { 448 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); 449 payload[0] = (val >> 0) & 0xff; 450 payload[1] = (val >> 8) & 0xff; 451 payload[2] = (val >> 16) & 0xff; 452 payload[3] = (val >> 24) & 0xff; 453 payload += 4; 454 xfer->rx_len += 4; 455 word_count -= 4; 456 } 457 458 if (word_count > 0) { 459 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); 460 switch (word_count) { 461 case 3: 462 payload[2] = (val >> 16) & 0xff; 463 ++xfer->rx_len; 464 fallthrough; 465 case 2: 466 payload[1] = (val >> 8) & 0xff; 467 ++xfer->rx_len; 468 fallthrough; 469 case 1: 470 payload[0] = (val >> 0) & 0xff; 471 ++xfer->rx_len; 472 break; 473 } 474 } 475 476 xfer->status = xfer->rx_len; 477 err = nwl_dsi_clear_error(dsi); 478 if (err) 479 xfer->status = err; 480 481 return true; 482 } 483 484 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status) 485 { 486 struct nwl_dsi_transfer *xfer = dsi->xfer; 487 bool end_packet = false; 488 489 if (!xfer) 490 return; 491 492 if (xfer->direction == DSI_PACKET_SEND && 493 status & NWL_DSI_TX_PKT_DONE) { 494 xfer->status = xfer->tx_len; 495 end_packet = true; 496 } else if (status & NWL_DSI_DPHY_DIRECTION && 497 ((status & (NWL_DSI_RX_PKT_HDR_RCVD | 498 NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) { 499 end_packet = nwl_dsi_read_packet(dsi, status); 500 } 501 502 if (end_packet) 503 complete(&xfer->completed); 504 } 505 506 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi) 507 { 508 struct nwl_dsi_transfer *xfer = dsi->xfer; 509 struct mipi_dsi_packet *pkt = &xfer->packet; 510 const u8 *payload; 511 size_t length; 512 u16 word_count; 513 u8 hs_mode; 514 u32 val; 515 u32 hs_workaround = 0; 516 517 /* Send the payload, if any */ 518 length = pkt->payload_length; 519 payload = pkt->payload; 520 521 while (length >= 4) { 522 val = *(u32 *)payload; 523 hs_workaround |= !(val & 0xFFFF00); 524 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); 525 payload += 4; 526 length -= 4; 527 } 528 /* Send the rest of the payload */ 529 val = 0; 530 switch (length) { 531 case 3: 532 val |= payload[2] << 16; 533 fallthrough; 534 case 2: 535 val |= payload[1] << 8; 536 hs_workaround |= !(val & 0xFFFF00); 537 fallthrough; 538 case 1: 539 val |= payload[0]; 540 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); 541 break; 542 } 543 xfer->tx_len = pkt->payload_length; 544 545 /* 546 * Send the header 547 * header[0] = Virtual Channel + Data Type 548 * header[1] = Word Count LSB (LP) or first param (SP) 549 * header[2] = Word Count MSB (LP) or second param (SP) 550 */ 551 word_count = pkt->header[1] | (pkt->header[2] << 8); 552 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) { 553 DRM_DEV_DEBUG_DRIVER(dsi->dev, 554 "Using hs mode workaround for cmd 0x%x\n", 555 xfer->cmd); 556 hs_mode = 1; 557 } else { 558 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1; 559 } 560 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) | 561 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) | 562 NWL_DSI_BTA_TX(xfer->need_bta); 563 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val); 564 565 /* Send packet command */ 566 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1); 567 } 568 569 static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host, 570 const struct mipi_dsi_msg *msg) 571 { 572 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); 573 struct nwl_dsi_transfer xfer; 574 ssize_t ret = 0; 575 576 /* Create packet to be sent */ 577 dsi->xfer = &xfer; 578 ret = mipi_dsi_create_packet(&xfer.packet, msg); 579 if (ret < 0) { 580 dsi->xfer = NULL; 581 return ret; 582 } 583 584 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM || 585 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM || 586 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM || 587 msg->type & MIPI_DSI_DCS_READ) && 588 msg->rx_len > 0 && msg->rx_buf) 589 xfer.direction = DSI_PACKET_RECEIVE; 590 else 591 xfer.direction = DSI_PACKET_SEND; 592 593 xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE); 594 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0; 595 xfer.msg = msg; 596 xfer.status = -ETIMEDOUT; 597 xfer.rx_word_count = 0; 598 xfer.rx_len = 0; 599 xfer.cmd = 0x00; 600 if (msg->tx_len > 0) 601 xfer.cmd = ((u8 *)(msg->tx_buf))[0]; 602 init_completion(&xfer.completed); 603 604 ret = clk_prepare_enable(dsi->rx_esc_clk); 605 if (ret < 0) { 606 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n", 607 ret); 608 return ret; 609 } 610 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n", 611 clk_get_rate(dsi->rx_esc_clk)); 612 613 /* Initiate the DSI packet transmision */ 614 nwl_dsi_begin_transmission(dsi); 615 616 if (!wait_for_completion_timeout(&xfer.completed, 617 NWL_DSI_MIPI_FIFO_TIMEOUT)) { 618 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n", 619 xfer.cmd); 620 ret = -ETIMEDOUT; 621 } else { 622 ret = xfer.status; 623 } 624 625 clk_disable_unprepare(dsi->rx_esc_clk); 626 627 return ret; 628 } 629 630 static const struct mipi_dsi_host_ops nwl_dsi_host_ops = { 631 .attach = nwl_dsi_host_attach, 632 .transfer = nwl_dsi_host_transfer, 633 }; 634 635 static irqreturn_t nwl_dsi_irq_handler(int irq, void *data) 636 { 637 u32 irq_status; 638 struct nwl_dsi *dsi = data; 639 640 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS); 641 642 if (irq_status & NWL_DSI_TX_FIFO_OVFLW) 643 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n"); 644 645 if (irq_status & NWL_DSI_HS_TX_TIMEOUT) 646 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n"); 647 648 if (irq_status & NWL_DSI_TX_PKT_DONE || 649 irq_status & NWL_DSI_RX_PKT_HDR_RCVD || 650 irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD) 651 nwl_dsi_finish_transmission(dsi, irq_status); 652 653 return IRQ_HANDLED; 654 } 655 656 static int nwl_dsi_mode_set(struct nwl_dsi *dsi) 657 { 658 struct device *dev = dsi->dev; 659 union phy_configure_opts *phy_cfg = &dsi->phy_cfg; 660 int ret; 661 662 if (!dsi->lanes) { 663 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes); 664 return -EINVAL; 665 } 666 667 ret = phy_init(dsi->phy); 668 if (ret < 0) { 669 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret); 670 return ret; 671 } 672 673 ret = phy_configure(dsi->phy, phy_cfg); 674 if (ret < 0) { 675 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret); 676 goto uninit_phy; 677 } 678 679 ret = clk_prepare_enable(dsi->tx_esc_clk); 680 if (ret < 0) { 681 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n", 682 ret); 683 goto uninit_phy; 684 } 685 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n", 686 clk_get_rate(dsi->tx_esc_clk)); 687 688 ret = nwl_dsi_config_host(dsi); 689 if (ret < 0) { 690 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret); 691 goto disable_clock; 692 } 693 694 ret = nwl_dsi_config_dpi(dsi); 695 if (ret < 0) { 696 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret); 697 goto disable_clock; 698 } 699 700 ret = phy_power_on(dsi->phy); 701 if (ret < 0) { 702 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret); 703 goto disable_clock; 704 } 705 706 ret = nwl_dsi_init_interrupts(dsi); 707 if (ret < 0) 708 goto power_off_phy; 709 710 return ret; 711 712 power_off_phy: 713 phy_power_off(dsi->phy); 714 disable_clock: 715 clk_disable_unprepare(dsi->tx_esc_clk); 716 uninit_phy: 717 phy_exit(dsi->phy); 718 719 return ret; 720 } 721 722 static int nwl_dsi_disable(struct nwl_dsi *dsi) 723 { 724 struct device *dev = dsi->dev; 725 726 DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n"); 727 728 phy_power_off(dsi->phy); 729 phy_exit(dsi->phy); 730 731 /* Disabling the clock before the phy breaks enabling dsi again */ 732 clk_disable_unprepare(dsi->tx_esc_clk); 733 734 return 0; 735 } 736 737 static void 738 nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge, 739 struct drm_bridge_state *old_bridge_state) 740 { 741 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 742 int ret; 743 744 nwl_dsi_disable(dsi); 745 746 ret = reset_control_assert(dsi->rst_dpi); 747 if (ret < 0) { 748 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret); 749 return; 750 } 751 ret = reset_control_assert(dsi->rst_byte); 752 if (ret < 0) { 753 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret); 754 return; 755 } 756 ret = reset_control_assert(dsi->rst_esc); 757 if (ret < 0) { 758 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret); 759 return; 760 } 761 ret = reset_control_assert(dsi->rst_pclk); 762 if (ret < 0) { 763 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret); 764 return; 765 } 766 767 clk_disable_unprepare(dsi->core_clk); 768 clk_disable_unprepare(dsi->lcdif_clk); 769 770 pm_runtime_put(dsi->dev); 771 } 772 773 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi, 774 const struct drm_display_mode *mode, 775 union phy_configure_opts *phy_opts) 776 { 777 unsigned long rate; 778 int ret; 779 780 if (dsi->lanes < 1 || dsi->lanes > 4) 781 return -EINVAL; 782 783 /* 784 * So far the DPHY spec minimal timings work for both mixel 785 * dphy and nwl dsi host 786 */ 787 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000, 788 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes, 789 &phy_opts->mipi_dphy); 790 if (ret < 0) 791 return ret; 792 793 rate = clk_get_rate(dsi->tx_esc_clk); 794 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate); 795 phy_opts->mipi_dphy.lp_clk_rate = rate; 796 797 return 0; 798 } 799 800 static enum drm_mode_status 801 nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge, 802 const struct drm_display_info *info, 803 const struct drm_display_mode *mode) 804 { 805 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 806 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 807 808 if (mode->clock * bpp > 15000000 * dsi->lanes) 809 return MODE_CLOCK_HIGH; 810 811 if (mode->clock * bpp < 80000 * dsi->lanes) 812 return MODE_CLOCK_LOW; 813 814 return MODE_OK; 815 } 816 817 static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge, 818 struct drm_bridge_state *bridge_state, 819 struct drm_crtc_state *crtc_state, 820 struct drm_connector_state *conn_state) 821 { 822 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 823 824 /* At least LCDIF + NWL needs active high sync */ 825 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 826 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 827 828 /* 829 * Do a full modeset if crtc_state->active is changed to be true. 830 * This ensures our ->mode_set() is called to get the DSI controller 831 * and the PHY ready to send DCS commands, when only the connector's 832 * DPMS is brought out of "Off" status. 833 */ 834 if (crtc_state->active_changed && crtc_state->active) 835 crtc_state->mode_changed = true; 836 837 return 0; 838 } 839 840 static void 841 nwl_dsi_bridge_mode_set(struct drm_bridge *bridge, 842 const struct drm_display_mode *mode, 843 const struct drm_display_mode *adjusted_mode) 844 { 845 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 846 struct device *dev = dsi->dev; 847 union phy_configure_opts new_cfg; 848 unsigned long phy_ref_rate; 849 int ret; 850 851 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg); 852 if (ret < 0) 853 return; 854 855 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk); 856 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate); 857 /* Save the new desired phy config */ 858 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg)); 859 860 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode)); 861 drm_mode_debug_printmodeline(adjusted_mode); 862 863 pm_runtime_get_sync(dev); 864 865 if (clk_prepare_enable(dsi->lcdif_clk) < 0) 866 return; 867 if (clk_prepare_enable(dsi->core_clk) < 0) 868 return; 869 870 /* Step 1 from DSI reset-out instructions */ 871 ret = reset_control_deassert(dsi->rst_pclk); 872 if (ret < 0) { 873 DRM_DEV_ERROR(dev, "Failed to deassert PCLK: %d\n", ret); 874 return; 875 } 876 877 /* Step 2 from DSI reset-out instructions */ 878 nwl_dsi_mode_set(dsi); 879 880 /* Step 3 from DSI reset-out instructions */ 881 ret = reset_control_deassert(dsi->rst_esc); 882 if (ret < 0) { 883 DRM_DEV_ERROR(dev, "Failed to deassert ESC: %d\n", ret); 884 return; 885 } 886 ret = reset_control_deassert(dsi->rst_byte); 887 if (ret < 0) { 888 DRM_DEV_ERROR(dev, "Failed to deassert BYTE: %d\n", ret); 889 return; 890 } 891 } 892 893 static void 894 nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 895 struct drm_bridge_state *old_bridge_state) 896 { 897 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 898 int ret; 899 900 /* Step 5 from DSI reset-out instructions */ 901 ret = reset_control_deassert(dsi->rst_dpi); 902 if (ret < 0) 903 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret); 904 } 905 906 static int nwl_dsi_bridge_attach(struct drm_bridge *bridge, 907 enum drm_bridge_attach_flags flags) 908 { 909 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 910 struct drm_bridge *panel_bridge; 911 struct drm_panel *panel; 912 int ret; 913 914 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel, 915 &panel_bridge); 916 if (ret) 917 return ret; 918 919 if (panel) { 920 panel_bridge = drm_panel_bridge_add(panel); 921 if (IS_ERR(panel_bridge)) 922 return PTR_ERR(panel_bridge); 923 } 924 925 if (!panel_bridge) 926 return -EPROBE_DEFER; 927 928 return drm_bridge_attach(bridge->encoder, panel_bridge, bridge, flags); 929 } 930 931 static void nwl_dsi_bridge_detach(struct drm_bridge *bridge) 932 { struct nwl_dsi *dsi = bridge_to_dsi(bridge); 933 934 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0); 935 } 936 937 static u32 *nwl_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 938 struct drm_bridge_state *bridge_state, 939 struct drm_crtc_state *crtc_state, 940 struct drm_connector_state *conn_state, 941 u32 output_fmt, 942 unsigned int *num_input_fmts) 943 { 944 u32 *input_fmts, input_fmt; 945 946 *num_input_fmts = 0; 947 948 switch (output_fmt) { 949 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 950 case MEDIA_BUS_FMT_FIXED: 951 input_fmt = MEDIA_BUS_FMT_RGB888_1X24; 952 break; 953 case MEDIA_BUS_FMT_RGB888_1X24: 954 case MEDIA_BUS_FMT_RGB666_1X18: 955 case MEDIA_BUS_FMT_RGB565_1X16: 956 input_fmt = output_fmt; 957 break; 958 default: 959 return NULL; 960 } 961 962 input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); 963 if (!input_fmts) 964 return NULL; 965 input_fmts[0] = input_fmt; 966 *num_input_fmts = 1; 967 968 return input_fmts; 969 } 970 971 static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = { 972 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 973 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 974 .atomic_reset = drm_atomic_helper_bridge_reset, 975 .atomic_check = nwl_dsi_bridge_atomic_check, 976 .atomic_enable = nwl_dsi_bridge_atomic_enable, 977 .atomic_disable = nwl_dsi_bridge_atomic_disable, 978 .atomic_get_input_bus_fmts = nwl_bridge_atomic_get_input_bus_fmts, 979 .mode_set = nwl_dsi_bridge_mode_set, 980 .mode_valid = nwl_dsi_bridge_mode_valid, 981 .attach = nwl_dsi_bridge_attach, 982 .detach = nwl_dsi_bridge_detach, 983 }; 984 985 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) 986 { 987 struct platform_device *pdev = to_platform_device(dsi->dev); 988 struct clk *clk; 989 void __iomem *base; 990 int ret; 991 992 dsi->phy = devm_phy_get(dsi->dev, "dphy"); 993 if (IS_ERR(dsi->phy)) { 994 ret = PTR_ERR(dsi->phy); 995 if (ret != -EPROBE_DEFER) 996 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret); 997 return ret; 998 } 999 1000 clk = devm_clk_get(dsi->dev, "lcdif"); 1001 if (IS_ERR(clk)) { 1002 ret = PTR_ERR(clk); 1003 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n", 1004 ret); 1005 return ret; 1006 } 1007 dsi->lcdif_clk = clk; 1008 1009 clk = devm_clk_get(dsi->dev, "core"); 1010 if (IS_ERR(clk)) { 1011 ret = PTR_ERR(clk); 1012 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n", 1013 ret); 1014 return ret; 1015 } 1016 dsi->core_clk = clk; 1017 1018 clk = devm_clk_get(dsi->dev, "phy_ref"); 1019 if (IS_ERR(clk)) { 1020 ret = PTR_ERR(clk); 1021 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n", 1022 ret); 1023 return ret; 1024 } 1025 dsi->phy_ref_clk = clk; 1026 1027 clk = devm_clk_get(dsi->dev, "rx_esc"); 1028 if (IS_ERR(clk)) { 1029 ret = PTR_ERR(clk); 1030 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n", 1031 ret); 1032 return ret; 1033 } 1034 dsi->rx_esc_clk = clk; 1035 1036 clk = devm_clk_get(dsi->dev, "tx_esc"); 1037 if (IS_ERR(clk)) { 1038 ret = PTR_ERR(clk); 1039 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n", 1040 ret); 1041 return ret; 1042 } 1043 dsi->tx_esc_clk = clk; 1044 1045 dsi->mux = devm_mux_control_get(dsi->dev, NULL); 1046 if (IS_ERR(dsi->mux)) { 1047 ret = PTR_ERR(dsi->mux); 1048 if (ret != -EPROBE_DEFER) 1049 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret); 1050 return ret; 1051 } 1052 1053 base = devm_platform_ioremap_resource(pdev, 0); 1054 if (IS_ERR(base)) 1055 return PTR_ERR(base); 1056 1057 dsi->regmap = 1058 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config); 1059 if (IS_ERR(dsi->regmap)) { 1060 ret = PTR_ERR(dsi->regmap); 1061 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", 1062 ret); 1063 return ret; 1064 } 1065 1066 dsi->irq = platform_get_irq(pdev, 0); 1067 if (dsi->irq < 0) { 1068 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n", 1069 dsi->irq); 1070 return dsi->irq; 1071 } 1072 1073 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk"); 1074 if (IS_ERR(dsi->rst_pclk)) { 1075 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n", 1076 PTR_ERR(dsi->rst_pclk)); 1077 return PTR_ERR(dsi->rst_pclk); 1078 } 1079 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte"); 1080 if (IS_ERR(dsi->rst_byte)) { 1081 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n", 1082 PTR_ERR(dsi->rst_byte)); 1083 return PTR_ERR(dsi->rst_byte); 1084 } 1085 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc"); 1086 if (IS_ERR(dsi->rst_esc)) { 1087 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n", 1088 PTR_ERR(dsi->rst_esc)); 1089 return PTR_ERR(dsi->rst_esc); 1090 } 1091 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi"); 1092 if (IS_ERR(dsi->rst_dpi)) { 1093 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n", 1094 PTR_ERR(dsi->rst_dpi)); 1095 return PTR_ERR(dsi->rst_dpi); 1096 } 1097 return 0; 1098 } 1099 1100 static int nwl_dsi_select_input(struct nwl_dsi *dsi) 1101 { 1102 struct device_node *remote; 1103 u32 use_dcss = 1; 1104 int ret; 1105 1106 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 1107 NWL_DSI_ENDPOINT_LCDIF); 1108 if (remote) { 1109 use_dcss = 0; 1110 } else { 1111 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 1112 NWL_DSI_ENDPOINT_DCSS); 1113 if (!remote) { 1114 DRM_DEV_ERROR(dsi->dev, 1115 "No valid input endpoint found\n"); 1116 return -EINVAL; 1117 } 1118 } 1119 1120 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n", 1121 (use_dcss) ? "DCSS" : "LCDIF"); 1122 ret = mux_control_try_select(dsi->mux, use_dcss); 1123 if (ret < 0) 1124 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret); 1125 1126 of_node_put(remote); 1127 return ret; 1128 } 1129 1130 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi) 1131 { 1132 int ret; 1133 1134 ret = mux_control_deselect(dsi->mux); 1135 if (ret < 0) 1136 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret); 1137 1138 return ret; 1139 } 1140 1141 static const struct drm_bridge_timings nwl_dsi_timings = { 1142 .input_bus_flags = DRM_BUS_FLAG_DE_LOW, 1143 }; 1144 1145 static const struct of_device_id nwl_dsi_dt_ids[] = { 1146 { .compatible = "fsl,imx8mq-nwl-dsi", }, 1147 { /* sentinel */ } 1148 }; 1149 MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids); 1150 1151 static const struct soc_device_attribute nwl_dsi_quirks_match[] = { 1152 { .soc_id = "i.MX8MQ", .revision = "2.0", 1153 .data = (void *)E11418_HS_MODE_QUIRK }, 1154 { /* sentinel. */ }, 1155 }; 1156 1157 static int nwl_dsi_probe(struct platform_device *pdev) 1158 { 1159 struct device *dev = &pdev->dev; 1160 const struct soc_device_attribute *attr; 1161 struct nwl_dsi *dsi; 1162 int ret; 1163 1164 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1165 if (!dsi) 1166 return -ENOMEM; 1167 1168 dsi->dev = dev; 1169 1170 ret = nwl_dsi_parse_dt(dsi); 1171 if (ret) 1172 return ret; 1173 1174 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0, 1175 dev_name(dev), dsi); 1176 if (ret < 0) { 1177 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq, 1178 ret); 1179 return ret; 1180 } 1181 1182 dsi->dsi_host.ops = &nwl_dsi_host_ops; 1183 dsi->dsi_host.dev = dev; 1184 ret = mipi_dsi_host_register(&dsi->dsi_host); 1185 if (ret) { 1186 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret); 1187 return ret; 1188 } 1189 1190 attr = soc_device_match(nwl_dsi_quirks_match); 1191 if (attr) 1192 dsi->quirks = (uintptr_t)attr->data; 1193 1194 dsi->bridge.driver_private = dsi; 1195 dsi->bridge.funcs = &nwl_dsi_bridge_funcs; 1196 dsi->bridge.of_node = dev->of_node; 1197 dsi->bridge.timings = &nwl_dsi_timings; 1198 1199 dev_set_drvdata(dev, dsi); 1200 pm_runtime_enable(dev); 1201 1202 ret = nwl_dsi_select_input(dsi); 1203 if (ret < 0) { 1204 pm_runtime_disable(dev); 1205 mipi_dsi_host_unregister(&dsi->dsi_host); 1206 return ret; 1207 } 1208 1209 drm_bridge_add(&dsi->bridge); 1210 return 0; 1211 } 1212 1213 static int nwl_dsi_remove(struct platform_device *pdev) 1214 { 1215 struct nwl_dsi *dsi = platform_get_drvdata(pdev); 1216 1217 nwl_dsi_deselect_input(dsi); 1218 mipi_dsi_host_unregister(&dsi->dsi_host); 1219 drm_bridge_remove(&dsi->bridge); 1220 pm_runtime_disable(&pdev->dev); 1221 return 0; 1222 } 1223 1224 static struct platform_driver nwl_dsi_driver = { 1225 .probe = nwl_dsi_probe, 1226 .remove = nwl_dsi_remove, 1227 .driver = { 1228 .of_match_table = nwl_dsi_dt_ids, 1229 .name = DRV_NAME, 1230 }, 1231 }; 1232 1233 module_platform_driver(nwl_dsi_driver); 1234 1235 MODULE_AUTHOR("NXP Semiconductor"); 1236 MODULE_AUTHOR("Purism SPC"); 1237 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver"); 1238 MODULE_LICENSE("GPL"); /* GPLv2 or later */ 1239