1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 BayLibre, SAS 4 * Author: Phong LE <ple@baylibre.com> 5 * Copyright (C) 2018-2019, Artem Mygaiev 6 * Copyright (C) 2017, Fresco Logic, Incorporated. 7 * 8 */ 9 10 #include <linux/media-bus-format.h> 11 #include <linux/module.h> 12 #include <linux/device.h> 13 #include <linux/interrupt.h> 14 #include <linux/i2c.h> 15 #include <linux/bitfield.h> 16 #include <linux/property.h> 17 #include <linux/regmap.h> 18 #include <linux/of_graph.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/regulator/consumer.h> 22 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_edid.h> 27 #include <drm/drm_modes.h> 28 #include <drm/drm_print.h> 29 #include <drm/drm_probe_helper.h> 30 31 #include <sound/hdmi-codec.h> 32 33 #define IT66121_VENDOR_ID0_REG 0x00 34 #define IT66121_VENDOR_ID1_REG 0x01 35 #define IT66121_DEVICE_ID0_REG 0x02 36 #define IT66121_DEVICE_ID1_REG 0x03 37 38 #define IT66121_REVISION_MASK GENMASK(7, 4) 39 #define IT66121_DEVICE_ID1_MASK GENMASK(3, 0) 40 41 #define IT66121_MASTER_SEL_REG 0x10 42 #define IT66121_MASTER_SEL_HOST BIT(0) 43 44 #define IT66121_AFE_DRV_REG 0x61 45 #define IT66121_AFE_DRV_RST BIT(4) 46 #define IT66121_AFE_DRV_PWD BIT(5) 47 48 #define IT66121_INPUT_MODE_REG 0x70 49 #define IT66121_INPUT_MODE_RGB (0 << 6) 50 #define IT66121_INPUT_MODE_YUV422 BIT(6) 51 #define IT66121_INPUT_MODE_YUV444 (2 << 6) 52 #define IT66121_INPUT_MODE_CCIR656 BIT(4) 53 #define IT66121_INPUT_MODE_SYNCEMB BIT(3) 54 #define IT66121_INPUT_MODE_DDR BIT(2) 55 56 #define IT66121_INPUT_CSC_REG 0x72 57 #define IT66121_INPUT_CSC_ENDITHER BIT(7) 58 #define IT66121_INPUT_CSC_ENUDFILTER BIT(6) 59 #define IT66121_INPUT_CSC_DNFREE_GO BIT(5) 60 #define IT66121_INPUT_CSC_RGB_TO_YUV 0x02 61 #define IT66121_INPUT_CSC_YUV_TO_RGB 0x03 62 #define IT66121_INPUT_CSC_NO_CONV 0x00 63 64 #define IT66121_AFE_XP_REG 0x62 65 #define IT66121_AFE_XP_GAINBIT BIT(7) 66 #define IT66121_AFE_XP_PWDPLL BIT(6) 67 #define IT66121_AFE_XP_ENI BIT(5) 68 #define IT66121_AFE_XP_ENO BIT(4) 69 #define IT66121_AFE_XP_RESETB BIT(3) 70 #define IT66121_AFE_XP_PWDI BIT(2) 71 #define IT6610_AFE_XP_BYPASS BIT(0) 72 73 #define IT66121_AFE_IP_REG 0x64 74 #define IT66121_AFE_IP_GAINBIT BIT(7) 75 #define IT66121_AFE_IP_PWDPLL BIT(6) 76 #define IT66121_AFE_IP_CKSEL_05 (0 << 4) 77 #define IT66121_AFE_IP_CKSEL_1 BIT(4) 78 #define IT66121_AFE_IP_CKSEL_2 (2 << 4) 79 #define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4) 80 #define IT66121_AFE_IP_ER0 BIT(3) 81 #define IT66121_AFE_IP_RESETB BIT(2) 82 #define IT66121_AFE_IP_ENC BIT(1) 83 #define IT66121_AFE_IP_EC1 BIT(0) 84 85 #define IT66121_AFE_XP_EC1_REG 0x68 86 #define IT66121_AFE_XP_EC1_LOWCLK BIT(4) 87 88 #define IT66121_SW_RST_REG 0x04 89 #define IT66121_SW_RST_REF BIT(5) 90 #define IT66121_SW_RST_AREF BIT(4) 91 #define IT66121_SW_RST_VID BIT(3) 92 #define IT66121_SW_RST_AUD BIT(2) 93 #define IT66121_SW_RST_HDCP BIT(0) 94 95 #define IT66121_DDC_COMMAND_REG 0x15 96 #define IT66121_DDC_COMMAND_BURST_READ 0x0 97 #define IT66121_DDC_COMMAND_EDID_READ 0x3 98 #define IT66121_DDC_COMMAND_FIFO_CLR 0x9 99 #define IT66121_DDC_COMMAND_SCL_PULSE 0xA 100 #define IT66121_DDC_COMMAND_ABORT 0xF 101 102 #define IT66121_HDCP_REG 0x20 103 #define IT66121_HDCP_CPDESIRED BIT(0) 104 #define IT66121_HDCP_EN1P1FEAT BIT(1) 105 106 #define IT66121_INT_STATUS1_REG 0x06 107 #define IT66121_INT_STATUS1_AUD_OVF BIT(7) 108 #define IT66121_INT_STATUS1_DDC_NOACK BIT(5) 109 #define IT66121_INT_STATUS1_DDC_FIFOERR BIT(4) 110 #define IT66121_INT_STATUS1_DDC_BUSHANG BIT(2) 111 #define IT66121_INT_STATUS1_RX_SENS_STATUS BIT(1) 112 #define IT66121_INT_STATUS1_HPD_STATUS BIT(0) 113 114 #define IT66121_DDC_HEADER_REG 0x11 115 #define IT66121_DDC_HEADER_HDCP 0x74 116 #define IT66121_DDC_HEADER_EDID 0xA0 117 118 #define IT66121_DDC_OFFSET_REG 0x12 119 #define IT66121_DDC_BYTE_REG 0x13 120 #define IT66121_DDC_SEGMENT_REG 0x14 121 #define IT66121_DDC_RD_FIFO_REG 0x17 122 123 #define IT66121_CLK_BANK_REG 0x0F 124 #define IT66121_CLK_BANK_PWROFF_RCLK BIT(6) 125 #define IT66121_CLK_BANK_PWROFF_ACLK BIT(5) 126 #define IT66121_CLK_BANK_PWROFF_TXCLK BIT(4) 127 #define IT66121_CLK_BANK_PWROFF_CRCLK BIT(3) 128 #define IT66121_CLK_BANK_0 0 129 #define IT66121_CLK_BANK_1 1 130 131 #define IT66121_INT_REG 0x05 132 #define IT66121_INT_ACTIVE_HIGH BIT(7) 133 #define IT66121_INT_OPEN_DRAIN BIT(6) 134 #define IT66121_INT_TX_CLK_OFF BIT(0) 135 136 #define IT66121_INT_MASK1_REG 0x09 137 #define IT66121_INT_MASK1_AUD_OVF BIT(7) 138 #define IT66121_INT_MASK1_DDC_NOACK BIT(5) 139 #define IT66121_INT_MASK1_DDC_FIFOERR BIT(4) 140 #define IT66121_INT_MASK1_DDC_BUSHANG BIT(2) 141 #define IT66121_INT_MASK1_RX_SENS BIT(1) 142 #define IT66121_INT_MASK1_HPD BIT(0) 143 144 #define IT66121_INT_CLR1_REG 0x0C 145 #define IT66121_INT_CLR1_PKTACP BIT(7) 146 #define IT66121_INT_CLR1_PKTNULL BIT(6) 147 #define IT66121_INT_CLR1_PKTGEN BIT(5) 148 #define IT66121_INT_CLR1_KSVLISTCHK BIT(4) 149 #define IT66121_INT_CLR1_AUTHDONE BIT(3) 150 #define IT66121_INT_CLR1_AUTHFAIL BIT(2) 151 #define IT66121_INT_CLR1_RX_SENS BIT(1) 152 #define IT66121_INT_CLR1_HPD BIT(0) 153 154 #define IT66121_AV_MUTE_REG 0xC1 155 #define IT66121_AV_MUTE_ON BIT(0) 156 #define IT66121_AV_MUTE_BLUESCR BIT(1) 157 158 #define IT66121_PKT_CTS_CTRL_REG 0xC5 159 #define IT66121_PKT_CTS_CTRL_SEL BIT(1) 160 161 #define IT66121_PKT_GEN_CTRL_REG 0xC6 162 #define IT66121_PKT_GEN_CTRL_ON BIT(0) 163 #define IT66121_PKT_GEN_CTRL_RPT BIT(1) 164 165 #define IT66121_AVIINFO_DB1_REG 0x158 166 #define IT66121_AVIINFO_DB2_REG 0x159 167 #define IT66121_AVIINFO_DB3_REG 0x15A 168 #define IT66121_AVIINFO_DB4_REG 0x15B 169 #define IT66121_AVIINFO_DB5_REG 0x15C 170 #define IT66121_AVIINFO_CSUM_REG 0x15D 171 #define IT66121_AVIINFO_DB6_REG 0x15E 172 #define IT66121_AVIINFO_DB7_REG 0x15F 173 #define IT66121_AVIINFO_DB8_REG 0x160 174 #define IT66121_AVIINFO_DB9_REG 0x161 175 #define IT66121_AVIINFO_DB10_REG 0x162 176 #define IT66121_AVIINFO_DB11_REG 0x163 177 #define IT66121_AVIINFO_DB12_REG 0x164 178 #define IT66121_AVIINFO_DB13_REG 0x165 179 180 #define IT66121_AVI_INFO_PKT_REG 0xCD 181 #define IT66121_AVI_INFO_PKT_ON BIT(0) 182 #define IT66121_AVI_INFO_PKT_RPT BIT(1) 183 184 #define IT66121_HDMI_MODE_REG 0xC0 185 #define IT66121_HDMI_MODE_HDMI BIT(0) 186 187 #define IT66121_SYS_STATUS_REG 0x0E 188 #define IT66121_SYS_STATUS_ACTIVE_IRQ BIT(7) 189 #define IT66121_SYS_STATUS_HPDETECT BIT(6) 190 #define IT66121_SYS_STATUS_SENDECTECT BIT(5) 191 #define IT66121_SYS_STATUS_VID_STABLE BIT(4) 192 #define IT66121_SYS_STATUS_AUD_CTS_CLR BIT(1) 193 #define IT66121_SYS_STATUS_CLEAR_IRQ BIT(0) 194 195 #define IT66121_DDC_STATUS_REG 0x16 196 #define IT66121_DDC_STATUS_TX_DONE BIT(7) 197 #define IT66121_DDC_STATUS_ACTIVE BIT(6) 198 #define IT66121_DDC_STATUS_NOACK BIT(5) 199 #define IT66121_DDC_STATUS_WAIT_BUS BIT(4) 200 #define IT66121_DDC_STATUS_ARBI_LOSE BIT(3) 201 #define IT66121_DDC_STATUS_FIFO_FULL BIT(2) 202 #define IT66121_DDC_STATUS_FIFO_EMPTY BIT(1) 203 #define IT66121_DDC_STATUS_FIFO_VALID BIT(0) 204 205 #define IT66121_EDID_SLEEP_US 20000 206 #define IT66121_EDID_TIMEOUT_US 200000 207 #define IT66121_EDID_FIFO_SIZE 32 208 209 #define IT66121_CLK_CTRL0_REG 0x58 210 #define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING BIT(4) 211 #define IT66121_CLK_CTRL0_EXT_MCLK_MASK GENMASK(3, 2) 212 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS (0 << 2) 213 #define IT66121_CLK_CTRL0_EXT_MCLK_256FS BIT(2) 214 #define IT66121_CLK_CTRL0_EXT_MCLK_512FS (2 << 2) 215 #define IT66121_CLK_CTRL0_EXT_MCLK_1024FS (3 << 2) 216 #define IT66121_CLK_CTRL0_AUTO_IPCLK BIT(0) 217 #define IT66121_CLK_STATUS1_REG 0x5E 218 #define IT66121_CLK_STATUS2_REG 0x5F 219 220 #define IT66121_AUD_CTRL0_REG 0xE0 221 #define IT66121_AUD_SWL (3 << 6) 222 #define IT66121_AUD_16BIT (0 << 6) 223 #define IT66121_AUD_18BIT BIT(6) 224 #define IT66121_AUD_20BIT (2 << 6) 225 #define IT66121_AUD_24BIT (3 << 6) 226 #define IT66121_AUD_SPDIFTC BIT(5) 227 #define IT66121_AUD_SPDIF BIT(4) 228 #define IT66121_AUD_I2S (0 << 4) 229 #define IT66121_AUD_EN_I2S3 BIT(3) 230 #define IT66121_AUD_EN_I2S2 BIT(2) 231 #define IT66121_AUD_EN_I2S1 BIT(1) 232 #define IT66121_AUD_EN_I2S0 BIT(0) 233 #define IT66121_AUD_CTRL0_AUD_SEL BIT(4) 234 235 #define IT66121_AUD_CTRL1_REG 0xE1 236 #define IT66121_AUD_FIFOMAP_REG 0xE2 237 #define IT66121_AUD_CTRL3_REG 0xE3 238 #define IT66121_AUD_SRCVALID_FLAT_REG 0xE4 239 #define IT66121_AUD_FLAT_SRC0 BIT(4) 240 #define IT66121_AUD_FLAT_SRC1 BIT(5) 241 #define IT66121_AUD_FLAT_SRC2 BIT(6) 242 #define IT66121_AUD_FLAT_SRC3 BIT(7) 243 #define IT66121_AUD_HDAUDIO_REG 0xE5 244 245 #define IT66121_AUD_PKT_CTS0_REG 0x130 246 #define IT66121_AUD_PKT_CTS1_REG 0x131 247 #define IT66121_AUD_PKT_CTS2_REG 0x132 248 #define IT66121_AUD_PKT_N0_REG 0x133 249 #define IT66121_AUD_PKT_N1_REG 0x134 250 #define IT66121_AUD_PKT_N2_REG 0x135 251 252 #define IT66121_AUD_CHST_MODE_REG 0x191 253 #define IT66121_AUD_CHST_CAT_REG 0x192 254 #define IT66121_AUD_CHST_SRCNUM_REG 0x193 255 #define IT66121_AUD_CHST_CHTNUM_REG 0x194 256 #define IT66121_AUD_CHST_CA_FS_REG 0x198 257 #define IT66121_AUD_CHST_OFS_WL_REG 0x199 258 259 #define IT66121_AUD_PKT_CTS_CNT0_REG 0x1A0 260 #define IT66121_AUD_PKT_CTS_CNT1_REG 0x1A1 261 #define IT66121_AUD_PKT_CTS_CNT2_REG 0x1A2 262 263 #define IT66121_AUD_FS_22P05K 0x4 264 #define IT66121_AUD_FS_44P1K 0x0 265 #define IT66121_AUD_FS_88P2K 0x8 266 #define IT66121_AUD_FS_176P4K 0xC 267 #define IT66121_AUD_FS_24K 0x6 268 #define IT66121_AUD_FS_48K 0x2 269 #define IT66121_AUD_FS_96K 0xA 270 #define IT66121_AUD_FS_192K 0xE 271 #define IT66121_AUD_FS_768K 0x9 272 #define IT66121_AUD_FS_32K 0x3 273 #define IT66121_AUD_FS_OTHER 0x1 274 275 #define IT66121_AUD_SWL_21BIT 0xD 276 #define IT66121_AUD_SWL_24BIT 0xB 277 #define IT66121_AUD_SWL_23BIT 0x9 278 #define IT66121_AUD_SWL_22BIT 0x5 279 #define IT66121_AUD_SWL_20BIT 0x3 280 #define IT66121_AUD_SWL_17BIT 0xC 281 #define IT66121_AUD_SWL_19BIT 0x8 282 #define IT66121_AUD_SWL_18BIT 0x4 283 #define IT66121_AUD_SWL_16BIT 0x2 284 #define IT66121_AUD_SWL_NOT_INDICATED 0x0 285 286 #define IT66121_AFE_CLK_HIGH 80000 /* Khz */ 287 288 enum chip_id { 289 ID_IT6610, 290 ID_IT66121, 291 }; 292 293 struct it66121_chip_info { 294 enum chip_id id; 295 u16 vid, pid; 296 }; 297 298 struct it66121_ctx { 299 struct regmap *regmap; 300 struct drm_bridge bridge; 301 struct drm_bridge *next_bridge; 302 struct drm_connector *connector; 303 struct device *dev; 304 struct gpio_desc *gpio_reset; 305 struct i2c_client *client; 306 u32 bus_width; 307 struct mutex lock; /* Protects fields below and device registers */ 308 struct hdmi_avi_infoframe hdmi_avi_infoframe; 309 struct { 310 struct platform_device *pdev; 311 u8 ch_enable; 312 u8 fs; 313 u8 swl; 314 bool auto_cts; 315 } audio; 316 const struct it66121_chip_info *info; 317 }; 318 319 static const struct regmap_range_cfg it66121_regmap_banks[] = { 320 { 321 .name = "it66121", 322 .range_min = 0x00, 323 .range_max = 0x1FF, 324 .selector_reg = IT66121_CLK_BANK_REG, 325 .selector_mask = 0x1, 326 .selector_shift = 0, 327 .window_start = 0x00, 328 .window_len = 0x100, 329 }, 330 }; 331 332 static const struct regmap_config it66121_regmap_config = { 333 .val_bits = 8, 334 .reg_bits = 8, 335 .max_register = 0x1FF, 336 .ranges = it66121_regmap_banks, 337 .num_ranges = ARRAY_SIZE(it66121_regmap_banks), 338 }; 339 340 static void it66121_hw_reset(struct it66121_ctx *ctx) 341 { 342 gpiod_set_value(ctx->gpio_reset, 1); 343 msleep(20); 344 gpiod_set_value(ctx->gpio_reset, 0); 345 } 346 347 static inline int it66121_preamble_ddc(struct it66121_ctx *ctx) 348 { 349 return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST); 350 } 351 352 static inline int it66121_fire_afe(struct it66121_ctx *ctx) 353 { 354 return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0); 355 } 356 357 /* TOFIX: Handle YCbCr Input & Output */ 358 static int it66121_configure_input(struct it66121_ctx *ctx) 359 { 360 int ret; 361 u8 mode = IT66121_INPUT_MODE_RGB; 362 363 if (ctx->bus_width == 12) 364 mode |= IT66121_INPUT_MODE_DDR; 365 366 ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode); 367 if (ret) 368 return ret; 369 370 return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV); 371 } 372 373 /** 374 * it66121_configure_afe() - Configure the analog front end 375 * @ctx: it66121_ctx object 376 * @mode: mode to configure 377 * 378 * RETURNS: 379 * zero if success, a negative error code otherwise. 380 */ 381 static int it66121_configure_afe(struct it66121_ctx *ctx, 382 const struct drm_display_mode *mode) 383 { 384 int ret; 385 386 ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 387 IT66121_AFE_DRV_RST); 388 if (ret) 389 return ret; 390 391 if (mode->clock > IT66121_AFE_CLK_HIGH) { 392 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 393 IT66121_AFE_XP_GAINBIT | 394 IT66121_AFE_XP_ENO, 395 IT66121_AFE_XP_GAINBIT); 396 if (ret) 397 return ret; 398 399 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 400 IT66121_AFE_IP_GAINBIT | 401 IT66121_AFE_IP_ER0, 402 IT66121_AFE_IP_GAINBIT); 403 if (ret) 404 return ret; 405 406 if (ctx->info->id == ID_IT66121) { 407 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 408 IT66121_AFE_IP_EC1, 0); 409 if (ret) 410 return ret; 411 412 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 413 IT66121_AFE_XP_EC1_LOWCLK, 0x80); 414 if (ret) 415 return ret; 416 } 417 } else { 418 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 419 IT66121_AFE_XP_GAINBIT | 420 IT66121_AFE_XP_ENO, 421 IT66121_AFE_XP_ENO); 422 if (ret) 423 return ret; 424 425 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 426 IT66121_AFE_IP_GAINBIT | 427 IT66121_AFE_IP_ER0, 428 IT66121_AFE_IP_ER0); 429 if (ret) 430 return ret; 431 432 if (ctx->info->id == ID_IT66121) { 433 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 434 IT66121_AFE_IP_EC1, 435 IT66121_AFE_IP_EC1); 436 if (ret) 437 return ret; 438 439 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 440 IT66121_AFE_XP_EC1_LOWCLK, 441 IT66121_AFE_XP_EC1_LOWCLK); 442 if (ret) 443 return ret; 444 } 445 } 446 447 /* Clear reset flags */ 448 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 449 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0); 450 if (ret) 451 return ret; 452 453 if (ctx->info->id == ID_IT6610) { 454 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 455 IT6610_AFE_XP_BYPASS, 456 IT6610_AFE_XP_BYPASS); 457 if (ret) 458 return ret; 459 } 460 461 return it66121_fire_afe(ctx); 462 } 463 464 static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx) 465 { 466 int ret, val; 467 u32 error = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS | 468 IT66121_DDC_STATUS_ARBI_LOSE; 469 u32 done = IT66121_DDC_STATUS_TX_DONE; 470 471 ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, 472 val & (error | done), IT66121_EDID_SLEEP_US, 473 IT66121_EDID_TIMEOUT_US); 474 if (ret) 475 return ret; 476 477 if (val & error) 478 return -EAGAIN; 479 480 return 0; 481 } 482 483 static int it66121_abort_ddc_ops(struct it66121_ctx *ctx) 484 { 485 int ret; 486 unsigned int swreset, cpdesire; 487 488 ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset); 489 if (ret) 490 return ret; 491 492 ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire); 493 if (ret) 494 return ret; 495 496 ret = regmap_write(ctx->regmap, IT66121_HDCP_REG, 497 cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF)); 498 if (ret) 499 return ret; 500 501 ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG, 502 (swreset | IT66121_SW_RST_HDCP)); 503 if (ret) 504 return ret; 505 506 ret = it66121_preamble_ddc(ctx); 507 if (ret) 508 return ret; 509 510 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 511 IT66121_DDC_COMMAND_ABORT); 512 if (ret) 513 return ret; 514 515 return it66121_wait_ddc_ready(ctx); 516 } 517 518 static int it66121_get_edid_block(void *context, u8 *buf, 519 unsigned int block, size_t len) 520 { 521 struct it66121_ctx *ctx = context; 522 int remain = len; 523 int offset = 0; 524 int ret, cnt; 525 526 offset = (block % 2) * len; 527 block = block / 2; 528 529 while (remain > 0) { 530 cnt = (remain > IT66121_EDID_FIFO_SIZE) ? 531 IT66121_EDID_FIFO_SIZE : remain; 532 533 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 534 IT66121_DDC_COMMAND_FIFO_CLR); 535 if (ret) 536 return ret; 537 538 ret = it66121_wait_ddc_ready(ctx); 539 if (ret) 540 return ret; 541 542 ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset); 543 if (ret) 544 return ret; 545 546 ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt); 547 if (ret) 548 return ret; 549 550 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block); 551 if (ret) 552 return ret; 553 554 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 555 IT66121_DDC_COMMAND_EDID_READ); 556 if (ret) 557 return ret; 558 559 offset += cnt; 560 remain -= cnt; 561 562 ret = it66121_wait_ddc_ready(ctx); 563 if (ret) { 564 it66121_abort_ddc_ops(ctx); 565 return ret; 566 } 567 568 ret = regmap_noinc_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, 569 buf, cnt); 570 if (ret) 571 return ret; 572 573 buf += cnt; 574 } 575 576 return 0; 577 } 578 579 static bool it66121_is_hpd_detect(struct it66121_ctx *ctx) 580 { 581 int val; 582 583 if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val)) 584 return false; 585 586 return val & IT66121_SYS_STATUS_HPDETECT; 587 } 588 589 static int it66121_bridge_attach(struct drm_bridge *bridge, 590 enum drm_bridge_attach_flags flags) 591 { 592 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 593 int ret; 594 595 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 596 return -EINVAL; 597 598 ret = drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags); 599 if (ret) 600 return ret; 601 602 if (ctx->info->id == ID_IT66121) { 603 ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 604 IT66121_CLK_BANK_PWROFF_RCLK, 0); 605 if (ret) 606 return ret; 607 } 608 609 ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG, 610 IT66121_INT_TX_CLK_OFF, 0); 611 if (ret) 612 return ret; 613 614 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 615 IT66121_AFE_DRV_PWD, 0); 616 if (ret) 617 return ret; 618 619 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 620 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0); 621 if (ret) 622 return ret; 623 624 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 625 IT66121_AFE_IP_PWDPLL, 0); 626 if (ret) 627 return ret; 628 629 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 630 IT66121_AFE_DRV_RST, 0); 631 if (ret) 632 return ret; 633 634 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 635 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB); 636 if (ret) 637 return ret; 638 639 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 640 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB); 641 if (ret) 642 return ret; 643 644 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 645 IT66121_SW_RST_REF, 646 IT66121_SW_RST_REF); 647 if (ret) 648 return ret; 649 650 /* Per programming manual, sleep here for bridge to settle */ 651 msleep(50); 652 653 return 0; 654 } 655 656 static int it66121_set_mute(struct it66121_ctx *ctx, bool mute) 657 { 658 int ret; 659 unsigned int val = 0; 660 661 if (mute) 662 val = IT66121_AV_MUTE_ON; 663 664 ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val); 665 if (ret) 666 return ret; 667 668 return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG, 669 IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT); 670 } 671 672 #define MAX_OUTPUT_SEL_FORMATS 1 673 674 static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 675 struct drm_bridge_state *bridge_state, 676 struct drm_crtc_state *crtc_state, 677 struct drm_connector_state *conn_state, 678 unsigned int *num_output_fmts) 679 { 680 u32 *output_fmts; 681 682 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 683 GFP_KERNEL); 684 if (!output_fmts) 685 return NULL; 686 687 /* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */ 688 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 689 *num_output_fmts = 1; 690 691 return output_fmts; 692 } 693 694 #define MAX_INPUT_SEL_FORMATS 1 695 696 static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 697 struct drm_bridge_state *bridge_state, 698 struct drm_crtc_state *crtc_state, 699 struct drm_connector_state *conn_state, 700 u32 output_fmt, 701 unsigned int *num_input_fmts) 702 { 703 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 704 u32 *input_fmts; 705 706 *num_input_fmts = 0; 707 708 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 709 GFP_KERNEL); 710 if (!input_fmts) 711 return NULL; 712 713 if (ctx->bus_width == 12) 714 /* IT66121FN Datasheet specifies Little-Endian ordering */ 715 input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE; 716 else 717 /* TOFIX support more input bus formats in 24bit width */ 718 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 719 *num_input_fmts = 1; 720 721 return input_fmts; 722 } 723 724 static void it66121_bridge_enable(struct drm_bridge *bridge, 725 struct drm_bridge_state *bridge_state) 726 { 727 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 728 struct drm_atomic_state *state = bridge_state->base.state; 729 730 ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 731 732 it66121_set_mute(ctx, false); 733 } 734 735 static void it66121_bridge_disable(struct drm_bridge *bridge, 736 struct drm_bridge_state *bridge_state) 737 { 738 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 739 740 it66121_set_mute(ctx, true); 741 742 ctx->connector = NULL; 743 } 744 745 static int it66121_bridge_check(struct drm_bridge *bridge, 746 struct drm_bridge_state *bridge_state, 747 struct drm_crtc_state *crtc_state, 748 struct drm_connector_state *conn_state) 749 { 750 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 751 752 if (ctx->info->id == ID_IT6610) { 753 /* The IT6610 only supports these settings */ 754 bridge_state->input_bus_cfg.flags |= DRM_BUS_FLAG_DE_HIGH | 755 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE; 756 bridge_state->input_bus_cfg.flags &= 757 ~DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE; 758 } 759 760 return 0; 761 } 762 763 static 764 void it66121_bridge_mode_set(struct drm_bridge *bridge, 765 const struct drm_display_mode *mode, 766 const struct drm_display_mode *adjusted_mode) 767 { 768 u8 buf[HDMI_INFOFRAME_SIZE(AVI)]; 769 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 770 int ret; 771 772 mutex_lock(&ctx->lock); 773 774 hdmi_avi_infoframe_init(&ctx->hdmi_avi_infoframe); 775 776 ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector, 777 adjusted_mode); 778 if (ret) { 779 DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret); 780 goto unlock; 781 } 782 783 ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf)); 784 if (ret < 0) { 785 DRM_ERROR("Failed to pack infoframe: %d\n", ret); 786 goto unlock; 787 } 788 789 /* Write new AVI infoframe packet */ 790 ret = regmap_bulk_write(ctx->regmap, IT66121_AVIINFO_DB1_REG, 791 &buf[HDMI_INFOFRAME_HEADER_SIZE], 792 HDMI_AVI_INFOFRAME_SIZE); 793 if (ret) 794 goto unlock; 795 796 if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3])) 797 goto unlock; 798 799 /* Enable AVI infoframe */ 800 if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG, 801 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT)) 802 goto unlock; 803 804 /* Set TX mode to HDMI */ 805 if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI)) 806 goto unlock; 807 808 if (ctx->info->id == ID_IT66121 && 809 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 810 IT66121_CLK_BANK_PWROFF_TXCLK, 811 IT66121_CLK_BANK_PWROFF_TXCLK)) { 812 goto unlock; 813 } 814 815 if (it66121_configure_input(ctx)) 816 goto unlock; 817 818 if (it66121_configure_afe(ctx, adjusted_mode)) 819 goto unlock; 820 821 if (ctx->info->id == ID_IT66121 && 822 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 823 IT66121_CLK_BANK_PWROFF_TXCLK, 0)) { 824 goto unlock; 825 } 826 827 unlock: 828 mutex_unlock(&ctx->lock); 829 } 830 831 static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge, 832 const struct drm_display_info *info, 833 const struct drm_display_mode *mode) 834 { 835 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 836 unsigned long max_clock; 837 838 max_clock = (ctx->bus_width == 12) ? 74250 : 148500; 839 840 if (mode->clock > max_clock) 841 return MODE_CLOCK_HIGH; 842 843 if (mode->clock < 25000) 844 return MODE_CLOCK_LOW; 845 846 return MODE_OK; 847 } 848 849 static enum drm_connector_status it66121_bridge_detect(struct drm_bridge *bridge) 850 { 851 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 852 853 return it66121_is_hpd_detect(ctx) ? connector_status_connected 854 : connector_status_disconnected; 855 } 856 857 static void it66121_bridge_hpd_enable(struct drm_bridge *bridge) 858 { 859 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 860 int ret; 861 862 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0); 863 if (ret) 864 dev_err(ctx->dev, "failed to enable HPD IRQ\n"); 865 } 866 867 static void it66121_bridge_hpd_disable(struct drm_bridge *bridge) 868 { 869 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 870 int ret; 871 872 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 873 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD); 874 if (ret) 875 dev_err(ctx->dev, "failed to disable HPD IRQ\n"); 876 } 877 878 static struct edid *it66121_bridge_get_edid(struct drm_bridge *bridge, 879 struct drm_connector *connector) 880 { 881 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 882 struct edid *edid; 883 int ret; 884 885 mutex_lock(&ctx->lock); 886 ret = it66121_preamble_ddc(ctx); 887 if (ret) { 888 edid = ERR_PTR(ret); 889 goto out_unlock; 890 } 891 892 ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG, 893 IT66121_DDC_HEADER_EDID); 894 if (ret) { 895 edid = ERR_PTR(ret); 896 goto out_unlock; 897 } 898 899 edid = drm_do_get_edid(connector, it66121_get_edid_block, ctx); 900 901 out_unlock: 902 mutex_unlock(&ctx->lock); 903 904 return edid; 905 } 906 907 static const struct drm_bridge_funcs it66121_bridge_funcs = { 908 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 909 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 910 .atomic_reset = drm_atomic_helper_bridge_reset, 911 .attach = it66121_bridge_attach, 912 .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts, 913 .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts, 914 .atomic_enable = it66121_bridge_enable, 915 .atomic_disable = it66121_bridge_disable, 916 .atomic_check = it66121_bridge_check, 917 .mode_set = it66121_bridge_mode_set, 918 .mode_valid = it66121_bridge_mode_valid, 919 .detect = it66121_bridge_detect, 920 .get_edid = it66121_bridge_get_edid, 921 .hpd_enable = it66121_bridge_hpd_enable, 922 .hpd_disable = it66121_bridge_hpd_disable, 923 }; 924 925 static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id) 926 { 927 int ret; 928 unsigned int val; 929 struct it66121_ctx *ctx = dev_id; 930 struct device *dev = ctx->dev; 931 enum drm_connector_status status; 932 bool event = false; 933 934 mutex_lock(&ctx->lock); 935 936 ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val); 937 if (ret) 938 goto unlock; 939 940 if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ)) 941 goto unlock; 942 943 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val); 944 if (ret) { 945 dev_err(dev, "Cannot read STATUS1_REG %d\n", ret); 946 } else if (val & IT66121_INT_STATUS1_HPD_STATUS) { 947 regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG, 948 IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD); 949 950 status = it66121_is_hpd_detect(ctx) ? connector_status_connected 951 : connector_status_disconnected; 952 953 event = true; 954 } 955 956 regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG, 957 IT66121_SYS_STATUS_CLEAR_IRQ, 958 IT66121_SYS_STATUS_CLEAR_IRQ); 959 960 unlock: 961 mutex_unlock(&ctx->lock); 962 963 if (event) 964 drm_bridge_hpd_notify(&ctx->bridge, status); 965 966 return IRQ_HANDLED; 967 } 968 969 static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[]) 970 { 971 int ret; 972 973 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C); 974 if (ret) 975 return ret; 976 977 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]); 978 if (ret) 979 return ret; 980 981 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F); 982 if (ret) 983 return ret; 984 985 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG, 986 (iec60958_chstat[2] >> 4) & 0x0F); 987 if (ret) 988 return ret; 989 990 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]); 991 if (ret) 992 return ret; 993 994 return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]); 995 } 996 997 static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl) 998 { 999 int ret; 1000 unsigned int audio_enable = 0; 1001 unsigned int audio_format = 0; 1002 1003 switch (audio_swl) { 1004 case 16: 1005 audio_enable |= IT66121_AUD_16BIT; 1006 break; 1007 case 18: 1008 audio_enable |= IT66121_AUD_18BIT; 1009 break; 1010 case 20: 1011 audio_enable |= IT66121_AUD_20BIT; 1012 break; 1013 case 24: 1014 default: 1015 audio_enable |= IT66121_AUD_24BIT; 1016 break; 1017 } 1018 1019 audio_format |= 0x40; 1020 switch (audio_src_num) { 1021 case 4: 1022 audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1023 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1024 break; 1025 case 3: 1026 audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 | 1027 IT66121_AUD_EN_I2S0; 1028 break; 1029 case 2: 1030 audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1031 break; 1032 case 1: 1033 default: 1034 audio_format &= ~0x40; 1035 audio_enable |= IT66121_AUD_EN_I2S0; 1036 break; 1037 } 1038 1039 audio_format |= 0x01; 1040 ctx->audio.ch_enable = audio_enable; 1041 1042 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0); 1043 if (ret) 1044 return ret; 1045 1046 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format); 1047 if (ret) 1048 return ret; 1049 1050 ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4); 1051 if (ret) 1052 return ret; 1053 1054 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00); 1055 if (ret) 1056 return ret; 1057 1058 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00); 1059 if (ret) 1060 return ret; 1061 1062 return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00); 1063 } 1064 1065 static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs) 1066 { 1067 int ret; 1068 unsigned int n; 1069 1070 switch (fs) { 1071 case IT66121_AUD_FS_32K: 1072 n = 4096; 1073 break; 1074 case IT66121_AUD_FS_44P1K: 1075 n = 6272; 1076 break; 1077 case IT66121_AUD_FS_48K: 1078 n = 6144; 1079 break; 1080 case IT66121_AUD_FS_88P2K: 1081 n = 12544; 1082 break; 1083 case IT66121_AUD_FS_96K: 1084 n = 12288; 1085 break; 1086 case IT66121_AUD_FS_176P4K: 1087 n = 25088; 1088 break; 1089 case IT66121_AUD_FS_192K: 1090 n = 24576; 1091 break; 1092 case IT66121_AUD_FS_768K: 1093 n = 24576; 1094 break; 1095 default: 1096 n = 6144; 1097 break; 1098 } 1099 1100 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF)); 1101 if (ret) 1102 return ret; 1103 1104 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF)); 1105 if (ret) 1106 return ret; 1107 1108 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF)); 1109 if (ret) 1110 return ret; 1111 1112 if (ctx->audio.auto_cts) { 1113 u8 loop_cnt = 255; 1114 u8 cts_stable_cnt = 0; 1115 unsigned int sum_cts = 0; 1116 unsigned int cts = 0; 1117 unsigned int last_cts = 0; 1118 unsigned int diff; 1119 unsigned int val; 1120 1121 while (loop_cnt--) { 1122 msleep(30); 1123 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val); 1124 cts = val << 12; 1125 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val); 1126 cts |= val << 4; 1127 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val); 1128 cts |= val >> 4; 1129 if (cts == 0) { 1130 continue; 1131 } else { 1132 if (last_cts > cts) 1133 diff = last_cts - cts; 1134 else 1135 diff = cts - last_cts; 1136 last_cts = cts; 1137 if (diff < 5) { 1138 cts_stable_cnt++; 1139 sum_cts += cts; 1140 } else { 1141 cts_stable_cnt = 0; 1142 sum_cts = 0; 1143 continue; 1144 } 1145 1146 if (cts_stable_cnt >= 32) { 1147 last_cts = (sum_cts >> 5); 1148 break; 1149 } 1150 } 1151 } 1152 1153 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF)); 1154 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF)); 1155 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F)); 1156 } 1157 1158 ret = regmap_write(ctx->regmap, 0xF8, 0xC3); 1159 if (ret) 1160 return ret; 1161 1162 ret = regmap_write(ctx->regmap, 0xF8, 0xA5); 1163 if (ret) 1164 return ret; 1165 1166 if (ctx->audio.auto_cts) { 1167 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1168 IT66121_PKT_CTS_CTRL_SEL, 1169 1); 1170 } else { 1171 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1172 IT66121_PKT_CTS_CTRL_SEL, 1173 0); 1174 } 1175 1176 if (ret) 1177 return ret; 1178 1179 return regmap_write(ctx->regmap, 0xF8, 0xFF); 1180 } 1181 1182 static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable) 1183 { 1184 int ret; 1185 1186 if (enable) { 1187 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1188 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1189 0); 1190 if (ret) 1191 return ret; 1192 1193 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1194 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1195 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1196 ctx->audio.ch_enable); 1197 } else { 1198 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1199 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1200 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1201 ctx->audio.ch_enable & 0xF0); 1202 if (ret) 1203 return ret; 1204 1205 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1206 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1207 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF); 1208 } 1209 1210 return ret; 1211 } 1212 1213 static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable) 1214 { 1215 int ret; 1216 1217 if (enable) { 1218 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0); 1219 if (ret) 1220 return ret; 1221 1222 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable); 1223 } else { 1224 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0); 1225 } 1226 1227 return ret; 1228 } 1229 1230 static int it66121_audio_hw_params(struct device *dev, void *data, 1231 struct hdmi_codec_daifmt *daifmt, 1232 struct hdmi_codec_params *params) 1233 { 1234 u8 fs; 1235 u8 swl; 1236 int ret; 1237 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1238 static u8 iec60958_chstat[5]; 1239 unsigned int channels = params->channels; 1240 unsigned int sample_rate = params->sample_rate; 1241 unsigned int sample_width = params->sample_width; 1242 1243 mutex_lock(&ctx->lock); 1244 dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__, 1245 daifmt->fmt, sample_rate, sample_width, channels); 1246 1247 switch (daifmt->fmt) { 1248 case HDMI_I2S: 1249 dev_dbg(dev, "Using HDMI I2S\n"); 1250 break; 1251 default: 1252 dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt); 1253 ret = -EINVAL; 1254 goto out; 1255 } 1256 1257 // Set audio clock recovery (N/CTS) 1258 ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG, 1259 IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING | 1260 IT66121_CLK_CTRL0_EXT_MCLK_256FS | 1261 IT66121_CLK_CTRL0_AUTO_IPCLK); 1262 if (ret) 1263 goto out; 1264 1265 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1266 IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection 1267 if (ret) 1268 goto out; 1269 1270 switch (sample_rate) { 1271 case 44100L: 1272 fs = IT66121_AUD_FS_44P1K; 1273 break; 1274 case 88200L: 1275 fs = IT66121_AUD_FS_88P2K; 1276 break; 1277 case 176400L: 1278 fs = IT66121_AUD_FS_176P4K; 1279 break; 1280 case 32000L: 1281 fs = IT66121_AUD_FS_32K; 1282 break; 1283 case 48000L: 1284 fs = IT66121_AUD_FS_48K; 1285 break; 1286 case 96000L: 1287 fs = IT66121_AUD_FS_96K; 1288 break; 1289 case 192000L: 1290 fs = IT66121_AUD_FS_192K; 1291 break; 1292 case 768000L: 1293 fs = IT66121_AUD_FS_768K; 1294 break; 1295 default: 1296 fs = IT66121_AUD_FS_48K; 1297 break; 1298 } 1299 1300 ctx->audio.fs = fs; 1301 ret = it661221_set_ncts(ctx, fs); 1302 if (ret) { 1303 dev_err(dev, "Failed to set N/CTS: %d\n", ret); 1304 goto out; 1305 } 1306 1307 // Set audio format register (except audio channel enable) 1308 ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width); 1309 if (ret) { 1310 dev_err(dev, "Failed to set LPCM audio: %d\n", ret); 1311 goto out; 1312 } 1313 1314 // Set audio channel status 1315 iec60958_chstat[0] = 0; 1316 if ((channels + 1) / 2 == 1) 1317 iec60958_chstat[0] |= 0x1; 1318 iec60958_chstat[0] &= ~(1 << 1); 1319 iec60958_chstat[1] = 0; 1320 iec60958_chstat[2] = (channels + 1) / 2; 1321 iec60958_chstat[2] |= (channels << 4) & 0xF0; 1322 iec60958_chstat[3] = fs; 1323 1324 switch (sample_width) { 1325 case 21L: 1326 swl = IT66121_AUD_SWL_21BIT; 1327 break; 1328 case 24L: 1329 swl = IT66121_AUD_SWL_24BIT; 1330 break; 1331 case 23L: 1332 swl = IT66121_AUD_SWL_23BIT; 1333 break; 1334 case 22L: 1335 swl = IT66121_AUD_SWL_22BIT; 1336 break; 1337 case 20L: 1338 swl = IT66121_AUD_SWL_20BIT; 1339 break; 1340 case 17L: 1341 swl = IT66121_AUD_SWL_17BIT; 1342 break; 1343 case 19L: 1344 swl = IT66121_AUD_SWL_19BIT; 1345 break; 1346 case 18L: 1347 swl = IT66121_AUD_SWL_18BIT; 1348 break; 1349 case 16L: 1350 swl = IT66121_AUD_SWL_16BIT; 1351 break; 1352 default: 1353 swl = IT66121_AUD_SWL_NOT_INDICATED; 1354 break; 1355 } 1356 1357 iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl; 1358 ret = it661221_set_chstat(ctx, iec60958_chstat); 1359 if (ret) { 1360 dev_err(dev, "Failed to set channel status: %d\n", ret); 1361 goto out; 1362 } 1363 1364 // Enable audio channel enable while input clock stable (if SPDIF). 1365 ret = it661221_audio_ch_enable(ctx, true); 1366 if (ret) { 1367 dev_err(dev, "Failed to enable audio channel: %d\n", ret); 1368 goto out; 1369 } 1370 1371 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 1372 IT66121_INT_MASK1_AUD_OVF, 1373 0); 1374 if (ret) 1375 goto out; 1376 1377 dev_dbg(dev, "HDMI audio enabled.\n"); 1378 out: 1379 mutex_unlock(&ctx->lock); 1380 1381 return ret; 1382 } 1383 1384 static int it66121_audio_startup(struct device *dev, void *data) 1385 { 1386 int ret; 1387 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1388 1389 dev_dbg(dev, "%s\n", __func__); 1390 1391 mutex_lock(&ctx->lock); 1392 ret = it661221_audio_output_enable(ctx, true); 1393 if (ret) 1394 dev_err(dev, "Failed to enable audio output: %d\n", ret); 1395 1396 mutex_unlock(&ctx->lock); 1397 1398 return ret; 1399 } 1400 1401 static void it66121_audio_shutdown(struct device *dev, void *data) 1402 { 1403 int ret; 1404 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1405 1406 dev_dbg(dev, "%s\n", __func__); 1407 1408 mutex_lock(&ctx->lock); 1409 ret = it661221_audio_output_enable(ctx, false); 1410 if (ret) 1411 dev_err(dev, "Failed to disable audio output: %d\n", ret); 1412 1413 mutex_unlock(&ctx->lock); 1414 } 1415 1416 static int it66121_audio_mute(struct device *dev, void *data, 1417 bool enable, int direction) 1418 { 1419 int ret; 1420 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1421 1422 dev_dbg(dev, "%s: enable=%s, direction=%d\n", 1423 __func__, enable ? "true" : "false", direction); 1424 1425 mutex_lock(&ctx->lock); 1426 1427 if (enable) { 1428 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1429 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1430 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1431 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1432 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3); 1433 } else { 1434 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1435 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1436 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1437 0); 1438 } 1439 1440 mutex_unlock(&ctx->lock); 1441 1442 return ret; 1443 } 1444 1445 static int it66121_audio_get_eld(struct device *dev, void *data, 1446 u8 *buf, size_t len) 1447 { 1448 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1449 1450 mutex_lock(&ctx->lock); 1451 1452 memcpy(buf, ctx->connector->eld, 1453 min(sizeof(ctx->connector->eld), len)); 1454 1455 mutex_unlock(&ctx->lock); 1456 1457 return 0; 1458 } 1459 1460 static const struct hdmi_codec_ops it66121_audio_codec_ops = { 1461 .hw_params = it66121_audio_hw_params, 1462 .audio_startup = it66121_audio_startup, 1463 .audio_shutdown = it66121_audio_shutdown, 1464 .mute_stream = it66121_audio_mute, 1465 .get_eld = it66121_audio_get_eld, 1466 .no_capture_mute = 1, 1467 }; 1468 1469 static int it66121_audio_codec_init(struct it66121_ctx *ctx, struct device *dev) 1470 { 1471 struct hdmi_codec_pdata codec_data = { 1472 .ops = &it66121_audio_codec_ops, 1473 .i2s = 1, /* Only i2s support for now */ 1474 .spdif = 0, 1475 .max_i2s_channels = 8, 1476 }; 1477 1478 dev_dbg(dev, "%s\n", __func__); 1479 1480 if (!of_property_read_bool(dev->of_node, "#sound-dai-cells")) { 1481 dev_info(dev, "No \"#sound-dai-cells\", no audio\n"); 1482 return 0; 1483 } 1484 1485 ctx->audio.pdev = platform_device_register_data(dev, 1486 HDMI_CODEC_DRV_NAME, 1487 PLATFORM_DEVID_AUTO, 1488 &codec_data, 1489 sizeof(codec_data)); 1490 1491 if (IS_ERR(ctx->audio.pdev)) { 1492 dev_err(dev, "Failed to initialize HDMI audio codec: %d\n", 1493 PTR_ERR_OR_ZERO(ctx->audio.pdev)); 1494 } 1495 1496 return PTR_ERR_OR_ZERO(ctx->audio.pdev); 1497 } 1498 1499 static const char * const it66121_supplies[] = { 1500 "vcn33", "vcn18", "vrf12" 1501 }; 1502 1503 static int it66121_probe(struct i2c_client *client) 1504 { 1505 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1506 u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 }; 1507 struct device_node *ep; 1508 int ret; 1509 struct it66121_ctx *ctx; 1510 struct device *dev = &client->dev; 1511 1512 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1513 dev_err(dev, "I2C check functionality failed.\n"); 1514 return -ENXIO; 1515 } 1516 1517 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1518 if (!ctx) 1519 return -ENOMEM; 1520 1521 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 1522 if (!ep) 1523 return -EINVAL; 1524 1525 ctx->dev = dev; 1526 ctx->client = client; 1527 ctx->info = (const struct it66121_chip_info *) id->driver_data; 1528 1529 of_property_read_u32(ep, "bus-width", &ctx->bus_width); 1530 of_node_put(ep); 1531 1532 if (ctx->bus_width != 12 && ctx->bus_width != 24) 1533 return -EINVAL; 1534 1535 ep = of_graph_get_remote_node(dev->of_node, 1, -1); 1536 if (!ep) { 1537 dev_err(ctx->dev, "The endpoint is unconnected\n"); 1538 return -EINVAL; 1539 } 1540 1541 if (!of_device_is_available(ep)) { 1542 of_node_put(ep); 1543 dev_err(ctx->dev, "The remote device is disabled\n"); 1544 return -ENODEV; 1545 } 1546 1547 ctx->next_bridge = of_drm_find_bridge(ep); 1548 of_node_put(ep); 1549 if (!ctx->next_bridge) { 1550 dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n"); 1551 return -EPROBE_DEFER; 1552 } 1553 1554 i2c_set_clientdata(client, ctx); 1555 mutex_init(&ctx->lock); 1556 1557 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it66121_supplies), 1558 it66121_supplies); 1559 if (ret) { 1560 dev_err(dev, "Failed to enable power supplies\n"); 1561 return ret; 1562 } 1563 1564 it66121_hw_reset(ctx); 1565 1566 ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config); 1567 if (IS_ERR(ctx->regmap)) 1568 return PTR_ERR(ctx->regmap); 1569 1570 regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]); 1571 regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]); 1572 regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]); 1573 regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]); 1574 1575 /* Revision is shared with DEVICE_ID1 */ 1576 revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]); 1577 device_ids[1] &= IT66121_DEVICE_ID1_MASK; 1578 1579 if ((vendor_ids[1] << 8 | vendor_ids[0]) != ctx->info->vid || 1580 (device_ids[1] << 8 | device_ids[0]) != ctx->info->pid) { 1581 return -ENODEV; 1582 } 1583 1584 ctx->bridge.funcs = &it66121_bridge_funcs; 1585 ctx->bridge.of_node = dev->of_node; 1586 ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1587 ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 1588 1589 ret = devm_request_threaded_irq(dev, client->irq, NULL, it66121_irq_threaded_handler, 1590 IRQF_ONESHOT, dev_name(dev), ctx); 1591 if (ret < 0) { 1592 dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret); 1593 return ret; 1594 } 1595 1596 it66121_audio_codec_init(ctx, dev); 1597 1598 drm_bridge_add(&ctx->bridge); 1599 1600 dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id); 1601 1602 return 0; 1603 } 1604 1605 static void it66121_remove(struct i2c_client *client) 1606 { 1607 struct it66121_ctx *ctx = i2c_get_clientdata(client); 1608 1609 drm_bridge_remove(&ctx->bridge); 1610 mutex_destroy(&ctx->lock); 1611 } 1612 1613 static const struct of_device_id it66121_dt_match[] = { 1614 { .compatible = "ite,it66121" }, 1615 { .compatible = "ite,it6610" }, 1616 { } 1617 }; 1618 MODULE_DEVICE_TABLE(of, it66121_dt_match); 1619 1620 static const struct it66121_chip_info it66121_chip_info = { 1621 .id = ID_IT66121, 1622 .vid = 0x4954, 1623 .pid = 0x0612, 1624 }; 1625 1626 static const struct it66121_chip_info it6610_chip_info = { 1627 .id = ID_IT6610, 1628 .vid = 0xca00, 1629 .pid = 0x0611, 1630 }; 1631 1632 static const struct i2c_device_id it66121_id[] = { 1633 { "it66121", (kernel_ulong_t) &it66121_chip_info }, 1634 { "it6610", (kernel_ulong_t) &it6610_chip_info }, 1635 { } 1636 }; 1637 MODULE_DEVICE_TABLE(i2c, it66121_id); 1638 1639 static struct i2c_driver it66121_driver = { 1640 .driver = { 1641 .name = "it66121", 1642 .of_match_table = it66121_dt_match, 1643 }, 1644 .probe_new = it66121_probe, 1645 .remove = it66121_remove, 1646 .id_table = it66121_id, 1647 }; 1648 1649 module_i2c_driver(it66121_driver); 1650 1651 MODULE_AUTHOR("Phong LE"); 1652 MODULE_DESCRIPTION("IT66121 HDMI transmitter driver"); 1653 MODULE_LICENSE("GPL v2"); 1654