1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4  */
5 #include <linux/bits.h>
6 #include <linux/delay.h>
7 #include <linux/device.h>
8 #include <linux/err.h>
9 #include <linux/extcon.h>
10 #include <linux/fs.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/types.h>
20 #include <linux/wait.h>
21 
22 #include <crypto/hash.h>
23 
24 #include <drm/display/drm_dp_helper.h>
25 #include <drm/display/drm_hdcp_helper.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_bridge.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
33 
34 #include <sound/hdmi-codec.h>
35 
36 #define REG_IC_VER 0x04
37 
38 #define REG_RESET_CTRL 0x05
39 #define VIDEO_RESET BIT(0)
40 #define AUDIO_RESET BIT(1)
41 #define ALL_LOGIC_RESET BIT(2)
42 #define AUX_RESET BIT(3)
43 #define HDCP_RESET BIT(4)
44 
45 #define INT_STATUS_01 0x06
46 #define INT_MASK_01 0x09
47 #define INT_HPD_CHANGE 0
48 #define INT_RECEIVE_HPD_IRQ 1
49 #define INT_SCDT_CHANGE 2
50 #define INT_HDCP_FAIL 3
51 #define INT_HDCP_DONE 4
52 #define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
53 #define BIT_INT_HPD INT_HPD_CHANGE
54 #define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
55 #define BIT_INT_SCDT INT_SCDT_CHANGE
56 #define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
57 #define BIT_INT_HDCP_DONE INT_HDCP_DONE
58 
59 #define INT_STATUS_02 0x07
60 #define INT_MASK_02 0x0A
61 #define INT_AUX_CMD_FAIL 0
62 #define INT_HDCP_KSV_CHECK 1
63 #define INT_AUDIO_FIFO_ERROR 2
64 #define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
65 #define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
66 #define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
67 
68 #define INT_STATUS_03 0x08
69 #define INT_MASK_03 0x0B
70 #define INT_LINK_TRAIN_FAIL 4
71 #define INT_VID_FIFO_ERROR 5
72 #define INT_IO_LATCH_FIFO_OVERFLOW 7
73 #define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
74 #define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
75 #define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
76 
77 #define REG_SYSTEM_STS 0x0D
78 #define INT_STS BIT(0)
79 #define HPD_STS BIT(1)
80 #define VIDEO_STB BIT(2)
81 
82 #define REG_LINK_TRAIN_STS 0x0E
83 #define LINK_STATE_CR BIT(2)
84 #define LINK_STATE_EQ BIT(3)
85 #define LINK_STATE_NORP BIT(4)
86 
87 #define REG_BANK_SEL 0x0F
88 #define REG_CLK_CTRL0 0x10
89 #define M_PCLK_DELAY 0x03
90 
91 #define REG_AUX_OPT 0x11
92 #define AUX_AUTO_RST BIT(0)
93 #define AUX_FIX_FREQ BIT(3)
94 
95 #define REG_DATA_CTRL0 0x12
96 #define VIDEO_LATCH_EDGE BIT(4)
97 #define ENABLE_PCLK_COUNTER BIT(7)
98 
99 #define REG_PCLK_COUNTER_VALUE 0x13
100 
101 #define REG_501_FIFO_CTRL 0x15
102 #define RST_501_FIFO BIT(1)
103 
104 #define REG_TRAIN_CTRL0 0x16
105 #define FORCE_LBR BIT(0)
106 #define LANE_COUNT_MASK 0x06
107 #define LANE_SWAP BIT(3)
108 #define SPREAD_AMP_5 BIT(4)
109 #define FORCE_CR_DONE BIT(5)
110 #define FORCE_EQ_DONE BIT(6)
111 
112 #define REG_TRAIN_CTRL1 0x17
113 #define AUTO_TRAIN BIT(0)
114 #define MANUAL_TRAIN BIT(1)
115 #define FORCE_RETRAIN BIT(2)
116 
117 #define REG_AUX_CTRL 0x23
118 #define CLR_EDID_FIFO BIT(0)
119 #define AUX_USER_MODE BIT(1)
120 #define AUX_NO_SEGMENT_WR BIT(6)
121 #define AUX_EN_FIFO_READ BIT(7)
122 
123 #define REG_AUX_ADR_0_7 0x24
124 #define REG_AUX_ADR_8_15 0x25
125 #define REG_AUX_ADR_16_19 0x26
126 #define REG_AUX_OUT_DATA0 0x27
127 
128 #define REG_AUX_CMD_REQ 0x2B
129 #define AUX_BUSY BIT(5)
130 
131 #define REG_AUX_DATA_0_7 0x2C
132 #define REG_AUX_DATA_8_15 0x2D
133 #define REG_AUX_DATA_16_23 0x2E
134 #define REG_AUX_DATA_24_31 0x2F
135 
136 #define REG_AUX_DATA_FIFO 0x2F
137 
138 #define REG_AUX_ERROR_STS 0x9F
139 #define M_AUX_REQ_FAIL 0x03
140 
141 #define REG_HDCP_CTRL1 0x38
142 #define HDCP_CP_ENABLE BIT(0)
143 
144 #define REG_HDCP_TRIGGER 0x39
145 #define HDCP_TRIGGER_START  BIT(0)
146 #define HDCP_TRIGGER_CPIRQ  BIT(1)
147 #define HDCP_TRIGGER_KSV_DONE  BIT(4)
148 #define HDCP_TRIGGER_KSV_FAIL BIT(5)
149 
150 #define REG_HDCP_CTRL2 0x3A
151 #define HDCP_AN_SEL BIT(0)
152 #define HDCP_AN_GEN BIT(1)
153 #define HDCP_HW_HPDIRQ_ACT BIT(2)
154 #define HDCP_EN_M0_READ BIT(5)
155 
156 #define REG_M0_0_7 0x4C
157 #define REG_AN_0_7 0x4C
158 #define REG_SP_CTRL0 0x58
159 #define REG_IP_CTRL1 0x59
160 #define REG_IP_CTRL2 0x5A
161 
162 #define REG_LINK_DRV 0x5C
163 #define DRV_HS BIT(1)
164 
165 #define REG_DRV_LN_DATA_SEL 0x5D
166 
167 #define REG_AUX 0x5E
168 
169 #define REG_VID_BUS_CTRL0 0x60
170 #define IN_DDR BIT(2)
171 #define DDR_CD (0x01 << 6)
172 
173 #define REG_VID_BUS_CTRL1 0x61
174 #define TX_FIFO_RESET BIT(1)
175 
176 #define REG_INPUT_CTRL 0xA0
177 #define INPUT_HSYNC_POL BIT(0)
178 #define INPUT_VSYNC_POL BIT(2)
179 #define INPUT_INTERLACED BIT(4)
180 
181 #define REG_INPUT_HTOTAL 0xA1
182 #define REG_INPUT_HACTIVE_START 0xA3
183 #define REG_INPUT_HACTIVE_WIDTH 0xA5
184 #define REG_INPUT_HFRONT_PORCH 0xA7
185 #define REG_INPUT_HSYNC_WIDTH 0xA9
186 #define REG_INPUT_VTOTAL 0xAB
187 #define REG_INPUT_VACTIVE_START 0xAD
188 #define REG_INPUT_VACTIVE_WIDTH 0xAF
189 #define REG_INPUT_VFRONT_PORCH 0xB1
190 #define REG_INPUT_VSYNC_WIDTH 0xB3
191 
192 #define REG_AUDIO_SRC_CTRL 0xB8
193 #define M_AUDIO_I2S_EN 0x0F
194 #define EN_I2S0 BIT(0)
195 #define EN_I2S1 BIT(1)
196 #define EN_I2S2 BIT(2)
197 #define EN_I2S3 BIT(3)
198 #define AUDIO_FIFO_RESET BIT(7)
199 
200 #define REG_AUDIO_FMT 0xB9
201 #define REG_AUDIO_FIFO_SEL 0xBA
202 
203 #define REG_AUDIO_CTRL0 0xBB
204 #define AUDIO_FULL_PKT BIT(4)
205 #define AUDIO_16B_BOUND BIT(5)
206 
207 #define REG_AUDIO_CTRL1 0xBC
208 #define REG_AUDIO_INPUT_FREQ 0xBE
209 
210 #define REG_IEC958_STS0 0xBF
211 #define REG_IEC958_STS1 0xC0
212 #define REG_IEC958_STS2 0xC1
213 #define REG_IEC958_STS3 0xC2
214 #define REG_IEC958_STS4 0xC3
215 
216 #define REG_HPD_IRQ_TIME 0xC9
217 #define REG_AUX_DEBUG_MODE 0xCA
218 #define REG_AUX_OPT2 0xCB
219 #define REG_HDCP_OPT 0xCE
220 #define REG_USER_DRV_PRE 0xCF
221 
222 #define REG_DATA_MUTE_CTRL 0xD3
223 #define ENABLE_ENHANCED_FRAME BIT(0)
224 #define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
225 #define EN_VID_MUTE BIT(4)
226 #define EN_AUD_MUTE BIT(5)
227 
228 #define REG_TIME_STMP_CTRL 0xD4
229 #define EN_ENHANCE_VID_STMP BIT(0)
230 #define EN_ENHANCE_AUD_STMP BIT(2)
231 #define M_STAMP_STEP 0x30
232 #define EN_SSC_GAT BIT(6)
233 
234 #define REG_INFOFRAME_CTRL 0xE8
235 #define EN_AVI_PKT BIT(0)
236 #define EN_AUD_PKT BIT(1)
237 #define EN_MPG_PKT BIT(2)
238 #define EN_GEN_PKT BIT(3)
239 #define EN_VID_TIME_STMP BIT(4)
240 #define EN_AUD_TIME_STMP BIT(5)
241 #define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
242 #define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
243 
244 #define REG_AUDIO_N_0_7 0xDE
245 #define REG_AUDIO_N_8_15 0xDF
246 #define REG_AUDIO_N_16_23 0xE0
247 
248 #define REG_AVI_INFO_DB1 0xE9
249 #define REG_AVI_INFO_DB2 0xEA
250 #define REG_AVI_INFO_DB3 0xEB
251 #define REG_AVI_INFO_DB4 0xEC
252 #define REG_AVI_INFO_DB5 0xED
253 #define REG_AVI_INFO_SUM 0xF6
254 
255 #define REG_AUD_INFOFRAM_DB1 0xF7
256 #define REG_AUD_INFOFRAM_DB2 0xF8
257 #define REG_AUD_INFOFRAM_DB3 0xF9
258 #define REG_AUD_INFOFRAM_DB4 0xFA
259 #define REG_AUD_INFOFRAM_SUM 0xFB
260 
261 /* the following six registers are in bank1 */
262 #define REG_DRV_0_DB_800_MV 0x7E
263 #define REG_PRE_0_DB_800_MV 0x7F
264 #define REG_PRE_3P5_DB_800_MV 0x81
265 #define REG_SSC_CTRL0 0x88
266 #define REG_SSC_CTRL1 0x89
267 #define REG_SSC_CTRL2 0x8A
268 
269 #define RBR DP_LINK_BW_1_62
270 #define HBR DP_LINK_BW_2_7
271 #define HBR2 DP_LINK_BW_5_4
272 #define HBR3 DP_LINK_BW_8_1
273 
274 #define DPCD_V_1_1 0x11
275 #define MISC_VERB 0xF0
276 #define MISC_VERC 0x70
277 #define I2S_INPUT_FORMAT_STANDARD 0
278 #define I2S_INPUT_FORMAT_32BIT 1
279 #define I2S_INPUT_LEFT_JUSTIFIED 0
280 #define I2S_INPUT_RIGHT_JUSTIFIED 1
281 #define I2S_DATA_1T_DELAY 0
282 #define I2S_DATA_NO_DELAY 1
283 #define I2S_WS_LEFT_CHANNEL 0
284 #define I2S_WS_RIGHT_CHANNEL 1
285 #define I2S_DATA_MSB_FIRST 0
286 #define I2S_DATA_LSB_FIRST 1
287 #define WORD_LENGTH_16BIT 0
288 #define WORD_LENGTH_18BIT 1
289 #define WORD_LENGTH_20BIT 2
290 #define WORD_LENGTH_24BIT 3
291 #define DEBUGFS_DIR_NAME "it6505-debugfs"
292 #define READ_BUFFER_SIZE 400
293 
294 /* Vendor option */
295 #define HDCP_DESIRED 1
296 #define MAX_LANE_COUNT 4
297 #define MAX_LINK_RATE HBR
298 #define AUTO_TRAIN_RETRY 3
299 #define MAX_HDCP_DOWN_STREAM_COUNT 10
300 #define MAX_CR_LEVEL 0x03
301 #define MAX_EQ_LEVEL 0x03
302 #define AUX_WAIT_TIMEOUT_MS 15
303 #define AUX_FIFO_MAX_SIZE 32
304 #define PIXEL_CLK_DELAY 1
305 #define PIXEL_CLK_INVERSE 0
306 #define ADJUST_PHASE_THRESHOLD 80000
307 #define DPI_PIXEL_CLK_MAX 95000
308 #define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
309 #define DEFAULT_PWR_ON 0
310 #define DEFAULT_DRV_HOLD 0
311 
312 #define AUDIO_SELECT I2S
313 #define AUDIO_TYPE LPCM
314 #define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
315 #define AUDIO_CHANNEL_COUNT 2
316 #define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
317 #define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
318 #define I2S_DATA_DELAY I2S_DATA_1T_DELAY
319 #define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
320 #define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
321 #define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
322 
323 enum aux_cmd_type {
324 	CMD_AUX_NATIVE_READ = 0x0,
325 	CMD_AUX_NATIVE_WRITE = 0x5,
326 	CMD_AUX_I2C_EDID_READ = 0xB,
327 };
328 
329 enum aux_cmd_reply {
330 	REPLY_ACK,
331 	REPLY_NACK,
332 	REPLY_DEFER,
333 };
334 
335 enum link_train_status {
336 	LINK_IDLE,
337 	LINK_BUSY,
338 	LINK_OK,
339 };
340 
341 enum hdcp_state {
342 	HDCP_AUTH_IDLE,
343 	HDCP_AUTH_GOING,
344 	HDCP_AUTH_DONE,
345 };
346 
347 struct it6505_platform_data {
348 	struct regulator *pwr18;
349 	struct regulator *ovdd;
350 	struct gpio_desc *gpiod_reset;
351 };
352 
353 enum it6505_audio_select {
354 	I2S = 0,
355 	SPDIF,
356 };
357 
358 enum it6505_audio_sample_rate {
359 	SAMPLE_RATE_24K = 0x6,
360 	SAMPLE_RATE_32K = 0x3,
361 	SAMPLE_RATE_48K = 0x2,
362 	SAMPLE_RATE_96K = 0xA,
363 	SAMPLE_RATE_192K = 0xE,
364 	SAMPLE_RATE_44_1K = 0x0,
365 	SAMPLE_RATE_88_2K = 0x8,
366 	SAMPLE_RATE_176_4K = 0xC,
367 };
368 
369 enum it6505_audio_type {
370 	LPCM = 0,
371 	NLPCM,
372 	DSS,
373 };
374 
375 struct it6505_audio_data {
376 	enum it6505_audio_select select;
377 	enum it6505_audio_sample_rate sample_rate;
378 	enum it6505_audio_type type;
379 	u8 word_length;
380 	u8 channel_count;
381 	u8 i2s_input_format;
382 	u8 i2s_justified;
383 	u8 i2s_data_delay;
384 	u8 i2s_ws_channel;
385 	u8 i2s_data_sequence;
386 };
387 
388 struct it6505_audio_sample_rate_map {
389 	enum it6505_audio_sample_rate rate;
390 	int sample_rate_value;
391 };
392 
393 struct it6505_drm_dp_link {
394 	unsigned char revision;
395 	unsigned int rate;
396 	unsigned int num_lanes;
397 	unsigned long capabilities;
398 };
399 
400 struct debugfs_entries {
401 	char *name;
402 	const struct file_operations *fops;
403 };
404 
405 struct it6505 {
406 	struct drm_dp_aux aux;
407 	struct drm_bridge bridge;
408 	struct i2c_client *client;
409 	struct it6505_drm_dp_link link;
410 	struct it6505_platform_data pdata;
411 	/*
412 	 * Mutex protects extcon and interrupt functions from interfering
413 	 * each other.
414 	 */
415 	struct mutex extcon_lock;
416 	struct mutex mode_lock; /* used to bridge_detect */
417 	struct mutex aux_lock; /* used to aux data transfers */
418 	struct regmap *regmap;
419 	struct drm_display_mode source_output_mode;
420 	struct drm_display_mode video_info;
421 	struct notifier_block event_nb;
422 	struct extcon_dev *extcon;
423 	struct work_struct extcon_wq;
424 	enum drm_connector_status connector_status;
425 	enum link_train_status link_state;
426 	struct work_struct link_works;
427 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
428 	u8 lane_count;
429 	u8 link_rate_bw_code;
430 	u8 sink_count;
431 	bool step_train;
432 	bool branch_device;
433 	bool enable_ssc;
434 	bool lane_swap_disabled;
435 	bool lane_swap;
436 	bool powered;
437 	bool hpd_state;
438 	u32 afe_setting;
439 	enum hdcp_state hdcp_status;
440 	struct delayed_work hdcp_work;
441 	struct work_struct hdcp_wait_ksv_list;
442 	struct completion wait_edid_complete;
443 	u8 auto_train_retry;
444 	bool hdcp_desired;
445 	bool is_repeater;
446 	u8 hdcp_down_stream_count;
447 	u8 bksvs[DRM_HDCP_KSV_LEN];
448 	u8 sha1_input[HDCP_SHA1_FIFO_LEN];
449 	bool enable_enhanced_frame;
450 	hdmi_codec_plugged_cb plugged_cb;
451 	struct device *codec_dev;
452 	struct delayed_work delayed_audio;
453 	struct it6505_audio_data audio;
454 	struct dentry *debugfs;
455 
456 	/* it6505 driver hold option */
457 	bool enable_drv_hold;
458 };
459 
460 struct it6505_step_train_para {
461 	u8 voltage_swing[MAX_LANE_COUNT];
462 	u8 pre_emphasis[MAX_LANE_COUNT];
463 };
464 
465 /*
466  * Vendor option afe settings for different platforms
467  * 0: without FPC cable
468  * 1: with FPC cable
469  */
470 
471 static const u8 afe_setting_table[][3] = {
472 	{0x82, 0x00, 0x45},
473 	{0x93, 0x2A, 0x85}
474 };
475 
476 static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
477 	{SAMPLE_RATE_24K, 24000},
478 	{SAMPLE_RATE_32K, 32000},
479 	{SAMPLE_RATE_48K, 48000},
480 	{SAMPLE_RATE_96K, 96000},
481 	{SAMPLE_RATE_192K, 192000},
482 	{SAMPLE_RATE_44_1K, 44100},
483 	{SAMPLE_RATE_88_2K, 88200},
484 	{SAMPLE_RATE_176_4K, 176400},
485 };
486 
487 static const struct regmap_range it6505_bridge_volatile_ranges[] = {
488 	{ .range_min = 0, .range_max = 0xFF },
489 };
490 
491 static const struct regmap_access_table it6505_bridge_volatile_table = {
492 	.yes_ranges = it6505_bridge_volatile_ranges,
493 	.n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
494 };
495 
496 static const struct regmap_config it6505_regmap_config = {
497 	.reg_bits = 8,
498 	.val_bits = 8,
499 	.volatile_table = &it6505_bridge_volatile_table,
500 	.cache_type = REGCACHE_NONE,
501 };
502 
503 static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
504 {
505 	unsigned int value;
506 	int err;
507 	struct device *dev = &it6505->client->dev;
508 
509 	if (!it6505->powered)
510 		return -ENODEV;
511 
512 	err = regmap_read(it6505->regmap, reg_addr, &value);
513 	if (err < 0) {
514 		dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
515 		return err;
516 	}
517 
518 	return value;
519 }
520 
521 static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
522 			unsigned int reg_val)
523 {
524 	int err;
525 	struct device *dev = &it6505->client->dev;
526 
527 	if (!it6505->powered)
528 		return -ENODEV;
529 
530 	err = regmap_write(it6505->regmap, reg_addr, reg_val);
531 
532 	if (err < 0) {
533 		dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
534 			reg_addr, reg_val, err);
535 		return err;
536 	}
537 
538 	return 0;
539 }
540 
541 static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
542 			   unsigned int mask, unsigned int value)
543 {
544 	int err;
545 	struct device *dev = &it6505->client->dev;
546 
547 	if (!it6505->powered)
548 		return -ENODEV;
549 
550 	err = regmap_update_bits(it6505->regmap, reg, mask, value);
551 	if (err < 0) {
552 		dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
553 			reg, value, mask, err);
554 		return err;
555 	}
556 
557 	return 0;
558 }
559 
560 static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
561 			       const char *prefix)
562 {
563 	struct device *dev = &it6505->client->dev;
564 	int val;
565 
566 	if (!drm_debug_enabled(DRM_UT_DRIVER))
567 		return;
568 
569 	val = it6505_read(it6505, reg);
570 	if (val < 0)
571 		DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
572 				     prefix, reg, val);
573 	else
574 		DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
575 				     val);
576 }
577 
578 static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
579 {
580 	u8 value;
581 	int ret;
582 	struct device *dev = &it6505->client->dev;
583 
584 	ret = drm_dp_dpcd_readb(&it6505->aux, offset, &value);
585 	if (ret < 0) {
586 		dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
587 		return ret;
588 	}
589 	return value;
590 }
591 
592 static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
593 			     u8 datain)
594 {
595 	int ret;
596 	struct device *dev = &it6505->client->dev;
597 
598 	ret = drm_dp_dpcd_writeb(&it6505->aux, offset, datain);
599 	if (ret < 0) {
600 		dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
601 		return ret;
602 	}
603 	return 0;
604 }
605 
606 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
607 {
608 	int ret;
609 	struct device *dev = &it6505->client->dev;
610 
611 	ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);
612 
613 	if (ret < 0)
614 		return ret;
615 
616 	DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
617 			     num, dpcd);
618 
619 	return 0;
620 }
621 
622 static void it6505_dump(struct it6505 *it6505)
623 {
624 	unsigned int i, j;
625 	u8 regs[16];
626 	struct device *dev = &it6505->client->dev;
627 
628 	for (i = 0; i <= 0xff; i += 16) {
629 		for (j = 0; j < 16; j++)
630 			regs[j] = it6505_read(it6505, i + j);
631 
632 		DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
633 	}
634 }
635 
636 static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
637 {
638 	int reg_0d;
639 
640 	reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
641 
642 	if (reg_0d < 0)
643 		return false;
644 
645 	return reg_0d & HPD_STS;
646 }
647 
648 static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
649 {
650 	int val0, val1;
651 
652 	val0 = it6505_read(it6505, reg);
653 	if (val0 < 0)
654 		return val0;
655 
656 	val1 = it6505_read(it6505, reg + 1);
657 	if (val1 < 0)
658 		return val1;
659 
660 	return (val1 << 8) | val0;
661 }
662 
663 static void it6505_calc_video_info(struct it6505 *it6505)
664 {
665 	struct device *dev = &it6505->client->dev;
666 	int hsync_pol, vsync_pol, interlaced;
667 	int htotal, hdes, hdew, hfph, hsyncw;
668 	int vtotal, vdes, vdew, vfph, vsyncw;
669 	int rddata, i, pclk, sum = 0;
670 
671 	usleep_range(10000, 15000);
672 	rddata = it6505_read(it6505, REG_INPUT_CTRL);
673 	hsync_pol = rddata & INPUT_HSYNC_POL;
674 	vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
675 	interlaced = (rddata & INPUT_INTERLACED) >> 4;
676 
677 	htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
678 	hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
679 	hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
680 	hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
681 	hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
682 
683 	vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
684 	vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
685 	vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
686 	vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
687 	vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
688 
689 	DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
690 			     hsync_pol, vsync_pol, interlaced);
691 	DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
692 			     hdes, vdes);
693 
694 	for (i = 0; i < 3; i++) {
695 		it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
696 				ENABLE_PCLK_COUNTER);
697 		usleep_range(10000, 15000);
698 		it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
699 				0x00);
700 		rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
701 			 0xFFF;
702 
703 		sum += rddata;
704 	}
705 
706 	if (sum == 0) {
707 		DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
708 		return;
709 	}
710 
711 	sum /= 3;
712 	pclk = 13500 * 2048 / sum;
713 	it6505->video_info.clock = pclk;
714 	it6505->video_info.hdisplay = hdew;
715 	it6505->video_info.hsync_start = hdew + hfph;
716 	it6505->video_info.hsync_end = hdew + hfph + hsyncw;
717 	it6505->video_info.htotal = htotal;
718 	it6505->video_info.vdisplay = vdew;
719 	it6505->video_info.vsync_start = vdew + vfph;
720 	it6505->video_info.vsync_end = vdew + vfph + vsyncw;
721 	it6505->video_info.vtotal = vtotal;
722 
723 	DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
724 			     DRM_MODE_ARG(&it6505->video_info));
725 }
726 
727 static int it6505_drm_dp_link_probe(struct drm_dp_aux *aux,
728 				    struct it6505_drm_dp_link *link)
729 {
730 	u8 values[3];
731 	int err;
732 
733 	memset(link, 0, sizeof(*link));
734 
735 	err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
736 	if (err < 0)
737 		return err;
738 
739 	link->revision = values[0];
740 	link->rate = drm_dp_bw_code_to_link_rate(values[1]);
741 	link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
742 
743 	if (values[2] & DP_ENHANCED_FRAME_CAP)
744 		link->capabilities = DP_ENHANCED_FRAME_CAP;
745 
746 	return 0;
747 }
748 
749 static int it6505_drm_dp_link_set_power(struct drm_dp_aux *aux,
750 					struct it6505_drm_dp_link *link,
751 					u8 mode)
752 {
753 	u8 value;
754 	int err;
755 
756 	/* DP_SET_POWER register is only available on DPCD v1.1 and later */
757 	if (link->revision < DPCD_V_1_1)
758 		return 0;
759 
760 	err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
761 	if (err < 0)
762 		return err;
763 
764 	value &= ~DP_SET_POWER_MASK;
765 	value |= mode;
766 
767 	err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
768 	if (err < 0)
769 		return err;
770 
771 	if (mode == DP_SET_POWER_D0) {
772 		/*
773 		 * According to the DP 1.1 specification, a "Sink Device must
774 		 * exit the power saving state within 1 ms" (Section 2.5.3.1,
775 		 * Table 5-52, "Sink Control Field" (register 0x600).
776 		 */
777 		usleep_range(1000, 2000);
778 	}
779 
780 	return 0;
781 }
782 
783 static void it6505_clear_int(struct it6505 *it6505)
784 {
785 	it6505_write(it6505, INT_STATUS_01, 0xFF);
786 	it6505_write(it6505, INT_STATUS_02, 0xFF);
787 	it6505_write(it6505, INT_STATUS_03, 0xFF);
788 }
789 
790 static void it6505_int_mask_enable(struct it6505 *it6505)
791 {
792 	it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
793 		     BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
794 		     BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
795 
796 	it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
797 		     BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
798 
799 	it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
800 		     BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
801 }
802 
803 static void it6505_int_mask_disable(struct it6505 *it6505)
804 {
805 	it6505_write(it6505, INT_MASK_01, 0x00);
806 	it6505_write(it6505, INT_MASK_02, 0x00);
807 	it6505_write(it6505, INT_MASK_03, 0x00);
808 }
809 
810 static void it6505_lane_termination_on(struct it6505 *it6505)
811 {
812 	int regcf;
813 
814 	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
815 
816 	if (regcf == MISC_VERB)
817 		it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x00);
818 
819 	if (regcf == MISC_VERC) {
820 		if (it6505->lane_swap) {
821 			switch (it6505->lane_count) {
822 			case 1:
823 			case 2:
824 				it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
825 						0x0C, 0x08);
826 				break;
827 			default:
828 				it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
829 						0x0C, 0x0C);
830 				break;
831 			}
832 		} else {
833 			switch (it6505->lane_count) {
834 			case 1:
835 			case 2:
836 				it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
837 						0x0C, 0x04);
838 				break;
839 			default:
840 				it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
841 						0x0C, 0x0C);
842 				break;
843 			}
844 		}
845 	}
846 }
847 
848 static void it6505_lane_termination_off(struct it6505 *it6505)
849 {
850 	int regcf;
851 
852 	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
853 
854 	if (regcf == MISC_VERB)
855 		it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
856 
857 	if (regcf == MISC_VERC)
858 		it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x0C, 0x00);
859 }
860 
861 static void it6505_lane_power_on(struct it6505 *it6505)
862 {
863 	it6505_set_bits(it6505, REG_LINK_DRV, 0xF1,
864 			(it6505->lane_swap ?
865 				 GENMASK(7, 8 - it6505->lane_count) :
866 				 GENMASK(3 + it6505->lane_count, 4)) |
867 				0x01);
868 }
869 
870 static void it6505_lane_power_off(struct it6505 *it6505)
871 {
872 	it6505_set_bits(it6505, REG_LINK_DRV, 0xF0, 0x00);
873 }
874 
875 static void it6505_lane_off(struct it6505 *it6505)
876 {
877 	it6505_lane_power_off(it6505);
878 	it6505_lane_termination_off(it6505);
879 }
880 
881 static void it6505_aux_termination_on(struct it6505 *it6505)
882 {
883 	int regcf;
884 
885 	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
886 
887 	if (regcf == MISC_VERB)
888 		it6505_lane_termination_on(it6505);
889 
890 	if (regcf == MISC_VERC)
891 		it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
892 }
893 
894 static void it6505_aux_power_on(struct it6505 *it6505)
895 {
896 	it6505_set_bits(it6505, REG_AUX, 0x02, 0x02);
897 }
898 
899 static void it6505_aux_on(struct it6505 *it6505)
900 {
901 	it6505_aux_power_on(it6505);
902 	it6505_aux_termination_on(it6505);
903 }
904 
905 static void it6505_aux_reset(struct it6505 *it6505)
906 {
907 	it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
908 	it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, 0x00);
909 }
910 
911 static void it6505_reset_logic(struct it6505 *it6505)
912 {
913 	regmap_write(it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
914 	usleep_range(1000, 1500);
915 }
916 
917 static bool it6505_aux_op_finished(struct it6505 *it6505)
918 {
919 	int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
920 
921 	if (reg2b < 0)
922 		return false;
923 
924 	return (reg2b & AUX_BUSY) == 0;
925 }
926 
927 static int it6505_aux_wait(struct it6505 *it6505)
928 {
929 	int status;
930 	unsigned long timeout;
931 	struct device *dev = &it6505->client->dev;
932 
933 	timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
934 
935 	while (!it6505_aux_op_finished(it6505)) {
936 		if (time_after(jiffies, timeout)) {
937 			dev_err(dev, "Timed out waiting AUX to finish");
938 			return -ETIMEDOUT;
939 		}
940 		usleep_range(1000, 2000);
941 	}
942 
943 	status = it6505_read(it6505, REG_AUX_ERROR_STS);
944 	if (status < 0) {
945 		dev_err(dev, "Failed to read AUX channel: %d", status);
946 		return status;
947 	}
948 
949 	return 0;
950 }
951 
952 static ssize_t it6505_aux_operation(struct it6505 *it6505,
953 				    enum aux_cmd_type cmd,
954 				    unsigned int address, u8 *buffer,
955 				    size_t size, enum aux_cmd_reply *reply)
956 {
957 	int i, ret;
958 	bool aux_write_check = false;
959 
960 	if (!it6505_get_sink_hpd_status(it6505))
961 		return -EIO;
962 
963 	/* set AUX user mode */
964 	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
965 
966 aux_op_start:
967 	if (cmd == CMD_AUX_I2C_EDID_READ) {
968 		/* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
969 		size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
970 		/* Enable AUX FIFO read back and clear FIFO */
971 		it6505_set_bits(it6505, REG_AUX_CTRL,
972 				AUX_EN_FIFO_READ | CLR_EDID_FIFO,
973 				AUX_EN_FIFO_READ | CLR_EDID_FIFO);
974 
975 		it6505_set_bits(it6505, REG_AUX_CTRL,
976 				AUX_EN_FIFO_READ | CLR_EDID_FIFO,
977 				AUX_EN_FIFO_READ);
978 	} else {
979 		/* The DP AUX transmit buffer has 4 bytes. */
980 		size = min_t(size_t, size, 4);
981 		it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
982 				AUX_NO_SEGMENT_WR);
983 	}
984 
985 	/* Start Address[7:0] */
986 	it6505_write(it6505, REG_AUX_ADR_0_7, (address >> 0) & 0xFF);
987 	/* Start Address[15:8] */
988 	it6505_write(it6505, REG_AUX_ADR_8_15, (address >> 8) & 0xFF);
989 	/* WriteNum[3:0]+StartAdr[19:16] */
990 	it6505_write(it6505, REG_AUX_ADR_16_19,
991 		     ((address >> 16) & 0x0F) | ((size - 1) << 4));
992 
993 	if (cmd == CMD_AUX_NATIVE_WRITE)
994 		regmap_bulk_write(it6505->regmap, REG_AUX_OUT_DATA0, buffer,
995 				  size);
996 
997 	/* Aux Fire */
998 	it6505_write(it6505, REG_AUX_CMD_REQ, cmd);
999 
1000 	ret = it6505_aux_wait(it6505);
1001 	if (ret < 0)
1002 		goto aux_op_err;
1003 
1004 	ret = it6505_read(it6505, REG_AUX_ERROR_STS);
1005 	if (ret < 0)
1006 		goto aux_op_err;
1007 
1008 	switch ((ret >> 6) & 0x3) {
1009 	case 0:
1010 		*reply = REPLY_ACK;
1011 		break;
1012 	case 1:
1013 		*reply = REPLY_DEFER;
1014 		ret = -EAGAIN;
1015 		goto aux_op_err;
1016 	case 2:
1017 		*reply = REPLY_NACK;
1018 		ret = -EIO;
1019 		goto aux_op_err;
1020 	case 3:
1021 		ret = -ETIMEDOUT;
1022 		goto aux_op_err;
1023 	}
1024 
1025 	/* Read back Native Write data */
1026 	if (cmd == CMD_AUX_NATIVE_WRITE) {
1027 		aux_write_check = true;
1028 		cmd = CMD_AUX_NATIVE_READ;
1029 		goto aux_op_start;
1030 	}
1031 
1032 	if (cmd == CMD_AUX_I2C_EDID_READ) {
1033 		for (i = 0; i < size; i++) {
1034 			ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1035 			if (ret < 0)
1036 				goto aux_op_err;
1037 			buffer[i] = ret;
1038 		}
1039 	} else {
1040 		for (i = 0; i < size; i++) {
1041 			ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1042 			if (ret < 0)
1043 				goto aux_op_err;
1044 
1045 			if (aux_write_check && buffer[size - 1 - i] != ret) {
1046 				ret = -EINVAL;
1047 				goto aux_op_err;
1048 			}
1049 
1050 			buffer[size - 1 - i] = ret;
1051 		}
1052 	}
1053 
1054 	ret = i;
1055 
1056 aux_op_err:
1057 	if (cmd == CMD_AUX_I2C_EDID_READ) {
1058 		/* clear AUX FIFO */
1059 		it6505_set_bits(it6505, REG_AUX_CTRL,
1060 				AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1061 				AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1062 		it6505_set_bits(it6505, REG_AUX_CTRL,
1063 				AUX_EN_FIFO_READ | CLR_EDID_FIFO, 0x00);
1064 	}
1065 
1066 	/* Leave AUX user mode */
1067 	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, 0);
1068 
1069 	return ret;
1070 }
1071 
1072 static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1073 				      enum aux_cmd_type cmd,
1074 				      unsigned int address, u8 *buffer,
1075 				      size_t size, enum aux_cmd_reply *reply)
1076 {
1077 	int i, ret_size, ret = 0, request_size;
1078 
1079 	mutex_lock(&it6505->aux_lock);
1080 	for (i = 0; i < size; i += 4) {
1081 		request_size = min((int)size - i, 4);
1082 		ret_size = it6505_aux_operation(it6505, cmd, address + i,
1083 						buffer + i, request_size,
1084 						reply);
1085 		if (ret_size < 0) {
1086 			ret = ret_size;
1087 			goto aux_op_err;
1088 		}
1089 
1090 		ret += ret_size;
1091 	}
1092 
1093 aux_op_err:
1094 	mutex_unlock(&it6505->aux_lock);
1095 	return ret;
1096 }
1097 
1098 static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1099 				   struct drm_dp_aux_msg *msg)
1100 {
1101 	struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1102 	u8 cmd;
1103 	bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1104 	int ret;
1105 	enum aux_cmd_reply reply;
1106 
1107 	/* IT6505 doesn't support arbitrary I2C read / write. */
1108 	if (is_i2c)
1109 		return -EINVAL;
1110 
1111 	switch (msg->request) {
1112 	case DP_AUX_NATIVE_READ:
1113 		cmd = CMD_AUX_NATIVE_READ;
1114 		break;
1115 	case DP_AUX_NATIVE_WRITE:
1116 		cmd = CMD_AUX_NATIVE_WRITE;
1117 		break;
1118 	default:
1119 		return -EINVAL;
1120 	}
1121 
1122 	ret = it6505_aux_do_transfer(it6505, cmd, msg->address, msg->buffer,
1123 				     msg->size, &reply);
1124 	if (ret < 0)
1125 		return ret;
1126 
1127 	switch (reply) {
1128 	case REPLY_ACK:
1129 		msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1130 		break;
1131 	case REPLY_NACK:
1132 		msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1133 		break;
1134 	case REPLY_DEFER:
1135 		msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1136 		break;
1137 	}
1138 
1139 	return ret;
1140 }
1141 
1142 static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1143 				 size_t len)
1144 {
1145 	struct it6505 *it6505 = data;
1146 	struct device *dev = &it6505->client->dev;
1147 	enum aux_cmd_reply reply;
1148 	int offset, ret, aux_retry = 100;
1149 
1150 	it6505_aux_reset(it6505);
1151 	DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1152 
1153 	for (offset = 0; offset < EDID_LENGTH;) {
1154 		ret = it6505_aux_do_transfer(it6505, CMD_AUX_I2C_EDID_READ,
1155 					     block * EDID_LENGTH + offset,
1156 					     buf + offset, 8, &reply);
1157 
1158 		if (ret < 0 && ret != -EAGAIN)
1159 			return ret;
1160 
1161 		switch (reply) {
1162 		case REPLY_ACK:
1163 			DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1164 					     buf + offset);
1165 			offset += 8;
1166 			aux_retry = 100;
1167 			break;
1168 		case REPLY_NACK:
1169 			return -EIO;
1170 		case REPLY_DEFER:
1171 			msleep(20);
1172 			if (!(--aux_retry))
1173 				return -EIO;
1174 		}
1175 	}
1176 
1177 	return 0;
1178 }
1179 
1180 static void it6505_variable_config(struct it6505 *it6505)
1181 {
1182 	it6505->link_rate_bw_code = HBR;
1183 	it6505->lane_count = MAX_LANE_COUNT;
1184 	it6505->link_state = LINK_IDLE;
1185 	it6505->hdcp_desired = HDCP_DESIRED;
1186 	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1187 	it6505->audio.select = AUDIO_SELECT;
1188 	it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1189 	it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1190 	it6505->audio.type = AUDIO_TYPE;
1191 	it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1192 	it6505->audio.i2s_justified = I2S_JUSTIFIED;
1193 	it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1194 	it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1195 	it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1196 	it6505->audio.word_length = AUDIO_WORD_LENGTH;
1197 	memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1198 	memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1199 }
1200 
1201 static int it6505_send_video_infoframe(struct it6505 *it6505,
1202 				       struct hdmi_avi_infoframe *frame)
1203 {
1204 	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1205 	int err;
1206 	struct device *dev = &it6505->client->dev;
1207 
1208 	err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
1209 	if (err < 0) {
1210 		dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1211 		return err;
1212 	}
1213 
1214 	err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, 0x00);
1215 	if (err)
1216 		return err;
1217 
1218 	err = regmap_bulk_write(it6505->regmap, REG_AVI_INFO_DB1,
1219 				buffer + HDMI_INFOFRAME_HEADER_SIZE,
1220 				frame->length);
1221 	if (err)
1222 		return err;
1223 
1224 	err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1225 			      EN_AVI_PKT);
1226 	if (err)
1227 		return err;
1228 
1229 	return 0;
1230 }
1231 
1232 static void it6505_get_extcon_property(struct it6505 *it6505)
1233 {
1234 	int err;
1235 	union extcon_property_value property;
1236 	struct device *dev = &it6505->client->dev;
1237 
1238 	if (it6505->extcon && !it6505->lane_swap_disabled) {
1239 		err = extcon_get_property(it6505->extcon, EXTCON_DISP_DP,
1240 					  EXTCON_PROP_USB_TYPEC_POLARITY,
1241 					  &property);
1242 		if (err) {
1243 			dev_err(dev, "get property fail!");
1244 			return;
1245 		}
1246 		it6505->lane_swap = property.intval;
1247 	}
1248 }
1249 
1250 static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1251 					const struct drm_display_mode *mode)
1252 {
1253 	int clock = mode->clock;
1254 
1255 	it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1256 			clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1257 	it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1258 			PIXEL_CLK_INVERSE << 4);
1259 }
1260 
1261 static void it6505_link_reset_step_train(struct it6505 *it6505)
1262 {
1263 	it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1264 			FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1265 	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1266 			  DP_TRAINING_PATTERN_DISABLE);
1267 }
1268 
1269 static void it6505_init(struct it6505 *it6505)
1270 {
1271 	it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1272 	it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1273 	it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1274 	it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1275 	it6505_write(it6505, REG_VID_BUS_CTRL1, 0x01);
1276 	it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1277 
1278 	/* chip internal setting, don't modify */
1279 	it6505_write(it6505, REG_HPD_IRQ_TIME, 0xF5);
1280 	it6505_write(it6505, REG_AUX_DEBUG_MODE, 0x4D);
1281 	it6505_write(it6505, REG_AUX_OPT2, 0x17);
1282 	it6505_write(it6505, REG_HDCP_OPT, 0x60);
1283 	it6505_write(it6505, REG_DATA_MUTE_CTRL,
1284 		     EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1285 	it6505_write(it6505, REG_TIME_STMP_CTRL,
1286 		     EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1287 	it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00);
1288 	it6505_write(it6505, REG_BANK_SEL, 0x01);
1289 	it6505_write(it6505, REG_DRV_0_DB_800_MV,
1290 		     afe_setting_table[it6505->afe_setting][0]);
1291 	it6505_write(it6505, REG_PRE_0_DB_800_MV,
1292 		     afe_setting_table[it6505->afe_setting][1]);
1293 	it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1294 		     afe_setting_table[it6505->afe_setting][2]);
1295 	it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1296 	it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1297 	it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1298 	it6505_write(it6505, REG_BANK_SEL, 0x00);
1299 }
1300 
1301 static void it6505_video_disable(struct it6505 *it6505)
1302 {
1303 	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1304 	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1305 	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1306 }
1307 
1308 static void it6505_video_reset(struct it6505 *it6505)
1309 {
1310 	it6505_link_reset_step_train(it6505);
1311 	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1312 	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1313 	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1314 	it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1315 	it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);
1316 	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);
1317 }
1318 
1319 static void it6505_update_video_parameter(struct it6505 *it6505,
1320 					  const struct drm_display_mode *mode)
1321 {
1322 	it6505_clk_phase_adjustment(it6505, mode);
1323 	it6505_video_disable(it6505);
1324 }
1325 
1326 static bool it6505_audio_input(struct it6505 *it6505)
1327 {
1328 	int reg05, regbe;
1329 
1330 	reg05 = it6505_read(it6505, REG_RESET_CTRL);
1331 	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1332 	usleep_range(3000, 4000);
1333 	regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1334 	it6505_write(it6505, REG_RESET_CTRL, reg05);
1335 
1336 	return regbe != 0xFF;
1337 }
1338 
1339 static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1340 {
1341 	enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1342 	u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1343 
1344 	/* Channel Status */
1345 	it6505_write(it6505, REG_IEC958_STS0, it6505->audio.type << 1);
1346 	it6505_write(it6505, REG_IEC958_STS1, 0x00);
1347 	it6505_write(it6505, REG_IEC958_STS2, 0x00);
1348 	it6505_write(it6505, REG_IEC958_STS3, sample_rate);
1349 	it6505_write(it6505, REG_IEC958_STS4, (~sample_rate << 4) |
1350 		     audio_word_length_map[it6505->audio.word_length]);
1351 }
1352 
1353 static void it6505_setup_audio_format(struct it6505 *it6505)
1354 {
1355 	/* I2S MODE */
1356 	it6505_write(it6505, REG_AUDIO_FMT,
1357 		     (it6505->audio.word_length << 5) |
1358 		     (it6505->audio.i2s_data_sequence << 4) |
1359 		     (it6505->audio.i2s_ws_channel << 3) |
1360 		     (it6505->audio.i2s_data_delay << 2) |
1361 		     (it6505->audio.i2s_justified << 1) |
1362 		     it6505->audio.i2s_input_format);
1363 	if (it6505->audio.select == SPDIF) {
1364 		it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0x00);
1365 		/* 0x30 = 128*FS */
1366 		it6505_set_bits(it6505, REG_AUX_OPT, 0xF0, 0x30);
1367 	} else {
1368 		it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0xE4);
1369 	}
1370 
1371 	it6505_write(it6505, REG_AUDIO_CTRL0, 0x20);
1372 	it6505_write(it6505, REG_AUDIO_CTRL1, 0x00);
1373 }
1374 
1375 static void it6505_enable_audio_source(struct it6505 *it6505)
1376 {
1377 	unsigned int audio_source_count;
1378 
1379 	audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1380 				 - 1;
1381 
1382 	audio_source_count |= it6505->audio.select << 4;
1383 
1384 	it6505_write(it6505, REG_AUDIO_SRC_CTRL, audio_source_count);
1385 }
1386 
1387 static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1388 {
1389 	struct device *dev = &it6505->client->dev;
1390 	u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1391 
1392 	DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1393 			     audio_info_ca[it6505->audio.channel_count - 1]);
1394 
1395 	it6505_write(it6505, REG_AUD_INFOFRAM_DB1, it6505->audio.channel_count
1396 		     - 1);
1397 	it6505_write(it6505, REG_AUD_INFOFRAM_DB2, 0x00);
1398 	it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1399 		     audio_info_ca[it6505->audio.channel_count - 1]);
1400 	it6505_write(it6505, REG_AUD_INFOFRAM_DB4, 0x00);
1401 	it6505_write(it6505, REG_AUD_INFOFRAM_SUM, 0x00);
1402 
1403 	/* Enable Audio InfoFrame */
1404 	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1405 			EN_AUD_CTRL_PKT);
1406 }
1407 
1408 static void it6505_disable_audio(struct it6505 *it6505)
1409 {
1410 	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1411 	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, 0x00);
1412 	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, 0x00);
1413 	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1414 }
1415 
1416 static void it6505_enable_audio(struct it6505 *it6505)
1417 {
1418 	struct device *dev = &it6505->client->dev;
1419 	int regbe;
1420 
1421 	DRM_DEV_DEBUG_DRIVER(dev, "start");
1422 	it6505_disable_audio(it6505);
1423 
1424 	it6505_setup_audio_channel_status(it6505);
1425 	it6505_setup_audio_format(it6505);
1426 	it6505_enable_audio_source(it6505);
1427 	it6505_enable_audio_infoframe(it6505);
1428 
1429 	it6505_write(it6505, REG_AUDIO_N_0_7, 0x00);
1430 	it6505_write(it6505, REG_AUDIO_N_8_15, 0x80);
1431 	it6505_write(it6505, REG_AUDIO_N_16_23, 0x00);
1432 
1433 	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1434 			AUDIO_FIFO_RESET);
1435 	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, 0x00);
1436 	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1437 	regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1438 	DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1439 			     regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1440 	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, 0x00);
1441 }
1442 
1443 static bool it6505_use_step_train_check(struct it6505 *it6505)
1444 {
1445 	if (it6505->link.revision >= 0x12)
1446 		return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1447 
1448 	return true;
1449 }
1450 
1451 static void it6505_parse_link_capabilities(struct it6505 *it6505)
1452 {
1453 	struct device *dev = &it6505->client->dev;
1454 	struct it6505_drm_dp_link *link = &it6505->link;
1455 	int bcaps;
1456 
1457 	if (it6505->dpcd[0] == 0) {
1458 		it6505_aux_on(it6505);
1459 		it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
1460 				ARRAY_SIZE(it6505->dpcd));
1461 	}
1462 
1463 	DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1464 			     link->revision >> 4, link->revision & 0x0F);
1465 
1466 	DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1467 			     link->rate / 100000, link->rate / 1000 % 100);
1468 
1469 	it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link->rate);
1470 	DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1471 			     it6505->link_rate_bw_code);
1472 	it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1473 					  MAX_LINK_RATE);
1474 
1475 	it6505->lane_count = link->num_lanes;
1476 	DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1477 			     it6505->lane_count);
1478 	it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT);
1479 
1480 	it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
1481 	DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1482 			     it6505->branch_device ? "" : "Not ");
1483 
1484 	it6505->enable_enhanced_frame = link->capabilities;
1485 	DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1486 			     it6505->enable_enhanced_frame ? "" : "Not ");
1487 
1488 	it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1489 				DP_MAX_DOWNSPREAD_0_5);
1490 	DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1491 			     it6505->enable_ssc ? "0.5" : "0",
1492 			     it6505->enable_ssc ? "" : "Not ");
1493 
1494 	it6505->step_train = it6505_use_step_train_check(it6505);
1495 	if (it6505->step_train)
1496 		DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1497 
1498 	bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1499 	DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1500 	if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1501 		it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1502 		DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1503 				     it6505->is_repeater ? "repeater" :
1504 				     "receiver");
1505 	} else {
1506 		DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1507 		it6505->hdcp_desired = false;
1508 	}
1509 	DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1510 			     it6505->hdcp_desired ? "desired" : "undesired");
1511 }
1512 
1513 static void it6505_setup_ssc(struct it6505 *it6505)
1514 {
1515 	it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1516 			it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1517 	if (it6505->enable_ssc) {
1518 		it6505_write(it6505, REG_BANK_SEL, 0x01);
1519 		it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1520 		it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1521 		it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1522 		it6505_write(it6505, REG_BANK_SEL, 0x00);
1523 		it6505_write(it6505, REG_SP_CTRL0, 0x07);
1524 		it6505_write(it6505, REG_IP_CTRL1, 0x29);
1525 		it6505_write(it6505, REG_IP_CTRL2, 0x03);
1526 		/* Stamp Interrupt Step */
1527 		it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1528 				0x10);
1529 		it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1530 				  DP_SPREAD_AMP_0_5);
1531 	} else {
1532 		it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, 0x00);
1533 		it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1534 				0x00);
1535 	}
1536 }
1537 
1538 static inline void it6505_link_rate_setup(struct it6505 *it6505)
1539 {
1540 	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1541 			(it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1542 	it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1543 			(it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1544 }
1545 
1546 static void it6505_lane_count_setup(struct it6505 *it6505)
1547 {
1548 	it6505_get_extcon_property(it6505);
1549 	it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1550 			it6505->lane_swap ? LANE_SWAP : 0x00);
1551 	it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1552 			(it6505->lane_count - 1) << 1);
1553 }
1554 
1555 static void it6505_link_training_setup(struct it6505 *it6505)
1556 {
1557 	struct device *dev = &it6505->client->dev;
1558 
1559 	if (it6505->enable_enhanced_frame)
1560 		it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1561 				ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1562 
1563 	it6505_link_rate_setup(it6505);
1564 	it6505_lane_count_setup(it6505);
1565 	it6505_setup_ssc(it6505);
1566 	DRM_DEV_DEBUG_DRIVER(dev,
1567 			     "%s, %d lanes, %sable ssc, %sable enhanced frame",
1568 			     it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1569 			     it6505->lane_count,
1570 			     it6505->enable_ssc ? "en" : "dis",
1571 			     it6505->enable_enhanced_frame ? "en" : "dis");
1572 }
1573 
1574 static bool it6505_link_start_auto_train(struct it6505 *it6505)
1575 {
1576 	int timeout = 500, link_training_state;
1577 	bool state = false;
1578 
1579 	mutex_lock(&it6505->aux_lock);
1580 	it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1581 			FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1582 	it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1583 	it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1584 
1585 	while (timeout > 0) {
1586 		usleep_range(1000, 2000);
1587 		link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1588 
1589 		if (link_training_state > 0 &&
1590 		    (link_training_state & LINK_STATE_NORP)) {
1591 			state = true;
1592 			goto unlock;
1593 		}
1594 
1595 		timeout--;
1596 	}
1597 unlock:
1598 	mutex_unlock(&it6505->aux_lock);
1599 
1600 	return state;
1601 }
1602 
1603 static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1604 {
1605 	u8 values[2];
1606 	int err;
1607 	struct drm_dp_aux *aux = &it6505->aux;
1608 
1609 	values[0] = it6505->link_rate_bw_code;
1610 	values[1] = it6505->lane_count;
1611 
1612 	if (it6505->enable_enhanced_frame)
1613 		values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1614 
1615 	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
1616 	if (err < 0)
1617 		return err;
1618 
1619 	return 0;
1620 }
1621 
1622 static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1623 {
1624 	return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1625 }
1626 
1627 static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1628 {
1629 	return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1630 }
1631 
1632 static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1633 						   u8 lane_count)
1634 {
1635 	u8 i;
1636 
1637 	for (i = 0; i < lane_count; i++) {
1638 		if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1639 			return true;
1640 	}
1641 
1642 	return false;
1643 }
1644 
1645 static bool
1646 step_train_lane_voltage_para_set(struct it6505 *it6505,
1647 				 struct it6505_step_train_para
1648 				 *lane_voltage_pre_emphasis,
1649 				 u8 *lane_voltage_pre_emphasis_set)
1650 {
1651 	u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1652 	u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1653 	u8 i;
1654 
1655 	for (i = 0; i < it6505->lane_count; i++) {
1656 		voltage_swing[i] &= 0x03;
1657 		lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1658 		if (it6505_check_voltage_swing_max(voltage_swing[i]))
1659 			lane_voltage_pre_emphasis_set[i] |=
1660 				DP_TRAIN_MAX_SWING_REACHED;
1661 
1662 		pre_emphasis[i] &= 0x03;
1663 		lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1664 			<< DP_TRAIN_PRE_EMPHASIS_SHIFT;
1665 		if (it6505_check_pre_emphasis_max(pre_emphasis[i]))
1666 			lane_voltage_pre_emphasis_set[i] |=
1667 				DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1668 		it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1669 				  lane_voltage_pre_emphasis_set[i]);
1670 
1671 		if (lane_voltage_pre_emphasis_set[i] !=
1672 		    it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1673 			return false;
1674 	}
1675 
1676 	return true;
1677 }
1678 
1679 static bool
1680 it6505_step_cr_train(struct it6505 *it6505,
1681 		     struct it6505_step_train_para *lane_voltage_pre_emphasis)
1682 {
1683 	u8 loop_count = 0, i = 0, j;
1684 	u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1685 	u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1686 	int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1687 	const struct drm_dp_aux *aux = &it6505->aux;
1688 
1689 	it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1690 			  it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1691 	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1692 			  DP_TRAINING_PATTERN_1);
1693 
1694 	while (loop_count < 5 && i < 10) {
1695 		i++;
1696 		if (!step_train_lane_voltage_para_set(it6505,
1697 						      lane_voltage_pre_emphasis,
1698 						      lane_level_config))
1699 			continue;
1700 		drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);
1701 		drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1702 
1703 		if (drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) {
1704 			it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1705 					FORCE_CR_DONE);
1706 			return true;
1707 		}
1708 		DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "cr not done");
1709 
1710 		if (it6505_check_max_voltage_swing_reached(lane_level_config,
1711 							   it6505->lane_count))
1712 			goto cr_train_fail;
1713 
1714 		for (j = 0; j < it6505->lane_count; j++) {
1715 			lane_voltage_pre_emphasis->voltage_swing[j] =
1716 				drm_dp_get_adjust_request_voltage(link_status,
1717 								  j) >>
1718 				DP_TRAIN_VOLTAGE_SWING_SHIFT;
1719 			lane_voltage_pre_emphasis->pre_emphasis[j] =
1720 			drm_dp_get_adjust_request_pre_emphasis(link_status,
1721 							       j) >>
1722 					DP_TRAIN_PRE_EMPHASIS_SHIFT;
1723 			if (voltage_swing_adjust ==
1724 			     lane_voltage_pre_emphasis->voltage_swing[j] &&
1725 			    pre_emphasis_adjust ==
1726 			     lane_voltage_pre_emphasis->pre_emphasis[j]) {
1727 				loop_count++;
1728 				continue;
1729 			}
1730 
1731 			voltage_swing_adjust =
1732 				lane_voltage_pre_emphasis->voltage_swing[j];
1733 			pre_emphasis_adjust =
1734 				lane_voltage_pre_emphasis->pre_emphasis[j];
1735 			loop_count = 0;
1736 
1737 			if (voltage_swing_adjust + pre_emphasis_adjust >
1738 			    MAX_EQ_LEVEL)
1739 				lane_voltage_pre_emphasis->voltage_swing[j] =
1740 					MAX_EQ_LEVEL -
1741 					lane_voltage_pre_emphasis
1742 						->pre_emphasis[j];
1743 		}
1744 	}
1745 
1746 cr_train_fail:
1747 	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1748 			  DP_TRAINING_PATTERN_DISABLE);
1749 
1750 	return false;
1751 }
1752 
1753 static bool
1754 it6505_step_eq_train(struct it6505 *it6505,
1755 		     struct it6505_step_train_para *lane_voltage_pre_emphasis)
1756 {
1757 	u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1758 	u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1759 	const struct drm_dp_aux *aux = &it6505->aux;
1760 
1761 	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1762 			  DP_TRAINING_PATTERN_2);
1763 
1764 	while (loop_count < 6) {
1765 		loop_count++;
1766 
1767 		if (!step_train_lane_voltage_para_set(it6505,
1768 						      lane_voltage_pre_emphasis,
1769 						      lane_level_config))
1770 			continue;
1771 
1772 		drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);
1773 		drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1774 
1775 		if (!drm_dp_clock_recovery_ok(link_status, it6505->lane_count))
1776 			goto eq_train_fail;
1777 
1778 		if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
1779 			it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1780 					  DP_TRAINING_PATTERN_DISABLE);
1781 			it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1782 					FORCE_EQ_DONE);
1783 			return true;
1784 		}
1785 		DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "eq not done");
1786 
1787 		for (i = 0; i < it6505->lane_count; i++) {
1788 			lane_voltage_pre_emphasis->voltage_swing[i] =
1789 				drm_dp_get_adjust_request_voltage(link_status,
1790 								  i) >>
1791 				DP_TRAIN_VOLTAGE_SWING_SHIFT;
1792 			lane_voltage_pre_emphasis->pre_emphasis[i] =
1793 			drm_dp_get_adjust_request_pre_emphasis(link_status,
1794 							       i) >>
1795 					DP_TRAIN_PRE_EMPHASIS_SHIFT;
1796 
1797 			if (lane_voltage_pre_emphasis->voltage_swing[i] +
1798 				    lane_voltage_pre_emphasis->pre_emphasis[i] >
1799 			    MAX_EQ_LEVEL)
1800 				lane_voltage_pre_emphasis->voltage_swing[i] =
1801 					0x03 - lane_voltage_pre_emphasis
1802 						       ->pre_emphasis[i];
1803 		}
1804 	}
1805 
1806 eq_train_fail:
1807 	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1808 			  DP_TRAINING_PATTERN_DISABLE);
1809 	return false;
1810 }
1811 
1812 static bool it6505_link_start_step_train(struct it6505 *it6505)
1813 {
1814 	int err;
1815 	struct it6505_step_train_para lane_voltage_pre_emphasis = {
1816 		.voltage_swing = { 0 },
1817 		.pre_emphasis = { 0 },
1818 	};
1819 
1820 	DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "start");
1821 	err = it6505_drm_dp_link_configure(it6505);
1822 
1823 	if (err < 0)
1824 		return false;
1825 	if (!it6505_step_cr_train(it6505, &lane_voltage_pre_emphasis))
1826 		return false;
1827 	if (!it6505_step_eq_train(it6505, &lane_voltage_pre_emphasis))
1828 		return false;
1829 	return true;
1830 }
1831 
1832 static bool it6505_get_video_status(struct it6505 *it6505)
1833 {
1834 	int reg_0d;
1835 
1836 	reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
1837 
1838 	if (reg_0d < 0)
1839 		return false;
1840 
1841 	return reg_0d & VIDEO_STB;
1842 }
1843 
1844 static void it6505_reset_hdcp(struct it6505 *it6505)
1845 {
1846 	it6505->hdcp_status = HDCP_AUTH_IDLE;
1847 	/* Disable CP_Desired */
1848 	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1849 	it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
1850 }
1851 
1852 static void it6505_start_hdcp(struct it6505 *it6505)
1853 {
1854 	struct device *dev = &it6505->client->dev;
1855 
1856 	DRM_DEV_DEBUG_DRIVER(dev, "start");
1857 	it6505_reset_hdcp(it6505);
1858 	queue_delayed_work(system_wq, &it6505->hdcp_work,
1859 			   msecs_to_jiffies(2400));
1860 }
1861 
1862 static void it6505_stop_hdcp(struct it6505 *it6505)
1863 {
1864 	it6505_reset_hdcp(it6505);
1865 	cancel_delayed_work(&it6505->hdcp_work);
1866 }
1867 
1868 static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
1869 {
1870 	int i, ones = 0;
1871 
1872 	/* KSV has 20 1's and 20 0's */
1873 	for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
1874 		ones += hweight8(ksv[i]);
1875 	if (ones != 20)
1876 		return false;
1877 	return true;
1878 }
1879 
1880 static void it6505_hdcp_part1_auth(struct it6505 *it6505)
1881 {
1882 	struct device *dev = &it6505->client->dev;
1883 	u8 hdcp_bcaps;
1884 
1885 	it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, 0x00);
1886 	/* Disable CP_Desired */
1887 	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1888 
1889 	usleep_range(1000, 1500);
1890 	hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1891 	DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
1892 			     hdcp_bcaps);
1893 
1894 	if (!hdcp_bcaps)
1895 		return;
1896 
1897 	/* clear the repeater List Chk Done and fail bit */
1898 	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
1899 			HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
1900 			0x00);
1901 
1902 	/* Enable An Generator */
1903 	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
1904 	/* delay1ms(10);*/
1905 	usleep_range(10000, 15000);
1906 	/* Stop An Generator */
1907 	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, 0x00);
1908 
1909 	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
1910 
1911 	it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
1912 			HDCP_TRIGGER_START);
1913 
1914 	it6505->hdcp_status = HDCP_AUTH_GOING;
1915 }
1916 
1917 static int it6505_sha1_digest(struct it6505 *it6505, u8 *sha1_input,
1918 			      unsigned int size, u8 *output_av)
1919 {
1920 	struct shash_desc *desc;
1921 	struct crypto_shash *tfm;
1922 	int err;
1923 	struct device *dev = &it6505->client->dev;
1924 
1925 	tfm = crypto_alloc_shash("sha1", 0, 0);
1926 	if (IS_ERR(tfm)) {
1927 		dev_err(dev, "crypto_alloc_shash sha1 failed");
1928 		return PTR_ERR(tfm);
1929 	}
1930 	desc = kzalloc(sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
1931 	if (!desc) {
1932 		crypto_free_shash(tfm);
1933 		return -ENOMEM;
1934 	}
1935 
1936 	desc->tfm = tfm;
1937 	err = crypto_shash_digest(desc, sha1_input, size, output_av);
1938 	if (err)
1939 		dev_err(dev, "crypto_shash_digest sha1 failed");
1940 
1941 	crypto_free_shash(tfm);
1942 	kfree(desc);
1943 	return err;
1944 }
1945 
1946 static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
1947 {
1948 	struct device *dev = &it6505->client->dev;
1949 	u8 binfo[2];
1950 	int down_stream_count, i, err, msg_count = 0;
1951 
1952 	err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, binfo,
1953 			      ARRAY_SIZE(binfo));
1954 
1955 	if (err < 0) {
1956 		dev_err(dev, "Read binfo value Fail");
1957 		return err;
1958 	}
1959 
1960 	down_stream_count = binfo[0] & 0x7F;
1961 	DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
1962 			     binfo);
1963 
1964 	if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
1965 		dev_err(dev, "HDCP max cascade device exceed");
1966 		return 0;
1967 	}
1968 
1969 	if (!down_stream_count ||
1970 	    down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
1971 		dev_err(dev, "HDCP down stream count Error %d",
1972 			down_stream_count);
1973 		return 0;
1974 	}
1975 
1976 	for (i = 0; i < down_stream_count; i++) {
1977 		err = it6505_get_dpcd(it6505, DP_AUX_HDCP_KSV_FIFO +
1978 				      (i % 3) * DRM_HDCP_KSV_LEN,
1979 				      sha1_input + msg_count,
1980 				      DRM_HDCP_KSV_LEN);
1981 
1982 		if (err < 0)
1983 			return err;
1984 
1985 		msg_count += 5;
1986 	}
1987 
1988 	it6505->hdcp_down_stream_count = down_stream_count;
1989 	sha1_input[msg_count++] = binfo[0];
1990 	sha1_input[msg_count++] = binfo[1];
1991 
1992 	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
1993 			HDCP_EN_M0_READ);
1994 
1995 	err = regmap_bulk_read(it6505->regmap, REG_M0_0_7,
1996 			       sha1_input + msg_count, 8);
1997 
1998 	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, 0x00);
1999 
2000 	if (err < 0) {
2001 		dev_err(dev, " Warning, Read M value Fail");
2002 		return err;
2003 	}
2004 
2005 	msg_count += 8;
2006 
2007 	return msg_count;
2008 }
2009 
2010 static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
2011 {
2012 	struct device *dev = &it6505->client->dev;
2013 	u8 av[5][4], bv[5][4];
2014 	int i, err;
2015 
2016 	i = it6505_setup_sha1_input(it6505, it6505->sha1_input);
2017 	if (i <= 0) {
2018 		dev_err(dev, "SHA-1 Input length error %d", i);
2019 		return false;
2020 	}
2021 
2022 	it6505_sha1_digest(it6505, it6505->sha1_input, i, (u8 *)av);
2023 
2024 	err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), (u8 *)bv,
2025 			      sizeof(bv));
2026 
2027 	if (err < 0) {
2028 		dev_err(dev, "Read V' value Fail");
2029 		return false;
2030 	}
2031 
2032 	for (i = 0; i < 5; i++)
2033 		if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2034 		    bv[i][1] != av[i][2] || bv[i][0] != av[i][3])
2035 			return false;
2036 
2037 	DRM_DEV_DEBUG_DRIVER(dev, "V' all match!!");
2038 	return true;
2039 }
2040 
2041 static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2042 {
2043 	struct it6505 *it6505 = container_of(work, struct it6505,
2044 					     hdcp_wait_ksv_list);
2045 	struct device *dev = &it6505->client->dev;
2046 	unsigned int timeout = 5000;
2047 	u8 bstatus = 0;
2048 	bool ksv_list_check;
2049 
2050 	timeout /= 20;
2051 	while (timeout > 0) {
2052 		if (!it6505_get_sink_hpd_status(it6505))
2053 			return;
2054 
2055 		bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2056 
2057 		if (bstatus & DP_BSTATUS_READY)
2058 			break;
2059 
2060 		msleep(20);
2061 		timeout--;
2062 	}
2063 
2064 	if (timeout == 0) {
2065 		DRM_DEV_DEBUG_DRIVER(dev, "timeout and ksv list wait failed");
2066 		goto timeout;
2067 	}
2068 
2069 	ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2070 	DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2071 			     ksv_list_check ? "pass" : "fail");
2072 	if (ksv_list_check) {
2073 		it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2074 				HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2075 		return;
2076 	}
2077 timeout:
2078 	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2079 			HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
2080 			HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL);
2081 }
2082 
2083 static void it6505_hdcp_work(struct work_struct *work)
2084 {
2085 	struct it6505 *it6505 = container_of(work, struct it6505,
2086 					     hdcp_work.work);
2087 	struct device *dev = &it6505->client->dev;
2088 	int ret;
2089 	u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2090 
2091 	DRM_DEV_DEBUG_DRIVER(dev, "start");
2092 
2093 	if (!it6505_get_sink_hpd_status(it6505))
2094 		return;
2095 
2096 	ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2097 	DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2098 			     (int)sizeof(link_status), link_status);
2099 
2100 	if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
2101 	    !it6505_get_video_status(it6505)) {
2102 		DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2103 		return;
2104 	}
2105 
2106 	ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, it6505->bksvs,
2107 			      ARRAY_SIZE(it6505->bksvs));
2108 	if (ret < 0) {
2109 		dev_err(dev, "fail to get bksv  ret: %d", ret);
2110 		it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2111 				HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2112 	}
2113 
2114 	DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2115 			     (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2116 
2117 	if (!it6505_hdcp_is_ksv_valid(it6505->bksvs)) {
2118 		dev_err(dev, "Display Port bksv not valid");
2119 		it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2120 				HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2121 	}
2122 
2123 	it6505_hdcp_part1_auth(it6505);
2124 }
2125 
2126 static void it6505_show_hdcp_info(struct it6505 *it6505)
2127 {
2128 	struct device *dev = &it6505->client->dev;
2129 	int i;
2130 	u8 *sha1 = it6505->sha1_input;
2131 
2132 	DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2133 			     it6505->hdcp_status, it6505->is_repeater);
2134 	DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2135 			     (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2136 
2137 	if (it6505->is_repeater) {
2138 		DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2139 				     it6505->hdcp_down_stream_count);
2140 		DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2141 				     (int)ARRAY_SIZE(it6505->sha1_input),
2142 				     it6505->sha1_input);
2143 		for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2144 			DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2145 					     DRM_HDCP_KSV_LEN, sha1);
2146 			sha1 += DRM_HDCP_KSV_LEN;
2147 		}
2148 		DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2149 				     sha1, sha1 + 2);
2150 	}
2151 }
2152 
2153 static void it6505_stop_link_train(struct it6505 *it6505)
2154 {
2155 	it6505->link_state = LINK_IDLE;
2156 	cancel_work_sync(&it6505->link_works);
2157 	it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2158 }
2159 
2160 static void it6505_link_train_ok(struct it6505 *it6505)
2161 {
2162 	struct device *dev = &it6505->client->dev;
2163 
2164 	it6505->link_state = LINK_OK;
2165 	/* disalbe mute enable avi info frame */
2166 	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, 0x00);
2167 	it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2168 			EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2169 
2170 	if (it6505_audio_input(it6505)) {
2171 		DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2172 		it6505_enable_audio(it6505);
2173 	}
2174 
2175 	if (it6505->hdcp_desired)
2176 		it6505_start_hdcp(it6505);
2177 }
2178 
2179 static void it6505_link_step_train_process(struct it6505 *it6505)
2180 {
2181 	struct device *dev = &it6505->client->dev;
2182 	int ret, i, step_retry = 3;
2183 
2184 	DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2185 
2186 	if (it6505->sink_count == 0) {
2187 		DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2188 				     it6505->sink_count);
2189 		it6505_set_bits(it6505,	REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2190 				FORCE_EQ_DONE);
2191 		return;
2192 	}
2193 
2194 	if (!it6505->step_train) {
2195 		DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2196 		return;
2197 	}
2198 
2199 	/* step training start here */
2200 	for (i = 0; i < step_retry; i++) {
2201 		it6505_link_reset_step_train(it6505);
2202 		ret = it6505_link_start_step_train(it6505);
2203 		DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2204 				     ret ? "pass" : "failed", i + 1);
2205 		if (ret) {
2206 			it6505_link_train_ok(it6505);
2207 			return;
2208 		}
2209 	}
2210 
2211 	DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2212 	it6505->link_state = LINK_IDLE;
2213 	it6505_video_reset(it6505);
2214 }
2215 
2216 static void it6505_link_training_work(struct work_struct *work)
2217 {
2218 	struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2219 	struct device *dev = &it6505->client->dev;
2220 	int ret;
2221 
2222 	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2223 			     it6505->sink_count);
2224 
2225 	if (!it6505_get_sink_hpd_status(it6505))
2226 		return;
2227 
2228 	it6505_link_training_setup(it6505);
2229 	it6505_reset_hdcp(it6505);
2230 	it6505_aux_reset(it6505);
2231 
2232 	if (it6505->auto_train_retry < 1) {
2233 		it6505_link_step_train_process(it6505);
2234 		return;
2235 	}
2236 
2237 	ret = it6505_link_start_auto_train(it6505);
2238 	DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2239 			     ret ? "pass" : "failed", it6505->auto_train_retry);
2240 	it6505->auto_train_retry--;
2241 
2242 	if (ret) {
2243 		it6505_link_train_ok(it6505);
2244 		return;
2245 	}
2246 
2247 	it6505_dump(it6505);
2248 }
2249 
2250 static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2251 {
2252 	enum drm_connector_status status = it6505->connector_status;
2253 
2254 	if (it6505->plugged_cb && it6505->codec_dev)
2255 		it6505->plugged_cb(it6505->codec_dev,
2256 				   status == connector_status_connected);
2257 }
2258 
2259 static int it6505_process_hpd_irq(struct it6505 *it6505)
2260 {
2261 	struct device *dev = &it6505->client->dev;
2262 	int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2263 	u8 link_status[DP_LINK_STATUS_SIZE];
2264 
2265 	if (!it6505_get_sink_hpd_status(it6505)) {
2266 		DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2267 		it6505->sink_count = 0;
2268 		return 0;
2269 	}
2270 
2271 	ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2272 	if (ret < 0)
2273 		return ret;
2274 
2275 	dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2276 	DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2277 			     dpcd_sink_count, it6505->sink_count);
2278 
2279 	if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2280 		memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2281 		it6505->sink_count = dpcd_sink_count;
2282 		it6505_reset_logic(it6505);
2283 		it6505_int_mask_enable(it6505);
2284 		it6505_init(it6505);
2285 		return 0;
2286 	}
2287 
2288 	dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2289 	if (dp_irq_vector < 0)
2290 		return dp_irq_vector;
2291 
2292 	DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2293 
2294 	if (dp_irq_vector & DP_CP_IRQ) {
2295 		it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2296 				HDCP_TRIGGER_CPIRQ);
2297 
2298 		bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2299 		if (bstatus < 0)
2300 			return bstatus;
2301 
2302 		DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2303 	}
2304 
2305 	ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2306 	if (ret < 0) {
2307 		dev_err(dev, "Fail to read link status ret: %d", ret);
2308 		return ret;
2309 	}
2310 
2311 	DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2312 			     (int)ARRAY_SIZE(link_status), link_status);
2313 
2314 	if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
2315 		it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2316 		it6505_video_reset(it6505);
2317 	}
2318 
2319 	return 0;
2320 }
2321 
2322 static void it6505_irq_hpd(struct it6505 *it6505)
2323 {
2324 	struct device *dev = &it6505->client->dev;
2325 
2326 	it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2327 	DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2328 			     it6505->hpd_state ? "high" : "low");
2329 
2330 	if (it6505->bridge.dev)
2331 		drm_helper_hpd_irq_event(it6505->bridge.dev);
2332 	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2333 			     it6505->sink_count);
2334 
2335 	if (it6505->hpd_state) {
2336 		wait_for_completion_timeout(&it6505->wait_edid_complete,
2337 					    msecs_to_jiffies(6000));
2338 		it6505_lane_termination_on(it6505);
2339 		it6505_lane_power_on(it6505);
2340 
2341 		/*
2342 		 * for some dongle which issue HPD_irq
2343 		 * when sink count change from  0->1
2344 		 * it6505 not able to receive HPD_IRQ
2345 		 * if HW never go into trainig done
2346 		 */
2347 
2348 		if (it6505->branch_device && it6505->sink_count == 0)
2349 			schedule_work(&it6505->link_works);
2350 
2351 		if (!it6505_get_video_status(it6505))
2352 			it6505_video_reset(it6505);
2353 	} else {
2354 		memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2355 
2356 		if (it6505->hdcp_desired)
2357 			it6505_stop_hdcp(it6505);
2358 
2359 		it6505_video_disable(it6505);
2360 		it6505_disable_audio(it6505);
2361 		it6505_stop_link_train(it6505);
2362 		it6505_lane_off(it6505);
2363 		it6505_link_reset_step_train(it6505);
2364 	}
2365 }
2366 
2367 static void it6505_irq_hpd_irq(struct it6505 *it6505)
2368 {
2369 	struct device *dev = &it6505->client->dev;
2370 
2371 	DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2372 
2373 	if (it6505_process_hpd_irq(it6505) < 0)
2374 		DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2375 }
2376 
2377 static void it6505_irq_scdt(struct it6505 *it6505)
2378 {
2379 	struct device *dev = &it6505->client->dev;
2380 	bool data;
2381 
2382 	data = it6505_get_video_status(it6505);
2383 	DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2384 			     data ? "stable" : "unstable");
2385 	it6505_calc_video_info(it6505);
2386 	it6505_link_reset_step_train(it6505);
2387 
2388 	if (data)
2389 		schedule_work(&it6505->link_works);
2390 }
2391 
2392 static void it6505_irq_hdcp_done(struct it6505 *it6505)
2393 {
2394 	struct device *dev = &it6505->client->dev;
2395 
2396 	DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2397 	it6505->hdcp_status = HDCP_AUTH_DONE;
2398 	it6505_show_hdcp_info(it6505);
2399 }
2400 
2401 static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2402 {
2403 	struct device *dev = &it6505->client->dev;
2404 
2405 	DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2406 	it6505->hdcp_status = HDCP_AUTH_IDLE;
2407 	it6505_show_hdcp_info(it6505);
2408 	it6505_start_hdcp(it6505);
2409 }
2410 
2411 static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2412 {
2413 	struct device *dev = &it6505->client->dev;
2414 
2415 	DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2416 }
2417 
2418 static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2419 {
2420 	struct device *dev = &it6505->client->dev;
2421 
2422 	DRM_DEV_DEBUG_DRIVER(dev, "HDCP event Interrupt");
2423 	schedule_work(&it6505->hdcp_wait_ksv_list);
2424 }
2425 
2426 static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2427 {
2428 	struct device *dev = &it6505->client->dev;
2429 
2430 	DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2431 
2432 	if (it6505_audio_input(it6505))
2433 		it6505_enable_audio(it6505);
2434 }
2435 
2436 static void it6505_irq_link_train_fail(struct it6505 *it6505)
2437 {
2438 	struct device *dev = &it6505->client->dev;
2439 
2440 	DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2441 	schedule_work(&it6505->link_works);
2442 }
2443 
2444 static void it6505_irq_video_fifo_error(struct it6505 *it6505)
2445 {
2446 	struct device *dev = &it6505->client->dev;
2447 
2448 	DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt");
2449 	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2450 	flush_work(&it6505->link_works);
2451 	it6505_stop_hdcp(it6505);
2452 	it6505_video_reset(it6505);
2453 }
2454 
2455 static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505)
2456 {
2457 	struct device *dev = &it6505->client->dev;
2458 
2459 	DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt");
2460 	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2461 	flush_work(&it6505->link_works);
2462 	it6505_stop_hdcp(it6505);
2463 	it6505_video_reset(it6505);
2464 }
2465 
2466 static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2467 {
2468 	return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2469 }
2470 
2471 static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2472 {
2473 	struct it6505 *it6505 = data;
2474 	struct device *dev = &it6505->client->dev;
2475 	static const struct {
2476 		int bit;
2477 		void (*handler)(struct it6505 *it6505);
2478 	} irq_vec[] = {
2479 		{ BIT_INT_HPD, it6505_irq_hpd },
2480 		{ BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2481 		{ BIT_INT_SCDT, it6505_irq_scdt },
2482 		{ BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2483 		{ BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2484 		{ BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2485 		{ BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2486 		{ BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2487 		{ BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2488 		{ BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error },
2489 		{ BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow },
2490 	};
2491 	int int_status[3], i;
2492 
2493 	msleep(100);
2494 	mutex_lock(&it6505->extcon_lock);
2495 
2496 	if (it6505->enable_drv_hold || !it6505->powered)
2497 		goto unlock;
2498 
2499 	int_status[0] = it6505_read(it6505, INT_STATUS_01);
2500 	int_status[1] = it6505_read(it6505, INT_STATUS_02);
2501 	int_status[2] = it6505_read(it6505, INT_STATUS_03);
2502 
2503 	it6505_write(it6505, INT_STATUS_01, int_status[0]);
2504 	it6505_write(it6505, INT_STATUS_02, int_status[1]);
2505 	it6505_write(it6505, INT_STATUS_03, int_status[2]);
2506 
2507 	DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2508 	DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2509 	DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2510 	it6505_debug_print(it6505, REG_SYSTEM_STS, "");
2511 
2512 	if (it6505_test_bit(irq_vec[0].bit, (unsigned int *)int_status))
2513 		irq_vec[0].handler(it6505);
2514 
2515 	if (!it6505->hpd_state)
2516 		goto unlock;
2517 
2518 	for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2519 		if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))
2520 			irq_vec[i].handler(it6505);
2521 	}
2522 
2523 unlock:
2524 	mutex_unlock(&it6505->extcon_lock);
2525 
2526 	return IRQ_HANDLED;
2527 }
2528 
2529 static int it6505_poweron(struct it6505 *it6505)
2530 {
2531 	struct device *dev = &it6505->client->dev;
2532 	struct it6505_platform_data *pdata = &it6505->pdata;
2533 	int err;
2534 
2535 	DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2536 
2537 	if (it6505->powered) {
2538 		DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2539 		return 0;
2540 	}
2541 
2542 	if (pdata->pwr18) {
2543 		err = regulator_enable(pdata->pwr18);
2544 		if (err) {
2545 			DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2546 					     err);
2547 			return err;
2548 		}
2549 	}
2550 
2551 	if (pdata->ovdd) {
2552 		/* time interval between IVDD and OVDD at least be 1ms */
2553 		usleep_range(1000, 2000);
2554 		err = regulator_enable(pdata->ovdd);
2555 		if (err) {
2556 			regulator_disable(pdata->pwr18);
2557 			return err;
2558 		}
2559 	}
2560 	/* time interval between OVDD and SYSRSTN at least be 10ms */
2561 	if (pdata->gpiod_reset) {
2562 		usleep_range(10000, 20000);
2563 		gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2564 		usleep_range(1000, 2000);
2565 		gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2566 		usleep_range(10000, 20000);
2567 	}
2568 
2569 	it6505->powered = true;
2570 	it6505_reset_logic(it6505);
2571 	it6505_int_mask_enable(it6505);
2572 	it6505_init(it6505);
2573 	it6505_lane_off(it6505);
2574 
2575 	return 0;
2576 }
2577 
2578 static int it6505_poweroff(struct it6505 *it6505)
2579 {
2580 	struct device *dev = &it6505->client->dev;
2581 	struct it6505_platform_data *pdata = &it6505->pdata;
2582 	int err;
2583 
2584 	DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2585 
2586 	if (!it6505->powered) {
2587 		DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2588 		return 0;
2589 	}
2590 
2591 	if (pdata->gpiod_reset)
2592 		gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2593 
2594 	if (pdata->pwr18) {
2595 		err = regulator_disable(pdata->pwr18);
2596 		if (err)
2597 			return err;
2598 	}
2599 
2600 	if (pdata->ovdd) {
2601 		err = regulator_disable(pdata->ovdd);
2602 		if (err)
2603 			return err;
2604 	}
2605 
2606 	it6505->powered = false;
2607 	it6505->sink_count = 0;
2608 
2609 	return 0;
2610 }
2611 
2612 static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2613 {
2614 	struct device *dev = &it6505->client->dev;
2615 	enum drm_connector_status status = connector_status_disconnected;
2616 	int dp_sink_count;
2617 
2618 	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2619 			     it6505->sink_count, it6505->powered);
2620 
2621 	mutex_lock(&it6505->mode_lock);
2622 
2623 	if (!it6505->powered)
2624 		goto unlock;
2625 
2626 	if (it6505->enable_drv_hold) {
2627 		status = it6505_get_sink_hpd_status(it6505) ?
2628 					connector_status_connected :
2629 					connector_status_disconnected;
2630 		goto unlock;
2631 	}
2632 
2633 	if (it6505_get_sink_hpd_status(it6505)) {
2634 		it6505_aux_on(it6505);
2635 		it6505_drm_dp_link_probe(&it6505->aux, &it6505->link);
2636 		it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2637 					     DP_SET_POWER_D0);
2638 		it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2639 
2640 		if (it6505->dpcd[0] == 0) {
2641 			it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
2642 					ARRAY_SIZE(it6505->dpcd));
2643 			it6505_variable_config(it6505);
2644 			it6505_parse_link_capabilities(it6505);
2645 		}
2646 
2647 		dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2648 		it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2649 		DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2650 				     it6505->sink_count, it6505->branch_device);
2651 
2652 		if (it6505->branch_device) {
2653 			status = (it6505->sink_count != 0) ?
2654 				 connector_status_connected :
2655 				 connector_status_disconnected;
2656 		} else {
2657 			status = connector_status_connected;
2658 		}
2659 	} else {
2660 		it6505->sink_count = 0;
2661 		memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2662 	}
2663 
2664 unlock:
2665 	if (it6505->connector_status != status) {
2666 		it6505->connector_status = status;
2667 		it6505_plugged_status_to_codec(it6505);
2668 	}
2669 
2670 	mutex_unlock(&it6505->mode_lock);
2671 
2672 	return status;
2673 }
2674 
2675 static int it6505_extcon_notifier(struct notifier_block *self,
2676 				  unsigned long event, void *ptr)
2677 {
2678 	struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2679 
2680 	schedule_work(&it6505->extcon_wq);
2681 	return NOTIFY_DONE;
2682 }
2683 
2684 static void it6505_extcon_work(struct work_struct *work)
2685 {
2686 	struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2687 	struct device *dev = &it6505->client->dev;
2688 	int state = extcon_get_state(it6505->extcon, EXTCON_DISP_DP);
2689 	unsigned int pwroffretry = 0;
2690 
2691 	if (it6505->enable_drv_hold)
2692 		return;
2693 
2694 	mutex_lock(&it6505->extcon_lock);
2695 
2696 	DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2697 	if (state > 0) {
2698 		DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2699 		msleep(100);
2700 		it6505_poweron(it6505);
2701 	} else {
2702 		DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2703 		while (it6505_poweroff(it6505) && pwroffretry++ < 5) {
2704 			DRM_DEV_DEBUG_DRIVER(dev, "power off fail %d times",
2705 					     pwroffretry);
2706 		}
2707 
2708 		drm_helper_hpd_irq_event(it6505->bridge.dev);
2709 		memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2710 		DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2711 	}
2712 
2713 	mutex_unlock(&it6505->extcon_lock);
2714 }
2715 
2716 static int it6505_use_notifier_module(struct it6505 *it6505)
2717 {
2718 	int ret;
2719 	struct device *dev = &it6505->client->dev;
2720 
2721 	it6505->event_nb.notifier_call = it6505_extcon_notifier;
2722 	INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2723 	ret = devm_extcon_register_notifier(&it6505->client->dev,
2724 					    it6505->extcon, EXTCON_DISP_DP,
2725 					    &it6505->event_nb);
2726 	if (ret) {
2727 		dev_err(dev, "failed to register notifier for DP");
2728 		return ret;
2729 	}
2730 
2731 	schedule_work(&it6505->extcon_wq);
2732 
2733 	return 0;
2734 }
2735 
2736 static void it6505_remove_notifier_module(struct it6505 *it6505)
2737 {
2738 	if (it6505->extcon) {
2739 		devm_extcon_unregister_notifier(&it6505->client->dev,
2740 						it6505->extcon,	EXTCON_DISP_DP,
2741 						&it6505->event_nb);
2742 
2743 		flush_work(&it6505->extcon_wq);
2744 	}
2745 }
2746 
2747 static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2748 {
2749 	struct it6505 *it6505 = container_of(work, struct it6505,
2750 					     delayed_audio.work);
2751 
2752 	DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "start");
2753 
2754 	if (!it6505->powered)
2755 		return;
2756 
2757 	if (!it6505->enable_drv_hold)
2758 		it6505_enable_audio(it6505);
2759 }
2760 
2761 static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2762 						       struct hdmi_codec_params
2763 						       *params)
2764 {
2765 	struct device *dev = &it6505->client->dev;
2766 	int i = 0;
2767 
2768 	DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2769 			     params->sample_rate, params->sample_width,
2770 			     params->cea.channels);
2771 
2772 	if (!it6505->bridge.encoder)
2773 		return -ENODEV;
2774 
2775 	if (params->cea.channels <= 1 || params->cea.channels > 8) {
2776 		DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2777 				     it6505->audio.channel_count);
2778 		return -EINVAL;
2779 	}
2780 
2781 	it6505->audio.channel_count = params->cea.channels;
2782 
2783 	while (i < ARRAY_SIZE(audio_sample_rate_map) &&
2784 	       params->sample_rate !=
2785 		       audio_sample_rate_map[i].sample_rate_value) {
2786 		i++;
2787 	}
2788 	if (i == ARRAY_SIZE(audio_sample_rate_map)) {
2789 		DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
2790 				     params->sample_rate);
2791 		return -EINVAL;
2792 	}
2793 	it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
2794 
2795 	switch (params->sample_width) {
2796 	case 16:
2797 		it6505->audio.word_length = WORD_LENGTH_16BIT;
2798 		break;
2799 	case 18:
2800 		it6505->audio.word_length = WORD_LENGTH_18BIT;
2801 		break;
2802 	case 20:
2803 		it6505->audio.word_length = WORD_LENGTH_20BIT;
2804 		break;
2805 	case 24:
2806 	case 32:
2807 		it6505->audio.word_length = WORD_LENGTH_24BIT;
2808 		break;
2809 	default:
2810 		DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
2811 				     params->sample_width);
2812 		return -EINVAL;
2813 	}
2814 
2815 	return 0;
2816 }
2817 
2818 static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
2819 {
2820 	struct it6505 *it6505 = dev_get_drvdata(dev);
2821 
2822 	if (it6505->powered)
2823 		it6505_disable_audio(it6505);
2824 }
2825 
2826 static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
2827 						       void *data,
2828 						       hdmi_codec_plugged_cb fn,
2829 						       struct device *codec_dev)
2830 {
2831 	struct it6505 *it6505 = data;
2832 
2833 	it6505->plugged_cb = fn;
2834 	it6505->codec_dev = codec_dev;
2835 	it6505_plugged_status_to_codec(it6505);
2836 
2837 	return 0;
2838 }
2839 
2840 static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
2841 {
2842 	return container_of(bridge, struct it6505, bridge);
2843 }
2844 
2845 static int it6505_bridge_attach(struct drm_bridge *bridge,
2846 				enum drm_bridge_attach_flags flags)
2847 {
2848 	struct it6505 *it6505 = bridge_to_it6505(bridge);
2849 	struct device *dev = &it6505->client->dev;
2850 	int ret;
2851 
2852 	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2853 		DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
2854 		return -EINVAL;
2855 	}
2856 
2857 	if (!bridge->encoder) {
2858 		dev_err(dev, "Parent encoder object not found");
2859 		return -ENODEV;
2860 	}
2861 
2862 	/* Register aux channel */
2863 	it6505->aux.name = "DP-AUX";
2864 	it6505->aux.dev = dev;
2865 	it6505->aux.drm_dev = bridge->dev;
2866 	it6505->aux.transfer = it6505_aux_transfer;
2867 
2868 	ret = drm_dp_aux_register(&it6505->aux);
2869 
2870 	if (ret < 0) {
2871 		dev_err(dev, "Failed to register aux: %d", ret);
2872 		return ret;
2873 	}
2874 
2875 	if (it6505->extcon) {
2876 		ret = it6505_use_notifier_module(it6505);
2877 		if (ret < 0) {
2878 			dev_err(dev, "use notifier module failed");
2879 			return ret;
2880 		}
2881 	}
2882 
2883 	return 0;
2884 }
2885 
2886 static void it6505_bridge_detach(struct drm_bridge *bridge)
2887 {
2888 	struct it6505 *it6505 = bridge_to_it6505(bridge);
2889 
2890 	flush_work(&it6505->link_works);
2891 	it6505_remove_notifier_module(it6505);
2892 }
2893 
2894 static enum drm_mode_status
2895 it6505_bridge_mode_valid(struct drm_bridge *bridge,
2896 			 const struct drm_display_info *info,
2897 			 const struct drm_display_mode *mode)
2898 {
2899 	struct it6505 *it6505 = bridge_to_it6505(bridge);
2900 
2901 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2902 		return MODE_NO_INTERLACE;
2903 
2904 	if (mode->clock > DPI_PIXEL_CLK_MAX)
2905 		return MODE_CLOCK_HIGH;
2906 
2907 	it6505->video_info.clock = mode->clock;
2908 
2909 	return MODE_OK;
2910 }
2911 
2912 static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
2913 					struct drm_bridge_state *old_state)
2914 {
2915 	struct it6505 *it6505 = bridge_to_it6505(bridge);
2916 	struct device *dev = &it6505->client->dev;
2917 	struct drm_atomic_state *state = old_state->base.state;
2918 	struct hdmi_avi_infoframe frame;
2919 	struct drm_crtc_state *crtc_state;
2920 	struct drm_connector_state *conn_state;
2921 	struct drm_display_mode *mode;
2922 	struct drm_connector *connector;
2923 	int ret;
2924 
2925 	DRM_DEV_DEBUG_DRIVER(dev, "start");
2926 
2927 	connector = drm_atomic_get_new_connector_for_encoder(state,
2928 							     bridge->encoder);
2929 
2930 	if (WARN_ON(!connector))
2931 		return;
2932 
2933 	conn_state = drm_atomic_get_new_connector_state(state, connector);
2934 
2935 	if (WARN_ON(!conn_state))
2936 		return;
2937 
2938 	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
2939 
2940 	if (WARN_ON(!crtc_state))
2941 		return;
2942 
2943 	mode = &crtc_state->adjusted_mode;
2944 
2945 	if (WARN_ON(!mode))
2946 		return;
2947 
2948 	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2949 						       connector,
2950 						       mode);
2951 	if (ret)
2952 		dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
2953 
2954 	it6505_update_video_parameter(it6505, mode);
2955 
2956 	ret = it6505_send_video_infoframe(it6505, &frame);
2957 
2958 	if (ret)
2959 		dev_err(dev, "Failed to send AVI infoframe: %d", ret);
2960 
2961 	it6505_int_mask_enable(it6505);
2962 	it6505_video_reset(it6505);
2963 
2964 	it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2965 				     DP_SET_POWER_D0);
2966 }
2967 
2968 static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
2969 					 struct drm_bridge_state *old_state)
2970 {
2971 	struct it6505 *it6505 = bridge_to_it6505(bridge);
2972 	struct device *dev = &it6505->client->dev;
2973 
2974 	DRM_DEV_DEBUG_DRIVER(dev, "start");
2975 
2976 	if (it6505->powered) {
2977 		it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2978 					     DP_SET_POWER_D3);
2979 		it6505_video_disable(it6505);
2980 	}
2981 }
2982 
2983 static enum drm_connector_status
2984 it6505_bridge_detect(struct drm_bridge *bridge)
2985 {
2986 	struct it6505 *it6505 = bridge_to_it6505(bridge);
2987 
2988 	return it6505_detect(it6505);
2989 }
2990 
2991 static struct edid *it6505_bridge_get_edid(struct drm_bridge *bridge,
2992 					   struct drm_connector *connector)
2993 {
2994 	struct it6505 *it6505 = bridge_to_it6505(bridge);
2995 	struct device *dev = &it6505->client->dev;
2996 	struct edid *edid;
2997 
2998 	edid = drm_do_get_edid(connector, it6505_get_edid_block, it6505);
2999 
3000 	if (!edid) {
3001 		DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
3002 		return NULL;
3003 	}
3004 
3005 	return edid;
3006 }
3007 
3008 static const struct drm_bridge_funcs it6505_bridge_funcs = {
3009 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3010 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3011 	.atomic_reset = drm_atomic_helper_bridge_reset,
3012 	.attach = it6505_bridge_attach,
3013 	.detach = it6505_bridge_detach,
3014 	.mode_valid = it6505_bridge_mode_valid,
3015 	.atomic_enable = it6505_bridge_atomic_enable,
3016 	.atomic_disable = it6505_bridge_atomic_disable,
3017 	.detect = it6505_bridge_detect,
3018 	.get_edid = it6505_bridge_get_edid,
3019 };
3020 
3021 static __maybe_unused int it6505_bridge_resume(struct device *dev)
3022 {
3023 	struct it6505 *it6505 = dev_get_drvdata(dev);
3024 
3025 	return it6505_poweron(it6505);
3026 }
3027 
3028 static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3029 {
3030 	struct it6505 *it6505 = dev_get_drvdata(dev);
3031 
3032 	return it6505_poweroff(it6505);
3033 }
3034 
3035 static SIMPLE_DEV_PM_OPS(it6505_bridge_pm_ops, it6505_bridge_suspend,
3036 			 it6505_bridge_resume);
3037 
3038 static int it6505_init_pdata(struct it6505 *it6505)
3039 {
3040 	struct it6505_platform_data *pdata = &it6505->pdata;
3041 	struct device *dev = &it6505->client->dev;
3042 
3043 	/* 1.0V digital core power regulator  */
3044 	pdata->pwr18 = devm_regulator_get(dev, "pwr18");
3045 	if (IS_ERR(pdata->pwr18)) {
3046 		dev_err(dev, "pwr18 regulator not found");
3047 		return PTR_ERR(pdata->pwr18);
3048 	}
3049 
3050 	pdata->ovdd = devm_regulator_get(dev, "ovdd");
3051 	if (IS_ERR(pdata->ovdd)) {
3052 		dev_err(dev, "ovdd regulator not found");
3053 		return PTR_ERR(pdata->ovdd);
3054 	}
3055 
3056 	pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3057 	if (IS_ERR(pdata->gpiod_reset)) {
3058 		dev_err(dev, "gpiod_reset gpio not found");
3059 		return PTR_ERR(pdata->gpiod_reset);
3060 	}
3061 
3062 	return 0;
3063 }
3064 
3065 static void it6505_parse_dt(struct it6505 *it6505)
3066 {
3067 	struct device *dev = &it6505->client->dev;
3068 	u32 *afe_setting = &it6505->afe_setting;
3069 
3070 	it6505->lane_swap_disabled =
3071 		device_property_read_bool(dev, "no-laneswap");
3072 
3073 	if (it6505->lane_swap_disabled)
3074 		it6505->lane_swap = false;
3075 
3076 	if (device_property_read_u32(dev, "afe-setting", afe_setting) == 0) {
3077 		if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3078 			dev_err(dev, "afe setting error, use default");
3079 			*afe_setting = 0;
3080 		}
3081 	} else {
3082 		*afe_setting = 0;
3083 	}
3084 	DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting);
3085 }
3086 
3087 static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3088 					   size_t len, loff_t *ppos)
3089 {
3090 	struct it6505 *it6505 = file->private_data;
3091 	struct drm_display_mode *vid = &it6505->video_info;
3092 	u8 read_buf[READ_BUFFER_SIZE];
3093 	u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3094 	ssize_t ret, count;
3095 
3096 	if (!it6505)
3097 		return -ENODEV;
3098 
3099 	it6505_calc_video_info(it6505);
3100 	str += scnprintf(str, end - str, "---video timing---\n");
3101 	str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
3102 			 vid->clock / 1000, vid->clock % 1000);
3103 	str += scnprintf(str, end - str, "HTotal:%d\n", vid->htotal);
3104 	str += scnprintf(str, end - str, "HActive:%d\n", vid->hdisplay);
3105 	str += scnprintf(str, end - str, "HFrontPorch:%d\n",
3106 			 vid->hsync_start - vid->hdisplay);
3107 	str += scnprintf(str, end - str, "HSyncWidth:%d\n",
3108 			 vid->hsync_end - vid->hsync_start);
3109 	str += scnprintf(str, end - str, "HBackPorch:%d\n",
3110 			 vid->htotal - vid->hsync_end);
3111 	str += scnprintf(str, end - str, "VTotal:%d\n", vid->vtotal);
3112 	str += scnprintf(str, end - str, "VActive:%d\n", vid->vdisplay);
3113 	str += scnprintf(str, end - str, "VFrontPorch:%d\n",
3114 			 vid->vsync_start - vid->vdisplay);
3115 	str += scnprintf(str, end - str, "VSyncWidth:%d\n",
3116 			 vid->vsync_end - vid->vsync_start);
3117 	str += scnprintf(str, end - str, "VBackPorch:%d\n",
3118 			 vid->vtotal - vid->vsync_end);
3119 
3120 	count = str - read_buf;
3121 	ret = simple_read_from_buffer(buf, len, ppos, read_buf, count);
3122 
3123 	return ret;
3124 }
3125 
3126 static int force_power_on_off_debugfs_write(void *data, u64 value)
3127 {
3128 	struct it6505 *it6505 = data;
3129 
3130 	if (!it6505)
3131 		return -ENODEV;
3132 
3133 	if (value)
3134 		it6505_poweron(it6505);
3135 	else
3136 		it6505_poweroff(it6505);
3137 
3138 	return 0;
3139 }
3140 
3141 static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3142 {
3143 	struct it6505 *it6505 = data;
3144 
3145 	if (!it6505)
3146 		return -ENODEV;
3147 
3148 	*buf = it6505->enable_drv_hold;
3149 
3150 	return 0;
3151 }
3152 
3153 static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3154 {
3155 	struct it6505 *it6505 = data;
3156 
3157 	if (!it6505)
3158 		return -ENODEV;
3159 
3160 	it6505->enable_drv_hold = drv_hold;
3161 
3162 	if (it6505->enable_drv_hold) {
3163 		it6505_int_mask_disable(it6505);
3164 	} else {
3165 		it6505_clear_int(it6505);
3166 		it6505_int_mask_enable(it6505);
3167 
3168 		if (it6505->powered) {
3169 			it6505->connector_status =
3170 					it6505_get_sink_hpd_status(it6505) ?
3171 					connector_status_connected :
3172 					connector_status_disconnected;
3173 		} else {
3174 			it6505->connector_status =
3175 					connector_status_disconnected;
3176 		}
3177 	}
3178 
3179 	return 0;
3180 }
3181 
3182 static const struct file_operations receive_timing_fops = {
3183 	.owner = THIS_MODULE,
3184 	.open = simple_open,
3185 	.read = receive_timing_debugfs_show,
3186 	.llseek = default_llseek,
3187 };
3188 
3189 DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3190 			 force_power_on_off_debugfs_write, "%llu\n");
3191 
3192 DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3193 			 enable_drv_hold_debugfs_write, "%llu\n");
3194 
3195 static const struct debugfs_entries debugfs_entry[] = {
3196 	{ "receive_timing", &receive_timing_fops },
3197 	{ "force_power_on_off", &fops_force_power },
3198 	{ "enable_drv_hold", &fops_enable_drv_hold },
3199 	{ NULL, NULL },
3200 };
3201 
3202 static void debugfs_create_files(struct it6505 *it6505)
3203 {
3204 	int i = 0;
3205 
3206 	while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3207 		debugfs_create_file(debugfs_entry[i].name, 0644,
3208 				    it6505->debugfs, it6505,
3209 				    debugfs_entry[i].fops);
3210 		i++;
3211 	}
3212 }
3213 
3214 static void debugfs_init(struct it6505 *it6505)
3215 {
3216 	struct device *dev = &it6505->client->dev;
3217 
3218 	it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3219 
3220 	if (IS_ERR(it6505->debugfs)) {
3221 		dev_err(dev, "failed to create debugfs root");
3222 		return;
3223 	}
3224 
3225 	debugfs_create_files(it6505);
3226 }
3227 
3228 static void it6505_debugfs_remove(struct it6505 *it6505)
3229 {
3230 	debugfs_remove_recursive(it6505->debugfs);
3231 }
3232 
3233 static void it6505_shutdown(struct i2c_client *client)
3234 {
3235 	struct it6505 *it6505 = dev_get_drvdata(&client->dev);
3236 
3237 	if (it6505->powered)
3238 		it6505_lane_off(it6505);
3239 }
3240 
3241 static int it6505_i2c_probe(struct i2c_client *client,
3242 			    const struct i2c_device_id *id)
3243 {
3244 	struct it6505 *it6505;
3245 	struct device *dev = &client->dev;
3246 	struct extcon_dev *extcon;
3247 	int err, intp_irq;
3248 
3249 	it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
3250 	if (!it6505)
3251 		return -ENOMEM;
3252 
3253 	mutex_init(&it6505->extcon_lock);
3254 	mutex_init(&it6505->mode_lock);
3255 	mutex_init(&it6505->aux_lock);
3256 
3257 	it6505->bridge.of_node = client->dev.of_node;
3258 	it6505->connector_status = connector_status_disconnected;
3259 	it6505->client = client;
3260 	i2c_set_clientdata(client, it6505);
3261 
3262 	/* get extcon device from DTS */
3263 	extcon = extcon_get_edev_by_phandle(dev, 0);
3264 	if (PTR_ERR(extcon) == -EPROBE_DEFER)
3265 		return -EPROBE_DEFER;
3266 	if (IS_ERR(extcon)) {
3267 		dev_err(dev, "can not get extcon device!");
3268 		return PTR_ERR(extcon);
3269 	}
3270 
3271 	it6505->extcon = extcon;
3272 
3273 	it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3274 	if (IS_ERR(it6505->regmap)) {
3275 		dev_err(dev, "regmap i2c init failed");
3276 		err = PTR_ERR(it6505->regmap);
3277 		return err;
3278 	}
3279 
3280 	err = it6505_init_pdata(it6505);
3281 	if (err) {
3282 		dev_err(dev, "Failed to initialize pdata: %d", err);
3283 		return err;
3284 	}
3285 
3286 	it6505_parse_dt(it6505);
3287 
3288 	intp_irq = client->irq;
3289 
3290 	if (!intp_irq) {
3291 		dev_err(dev, "Failed to get INTP IRQ");
3292 		err = -ENODEV;
3293 		return err;
3294 	}
3295 
3296 	err = devm_request_threaded_irq(&client->dev, intp_irq, NULL,
3297 					it6505_int_threaded_handler,
3298 					IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3299 					"it6505-intp", it6505);
3300 	if (err) {
3301 		dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3302 		return err;
3303 	}
3304 
3305 	INIT_WORK(&it6505->link_works, it6505_link_training_work);
3306 	INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3307 	INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3308 	init_completion(&it6505->wait_edid_complete);
3309 	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3310 	it6505->powered = false;
3311 	it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3312 
3313 	if (DEFAULT_PWR_ON)
3314 		it6505_poweron(it6505);
3315 
3316 	DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3317 	debugfs_init(it6505);
3318 
3319 	it6505->bridge.funcs = &it6505_bridge_funcs;
3320 	it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3321 	it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3322 			     DRM_BRIDGE_OP_HPD;
3323 	drm_bridge_add(&it6505->bridge);
3324 
3325 	return 0;
3326 }
3327 
3328 static void it6505_i2c_remove(struct i2c_client *client)
3329 {
3330 	struct it6505 *it6505 = i2c_get_clientdata(client);
3331 
3332 	drm_bridge_remove(&it6505->bridge);
3333 	drm_dp_aux_unregister(&it6505->aux);
3334 	it6505_debugfs_remove(it6505);
3335 	it6505_poweroff(it6505);
3336 }
3337 
3338 static const struct i2c_device_id it6505_id[] = {
3339 	{ "it6505", 0 },
3340 	{ }
3341 };
3342 
3343 MODULE_DEVICE_TABLE(i2c, it6505_id);
3344 
3345 static const struct of_device_id it6505_of_match[] = {
3346 	{ .compatible = "ite,it6505" },
3347 	{ }
3348 };
3349 
3350 static struct i2c_driver it6505_i2c_driver = {
3351 	.driver = {
3352 		.name = "it6505",
3353 		.of_match_table = it6505_of_match,
3354 		.pm = &it6505_bridge_pm_ops,
3355 	},
3356 	.probe = it6505_i2c_probe,
3357 	.remove = it6505_i2c_remove,
3358 	.shutdown = it6505_shutdown,
3359 	.id_table = it6505_id,
3360 };
3361 
3362 module_i2c_driver(it6505_i2c_driver);
3363 
3364 MODULE_AUTHOR("Allen Chen <allen.chen@ite.com.tw>");
3365 MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3366 MODULE_LICENSE("GPL v2");
3367