1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * Copyright 2020 NXP 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/media-bus-format.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_graph.h> 14 #include <linux/phy/phy.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 18 #include <drm/drm_atomic_state_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_connector.h> 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_print.h> 24 25 #include "imx-ldb-helper.h" 26 27 #define LDB_CH_SEL BIT(28) 28 29 #define SS_CTRL 0x20 30 #define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) 31 #define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) 32 #define CH_PHSYNC(id) BIT(0 + ((id) * 2)) 33 #define CH_PVSYNC(id) BIT(1 + ((id) * 2)) 34 35 #define DRIVER_NAME "imx8qxp-ldb" 36 37 struct imx8qxp_ldb_channel { 38 struct ldb_channel base; 39 struct phy *phy; 40 unsigned int di_id; 41 }; 42 43 struct imx8qxp_ldb { 44 struct ldb base; 45 struct device *dev; 46 struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM]; 47 struct clk *clk_pixel; 48 struct clk *clk_bypass; 49 struct drm_bridge *companion; 50 int active_chno; 51 }; 52 53 static inline struct imx8qxp_ldb_channel * 54 base_to_imx8qxp_ldb_channel(struct ldb_channel *base) 55 { 56 return container_of(base, struct imx8qxp_ldb_channel, base); 57 } 58 59 static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) 60 { 61 return container_of(base, struct imx8qxp_ldb, base); 62 } 63 64 static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb, 65 unsigned long di_clk, bool is_split, 66 struct phy_configure_opts_lvds *phy_cfg) 67 { 68 phy_cfg->bits_per_lane_and_dclk_cycle = 7; 69 phy_cfg->lanes = 4; 70 71 if (is_split) { 72 phy_cfg->differential_clk_rate = di_clk / 2; 73 phy_cfg->is_slave = !imx8qxp_ldb->companion; 74 } else { 75 phy_cfg->differential_clk_rate = di_clk; 76 phy_cfg->is_slave = false; 77 } 78 } 79 80 static int 81 imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge, 82 struct drm_bridge_state *bridge_state, 83 struct drm_crtc_state *crtc_state, 84 struct drm_connector_state *conn_state) 85 { 86 struct ldb_channel *ldb_ch = bridge->driver_private; 87 struct ldb *ldb = ldb_ch->ldb; 88 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 89 base_to_imx8qxp_ldb_channel(ldb_ch); 90 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 91 struct drm_bridge *companion = imx8qxp_ldb->companion; 92 struct drm_display_mode *adj = &crtc_state->adjusted_mode; 93 unsigned long di_clk = adj->clock * 1000; 94 bool is_split = ldb_channel_is_split_link(ldb_ch); 95 union phy_configure_opts opts = { }; 96 struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; 97 int ret; 98 99 ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, 100 crtc_state, conn_state); 101 if (ret) 102 return ret; 103 104 imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); 105 ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); 106 if (ret < 0) { 107 DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev, 108 "failed to validate PHY: %d\n", ret); 109 return ret; 110 } 111 112 if (is_split && companion) { 113 ret = companion->funcs->atomic_check(companion, 114 bridge_state, crtc_state, conn_state); 115 if (ret) 116 return ret; 117 } 118 119 return ret; 120 } 121 122 static void 123 imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge, 124 const struct drm_display_mode *mode, 125 const struct drm_display_mode *adjusted_mode) 126 { 127 struct ldb_channel *ldb_ch = bridge->driver_private; 128 struct ldb_channel *companion_ldb_ch; 129 struct ldb *ldb = ldb_ch->ldb; 130 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 131 base_to_imx8qxp_ldb_channel(ldb_ch); 132 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 133 struct drm_bridge *companion = imx8qxp_ldb->companion; 134 struct device *dev = imx8qxp_ldb->dev; 135 unsigned long di_clk = adjusted_mode->clock * 1000; 136 bool is_split = ldb_channel_is_split_link(ldb_ch); 137 union phy_configure_opts opts = { }; 138 struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; 139 u32 chno = ldb_ch->chno; 140 int ret; 141 142 ret = pm_runtime_get_sync(dev); 143 if (ret < 0) 144 DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); 145 146 ret = phy_init(imx8qxp_ldb_ch->phy); 147 if (ret < 0) 148 DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); 149 150 ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS); 151 if (ret < 0) 152 DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret); 153 154 if (is_split && companion) { 155 companion_ldb_ch = bridge_to_ldb_ch(companion); 156 157 companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format; 158 companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format; 159 } 160 161 clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk); 162 clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk); 163 164 imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); 165 ret = phy_configure(imx8qxp_ldb_ch->phy, &opts); 166 if (ret < 0) 167 DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); 168 169 if (chno == 0) 170 ldb->ldb_ctrl &= ~LDB_CH_SEL; 171 else 172 ldb->ldb_ctrl |= LDB_CH_SEL; 173 174 /* input VSYNC signal from pixel link is active low */ 175 if (imx8qxp_ldb_ch->di_id == 0) 176 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; 177 else 178 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; 179 180 /* 181 * For split mode, settle input VSYNC signal polarity and 182 * channel selection down early. 183 */ 184 if (is_split) 185 regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); 186 187 ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); 188 189 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 190 regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); 191 else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 192 regmap_update_bits(ldb->regmap, SS_CTRL, 193 CH_VSYNC_M(chno), CH_PVSYNC(chno)); 194 195 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 196 regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); 197 else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 198 regmap_update_bits(ldb->regmap, SS_CTRL, 199 CH_HSYNC_M(chno), CH_PHSYNC(chno)); 200 201 if (is_split && companion) 202 companion->funcs->mode_set(companion, mode, adjusted_mode); 203 } 204 205 static void 206 imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge, 207 struct drm_bridge_state *old_bridge_state) 208 { 209 struct ldb_channel *ldb_ch = bridge->driver_private; 210 struct ldb *ldb = ldb_ch->ldb; 211 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 212 struct drm_bridge *companion = imx8qxp_ldb->companion; 213 bool is_split = ldb_channel_is_split_link(ldb_ch); 214 215 clk_prepare_enable(imx8qxp_ldb->clk_pixel); 216 clk_prepare_enable(imx8qxp_ldb->clk_bypass); 217 218 if (is_split && companion) 219 companion->funcs->atomic_pre_enable(companion, old_bridge_state); 220 } 221 222 static void 223 imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge, 224 struct drm_bridge_state *old_bridge_state) 225 { 226 struct ldb_channel *ldb_ch = bridge->driver_private; 227 struct ldb *ldb = ldb_ch->ldb; 228 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 229 base_to_imx8qxp_ldb_channel(ldb_ch); 230 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 231 struct drm_bridge *companion = imx8qxp_ldb->companion; 232 struct device *dev = imx8qxp_ldb->dev; 233 bool is_split = ldb_channel_is_split_link(ldb_ch); 234 int ret; 235 236 if (ldb_ch->chno == 0 || is_split) { 237 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; 238 ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? 239 LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1; 240 } 241 if (ldb_ch->chno == 1 || is_split) { 242 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; 243 ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? 244 LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1; 245 } 246 247 ldb_bridge_enable_helper(bridge); 248 249 ret = phy_power_on(imx8qxp_ldb_ch->phy); 250 if (ret) 251 DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); 252 253 if (is_split && companion) 254 companion->funcs->atomic_enable(companion, old_bridge_state); 255 } 256 257 static void 258 imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge, 259 struct drm_bridge_state *old_bridge_state) 260 { 261 struct ldb_channel *ldb_ch = bridge->driver_private; 262 struct ldb *ldb = ldb_ch->ldb; 263 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 264 base_to_imx8qxp_ldb_channel(ldb_ch); 265 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 266 struct drm_bridge *companion = imx8qxp_ldb->companion; 267 struct device *dev = imx8qxp_ldb->dev; 268 bool is_split = ldb_channel_is_split_link(ldb_ch); 269 int ret; 270 271 ret = phy_power_off(imx8qxp_ldb_ch->phy); 272 if (ret) 273 DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); 274 275 ret = phy_exit(imx8qxp_ldb_ch->phy); 276 if (ret < 0) 277 DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret); 278 279 ldb_bridge_disable_helper(bridge); 280 281 clk_disable_unprepare(imx8qxp_ldb->clk_bypass); 282 clk_disable_unprepare(imx8qxp_ldb->clk_pixel); 283 284 if (is_split && companion) 285 companion->funcs->atomic_disable(companion, old_bridge_state); 286 287 ret = pm_runtime_put(dev); 288 if (ret < 0) 289 DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret); 290 } 291 292 static const u32 imx8qxp_ldb_bus_output_fmts[] = { 293 MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 294 MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 295 MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 296 MEDIA_BUS_FMT_FIXED, 297 }; 298 299 static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt) 300 { 301 int i; 302 303 for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) { 304 if (imx8qxp_ldb_bus_output_fmts[i] == fmt) 305 return true; 306 } 307 308 return false; 309 } 310 311 static u32 * 312 imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 313 struct drm_bridge_state *bridge_state, 314 struct drm_crtc_state *crtc_state, 315 struct drm_connector_state *conn_state, 316 u32 output_fmt, 317 unsigned int *num_input_fmts) 318 { 319 struct drm_display_info *di; 320 const struct drm_format_info *finfo; 321 u32 *input_fmts; 322 323 if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt)) 324 return NULL; 325 326 *num_input_fmts = 1; 327 328 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); 329 if (!input_fmts) 330 return NULL; 331 332 switch (output_fmt) { 333 case MEDIA_BUS_FMT_FIXED: 334 di = &conn_state->connector->display_info; 335 336 /* 337 * Look at the first bus format to determine input format. 338 * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match. 339 */ 340 if (di->num_bus_formats) { 341 finfo = drm_format_info(di->bus_formats[0]); 342 343 input_fmts[0] = finfo->depth == 18 ? 344 MEDIA_BUS_FMT_RGB666_1X24_CPADHI : 345 MEDIA_BUS_FMT_RGB888_1X24; 346 } else { 347 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 348 } 349 break; 350 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 351 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; 352 break; 353 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 354 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 355 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 356 break; 357 default: 358 kfree(input_fmts); 359 input_fmts = NULL; 360 break; 361 } 362 363 return input_fmts; 364 } 365 366 static u32 * 367 imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 368 struct drm_bridge_state *bridge_state, 369 struct drm_crtc_state *crtc_state, 370 struct drm_connector_state *conn_state, 371 unsigned int *num_output_fmts) 372 { 373 *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); 374 return kmemdup(imx8qxp_ldb_bus_output_fmts, 375 sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL); 376 } 377 378 static enum drm_mode_status 379 imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge, 380 const struct drm_display_info *info, 381 const struct drm_display_mode *mode) 382 { 383 struct ldb_channel *ldb_ch = bridge->driver_private; 384 bool is_single = ldb_channel_is_single_link(ldb_ch); 385 386 if (mode->clock > 170000) 387 return MODE_CLOCK_HIGH; 388 389 if (mode->clock > 150000 && is_single) 390 return MODE_CLOCK_HIGH; 391 392 return MODE_OK; 393 } 394 395 static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = { 396 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 397 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 398 .atomic_reset = drm_atomic_helper_bridge_reset, 399 .mode_valid = imx8qxp_ldb_bridge_mode_valid, 400 .attach = ldb_bridge_attach_helper, 401 .atomic_check = imx8qxp_ldb_bridge_atomic_check, 402 .mode_set = imx8qxp_ldb_bridge_mode_set, 403 .atomic_pre_enable = imx8qxp_ldb_bridge_atomic_pre_enable, 404 .atomic_enable = imx8qxp_ldb_bridge_atomic_enable, 405 .atomic_disable = imx8qxp_ldb_bridge_atomic_disable, 406 .atomic_get_input_bus_fmts = 407 imx8qxp_ldb_bridge_atomic_get_input_bus_fmts, 408 .atomic_get_output_bus_fmts = 409 imx8qxp_ldb_bridge_atomic_get_output_bus_fmts, 410 }; 411 412 static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb) 413 { 414 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 415 &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; 416 struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; 417 struct device_node *ep, *remote; 418 struct device *dev = imx8qxp_ldb->dev; 419 struct of_endpoint endpoint; 420 int ret; 421 422 ep = of_graph_get_endpoint_by_regs(ldb_ch->np, 0, -1); 423 if (!ep) { 424 DRM_DEV_ERROR(dev, "failed to get port0 endpoint\n"); 425 return -EINVAL; 426 } 427 428 remote = of_graph_get_remote_endpoint(ep); 429 of_node_put(ep); 430 if (!remote) { 431 DRM_DEV_ERROR(dev, "failed to get port0 remote endpoint\n"); 432 return -EINVAL; 433 } 434 435 ret = of_graph_parse_endpoint(remote, &endpoint); 436 of_node_put(remote); 437 if (ret) { 438 DRM_DEV_ERROR(dev, "failed to parse port0 remote endpoint: %d\n", 439 ret); 440 return ret; 441 } 442 443 imx8qxp_ldb_ch->di_id = endpoint.id; 444 445 return 0; 446 } 447 448 static int 449 imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link) 450 { 451 if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) || 452 (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1)) 453 return -EINVAL; 454 455 return 0; 456 } 457 458 static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) 459 { 460 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 461 &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; 462 struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; 463 struct ldb_channel *companion_ldb_ch; 464 struct device_node *companion; 465 struct device_node *child; 466 struct device_node *companion_port = NULL; 467 struct device_node *port1, *port2; 468 struct device *dev = imx8qxp_ldb->dev; 469 const struct of_device_id *match; 470 u32 i; 471 int dual_link; 472 int ret; 473 474 /* Locate the companion LDB for dual-link operation, if any. */ 475 companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0); 476 if (!companion) 477 return 0; 478 479 if (!of_device_is_available(companion)) { 480 DRM_DEV_ERROR(dev, "companion LDB is not available\n"); 481 ret = -ENODEV; 482 goto out; 483 } 484 485 /* 486 * Sanity check: the companion bridge must have the same compatible 487 * string. 488 */ 489 match = of_match_device(dev->driver->of_match_table, dev); 490 if (!of_device_is_compatible(companion, match->compatible)) { 491 DRM_DEV_ERROR(dev, "companion LDB is incompatible\n"); 492 ret = -ENXIO; 493 goto out; 494 } 495 496 for_each_available_child_of_node(companion, child) { 497 ret = of_property_read_u32(child, "reg", &i); 498 if (ret || i > MAX_LDB_CHAN_NUM - 1) { 499 DRM_DEV_ERROR(dev, 500 "invalid channel node address: %u\n", i); 501 ret = -EINVAL; 502 of_node_put(child); 503 goto out; 504 } 505 506 /* 507 * Channel numbers have to be different, because channel0 508 * transmits odd pixels and channel1 transmits even pixels. 509 */ 510 if (i == (ldb_ch->chno ^ 0x1)) { 511 companion_port = child; 512 break; 513 } 514 } 515 516 if (!companion_port) { 517 DRM_DEV_ERROR(dev, 518 "failed to find companion LDB channel port\n"); 519 ret = -EINVAL; 520 goto out; 521 } 522 523 /* 524 * We need to work out if the sink is expecting us to function in 525 * dual-link mode. We do this by looking at the DT port nodes we are 526 * connected to. If they are marked as expecting odd pixels and 527 * even pixels than we need to enable LDB split mode. 528 */ 529 port1 = of_graph_get_port_by_id(ldb_ch->np, 1); 530 port2 = of_graph_get_port_by_id(companion_port, 1); 531 dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); 532 of_node_put(port1); 533 of_node_put(port2); 534 535 switch (dual_link) { 536 case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: 537 ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; 538 break; 539 case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: 540 ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS; 541 break; 542 default: 543 ret = dual_link; 544 DRM_DEV_ERROR(dev, 545 "failed to get dual link pixel order: %d\n", ret); 546 goto out; 547 } 548 549 ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link); 550 if (ret < 0) { 551 DRM_DEV_ERROR(dev, 552 "unmatched channel number(%u) vs dual link(%d)\n", 553 ldb_ch->chno, dual_link); 554 goto out; 555 } 556 557 imx8qxp_ldb->companion = of_drm_find_bridge(companion_port); 558 if (!imx8qxp_ldb->companion) { 559 ret = -EPROBE_DEFER; 560 DRM_DEV_DEBUG_DRIVER(dev, 561 "failed to find bridge for companion bridge: %d\n", 562 ret); 563 goto out; 564 } 565 566 DRM_DEV_DEBUG_DRIVER(dev, 567 "dual-link configuration detected (companion bridge %pOF)\n", 568 companion); 569 570 companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion); 571 companion_ldb_ch->link_type = ldb_ch->link_type; 572 out: 573 of_node_put(companion_port); 574 of_node_put(companion); 575 return ret; 576 } 577 578 static int imx8qxp_ldb_probe(struct platform_device *pdev) 579 { 580 struct device *dev = &pdev->dev; 581 struct imx8qxp_ldb *imx8qxp_ldb; 582 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch; 583 struct ldb *ldb; 584 struct ldb_channel *ldb_ch; 585 int ret, i; 586 587 imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL); 588 if (!imx8qxp_ldb) 589 return -ENOMEM; 590 591 imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel"); 592 if (IS_ERR(imx8qxp_ldb->clk_pixel)) { 593 ret = PTR_ERR(imx8qxp_ldb->clk_pixel); 594 if (ret != -EPROBE_DEFER) 595 DRM_DEV_ERROR(dev, 596 "failed to get pixel clock: %d\n", ret); 597 return ret; 598 } 599 600 imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass"); 601 if (IS_ERR(imx8qxp_ldb->clk_bypass)) { 602 ret = PTR_ERR(imx8qxp_ldb->clk_bypass); 603 if (ret != -EPROBE_DEFER) 604 DRM_DEV_ERROR(dev, 605 "failed to get bypass clock: %d\n", ret); 606 return ret; 607 } 608 609 imx8qxp_ldb->dev = dev; 610 611 ldb = &imx8qxp_ldb->base; 612 ldb->dev = dev; 613 ldb->ctrl_reg = 0xe0; 614 615 for (i = 0; i < MAX_LDB_CHAN_NUM; i++) 616 ldb->channel[i] = &imx8qxp_ldb->channel[i].base; 617 618 ret = ldb_init_helper(ldb); 619 if (ret) 620 return ret; 621 622 if (ldb->available_ch_cnt == 0) { 623 DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); 624 return 0; 625 } else if (ldb->available_ch_cnt > 1) { 626 DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n", 627 ldb->available_ch_cnt); 628 return -EINVAL; 629 } 630 631 for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { 632 imx8qxp_ldb_ch = &imx8qxp_ldb->channel[i]; 633 ldb_ch = &imx8qxp_ldb_ch->base; 634 635 if (ldb_ch->is_available) { 636 imx8qxp_ldb->active_chno = ldb_ch->chno; 637 break; 638 } 639 } 640 641 imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy"); 642 if (IS_ERR(imx8qxp_ldb_ch->phy)) { 643 ret = PTR_ERR(imx8qxp_ldb_ch->phy); 644 if (ret != -EPROBE_DEFER) 645 DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n", 646 imx8qxp_ldb->active_chno, ret); 647 return ret; 648 } 649 650 ret = ldb_find_next_bridge_helper(ldb); 651 if (ret) 652 return ret; 653 654 ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb); 655 if (ret) 656 return ret; 657 658 ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb); 659 if (ret) 660 return ret; 661 662 platform_set_drvdata(pdev, imx8qxp_ldb); 663 pm_runtime_enable(dev); 664 665 ldb_add_bridge_helper(ldb, &imx8qxp_ldb_bridge_funcs); 666 667 return ret; 668 } 669 670 static void imx8qxp_ldb_remove(struct platform_device *pdev) 671 { 672 struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev); 673 struct ldb *ldb = &imx8qxp_ldb->base; 674 675 ldb_remove_bridge_helper(ldb); 676 677 pm_runtime_disable(&pdev->dev); 678 } 679 680 static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev) 681 { 682 return 0; 683 } 684 685 static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev) 686 { 687 struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev); 688 struct ldb *ldb = &imx8qxp_ldb->base; 689 690 /* disable LDB by resetting the control register to POR default */ 691 regmap_write(ldb->regmap, ldb->ctrl_reg, 0); 692 693 return 0; 694 } 695 696 static const struct dev_pm_ops imx8qxp_ldb_pm_ops = { 697 SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend, 698 imx8qxp_ldb_runtime_resume, NULL) 699 }; 700 701 static const struct of_device_id imx8qxp_ldb_dt_ids[] = { 702 { .compatible = "fsl,imx8qxp-ldb" }, 703 { /* sentinel */ } 704 }; 705 MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids); 706 707 static struct platform_driver imx8qxp_ldb_driver = { 708 .probe = imx8qxp_ldb_probe, 709 .remove_new = imx8qxp_ldb_remove, 710 .driver = { 711 .pm = &imx8qxp_ldb_pm_ops, 712 .name = DRIVER_NAME, 713 .of_match_table = imx8qxp_ldb_dt_ids, 714 }, 715 }; 716 module_platform_driver(imx8qxp_ldb_driver); 717 718 MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB)/Pixel Mapper bridge driver"); 719 MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); 720 MODULE_LICENSE("GPL v2"); 721 MODULE_ALIAS("platform:" DRIVER_NAME); 722