1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_device.h> 11 #include <linux/of_graph.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_bridge.h> 17 #include <drm/drm_of.h> 18 #include <drm/drm_panel.h> 19 20 #define LDB_CTRL 0x5c 21 #define LDB_CTRL_CH0_ENABLE BIT(0) 22 #define LDB_CTRL_CH0_DI_SELECT BIT(1) 23 #define LDB_CTRL_CH1_ENABLE BIT(2) 24 #define LDB_CTRL_CH1_DI_SELECT BIT(3) 25 #define LDB_CTRL_SPLIT_MODE BIT(4) 26 #define LDB_CTRL_CH0_DATA_WIDTH BIT(5) 27 #define LDB_CTRL_CH0_BIT_MAPPING BIT(6) 28 #define LDB_CTRL_CH1_DATA_WIDTH BIT(7) 29 #define LDB_CTRL_CH1_BIT_MAPPING BIT(8) 30 #define LDB_CTRL_DI0_VSYNC_POLARITY BIT(9) 31 #define LDB_CTRL_DI1_VSYNC_POLARITY BIT(10) 32 #define LDB_CTRL_REG_CH0_FIFO_RESET BIT(11) 33 #define LDB_CTRL_REG_CH1_FIFO_RESET BIT(12) 34 #define LDB_CTRL_ASYNC_FIFO_ENABLE BIT(24) 35 #define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25) 36 37 #define LVDS_CTRL 0x128 38 #define LVDS_CTRL_CH0_EN BIT(0) 39 #define LVDS_CTRL_CH1_EN BIT(1) 40 #define LVDS_CTRL_VBG_EN BIT(2) 41 #define LVDS_CTRL_HS_EN BIT(3) 42 #define LVDS_CTRL_PRE_EMPH_EN BIT(4) 43 #define LVDS_CTRL_PRE_EMPH_ADJ(n) (((n) & 0x7) << 5) 44 #define LVDS_CTRL_PRE_EMPH_ADJ_MASK GENMASK(7, 5) 45 #define LVDS_CTRL_CM_ADJ(n) (((n) & 0x7) << 8) 46 #define LVDS_CTRL_CM_ADJ_MASK GENMASK(10, 8) 47 #define LVDS_CTRL_CC_ADJ(n) (((n) & 0x7) << 11) 48 #define LVDS_CTRL_CC_ADJ_MASK GENMASK(13, 11) 49 #define LVDS_CTRL_SLEW_ADJ(n) (((n) & 0x7) << 14) 50 #define LVDS_CTRL_SLEW_ADJ_MASK GENMASK(16, 14) 51 #define LVDS_CTRL_VBG_ADJ(n) (((n) & 0x7) << 17) 52 #define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17) 53 54 struct fsl_ldb { 55 struct device *dev; 56 struct drm_bridge bridge; 57 struct drm_bridge *panel_bridge; 58 struct clk *clk; 59 struct regmap *regmap; 60 bool lvds_dual_link; 61 }; 62 63 static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge) 64 { 65 return container_of(bridge, struct fsl_ldb, bridge); 66 } 67 68 static int fsl_ldb_attach(struct drm_bridge *bridge, 69 enum drm_bridge_attach_flags flags) 70 { 71 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 72 73 return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge, 74 bridge, flags); 75 } 76 77 static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, 78 struct drm_bridge_state *old_bridge_state) 79 { 80 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 81 struct drm_atomic_state *state = old_bridge_state->base.state; 82 const struct drm_bridge_state *bridge_state; 83 const struct drm_crtc_state *crtc_state; 84 const struct drm_display_mode *mode; 85 struct drm_connector *connector; 86 struct drm_crtc *crtc; 87 bool lvds_format_24bpp; 88 bool lvds_format_jeida; 89 u32 reg; 90 91 /* Get the LVDS format from the bridge state. */ 92 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 93 94 switch (bridge_state->output_bus_cfg.format) { 95 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 96 lvds_format_24bpp = false; 97 lvds_format_jeida = true; 98 break; 99 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 100 lvds_format_24bpp = true; 101 lvds_format_jeida = true; 102 break; 103 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 104 lvds_format_24bpp = true; 105 lvds_format_jeida = false; 106 break; 107 default: 108 /* 109 * Some bridges still don't set the correct LVDS bus pixel 110 * format, use SPWG24 default format until those are fixed. 111 */ 112 lvds_format_24bpp = true; 113 lvds_format_jeida = false; 114 dev_warn(fsl_ldb->dev, 115 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 116 bridge_state->output_bus_cfg.format); 117 break; 118 } 119 120 /* 121 * Retrieve the CRTC adjusted mode. This requires a little dance to go 122 * from the bridge to the encoder, to the connector and to the CRTC. 123 */ 124 connector = drm_atomic_get_new_connector_for_encoder(state, 125 bridge->encoder); 126 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 127 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 128 mode = &crtc_state->adjusted_mode; 129 130 if (fsl_ldb->lvds_dual_link) 131 clk_set_rate(fsl_ldb->clk, mode->clock * 3500); 132 else 133 clk_set_rate(fsl_ldb->clk, mode->clock * 7000); 134 clk_prepare_enable(fsl_ldb->clk); 135 136 /* Program LDB_CTRL */ 137 reg = LDB_CTRL_CH0_ENABLE; 138 139 if (fsl_ldb->lvds_dual_link) 140 reg |= LDB_CTRL_CH1_ENABLE | LDB_CTRL_SPLIT_MODE; 141 142 if (lvds_format_24bpp) { 143 reg |= LDB_CTRL_CH0_DATA_WIDTH; 144 if (fsl_ldb->lvds_dual_link) 145 reg |= LDB_CTRL_CH1_DATA_WIDTH; 146 } 147 148 if (lvds_format_jeida) { 149 reg |= LDB_CTRL_CH0_BIT_MAPPING; 150 if (fsl_ldb->lvds_dual_link) 151 reg |= LDB_CTRL_CH1_BIT_MAPPING; 152 } 153 154 if (mode->flags & DRM_MODE_FLAG_PVSYNC) { 155 reg |= LDB_CTRL_DI0_VSYNC_POLARITY; 156 if (fsl_ldb->lvds_dual_link) 157 reg |= LDB_CTRL_DI1_VSYNC_POLARITY; 158 } 159 160 regmap_write(fsl_ldb->regmap, LDB_CTRL, reg); 161 162 /* Program LVDS_CTRL */ 163 reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN | 164 LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN; 165 regmap_write(fsl_ldb->regmap, LVDS_CTRL, reg); 166 167 /* Wait for VBG to stabilize. */ 168 usleep_range(15, 20); 169 170 reg |= LVDS_CTRL_CH0_EN; 171 if (fsl_ldb->lvds_dual_link) 172 reg |= LVDS_CTRL_CH1_EN; 173 174 regmap_write(fsl_ldb->regmap, LVDS_CTRL, reg); 175 } 176 177 static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, 178 struct drm_bridge_state *old_bridge_state) 179 { 180 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 181 182 /* Stop both channels. */ 183 regmap_write(fsl_ldb->regmap, LVDS_CTRL, 0); 184 regmap_write(fsl_ldb->regmap, LDB_CTRL, 0); 185 186 clk_disable_unprepare(fsl_ldb->clk); 187 } 188 189 #define MAX_INPUT_SEL_FORMATS 1 190 static u32 * 191 fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 192 struct drm_bridge_state *bridge_state, 193 struct drm_crtc_state *crtc_state, 194 struct drm_connector_state *conn_state, 195 u32 output_fmt, 196 unsigned int *num_input_fmts) 197 { 198 u32 *input_fmts; 199 200 *num_input_fmts = 0; 201 202 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 203 GFP_KERNEL); 204 if (!input_fmts) 205 return NULL; 206 207 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 208 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 209 210 return input_fmts; 211 } 212 213 static enum drm_mode_status 214 fsl_ldb_mode_valid(struct drm_bridge *bridge, 215 const struct drm_display_info *info, 216 const struct drm_display_mode *mode) 217 { 218 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 219 220 if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000)) 221 return MODE_CLOCK_HIGH; 222 223 return MODE_OK; 224 } 225 226 static const struct drm_bridge_funcs funcs = { 227 .attach = fsl_ldb_attach, 228 .atomic_enable = fsl_ldb_atomic_enable, 229 .atomic_disable = fsl_ldb_atomic_disable, 230 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 231 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 232 .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts, 233 .atomic_reset = drm_atomic_helper_bridge_reset, 234 .mode_valid = fsl_ldb_mode_valid, 235 }; 236 237 static int fsl_ldb_probe(struct platform_device *pdev) 238 { 239 struct device *dev = &pdev->dev; 240 struct device_node *panel_node; 241 struct device_node *port1, *port2; 242 struct drm_panel *panel; 243 struct fsl_ldb *fsl_ldb; 244 int dual_link; 245 246 fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL); 247 if (!fsl_ldb) 248 return -ENOMEM; 249 250 fsl_ldb->dev = &pdev->dev; 251 fsl_ldb->bridge.funcs = &funcs; 252 fsl_ldb->bridge.of_node = dev->of_node; 253 254 fsl_ldb->clk = devm_clk_get(dev, "ldb"); 255 if (IS_ERR(fsl_ldb->clk)) 256 return PTR_ERR(fsl_ldb->clk); 257 258 fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent); 259 if (IS_ERR(fsl_ldb->regmap)) 260 return PTR_ERR(fsl_ldb->regmap); 261 262 /* Locate the panel DT node. */ 263 panel_node = of_graph_get_remote_node(dev->of_node, 1, 0); 264 if (!panel_node) 265 return -ENXIO; 266 267 panel = of_drm_find_panel(panel_node); 268 of_node_put(panel_node); 269 if (IS_ERR(panel)) 270 return PTR_ERR(panel); 271 272 fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 273 if (IS_ERR(fsl_ldb->panel_bridge)) 274 return PTR_ERR(fsl_ldb->panel_bridge); 275 276 /* Determine whether this is dual-link configuration */ 277 port1 = of_graph_get_port_by_id(dev->of_node, 1); 278 port2 = of_graph_get_port_by_id(dev->of_node, 2); 279 dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); 280 of_node_put(port1); 281 of_node_put(port2); 282 283 if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 284 dev_err(dev, "LVDS channel pixel swap not supported.\n"); 285 return -EINVAL; 286 } 287 288 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) 289 fsl_ldb->lvds_dual_link = true; 290 291 platform_set_drvdata(pdev, fsl_ldb); 292 293 drm_bridge_add(&fsl_ldb->bridge); 294 295 return 0; 296 } 297 298 static int fsl_ldb_remove(struct platform_device *pdev) 299 { 300 struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev); 301 302 drm_bridge_remove(&fsl_ldb->bridge); 303 304 return 0; 305 } 306 307 static const struct of_device_id fsl_ldb_match[] = { 308 { .compatible = "fsl,imx8mp-ldb", }, 309 { /* sentinel */ }, 310 }; 311 MODULE_DEVICE_TABLE(of, fsl_ldb_match); 312 313 static struct platform_driver fsl_ldb_driver = { 314 .probe = fsl_ldb_probe, 315 .remove = fsl_ldb_remove, 316 .driver = { 317 .name = "fsl-ldb", 318 .of_match_table = fsl_ldb_match, 319 }, 320 }; 321 module_platform_driver(fsl_ldb_driver); 322 323 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 324 MODULE_DESCRIPTION("Freescale i.MX8MP LDB"); 325 MODULE_LICENSE("GPL"); 326