1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/media-bus-format.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/of_graph.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_bridge.h> 18 #include <drm/drm_of.h> 19 #include <drm/drm_panel.h> 20 21 #define LDB_CTRL_CH0_ENABLE BIT(0) 22 #define LDB_CTRL_CH0_DI_SELECT BIT(1) 23 #define LDB_CTRL_CH1_ENABLE BIT(2) 24 #define LDB_CTRL_CH1_DI_SELECT BIT(3) 25 #define LDB_CTRL_SPLIT_MODE BIT(4) 26 #define LDB_CTRL_CH0_DATA_WIDTH BIT(5) 27 #define LDB_CTRL_CH0_BIT_MAPPING BIT(6) 28 #define LDB_CTRL_CH1_DATA_WIDTH BIT(7) 29 #define LDB_CTRL_CH1_BIT_MAPPING BIT(8) 30 #define LDB_CTRL_DI0_VSYNC_POLARITY BIT(9) 31 #define LDB_CTRL_DI1_VSYNC_POLARITY BIT(10) 32 #define LDB_CTRL_REG_CH0_FIFO_RESET BIT(11) 33 #define LDB_CTRL_REG_CH1_FIFO_RESET BIT(12) 34 #define LDB_CTRL_ASYNC_FIFO_ENABLE BIT(24) 35 #define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25) 36 37 #define LVDS_CTRL_CH0_EN BIT(0) 38 #define LVDS_CTRL_CH1_EN BIT(1) 39 /* 40 * LVDS_CTRL_LVDS_EN bit is poorly named in i.MX93 reference manual. 41 * Clear it to enable LVDS and set it to disable LVDS. 42 */ 43 #define LVDS_CTRL_LVDS_EN BIT(1) 44 #define LVDS_CTRL_VBG_EN BIT(2) 45 #define LVDS_CTRL_HS_EN BIT(3) 46 #define LVDS_CTRL_PRE_EMPH_EN BIT(4) 47 #define LVDS_CTRL_PRE_EMPH_ADJ(n) (((n) & 0x7) << 5) 48 #define LVDS_CTRL_PRE_EMPH_ADJ_MASK GENMASK(7, 5) 49 #define LVDS_CTRL_CM_ADJ(n) (((n) & 0x7) << 8) 50 #define LVDS_CTRL_CM_ADJ_MASK GENMASK(10, 8) 51 #define LVDS_CTRL_CC_ADJ(n) (((n) & 0x7) << 11) 52 #define LVDS_CTRL_CC_ADJ_MASK GENMASK(13, 11) 53 #define LVDS_CTRL_SLEW_ADJ(n) (((n) & 0x7) << 14) 54 #define LVDS_CTRL_SLEW_ADJ_MASK GENMASK(16, 14) 55 #define LVDS_CTRL_VBG_ADJ(n) (((n) & 0x7) << 17) 56 #define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17) 57 58 enum fsl_ldb_devtype { 59 IMX6SX_LDB, 60 IMX8MP_LDB, 61 IMX93_LDB, 62 }; 63 64 struct fsl_ldb_devdata { 65 u32 ldb_ctrl; 66 u32 lvds_ctrl; 67 bool lvds_en_bit; 68 bool single_ctrl_reg; 69 }; 70 71 static const struct fsl_ldb_devdata fsl_ldb_devdata[] = { 72 [IMX6SX_LDB] = { 73 .ldb_ctrl = 0x18, 74 .single_ctrl_reg = true, 75 }, 76 [IMX8MP_LDB] = { 77 .ldb_ctrl = 0x5c, 78 .lvds_ctrl = 0x128, 79 }, 80 [IMX93_LDB] = { 81 .ldb_ctrl = 0x20, 82 .lvds_ctrl = 0x24, 83 .lvds_en_bit = true, 84 }, 85 }; 86 87 struct fsl_ldb { 88 struct device *dev; 89 struct drm_bridge bridge; 90 struct drm_bridge *panel_bridge; 91 struct clk *clk; 92 struct regmap *regmap; 93 const struct fsl_ldb_devdata *devdata; 94 bool ch0_enabled; 95 bool ch1_enabled; 96 }; 97 98 static bool fsl_ldb_is_dual(const struct fsl_ldb *fsl_ldb) 99 { 100 return (fsl_ldb->ch0_enabled && fsl_ldb->ch1_enabled); 101 } 102 103 static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge) 104 { 105 return container_of(bridge, struct fsl_ldb, bridge); 106 } 107 108 static unsigned long fsl_ldb_link_frequency(struct fsl_ldb *fsl_ldb, int clock) 109 { 110 if (fsl_ldb_is_dual(fsl_ldb)) 111 return clock * 3500; 112 else 113 return clock * 7000; 114 } 115 116 static int fsl_ldb_attach(struct drm_bridge *bridge, 117 enum drm_bridge_attach_flags flags) 118 { 119 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 120 121 return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge, 122 bridge, flags); 123 } 124 125 static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, 126 struct drm_bridge_state *old_bridge_state) 127 { 128 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 129 struct drm_atomic_state *state = old_bridge_state->base.state; 130 const struct drm_bridge_state *bridge_state; 131 const struct drm_crtc_state *crtc_state; 132 const struct drm_display_mode *mode; 133 struct drm_connector *connector; 134 struct drm_crtc *crtc; 135 unsigned long configured_link_freq; 136 unsigned long requested_link_freq; 137 bool lvds_format_24bpp; 138 bool lvds_format_jeida; 139 u32 reg; 140 141 /* Get the LVDS format from the bridge state. */ 142 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 143 144 switch (bridge_state->output_bus_cfg.format) { 145 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 146 lvds_format_24bpp = false; 147 lvds_format_jeida = true; 148 break; 149 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 150 lvds_format_24bpp = true; 151 lvds_format_jeida = true; 152 break; 153 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 154 lvds_format_24bpp = true; 155 lvds_format_jeida = false; 156 break; 157 default: 158 /* 159 * Some bridges still don't set the correct LVDS bus pixel 160 * format, use SPWG24 default format until those are fixed. 161 */ 162 lvds_format_24bpp = true; 163 lvds_format_jeida = false; 164 dev_warn(fsl_ldb->dev, 165 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 166 bridge_state->output_bus_cfg.format); 167 break; 168 } 169 170 /* 171 * Retrieve the CRTC adjusted mode. This requires a little dance to go 172 * from the bridge to the encoder, to the connector and to the CRTC. 173 */ 174 connector = drm_atomic_get_new_connector_for_encoder(state, 175 bridge->encoder); 176 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 177 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 178 mode = &crtc_state->adjusted_mode; 179 180 requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); 181 clk_set_rate(fsl_ldb->clk, requested_link_freq); 182 183 configured_link_freq = clk_get_rate(fsl_ldb->clk); 184 if (configured_link_freq != requested_link_freq) 185 dev_warn(fsl_ldb->dev, "Configured LDB clock (%lu Hz) does not match requested LVDS clock: %lu Hz\n", 186 configured_link_freq, 187 requested_link_freq); 188 189 clk_prepare_enable(fsl_ldb->clk); 190 191 /* Program LDB_CTRL */ 192 reg = (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_ENABLE : 0) | 193 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_ENABLE : 0) | 194 (fsl_ldb_is_dual(fsl_ldb) ? LDB_CTRL_SPLIT_MODE : 0); 195 196 if (lvds_format_24bpp) 197 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_DATA_WIDTH : 0) | 198 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_DATA_WIDTH : 0); 199 200 if (lvds_format_jeida) 201 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_BIT_MAPPING : 0) | 202 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_BIT_MAPPING : 0); 203 204 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 205 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_DI0_VSYNC_POLARITY : 0) | 206 (fsl_ldb->ch1_enabled ? LDB_CTRL_DI1_VSYNC_POLARITY : 0); 207 208 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg); 209 210 if (fsl_ldb->devdata->single_ctrl_reg) 211 return; 212 213 /* Program LVDS_CTRL */ 214 reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN | 215 LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN; 216 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg); 217 218 /* Wait for VBG to stabilize. */ 219 usleep_range(15, 20); 220 221 reg |= (fsl_ldb->ch0_enabled ? LVDS_CTRL_CH0_EN : 0) | 222 (fsl_ldb->ch1_enabled ? LVDS_CTRL_CH1_EN : 0); 223 224 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg); 225 } 226 227 static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, 228 struct drm_bridge_state *old_bridge_state) 229 { 230 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 231 232 /* Stop channel(s). */ 233 if (fsl_ldb->devdata->lvds_en_bit) 234 /* Set LVDS_CTRL_LVDS_EN bit to disable. */ 235 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 236 LVDS_CTRL_LVDS_EN); 237 else 238 if (!fsl_ldb->devdata->single_ctrl_reg) 239 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); 240 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0); 241 242 clk_disable_unprepare(fsl_ldb->clk); 243 } 244 245 #define MAX_INPUT_SEL_FORMATS 1 246 static u32 * 247 fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 248 struct drm_bridge_state *bridge_state, 249 struct drm_crtc_state *crtc_state, 250 struct drm_connector_state *conn_state, 251 u32 output_fmt, 252 unsigned int *num_input_fmts) 253 { 254 u32 *input_fmts; 255 256 *num_input_fmts = 0; 257 258 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 259 GFP_KERNEL); 260 if (!input_fmts) 261 return NULL; 262 263 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 264 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 265 266 return input_fmts; 267 } 268 269 static enum drm_mode_status 270 fsl_ldb_mode_valid(struct drm_bridge *bridge, 271 const struct drm_display_info *info, 272 const struct drm_display_mode *mode) 273 { 274 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 275 276 if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) 277 return MODE_CLOCK_HIGH; 278 279 return MODE_OK; 280 } 281 282 static const struct drm_bridge_funcs funcs = { 283 .attach = fsl_ldb_attach, 284 .atomic_enable = fsl_ldb_atomic_enable, 285 .atomic_disable = fsl_ldb_atomic_disable, 286 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 287 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 288 .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts, 289 .atomic_reset = drm_atomic_helper_bridge_reset, 290 .mode_valid = fsl_ldb_mode_valid, 291 }; 292 293 static int fsl_ldb_probe(struct platform_device *pdev) 294 { 295 struct device *dev = &pdev->dev; 296 struct device_node *panel_node; 297 struct device_node *remote1, *remote2; 298 struct drm_panel *panel; 299 struct fsl_ldb *fsl_ldb; 300 int dual_link; 301 302 fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL); 303 if (!fsl_ldb) 304 return -ENOMEM; 305 306 fsl_ldb->devdata = of_device_get_match_data(dev); 307 if (!fsl_ldb->devdata) 308 return -EINVAL; 309 310 fsl_ldb->dev = &pdev->dev; 311 fsl_ldb->bridge.funcs = &funcs; 312 fsl_ldb->bridge.of_node = dev->of_node; 313 314 fsl_ldb->clk = devm_clk_get(dev, "ldb"); 315 if (IS_ERR(fsl_ldb->clk)) 316 return PTR_ERR(fsl_ldb->clk); 317 318 fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent); 319 if (IS_ERR(fsl_ldb->regmap)) 320 return PTR_ERR(fsl_ldb->regmap); 321 322 /* Locate the remote ports and the panel node */ 323 remote1 = of_graph_get_remote_node(dev->of_node, 1, 0); 324 remote2 = of_graph_get_remote_node(dev->of_node, 2, 0); 325 fsl_ldb->ch0_enabled = (remote1 != NULL); 326 fsl_ldb->ch1_enabled = (remote2 != NULL); 327 panel_node = of_node_get(remote1 ? remote1 : remote2); 328 of_node_put(remote1); 329 of_node_put(remote2); 330 331 if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) { 332 of_node_put(panel_node); 333 return dev_err_probe(dev, -ENXIO, "No panel node found"); 334 } 335 336 dev_dbg(dev, "Using %s\n", 337 fsl_ldb_is_dual(fsl_ldb) ? "dual-link mode" : 338 fsl_ldb->ch0_enabled ? "channel 0" : "channel 1"); 339 340 panel = of_drm_find_panel(panel_node); 341 of_node_put(panel_node); 342 if (IS_ERR(panel)) 343 return PTR_ERR(panel); 344 345 fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 346 if (IS_ERR(fsl_ldb->panel_bridge)) 347 return PTR_ERR(fsl_ldb->panel_bridge); 348 349 350 if (fsl_ldb_is_dual(fsl_ldb)) { 351 struct device_node *port1, *port2; 352 353 port1 = of_graph_get_port_by_id(dev->of_node, 1); 354 port2 = of_graph_get_port_by_id(dev->of_node, 2); 355 dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); 356 of_node_put(port1); 357 of_node_put(port2); 358 359 if (dual_link < 0) 360 return dev_err_probe(dev, dual_link, 361 "Error getting dual link configuration\n"); 362 363 /* Only DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS is supported */ 364 if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 365 dev_err(dev, "LVDS channel pixel swap not supported.\n"); 366 return -EINVAL; 367 } 368 } 369 370 platform_set_drvdata(pdev, fsl_ldb); 371 372 drm_bridge_add(&fsl_ldb->bridge); 373 374 return 0; 375 } 376 377 static void fsl_ldb_remove(struct platform_device *pdev) 378 { 379 struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev); 380 381 drm_bridge_remove(&fsl_ldb->bridge); 382 } 383 384 static const struct of_device_id fsl_ldb_match[] = { 385 { .compatible = "fsl,imx6sx-ldb", 386 .data = &fsl_ldb_devdata[IMX6SX_LDB], }, 387 { .compatible = "fsl,imx8mp-ldb", 388 .data = &fsl_ldb_devdata[IMX8MP_LDB], }, 389 { .compatible = "fsl,imx93-ldb", 390 .data = &fsl_ldb_devdata[IMX93_LDB], }, 391 { /* sentinel */ }, 392 }; 393 MODULE_DEVICE_TABLE(of, fsl_ldb_match); 394 395 static struct platform_driver fsl_ldb_driver = { 396 .probe = fsl_ldb_probe, 397 .remove_new = fsl_ldb_remove, 398 .driver = { 399 .name = "fsl-ldb", 400 .of_match_table = fsl_ldb_match, 401 }, 402 }; 403 module_platform_driver(fsl_ldb_driver); 404 405 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 406 MODULE_DESCRIPTION("Freescale i.MX8MP LDB"); 407 MODULE_LICENSE("GPL"); 408