1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/media-bus-format.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/of_graph.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_bridge.h> 18 #include <drm/drm_of.h> 19 #include <drm/drm_panel.h> 20 21 #define LDB_CTRL_CH0_ENABLE BIT(0) 22 #define LDB_CTRL_CH0_DI_SELECT BIT(1) 23 #define LDB_CTRL_CH1_ENABLE BIT(2) 24 #define LDB_CTRL_CH1_DI_SELECT BIT(3) 25 #define LDB_CTRL_SPLIT_MODE BIT(4) 26 #define LDB_CTRL_CH0_DATA_WIDTH BIT(5) 27 #define LDB_CTRL_CH0_BIT_MAPPING BIT(6) 28 #define LDB_CTRL_CH1_DATA_WIDTH BIT(7) 29 #define LDB_CTRL_CH1_BIT_MAPPING BIT(8) 30 #define LDB_CTRL_DI0_VSYNC_POLARITY BIT(9) 31 #define LDB_CTRL_DI1_VSYNC_POLARITY BIT(10) 32 #define LDB_CTRL_REG_CH0_FIFO_RESET BIT(11) 33 #define LDB_CTRL_REG_CH1_FIFO_RESET BIT(12) 34 #define LDB_CTRL_ASYNC_FIFO_ENABLE BIT(24) 35 #define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25) 36 37 #define LVDS_CTRL_CH0_EN BIT(0) 38 #define LVDS_CTRL_CH1_EN BIT(1) 39 /* 40 * LVDS_CTRL_LVDS_EN bit is poorly named in i.MX93 reference manual. 41 * Clear it to enable LVDS and set it to disable LVDS. 42 */ 43 #define LVDS_CTRL_LVDS_EN BIT(1) 44 #define LVDS_CTRL_VBG_EN BIT(2) 45 #define LVDS_CTRL_HS_EN BIT(3) 46 #define LVDS_CTRL_PRE_EMPH_EN BIT(4) 47 #define LVDS_CTRL_PRE_EMPH_ADJ(n) (((n) & 0x7) << 5) 48 #define LVDS_CTRL_PRE_EMPH_ADJ_MASK GENMASK(7, 5) 49 #define LVDS_CTRL_CM_ADJ(n) (((n) & 0x7) << 8) 50 #define LVDS_CTRL_CM_ADJ_MASK GENMASK(10, 8) 51 #define LVDS_CTRL_CC_ADJ(n) (((n) & 0x7) << 11) 52 #define LVDS_CTRL_CC_ADJ_MASK GENMASK(13, 11) 53 #define LVDS_CTRL_SLEW_ADJ(n) (((n) & 0x7) << 14) 54 #define LVDS_CTRL_SLEW_ADJ_MASK GENMASK(16, 14) 55 #define LVDS_CTRL_VBG_ADJ(n) (((n) & 0x7) << 17) 56 #define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17) 57 58 enum fsl_ldb_devtype { 59 IMX8MP_LDB, 60 IMX93_LDB, 61 }; 62 63 struct fsl_ldb_devdata { 64 u32 ldb_ctrl; 65 u32 lvds_ctrl; 66 bool lvds_en_bit; 67 }; 68 69 static const struct fsl_ldb_devdata fsl_ldb_devdata[] = { 70 [IMX8MP_LDB] = { 71 .ldb_ctrl = 0x5c, 72 .lvds_ctrl = 0x128, 73 }, 74 [IMX93_LDB] = { 75 .ldb_ctrl = 0x20, 76 .lvds_ctrl = 0x24, 77 .lvds_en_bit = true, 78 }, 79 }; 80 81 struct fsl_ldb { 82 struct device *dev; 83 struct drm_bridge bridge; 84 struct drm_bridge *panel_bridge; 85 struct clk *clk; 86 struct regmap *regmap; 87 const struct fsl_ldb_devdata *devdata; 88 bool ch0_enabled; 89 bool ch1_enabled; 90 }; 91 92 static bool fsl_ldb_is_dual(const struct fsl_ldb *fsl_ldb) 93 { 94 return (fsl_ldb->ch0_enabled && fsl_ldb->ch1_enabled); 95 } 96 97 static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge) 98 { 99 return container_of(bridge, struct fsl_ldb, bridge); 100 } 101 102 static unsigned long fsl_ldb_link_frequency(struct fsl_ldb *fsl_ldb, int clock) 103 { 104 if (fsl_ldb_is_dual(fsl_ldb)) 105 return clock * 3500; 106 else 107 return clock * 7000; 108 } 109 110 static int fsl_ldb_attach(struct drm_bridge *bridge, 111 enum drm_bridge_attach_flags flags) 112 { 113 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 114 115 return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge, 116 bridge, flags); 117 } 118 119 static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, 120 struct drm_bridge_state *old_bridge_state) 121 { 122 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 123 struct drm_atomic_state *state = old_bridge_state->base.state; 124 const struct drm_bridge_state *bridge_state; 125 const struct drm_crtc_state *crtc_state; 126 const struct drm_display_mode *mode; 127 struct drm_connector *connector; 128 struct drm_crtc *crtc; 129 unsigned long configured_link_freq; 130 unsigned long requested_link_freq; 131 bool lvds_format_24bpp; 132 bool lvds_format_jeida; 133 u32 reg; 134 135 /* Get the LVDS format from the bridge state. */ 136 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 137 138 switch (bridge_state->output_bus_cfg.format) { 139 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 140 lvds_format_24bpp = false; 141 lvds_format_jeida = true; 142 break; 143 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 144 lvds_format_24bpp = true; 145 lvds_format_jeida = true; 146 break; 147 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 148 lvds_format_24bpp = true; 149 lvds_format_jeida = false; 150 break; 151 default: 152 /* 153 * Some bridges still don't set the correct LVDS bus pixel 154 * format, use SPWG24 default format until those are fixed. 155 */ 156 lvds_format_24bpp = true; 157 lvds_format_jeida = false; 158 dev_warn(fsl_ldb->dev, 159 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 160 bridge_state->output_bus_cfg.format); 161 break; 162 } 163 164 /* 165 * Retrieve the CRTC adjusted mode. This requires a little dance to go 166 * from the bridge to the encoder, to the connector and to the CRTC. 167 */ 168 connector = drm_atomic_get_new_connector_for_encoder(state, 169 bridge->encoder); 170 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 171 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 172 mode = &crtc_state->adjusted_mode; 173 174 requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); 175 clk_set_rate(fsl_ldb->clk, requested_link_freq); 176 177 configured_link_freq = clk_get_rate(fsl_ldb->clk); 178 if (configured_link_freq != requested_link_freq) 179 dev_warn(fsl_ldb->dev, "Configured LDB clock (%lu Hz) does not match requested LVDS clock: %lu Hz\n", 180 configured_link_freq, 181 requested_link_freq); 182 183 clk_prepare_enable(fsl_ldb->clk); 184 185 /* Program LDB_CTRL */ 186 reg = (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_ENABLE : 0) | 187 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_ENABLE : 0) | 188 (fsl_ldb_is_dual(fsl_ldb) ? LDB_CTRL_SPLIT_MODE : 0); 189 190 if (lvds_format_24bpp) 191 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_DATA_WIDTH : 0) | 192 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_DATA_WIDTH : 0); 193 194 if (lvds_format_jeida) 195 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_BIT_MAPPING : 0) | 196 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_BIT_MAPPING : 0); 197 198 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 199 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_DI0_VSYNC_POLARITY : 0) | 200 (fsl_ldb->ch1_enabled ? LDB_CTRL_DI1_VSYNC_POLARITY : 0); 201 202 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg); 203 204 /* Program LVDS_CTRL */ 205 reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN | 206 LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN; 207 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg); 208 209 /* Wait for VBG to stabilize. */ 210 usleep_range(15, 20); 211 212 reg |= (fsl_ldb->ch0_enabled ? LVDS_CTRL_CH0_EN : 0) | 213 (fsl_ldb->ch1_enabled ? LVDS_CTRL_CH1_EN : 0); 214 215 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg); 216 } 217 218 static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, 219 struct drm_bridge_state *old_bridge_state) 220 { 221 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 222 223 /* Stop channel(s). */ 224 if (fsl_ldb->devdata->lvds_en_bit) 225 /* Set LVDS_CTRL_LVDS_EN bit to disable. */ 226 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 227 LVDS_CTRL_LVDS_EN); 228 else 229 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); 230 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0); 231 232 clk_disable_unprepare(fsl_ldb->clk); 233 } 234 235 #define MAX_INPUT_SEL_FORMATS 1 236 static u32 * 237 fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 238 struct drm_bridge_state *bridge_state, 239 struct drm_crtc_state *crtc_state, 240 struct drm_connector_state *conn_state, 241 u32 output_fmt, 242 unsigned int *num_input_fmts) 243 { 244 u32 *input_fmts; 245 246 *num_input_fmts = 0; 247 248 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 249 GFP_KERNEL); 250 if (!input_fmts) 251 return NULL; 252 253 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 254 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 255 256 return input_fmts; 257 } 258 259 static enum drm_mode_status 260 fsl_ldb_mode_valid(struct drm_bridge *bridge, 261 const struct drm_display_info *info, 262 const struct drm_display_mode *mode) 263 { 264 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 265 266 if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) 267 return MODE_CLOCK_HIGH; 268 269 return MODE_OK; 270 } 271 272 static const struct drm_bridge_funcs funcs = { 273 .attach = fsl_ldb_attach, 274 .atomic_enable = fsl_ldb_atomic_enable, 275 .atomic_disable = fsl_ldb_atomic_disable, 276 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 277 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 278 .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts, 279 .atomic_reset = drm_atomic_helper_bridge_reset, 280 .mode_valid = fsl_ldb_mode_valid, 281 }; 282 283 static int fsl_ldb_probe(struct platform_device *pdev) 284 { 285 struct device *dev = &pdev->dev; 286 struct device_node *panel_node; 287 struct device_node *remote1, *remote2; 288 struct drm_panel *panel; 289 struct fsl_ldb *fsl_ldb; 290 int dual_link; 291 292 fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL); 293 if (!fsl_ldb) 294 return -ENOMEM; 295 296 fsl_ldb->devdata = of_device_get_match_data(dev); 297 if (!fsl_ldb->devdata) 298 return -EINVAL; 299 300 fsl_ldb->dev = &pdev->dev; 301 fsl_ldb->bridge.funcs = &funcs; 302 fsl_ldb->bridge.of_node = dev->of_node; 303 304 fsl_ldb->clk = devm_clk_get(dev, "ldb"); 305 if (IS_ERR(fsl_ldb->clk)) 306 return PTR_ERR(fsl_ldb->clk); 307 308 fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent); 309 if (IS_ERR(fsl_ldb->regmap)) 310 return PTR_ERR(fsl_ldb->regmap); 311 312 /* Locate the remote ports and the panel node */ 313 remote1 = of_graph_get_remote_node(dev->of_node, 1, 0); 314 remote2 = of_graph_get_remote_node(dev->of_node, 2, 0); 315 fsl_ldb->ch0_enabled = (remote1 != NULL); 316 fsl_ldb->ch1_enabled = (remote2 != NULL); 317 panel_node = of_node_get(remote1 ? remote1 : remote2); 318 of_node_put(remote1); 319 of_node_put(remote2); 320 321 if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) { 322 of_node_put(panel_node); 323 return dev_err_probe(dev, -ENXIO, "No panel node found"); 324 } 325 326 dev_dbg(dev, "Using %s\n", 327 fsl_ldb_is_dual(fsl_ldb) ? "dual-link mode" : 328 fsl_ldb->ch0_enabled ? "channel 0" : "channel 1"); 329 330 panel = of_drm_find_panel(panel_node); 331 of_node_put(panel_node); 332 if (IS_ERR(panel)) 333 return PTR_ERR(panel); 334 335 fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 336 if (IS_ERR(fsl_ldb->panel_bridge)) 337 return PTR_ERR(fsl_ldb->panel_bridge); 338 339 340 if (fsl_ldb_is_dual(fsl_ldb)) { 341 struct device_node *port1, *port2; 342 343 port1 = of_graph_get_port_by_id(dev->of_node, 1); 344 port2 = of_graph_get_port_by_id(dev->of_node, 2); 345 dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); 346 of_node_put(port1); 347 of_node_put(port2); 348 349 if (dual_link < 0) 350 return dev_err_probe(dev, dual_link, 351 "Error getting dual link configuration\n"); 352 353 /* Only DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS is supported */ 354 if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 355 dev_err(dev, "LVDS channel pixel swap not supported.\n"); 356 return -EINVAL; 357 } 358 } 359 360 platform_set_drvdata(pdev, fsl_ldb); 361 362 drm_bridge_add(&fsl_ldb->bridge); 363 364 return 0; 365 } 366 367 static void fsl_ldb_remove(struct platform_device *pdev) 368 { 369 struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev); 370 371 drm_bridge_remove(&fsl_ldb->bridge); 372 } 373 374 static const struct of_device_id fsl_ldb_match[] = { 375 { .compatible = "fsl,imx8mp-ldb", 376 .data = &fsl_ldb_devdata[IMX8MP_LDB], }, 377 { .compatible = "fsl,imx93-ldb", 378 .data = &fsl_ldb_devdata[IMX93_LDB], }, 379 { /* sentinel */ }, 380 }; 381 MODULE_DEVICE_TABLE(of, fsl_ldb_match); 382 383 static struct platform_driver fsl_ldb_driver = { 384 .probe = fsl_ldb_probe, 385 .remove_new = fsl_ldb_remove, 386 .driver = { 387 .name = "fsl-ldb", 388 .of_match_table = fsl_ldb_match, 389 }, 390 }; 391 module_platform_driver(fsl_ldb_driver); 392 393 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 394 MODULE_DESCRIPTION("Freescale i.MX8MP LDB"); 395 MODULE_LICENSE("GPL"); 396