1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Chrontel CH7033 Video Encoder Driver 4 * 5 * Copyright (C) 2019,2020 Lubomir Rintel 6 */ 7 8 #include <linux/gpio/consumer.h> 9 #include <linux/module.h> 10 #include <linux/regmap.h> 11 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_bridge.h> 14 #include <drm/drm_edid.h> 15 #include <drm/drm_of.h> 16 #include <drm/drm_print.h> 17 #include <drm/drm_probe_helper.h> 18 19 /* Page 0, Register 0x07 */ 20 enum { 21 DRI_PD = BIT(3), 22 IO_PD = BIT(5), 23 }; 24 25 /* Page 0, Register 0x08 */ 26 enum { 27 DRI_PDDRI = GENMASK(7, 4), 28 PDDAC = GENMASK(3, 1), 29 PANEN = BIT(0), 30 }; 31 32 /* Page 0, Register 0x09 */ 33 enum { 34 DPD = BIT(7), 35 GCKOFF = BIT(6), 36 TV_BP = BIT(5), 37 SCLPD = BIT(4), 38 SDPD = BIT(3), 39 VGA_PD = BIT(2), 40 HDBKPD = BIT(1), 41 HDMI_PD = BIT(0), 42 }; 43 44 /* Page 0, Register 0x0a */ 45 enum { 46 MEMINIT = BIT(7), 47 MEMIDLE = BIT(6), 48 MEMPD = BIT(5), 49 STOP = BIT(4), 50 LVDS_PD = BIT(3), 51 HD_DVIB = BIT(2), 52 HDCP_PD = BIT(1), 53 MCU_PD = BIT(0), 54 }; 55 56 /* Page 0, Register 0x18 */ 57 enum { 58 IDF = GENMASK(7, 4), 59 INTEN = BIT(3), 60 SWAP = GENMASK(2, 0), 61 }; 62 63 enum { 64 BYTE_SWAP_RGB = 0, 65 BYTE_SWAP_RBG = 1, 66 BYTE_SWAP_GRB = 2, 67 BYTE_SWAP_GBR = 3, 68 BYTE_SWAP_BRG = 4, 69 BYTE_SWAP_BGR = 5, 70 }; 71 72 /* Page 0, Register 0x19 */ 73 enum { 74 HPO_I = BIT(5), 75 VPO_I = BIT(4), 76 DEPO_I = BIT(3), 77 CRYS_EN = BIT(2), 78 GCLKFREQ = GENMASK(2, 0), 79 }; 80 81 /* Page 0, Register 0x2e */ 82 enum { 83 HFLIP = BIT(7), 84 VFLIP = BIT(6), 85 DEPO_O = BIT(5), 86 HPO_O = BIT(4), 87 VPO_O = BIT(3), 88 TE = GENMASK(2, 0), 89 }; 90 91 /* Page 0, Register 0x2b */ 92 enum { 93 SWAPS = GENMASK(7, 4), 94 VFMT = GENMASK(3, 0), 95 }; 96 97 /* Page 0, Register 0x54 */ 98 enum { 99 COMP_BP = BIT(7), 100 DAC_EN_T = BIT(6), 101 HWO_HDMI_HI = GENMASK(5, 3), 102 HOO_HDMI_HI = GENMASK(2, 0), 103 }; 104 105 /* Page 0, Register 0x57 */ 106 enum { 107 FLDSEN = BIT(7), 108 VWO_HDMI_HI = GENMASK(5, 3), 109 VOO_HDMI_HI = GENMASK(2, 0), 110 }; 111 112 /* Page 0, Register 0x7e */ 113 enum { 114 HDMI_LVDS_SEL = BIT(7), 115 DE_GEN = BIT(6), 116 PWM_INDEX_HI = BIT(5), 117 USE_DE = BIT(4), 118 R_INT = GENMASK(3, 0), 119 }; 120 121 /* Page 1, Register 0x07 */ 122 enum { 123 BPCKSEL = BIT(7), 124 DRI_CMFB_EN = BIT(6), 125 CEC_PUEN = BIT(5), 126 CEC_T = BIT(3), 127 CKINV = BIT(2), 128 CK_TVINV = BIT(1), 129 DRI_CKS2 = BIT(0), 130 }; 131 132 /* Page 1, Register 0x08 */ 133 enum { 134 DACG = BIT(6), 135 DACKTST = BIT(5), 136 DEDGEB = BIT(4), 137 SYO = BIT(3), 138 DRI_IT_LVDS = GENMASK(2, 1), 139 DISPON = BIT(0), 140 }; 141 142 /* Page 1, Register 0x0c */ 143 enum { 144 DRI_PLL_CP = GENMASK(7, 6), 145 DRI_PLL_DIVSEL = BIT(5), 146 DRI_PLL_N1_1 = BIT(4), 147 DRI_PLL_N1_0 = BIT(3), 148 DRI_PLL_N3_1 = BIT(2), 149 DRI_PLL_N3_0 = BIT(1), 150 DRI_PLL_CKTSTEN = BIT(0), 151 }; 152 153 /* Page 1, Register 0x6b */ 154 enum { 155 VCO3CS = GENMASK(7, 6), 156 ICPGBK2_0 = GENMASK(5, 3), 157 DRI_VCO357SC = BIT(2), 158 PDPLL2 = BIT(1), 159 DRI_PD_SER = BIT(0), 160 }; 161 162 /* Page 1, Register 0x6c */ 163 enum { 164 PLL2N11 = GENMASK(7, 4), 165 PLL2N5_4 = BIT(3), 166 PLL2N5_TOP = BIT(2), 167 DRI_PLL_PD = BIT(1), 168 PD_I2CM = BIT(0), 169 }; 170 171 /* Page 3, Register 0x28 */ 172 enum { 173 DIFF_EN = GENMASK(7, 6), 174 CORREC_EN = GENMASK(5, 4), 175 VGACLK_BP = BIT(3), 176 HM_LV_SEL = BIT(2), 177 HD_VGA_SEL = BIT(1), 178 }; 179 180 /* Page 3, Register 0x2a */ 181 enum { 182 LVDSCLK_BP = BIT(7), 183 HDTVCLK_BP = BIT(6), 184 HDMICLK_BP = BIT(5), 185 HDTV_BP = BIT(4), 186 HDMI_BP = BIT(3), 187 THRWL = GENMASK(2, 0), 188 }; 189 190 /* Page 4, Register 0x52 */ 191 enum { 192 PGM_ARSTB = BIT(7), 193 MCU_ARSTB = BIT(6), 194 MCU_RETB = BIT(2), 195 RESETIB = BIT(1), 196 RESETDB = BIT(0), 197 }; 198 199 struct ch7033_priv { 200 struct regmap *regmap; 201 struct drm_bridge *next_bridge; 202 struct drm_bridge bridge; 203 struct drm_connector connector; 204 }; 205 206 #define conn_to_ch7033_priv(x) \ 207 container_of(x, struct ch7033_priv, connector) 208 #define bridge_to_ch7033_priv(x) \ 209 container_of(x, struct ch7033_priv, bridge) 210 211 212 static enum drm_connector_status ch7033_connector_detect( 213 struct drm_connector *connector, bool force) 214 { 215 struct ch7033_priv *priv = conn_to_ch7033_priv(connector); 216 217 return drm_bridge_detect(priv->next_bridge); 218 } 219 220 static const struct drm_connector_funcs ch7033_connector_funcs = { 221 .reset = drm_atomic_helper_connector_reset, 222 .fill_modes = drm_helper_probe_single_connector_modes, 223 .detect = ch7033_connector_detect, 224 .destroy = drm_connector_cleanup, 225 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 226 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 227 }; 228 229 static int ch7033_connector_get_modes(struct drm_connector *connector) 230 { 231 struct ch7033_priv *priv = conn_to_ch7033_priv(connector); 232 struct edid *edid; 233 int ret; 234 235 edid = drm_bridge_get_edid(priv->next_bridge, connector); 236 drm_connector_update_edid_property(connector, edid); 237 if (edid) { 238 ret = drm_add_edid_modes(connector, edid); 239 kfree(edid); 240 } else { 241 ret = drm_add_modes_noedid(connector, 1920, 1080); 242 drm_set_preferred_mode(connector, 1024, 768); 243 } 244 245 return ret; 246 } 247 248 static struct drm_encoder *ch7033_connector_best_encoder( 249 struct drm_connector *connector) 250 { 251 struct ch7033_priv *priv = conn_to_ch7033_priv(connector); 252 253 return priv->bridge.encoder; 254 } 255 256 static const struct drm_connector_helper_funcs ch7033_connector_helper_funcs = { 257 .get_modes = ch7033_connector_get_modes, 258 .best_encoder = ch7033_connector_best_encoder, 259 }; 260 261 static void ch7033_hpd_event(void *arg, enum drm_connector_status status) 262 { 263 struct ch7033_priv *priv = arg; 264 265 if (priv->bridge.dev) 266 drm_helper_hpd_irq_event(priv->connector.dev); 267 } 268 269 static int ch7033_bridge_attach(struct drm_bridge *bridge, 270 enum drm_bridge_attach_flags flags) 271 { 272 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge); 273 struct drm_connector *connector = &priv->connector; 274 int ret; 275 276 ret = drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge, 277 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 278 if (ret) 279 return ret; 280 281 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 282 return 0; 283 284 if (priv->next_bridge->ops & DRM_BRIDGE_OP_DETECT) { 285 connector->polled = DRM_CONNECTOR_POLL_HPD; 286 } else { 287 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 288 DRM_CONNECTOR_POLL_DISCONNECT; 289 } 290 291 if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) { 292 drm_bridge_hpd_enable(priv->next_bridge, ch7033_hpd_event, 293 priv); 294 } 295 296 drm_connector_helper_add(connector, 297 &ch7033_connector_helper_funcs); 298 ret = drm_connector_init_with_ddc(bridge->dev, &priv->connector, 299 &ch7033_connector_funcs, 300 priv->next_bridge->type, 301 priv->next_bridge->ddc); 302 if (ret) { 303 DRM_ERROR("Failed to initialize connector\n"); 304 return ret; 305 } 306 307 return drm_connector_attach_encoder(&priv->connector, bridge->encoder); 308 } 309 310 static void ch7033_bridge_detach(struct drm_bridge *bridge) 311 { 312 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge); 313 314 if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) 315 drm_bridge_hpd_disable(priv->next_bridge); 316 drm_connector_cleanup(&priv->connector); 317 } 318 319 static enum drm_mode_status ch7033_bridge_mode_valid(struct drm_bridge *bridge, 320 const struct drm_display_mode *mode) 321 { 322 if (mode->clock > 165000) 323 return MODE_CLOCK_HIGH; 324 if (mode->hdisplay >= 1920) 325 return MODE_BAD_HVALUE; 326 if (mode->vdisplay >= 1080) 327 return MODE_BAD_VVALUE; 328 return MODE_OK; 329 } 330 331 static void ch7033_bridge_disable(struct drm_bridge *bridge) 332 { 333 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge); 334 335 regmap_write(priv->regmap, 0x03, 0x04); 336 regmap_update_bits(priv->regmap, 0x52, RESETDB, 0x00); 337 } 338 339 static void ch7033_bridge_enable(struct drm_bridge *bridge) 340 { 341 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge); 342 343 regmap_write(priv->regmap, 0x03, 0x04); 344 regmap_update_bits(priv->regmap, 0x52, RESETDB, RESETDB); 345 } 346 347 static void ch7033_bridge_mode_set(struct drm_bridge *bridge, 348 const struct drm_display_mode *mode, 349 const struct drm_display_mode *adjusted_mode) 350 { 351 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge); 352 int hbporch = mode->hsync_start - mode->hdisplay; 353 int hsynclen = mode->hsync_end - mode->hsync_start; 354 int vbporch = mode->vsync_start - mode->vdisplay; 355 int vsynclen = mode->vsync_end - mode->vsync_start; 356 357 /* 358 * Page 4 359 */ 360 regmap_write(priv->regmap, 0x03, 0x04); 361 362 /* Turn everything off to set all the registers to their defaults. */ 363 regmap_write(priv->regmap, 0x52, 0x00); 364 /* Bring I/O block up. */ 365 regmap_write(priv->regmap, 0x52, RESETIB); 366 367 /* 368 * Page 0 369 */ 370 regmap_write(priv->regmap, 0x03, 0x00); 371 372 /* Bring up parts we need from the power down. */ 373 regmap_update_bits(priv->regmap, 0x07, DRI_PD | IO_PD, 0); 374 regmap_update_bits(priv->regmap, 0x08, DRI_PDDRI | PDDAC | PANEN, 0); 375 regmap_update_bits(priv->regmap, 0x09, DPD | GCKOFF | 376 HDMI_PD | VGA_PD, 0); 377 regmap_update_bits(priv->regmap, 0x0a, HD_DVIB, 0); 378 379 /* Horizontal input timing. */ 380 regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 | 381 (mode->hdisplay >> 8)); 382 regmap_write(priv->regmap, 0x0c, mode->hdisplay); 383 regmap_write(priv->regmap, 0x0d, mode->htotal); 384 regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 | 385 (hbporch >> 8)); 386 regmap_write(priv->regmap, 0x0f, hbporch); 387 regmap_write(priv->regmap, 0x10, hsynclen); 388 389 /* Vertical input timing. */ 390 regmap_write(priv->regmap, 0x11, (mode->vtotal >> 8) << 3 | 391 (mode->vdisplay >> 8)); 392 regmap_write(priv->regmap, 0x12, mode->vdisplay); 393 regmap_write(priv->regmap, 0x13, mode->vtotal); 394 regmap_write(priv->regmap, 0x14, ((vsynclen >> 8) << 3) | 395 (vbporch >> 8)); 396 regmap_write(priv->regmap, 0x15, vbporch); 397 regmap_write(priv->regmap, 0x16, vsynclen); 398 399 /* Input color swap. */ 400 regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); 401 402 /* Input clock and sync polarity. */ 403 regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16); 404 regmap_update_bits(priv->regmap, 0x19, HPO_I | VPO_I | GCLKFREQ, 405 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0 | 406 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0 | 407 mode->clock >> 16); 408 regmap_write(priv->regmap, 0x1a, mode->clock >> 8); 409 regmap_write(priv->regmap, 0x1b, mode->clock); 410 411 /* Horizontal output timing. */ 412 regmap_write(priv->regmap, 0x1f, (mode->htotal >> 8) << 3 | 413 (mode->hdisplay >> 8)); 414 regmap_write(priv->regmap, 0x20, mode->hdisplay); 415 regmap_write(priv->regmap, 0x21, mode->htotal); 416 417 /* Vertical output timing. */ 418 regmap_write(priv->regmap, 0x25, (mode->vtotal >> 8) << 3 | 419 (mode->vdisplay >> 8)); 420 regmap_write(priv->regmap, 0x26, mode->vdisplay); 421 regmap_write(priv->regmap, 0x27, mode->vtotal); 422 423 /* VGA channel bypass */ 424 regmap_update_bits(priv->regmap, 0x2b, VFMT, 9); 425 426 /* Output sync polarity. */ 427 regmap_update_bits(priv->regmap, 0x2e, HPO_O | VPO_O, 428 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0 | 429 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0); 430 431 /* HDMI horizontal output timing. */ 432 regmap_update_bits(priv->regmap, 0x54, HWO_HDMI_HI | HOO_HDMI_HI, 433 (hsynclen >> 8) << 3 | 434 (hbporch >> 8)); 435 regmap_write(priv->regmap, 0x55, hbporch); 436 regmap_write(priv->regmap, 0x56, hsynclen); 437 438 /* HDMI vertical output timing. */ 439 regmap_update_bits(priv->regmap, 0x57, VWO_HDMI_HI | VOO_HDMI_HI, 440 (vsynclen >> 8) << 3 | 441 (vbporch >> 8)); 442 regmap_write(priv->regmap, 0x58, vbporch); 443 regmap_write(priv->regmap, 0x59, vsynclen); 444 445 /* Pick HDMI, not LVDS. */ 446 regmap_update_bits(priv->regmap, 0x7e, HDMI_LVDS_SEL, HDMI_LVDS_SEL); 447 448 /* 449 * Page 1 450 */ 451 regmap_write(priv->regmap, 0x03, 0x01); 452 453 /* No idea what these do, but VGA is wobbly and blinky without them. */ 454 regmap_update_bits(priv->regmap, 0x07, CKINV, CKINV); 455 regmap_update_bits(priv->regmap, 0x08, DISPON, DISPON); 456 457 /* DRI PLL */ 458 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_DIVSEL, DRI_PLL_DIVSEL); 459 if (mode->clock <= 40000) { 460 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | 461 DRI_PLL_N1_0 | 462 DRI_PLL_N3_1 | 463 DRI_PLL_N3_0, 464 0); 465 } else if (mode->clock < 80000) { 466 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | 467 DRI_PLL_N1_0 | 468 DRI_PLL_N3_1 | 469 DRI_PLL_N3_0, 470 DRI_PLL_N3_0 | 471 DRI_PLL_N1_0); 472 } else { 473 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | 474 DRI_PLL_N1_0 | 475 DRI_PLL_N3_1 | 476 DRI_PLL_N3_0, 477 DRI_PLL_N3_1 | 478 DRI_PLL_N1_1); 479 } 480 481 /* This seems to be color calibration for VGA. */ 482 regmap_write(priv->regmap, 0x64, 0x29); /* LSB Blue */ 483 regmap_write(priv->regmap, 0x65, 0x29); /* LSB Green */ 484 regmap_write(priv->regmap, 0x66, 0x29); /* LSB Red */ 485 regmap_write(priv->regmap, 0x67, 0x00); /* MSB Blue */ 486 regmap_write(priv->regmap, 0x68, 0x00); /* MSB Green */ 487 regmap_write(priv->regmap, 0x69, 0x00); /* MSB Red */ 488 489 regmap_update_bits(priv->regmap, 0x6b, DRI_PD_SER, 0x00); 490 regmap_update_bits(priv->regmap, 0x6c, DRI_PLL_PD, 0x00); 491 492 /* 493 * Page 3 494 */ 495 regmap_write(priv->regmap, 0x03, 0x03); 496 497 /* More bypasses and apparently another HDMI/LVDS selector. */ 498 regmap_update_bits(priv->regmap, 0x28, VGACLK_BP | HM_LV_SEL, 499 VGACLK_BP | HM_LV_SEL); 500 regmap_update_bits(priv->regmap, 0x2a, HDMICLK_BP | HDMI_BP, 501 HDMICLK_BP | HDMI_BP); 502 503 /* 504 * Page 4 505 */ 506 regmap_write(priv->regmap, 0x03, 0x04); 507 508 /* Output clock. */ 509 regmap_write(priv->regmap, 0x10, mode->clock >> 16); 510 regmap_write(priv->regmap, 0x11, mode->clock >> 8); 511 regmap_write(priv->regmap, 0x12, mode->clock); 512 } 513 514 static const struct drm_bridge_funcs ch7033_bridge_funcs = { 515 .attach = ch7033_bridge_attach, 516 .detach = ch7033_bridge_detach, 517 .mode_valid = ch7033_bridge_mode_valid, 518 .disable = ch7033_bridge_disable, 519 .enable = ch7033_bridge_enable, 520 .mode_set = ch7033_bridge_mode_set, 521 }; 522 523 static const struct regmap_config ch7033_regmap_config = { 524 .reg_bits = 8, 525 .val_bits = 8, 526 .max_register = 0x7f, 527 }; 528 529 static int ch7033_probe(struct i2c_client *client, 530 const struct i2c_device_id *id) 531 { 532 struct device *dev = &client->dev; 533 struct ch7033_priv *priv; 534 unsigned int val; 535 int ret; 536 537 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 538 if (!priv) 539 return -ENOMEM; 540 541 dev_set_drvdata(dev, priv); 542 543 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, NULL, 544 &priv->next_bridge); 545 if (ret) 546 return ret; 547 548 priv->regmap = devm_regmap_init_i2c(client, &ch7033_regmap_config); 549 if (IS_ERR(priv->regmap)) { 550 dev_err(&client->dev, "regmap init failed\n"); 551 return PTR_ERR(priv->regmap); 552 } 553 554 ret = regmap_read(priv->regmap, 0x00, &val); 555 if (ret < 0) { 556 dev_err(&client->dev, "error reading the model id: %d\n", ret); 557 return ret; 558 } 559 if ((val & 0xf7) != 0x56) { 560 dev_err(&client->dev, "the device is not a ch7033\n"); 561 return -ENODEV; 562 } 563 564 regmap_write(priv->regmap, 0x03, 0x04); 565 ret = regmap_read(priv->regmap, 0x51, &val); 566 if (ret < 0) { 567 dev_err(&client->dev, "error reading the model id: %d\n", ret); 568 return ret; 569 } 570 if ((val & 0x0f) != 3) { 571 dev_err(&client->dev, "unknown revision %u\n", val); 572 return -ENODEV; 573 } 574 575 INIT_LIST_HEAD(&priv->bridge.list); 576 priv->bridge.funcs = &ch7033_bridge_funcs; 577 priv->bridge.of_node = dev->of_node; 578 drm_bridge_add(&priv->bridge); 579 580 dev_info(dev, "Chrontel CH7033 Video Encoder\n"); 581 return 0; 582 } 583 584 static int ch7033_remove(struct i2c_client *client) 585 { 586 struct device *dev = &client->dev; 587 struct ch7033_priv *priv = dev_get_drvdata(dev); 588 589 drm_bridge_remove(&priv->bridge); 590 591 return 0; 592 } 593 594 static const struct of_device_id ch7033_dt_ids[] = { 595 { .compatible = "chrontel,ch7033", }, 596 { } 597 }; 598 MODULE_DEVICE_TABLE(of, ch7033_dt_ids); 599 600 static const struct i2c_device_id ch7033_ids[] = { 601 { "ch7033", 0 }, 602 { } 603 }; 604 MODULE_DEVICE_TABLE(i2c, ch7033_ids); 605 606 static struct i2c_driver ch7033_driver = { 607 .probe = ch7033_probe, 608 .remove = ch7033_remove, 609 .driver = { 610 .name = "ch7033", 611 .of_match_table = of_match_ptr(ch7033_dt_ids), 612 }, 613 .id_table = ch7033_ids, 614 }; 615 616 module_i2c_driver(ch7033_driver); 617 618 MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>"); 619 MODULE_DESCRIPTION("Chrontel CH7033 Video Encoder Driver"); 620 MODULE_LICENSE("GPL v2"); 621