1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2020 Amarula Solutions(India) 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 */ 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_of.h> 9 #include <drm/drm_print.h> 10 #include <drm/drm_mipi_dsi.h> 11 12 #include <linux/bitfield.h> 13 #include <linux/bits.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/i2c.h> 17 #include <linux/media-bus-format.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 23 #define VENDOR_ID 0x00 24 #define DEVICE_ID_H 0x01 25 #define DEVICE_ID_L 0x02 26 #define VERSION_ID 0x03 27 #define FIRMWARE_VERSION 0x08 28 #define CONFIG_FINISH 0x09 29 #define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */ 30 #define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */ 31 #define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */ 32 #define SYS_CTRL_1_CLK_PHASE_MSK GENMASK(5, 4) 33 #define CLK_PHASE_0 0 34 #define CLK_PHASE_1_4 1 35 #define CLK_PHASE_1_2 2 36 #define CLK_PHASE_3_4 3 37 #define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */ 38 #define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */ 39 #define RGB_TEST_CTRL 0x1e 40 #define ATE_PLL_EN 0x1f 41 #define HACTIVE_LI 0x20 42 #define VACTIVE_LI 0x21 43 #define VACTIVE_HACTIVE_HI 0x22 44 #define HFP_LI 0x23 45 #define HSYNC_LI 0x24 46 #define HBP_LI 0x25 47 #define HFP_HSW_HBP_HI 0x26 48 #define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4) 49 #define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6) 50 #define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8) 51 #define VFP 0x27 52 #define VSYNC 0x28 53 #define VBP 0x29 54 #define BIST_POL 0x2a 55 #define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4) 56 #define BIST_POL_BIST_GEN BIT(3) 57 #define BIST_POL_HSYNC_POL BIT(2) 58 #define BIST_POL_VSYNC_POL BIT(1) 59 #define BIST_POL_DE_POL BIT(0) 60 #define BIST_RED 0x2b 61 #define BIST_GREEN 0x2c 62 #define BIST_BLUE 0x2d 63 #define BIST_CHESS_X 0x2e 64 #define BIST_CHESS_Y 0x2f 65 #define BIST_CHESS_XY_H 0x30 66 #define BIST_FRAME_TIME_L 0x31 67 #define BIST_FRAME_TIME_H 0x32 68 #define FIFO_MAX_ADDR_LOW 0x33 69 #define SYNC_EVENT_DLY 0x34 70 #define HSW_MIN 0x35 71 #define HFP_MIN 0x36 72 #define LOGIC_RST_NUM 0x37 73 #define OSC_CTRL(n) (0x48 + ((n) & 0x7)) /* 0..5 */ 74 #define BG_CTRL 0x4e 75 #define LDO_PLL 0x4f 76 #define PLL_CTRL(n) (0x50 + ((n) & 0xf)) /* 0..15 */ 77 #define PLL_CTRL_6_EXTERNAL 0x90 78 #define PLL_CTRL_6_MIPI_CLK 0x92 79 #define PLL_CTRL_6_INTERNAL 0x93 80 #define PLL_REM(n) (0x60 + ((n) & 0x3)) /* 0..2 */ 81 #define PLL_DIV(n) (0x63 + ((n) & 0x3)) /* 0..2 */ 82 #define PLL_FRAC(n) (0x66 + ((n) & 0x3)) /* 0..2 */ 83 #define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 */ 84 #define PLL_REF_DIV 0x6b 85 #define PLL_REF_DIV_P(n) ((n) & 0xf) 86 #define PLL_REF_DIV_Pe BIT(4) 87 #define PLL_REF_DIV_S(n) (((n) & 0x7) << 5) 88 #define PLL_SSC_P(n) (0x6c + ((n) & 0x3)) /* 0..2 */ 89 #define PLL_SSC_STEP(n) (0x6f + ((n) & 0x3)) /* 0..2 */ 90 #define PLL_SSC_OFFSET(n) (0x72 + ((n) & 0x3)) /* 0..3 */ 91 #define GPIO_OEN 0x79 92 #define MIPI_CFG_PW 0x7a 93 #define MIPI_CFG_PW_CONFIG_DSI 0xc1 94 #define MIPI_CFG_PW_CONFIG_I2C 0x3e 95 #define GPIO_SEL(n) (0x7b + ((n) & 0x1)) /* 0..1 */ 96 #define IRQ_SEL 0x7d 97 #define DBG_SEL 0x7e 98 #define DBG_SIGNAL 0x7f 99 #define MIPI_ERR_VECTOR_L 0x80 100 #define MIPI_ERR_VECTOR_H 0x81 101 #define MIPI_ERR_VECTOR_EN_L 0x82 102 #define MIPI_ERR_VECTOR_EN_H 0x83 103 #define MIPI_MAX_SIZE_L 0x84 104 #define MIPI_MAX_SIZE_H 0x85 105 #define DSI_CTRL 0x86 106 #define DSI_CTRL_UNKNOWN 0x28 107 #define DSI_CTRL_DSI_LANES(n) ((n) & 0x3) 108 #define MIPI_PN_SWAP 0x87 109 #define MIPI_PN_SWAP_CLK BIT(4) 110 #define MIPI_PN_SWAP_D(n) BIT((n) & 0x3) 111 #define MIPI_SOT_SYNC_BIT(n) (0x88 + ((n) & 0x1)) /* 0..1 */ 112 #define MIPI_ULPS_CTRL 0x8a 113 #define MIPI_CLK_CHK_VAR 0x8e 114 #define MIPI_CLK_CHK_INI 0x8f 115 #define MIPI_T_TERM_EN 0x90 116 #define MIPI_T_HS_SETTLE 0x91 117 #define MIPI_T_TA_SURE_PRE 0x92 118 #define MIPI_T_LPX_SET 0x94 119 #define MIPI_T_CLK_MISS 0x95 120 #define MIPI_INIT_TIME_L 0x96 121 #define MIPI_INIT_TIME_H 0x97 122 #define MIPI_T_CLK_TERM_EN 0x99 123 #define MIPI_T_CLK_SETTLE 0x9a 124 #define MIPI_TO_HS_RX_L 0x9e 125 #define MIPI_TO_HS_RX_H 0x9f 126 #define MIPI_PHY(n) (0xa0 + ((n) & 0x7)) /* 0..5 */ 127 #define MIPI_PD_RX 0xb0 128 #define MIPI_PD_TERM 0xb1 129 #define MIPI_PD_HSRX 0xb2 130 #define MIPI_PD_LPTX 0xb3 131 #define MIPI_PD_LPRX 0xb4 132 #define MIPI_PD_CK_LANE 0xb5 133 #define MIPI_FORCE_0 0xb6 134 #define MIPI_RST_CTRL 0xb7 135 #define MIPI_RST_NUM 0xb8 136 #define MIPI_DBG_SET(n) (0xc0 + ((n) & 0xf)) /* 0..9 */ 137 #define MIPI_DBG_SEL 0xe0 138 #define MIPI_DBG_DATA 0xe1 139 #define MIPI_ATE_TEST_SEL 0xe2 140 #define MIPI_ATE_STATUS(n) (0xe3 + ((n) & 0x1)) /* 0..1 */ 141 142 struct chipone { 143 struct device *dev; 144 struct regmap *regmap; 145 struct i2c_client *client; 146 struct drm_bridge bridge; 147 struct drm_display_mode mode; 148 struct drm_bridge *panel_bridge; 149 struct mipi_dsi_device *dsi; 150 struct gpio_desc *enable_gpio; 151 struct regulator *vdd1; 152 struct regulator *vdd2; 153 struct regulator *vdd3; 154 bool interface_i2c; 155 }; 156 157 static const struct regmap_range chipone_dsi_readable_ranges[] = { 158 regmap_reg_range(VENDOR_ID, VERSION_ID), 159 regmap_reg_range(FIRMWARE_VERSION, PLL_SSC_OFFSET(3)), 160 regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL), 161 regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE), 162 regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H), 163 regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE), 164 regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)), 165 regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM), 166 regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)), 167 regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)), 168 }; 169 170 static const struct regmap_access_table chipone_dsi_readable_table = { 171 .yes_ranges = chipone_dsi_readable_ranges, 172 .n_yes_ranges = ARRAY_SIZE(chipone_dsi_readable_ranges), 173 }; 174 175 static const struct regmap_range chipone_dsi_writeable_ranges[] = { 176 regmap_reg_range(CONFIG_FINISH, PLL_SSC_OFFSET(3)), 177 regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL), 178 regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE), 179 regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H), 180 regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE), 181 regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)), 182 regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM), 183 regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)), 184 regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)), 185 }; 186 187 static const struct regmap_access_table chipone_dsi_writeable_table = { 188 .yes_ranges = chipone_dsi_writeable_ranges, 189 .n_yes_ranges = ARRAY_SIZE(chipone_dsi_writeable_ranges), 190 }; 191 192 static const struct regmap_config chipone_regmap_config = { 193 .reg_bits = 8, 194 .val_bits = 8, 195 .rd_table = &chipone_dsi_readable_table, 196 .wr_table = &chipone_dsi_writeable_table, 197 .cache_type = REGCACHE_RBTREE, 198 .max_register = MIPI_ATE_STATUS(1), 199 }; 200 201 static int chipone_dsi_read(void *context, 202 const void *reg, size_t reg_size, 203 void *val, size_t val_size) 204 { 205 struct mipi_dsi_device *dsi = context; 206 const u16 reg16 = (val_size << 8) | *(u8 *)reg; 207 int ret; 208 209 ret = mipi_dsi_generic_read(dsi, ®16, 2, val, val_size); 210 211 return ret == val_size ? 0 : -EINVAL; 212 } 213 214 static int chipone_dsi_write(void *context, const void *data, size_t count) 215 { 216 struct mipi_dsi_device *dsi = context; 217 218 return mipi_dsi_generic_write(dsi, data, 2); 219 } 220 221 static const struct regmap_bus chipone_dsi_regmap_bus = { 222 .read = chipone_dsi_read, 223 .write = chipone_dsi_write, 224 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, 225 .val_format_endian_default = REGMAP_ENDIAN_NATIVE, 226 }; 227 228 static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge) 229 { 230 return container_of(bridge, struct chipone, bridge); 231 } 232 233 static void chipone_readb(struct chipone *icn, u8 reg, u8 *val) 234 { 235 int ret, pval; 236 237 ret = regmap_read(icn->regmap, reg, &pval); 238 239 *val = ret ? 0 : pval & 0xff; 240 } 241 242 static int chipone_writeb(struct chipone *icn, u8 reg, u8 val) 243 { 244 return regmap_write(icn->regmap, reg, val); 245 } 246 247 static void chipone_configure_pll(struct chipone *icn, 248 const struct drm_display_mode *mode) 249 { 250 unsigned int best_p = 0, best_m = 0, best_s = 0; 251 unsigned int mode_clock = mode->clock * 1000; 252 unsigned int delta, min_delta = 0xffffffff; 253 unsigned int freq_p, freq_s, freq_out; 254 unsigned int p_min, p_max; 255 unsigned int p, m, s; 256 unsigned int fin; 257 bool best_p_pot; 258 u8 ref_div; 259 260 /* 261 * DSI byte clock frequency (input into PLL) is calculated as: 262 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 8 263 * 264 * DPI pixel clock frequency (output from PLL) is mode clock. 265 * 266 * The chip contains fractional PLL which works as follows: 267 * DPI_CLK = ((DSI_CLK / P) * M) / S 268 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider 269 * register PLL_REF_DIV[4] is extra 1:2 divider 270 * M is integer multiplier, register PLL_INT(0) is multiplier 271 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider 272 * 273 * It seems the PLL input clock after applying P pre-divider have 274 * to be lower than 20 MHz. 275 */ 276 fin = mode_clock * mipi_dsi_pixel_format_to_bpp(icn->dsi->format) / 277 icn->dsi->lanes / 8; /* in Hz */ 278 279 /* Minimum value of P predivider for PLL input in 5..20 MHz */ 280 p_min = clamp(DIV_ROUND_UP(fin, 20000000), 1U, 31U); 281 p_max = clamp(fin / 5000000, 1U, 31U); 282 283 for (p = p_min; p < p_max; p++) { /* PLL_REF_DIV[4,3:0] */ 284 if (p > 16 && p & 1) /* P > 16 uses extra /2 */ 285 continue; 286 freq_p = fin / p; 287 if (freq_p == 0) /* Divider too high */ 288 break; 289 290 for (s = 0; s < 0x7; s++) { /* PLL_REF_DIV[7:5] */ 291 freq_s = freq_p / BIT(s + 1); 292 if (freq_s == 0) /* Divider too high */ 293 break; 294 295 m = mode_clock / freq_s; 296 297 /* Multiplier is 8 bit */ 298 if (m > 0xff) 299 continue; 300 301 /* Limit PLL VCO frequency to 1 GHz */ 302 freq_out = (fin * m) / p; 303 if (freq_out > 1000000000) 304 continue; 305 306 /* Apply post-divider */ 307 freq_out /= BIT(s + 1); 308 309 delta = abs(mode_clock - freq_out); 310 if (delta < min_delta) { 311 best_p = p; 312 best_m = m; 313 best_s = s; 314 min_delta = delta; 315 } 316 } 317 } 318 319 best_p_pot = !(best_p & 1); 320 321 dev_dbg(icn->dev, 322 "PLL: P[3:0]=%d P[4]=2*%d M=%d S[7:5]=2^%d delta=%d => DSI f_in=%d Hz ; DPI f_out=%d Hz\n", 323 best_p >> best_p_pot, best_p_pot, best_m, best_s + 1, 324 min_delta, fin, (fin * best_m) / (best_p << (best_s + 1))); 325 326 ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s); 327 if (best_p_pot) /* Prefer /2 pre-divider */ 328 ref_div |= PLL_REF_DIV_Pe; 329 330 /* Clock source selection fixed to MIPI DSI clock lane */ 331 chipone_writeb(icn, PLL_CTRL(6), PLL_CTRL_6_MIPI_CLK); 332 chipone_writeb(icn, PLL_REF_DIV, ref_div); 333 chipone_writeb(icn, PLL_INT(0), best_m); 334 } 335 336 static void chipone_atomic_enable(struct drm_bridge *bridge, 337 struct drm_bridge_state *old_bridge_state) 338 { 339 struct chipone *icn = bridge_to_chipone(bridge); 340 struct drm_atomic_state *state = old_bridge_state->base.state; 341 struct drm_display_mode *mode = &icn->mode; 342 const struct drm_bridge_state *bridge_state; 343 u16 hfp, hbp, hsync; 344 u32 bus_flags; 345 u8 pol, sys_ctrl_1, id[4]; 346 347 chipone_readb(icn, VENDOR_ID, id); 348 chipone_readb(icn, DEVICE_ID_H, id + 1); 349 chipone_readb(icn, DEVICE_ID_L, id + 2); 350 chipone_readb(icn, VERSION_ID, id + 3); 351 352 dev_dbg(icn->dev, 353 "Chip IDs: Vendor=0x%02x Device=0x%02x:0x%02x Version=0x%02x\n", 354 id[0], id[1], id[2], id[3]); 355 356 if (id[0] != 0xc1 || id[1] != 0x62 || id[2] != 0x11) { 357 dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n"); 358 return; 359 } 360 361 /* Get the DPI flags from the bridge state. */ 362 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 363 bus_flags = bridge_state->output_bus_cfg.flags; 364 365 if (icn->interface_i2c) 366 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C); 367 else 368 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI); 369 370 chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff); 371 372 chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff); 373 374 /* 375 * lsb nibble: 2nd nibble of hdisplay 376 * msb nibble: 2nd nibble of vdisplay 377 */ 378 chipone_writeb(icn, VACTIVE_HACTIVE_HI, 379 ((mode->hdisplay >> 8) & 0xf) | 380 (((mode->vdisplay >> 8) & 0xf) << 4)); 381 382 hfp = mode->hsync_start - mode->hdisplay; 383 hsync = mode->hsync_end - mode->hsync_start; 384 hbp = mode->htotal - mode->hsync_end; 385 386 chipone_writeb(icn, HFP_LI, hfp & 0xff); 387 chipone_writeb(icn, HSYNC_LI, hsync & 0xff); 388 chipone_writeb(icn, HBP_LI, hbp & 0xff); 389 /* Top two bits of Horizontal Front porch/Sync/Back porch */ 390 chipone_writeb(icn, HFP_HSW_HBP_HI, 391 HFP_HSW_HBP_HI_HFP(hfp) | 392 HFP_HSW_HBP_HI_HS(hsync) | 393 HFP_HSW_HBP_HI_HBP(hbp)); 394 395 chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay); 396 397 chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start); 398 399 chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end); 400 401 /* dsi specific sequence */ 402 chipone_writeb(icn, SYNC_EVENT_DLY, 0x80); 403 chipone_writeb(icn, HFP_MIN, hfp & 0xff); 404 405 /* DSI data lane count */ 406 chipone_writeb(icn, DSI_CTRL, 407 DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1)); 408 409 chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0); 410 chipone_writeb(icn, PLL_CTRL(12), 0xff); 411 chipone_writeb(icn, MIPI_PN_SWAP, 0x00); 412 413 /* DPI HS/VS/DE polarity */ 414 pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) | 415 ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) | 416 ((bus_flags & DRM_BUS_FLAG_DE_HIGH) ? BIST_POL_DE_POL : 0); 417 chipone_writeb(icn, BIST_POL, pol); 418 419 /* Configure PLL settings */ 420 chipone_configure_pll(icn, mode); 421 422 chipone_writeb(icn, SYS_CTRL(0), 0x40); 423 sys_ctrl_1 = 0x88; 424 425 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) 426 sys_ctrl_1 |= FIELD_PREP(SYS_CTRL_1_CLK_PHASE_MSK, CLK_PHASE_0); 427 else 428 sys_ctrl_1 |= FIELD_PREP(SYS_CTRL_1_CLK_PHASE_MSK, CLK_PHASE_1_2); 429 430 chipone_writeb(icn, SYS_CTRL(1), sys_ctrl_1); 431 432 /* icn6211 specific sequence */ 433 chipone_writeb(icn, MIPI_FORCE_0, 0x20); 434 chipone_writeb(icn, PLL_CTRL(1), 0x20); 435 chipone_writeb(icn, CONFIG_FINISH, 0x10); 436 437 usleep_range(10000, 11000); 438 } 439 440 static void chipone_atomic_pre_enable(struct drm_bridge *bridge, 441 struct drm_bridge_state *old_bridge_state) 442 { 443 struct chipone *icn = bridge_to_chipone(bridge); 444 int ret; 445 446 if (icn->vdd1) { 447 ret = regulator_enable(icn->vdd1); 448 if (ret) 449 DRM_DEV_ERROR(icn->dev, 450 "failed to enable VDD1 regulator: %d\n", ret); 451 } 452 453 if (icn->vdd2) { 454 ret = regulator_enable(icn->vdd2); 455 if (ret) 456 DRM_DEV_ERROR(icn->dev, 457 "failed to enable VDD2 regulator: %d\n", ret); 458 } 459 460 if (icn->vdd3) { 461 ret = regulator_enable(icn->vdd3); 462 if (ret) 463 DRM_DEV_ERROR(icn->dev, 464 "failed to enable VDD3 regulator: %d\n", ret); 465 } 466 467 gpiod_set_value(icn->enable_gpio, 1); 468 469 usleep_range(10000, 11000); 470 } 471 472 static void chipone_atomic_post_disable(struct drm_bridge *bridge, 473 struct drm_bridge_state *old_bridge_state) 474 { 475 struct chipone *icn = bridge_to_chipone(bridge); 476 477 if (icn->vdd1) 478 regulator_disable(icn->vdd1); 479 480 if (icn->vdd2) 481 regulator_disable(icn->vdd2); 482 483 if (icn->vdd3) 484 regulator_disable(icn->vdd3); 485 486 gpiod_set_value(icn->enable_gpio, 0); 487 } 488 489 static void chipone_mode_set(struct drm_bridge *bridge, 490 const struct drm_display_mode *mode, 491 const struct drm_display_mode *adjusted_mode) 492 { 493 struct chipone *icn = bridge_to_chipone(bridge); 494 495 drm_mode_copy(&icn->mode, adjusted_mode); 496 }; 497 498 static int chipone_dsi_attach(struct chipone *icn) 499 { 500 struct mipi_dsi_device *dsi = icn->dsi; 501 struct device *dev = icn->dev; 502 int dsi_lanes, ret; 503 504 dsi_lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4); 505 506 /* 507 * If the 'data-lanes' property does not exist in DT or is invalid, 508 * default to previously hard-coded behavior, which was 4 data lanes. 509 */ 510 if (dsi_lanes < 0) 511 icn->dsi->lanes = 4; 512 else 513 icn->dsi->lanes = dsi_lanes; 514 515 dsi->format = MIPI_DSI_FMT_RGB888; 516 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 517 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET; 518 519 ret = mipi_dsi_attach(dsi); 520 if (ret < 0) 521 dev_err(icn->dev, "failed to attach dsi\n"); 522 523 return ret; 524 } 525 526 static int chipone_dsi_host_attach(struct chipone *icn) 527 { 528 struct device *dev = icn->dev; 529 struct device_node *host_node; 530 struct device_node *endpoint; 531 struct mipi_dsi_device *dsi; 532 struct mipi_dsi_host *host; 533 int ret = 0; 534 535 const struct mipi_dsi_device_info info = { 536 .type = "chipone", 537 .channel = 0, 538 .node = NULL, 539 }; 540 541 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 542 host_node = of_graph_get_remote_port_parent(endpoint); 543 of_node_put(endpoint); 544 545 if (!host_node) 546 return -EINVAL; 547 548 host = of_find_mipi_dsi_host_by_node(host_node); 549 of_node_put(host_node); 550 if (!host) { 551 dev_err(dev, "failed to find dsi host\n"); 552 return -EPROBE_DEFER; 553 } 554 555 dsi = mipi_dsi_device_register_full(host, &info); 556 if (IS_ERR(dsi)) { 557 return dev_err_probe(dev, PTR_ERR(dsi), 558 "failed to create dsi device\n"); 559 } 560 561 icn->dsi = dsi; 562 563 ret = chipone_dsi_attach(icn); 564 if (ret < 0) 565 mipi_dsi_device_unregister(dsi); 566 567 return ret; 568 } 569 570 static int chipone_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) 571 { 572 struct chipone *icn = bridge_to_chipone(bridge); 573 574 return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags); 575 } 576 577 #define MAX_INPUT_SEL_FORMATS 1 578 579 static u32 * 580 chipone_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 581 struct drm_bridge_state *bridge_state, 582 struct drm_crtc_state *crtc_state, 583 struct drm_connector_state *conn_state, 584 u32 output_fmt, 585 unsigned int *num_input_fmts) 586 { 587 u32 *input_fmts; 588 589 *num_input_fmts = 0; 590 591 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 592 GFP_KERNEL); 593 if (!input_fmts) 594 return NULL; 595 596 /* This is the DSI-end bus format */ 597 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 598 *num_input_fmts = 1; 599 600 return input_fmts; 601 } 602 603 static const struct drm_bridge_funcs chipone_bridge_funcs = { 604 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 605 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 606 .atomic_reset = drm_atomic_helper_bridge_reset, 607 .atomic_pre_enable = chipone_atomic_pre_enable, 608 .atomic_enable = chipone_atomic_enable, 609 .atomic_post_disable = chipone_atomic_post_disable, 610 .mode_set = chipone_mode_set, 611 .attach = chipone_attach, 612 .atomic_get_input_bus_fmts = chipone_atomic_get_input_bus_fmts, 613 }; 614 615 static int chipone_parse_dt(struct chipone *icn) 616 { 617 struct device *dev = icn->dev; 618 int ret; 619 620 icn->vdd1 = devm_regulator_get_optional(dev, "vdd1"); 621 if (IS_ERR(icn->vdd1)) { 622 ret = PTR_ERR(icn->vdd1); 623 if (ret == -EPROBE_DEFER) 624 return -EPROBE_DEFER; 625 icn->vdd1 = NULL; 626 DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret); 627 } 628 629 icn->vdd2 = devm_regulator_get_optional(dev, "vdd2"); 630 if (IS_ERR(icn->vdd2)) { 631 ret = PTR_ERR(icn->vdd2); 632 if (ret == -EPROBE_DEFER) 633 return -EPROBE_DEFER; 634 icn->vdd2 = NULL; 635 DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret); 636 } 637 638 icn->vdd3 = devm_regulator_get_optional(dev, "vdd3"); 639 if (IS_ERR(icn->vdd3)) { 640 ret = PTR_ERR(icn->vdd3); 641 if (ret == -EPROBE_DEFER) 642 return -EPROBE_DEFER; 643 icn->vdd3 = NULL; 644 DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret); 645 } 646 647 icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); 648 if (IS_ERR(icn->enable_gpio)) { 649 DRM_DEV_ERROR(dev, "failed to get enable GPIO\n"); 650 return PTR_ERR(icn->enable_gpio); 651 } 652 653 icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); 654 if (IS_ERR(icn->panel_bridge)) 655 return PTR_ERR(icn->panel_bridge); 656 657 return 0; 658 } 659 660 static int chipone_common_probe(struct device *dev, struct chipone **icnr) 661 { 662 struct chipone *icn; 663 int ret; 664 665 icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL); 666 if (!icn) 667 return -ENOMEM; 668 669 icn->dev = dev; 670 671 ret = chipone_parse_dt(icn); 672 if (ret) 673 return ret; 674 675 icn->bridge.funcs = &chipone_bridge_funcs; 676 icn->bridge.type = DRM_MODE_CONNECTOR_DPI; 677 icn->bridge.of_node = dev->of_node; 678 679 *icnr = icn; 680 681 return ret; 682 } 683 684 static int chipone_dsi_probe(struct mipi_dsi_device *dsi) 685 { 686 struct device *dev = &dsi->dev; 687 struct chipone *icn; 688 int ret; 689 690 ret = chipone_common_probe(dev, &icn); 691 if (ret) 692 return ret; 693 694 icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus, 695 dsi, &chipone_regmap_config); 696 if (IS_ERR(icn->regmap)) 697 return PTR_ERR(icn->regmap); 698 699 icn->interface_i2c = false; 700 icn->dsi = dsi; 701 702 mipi_dsi_set_drvdata(dsi, icn); 703 704 drm_bridge_add(&icn->bridge); 705 706 ret = chipone_dsi_attach(icn); 707 if (ret) 708 drm_bridge_remove(&icn->bridge); 709 710 return ret; 711 } 712 713 static int chipone_i2c_probe(struct i2c_client *client, 714 const struct i2c_device_id *id) 715 { 716 struct device *dev = &client->dev; 717 struct chipone *icn; 718 int ret; 719 720 ret = chipone_common_probe(dev, &icn); 721 if (ret) 722 return ret; 723 724 icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config); 725 if (IS_ERR(icn->regmap)) 726 return PTR_ERR(icn->regmap); 727 728 icn->interface_i2c = true; 729 icn->client = client; 730 dev_set_drvdata(dev, icn); 731 i2c_set_clientdata(client, icn); 732 733 drm_bridge_add(&icn->bridge); 734 735 return chipone_dsi_host_attach(icn); 736 } 737 738 static int chipone_dsi_remove(struct mipi_dsi_device *dsi) 739 { 740 struct chipone *icn = mipi_dsi_get_drvdata(dsi); 741 742 mipi_dsi_detach(dsi); 743 drm_bridge_remove(&icn->bridge); 744 745 return 0; 746 } 747 748 static const struct of_device_id chipone_of_match[] = { 749 { .compatible = "chipone,icn6211", }, 750 { /* sentinel */ } 751 }; 752 MODULE_DEVICE_TABLE(of, chipone_of_match); 753 754 static struct mipi_dsi_driver chipone_dsi_driver = { 755 .probe = chipone_dsi_probe, 756 .remove = chipone_dsi_remove, 757 .driver = { 758 .name = "chipone-icn6211", 759 .owner = THIS_MODULE, 760 .of_match_table = chipone_of_match, 761 }, 762 }; 763 764 static struct i2c_device_id chipone_i2c_id[] = { 765 { "chipone,icn6211" }, 766 {}, 767 }; 768 MODULE_DEVICE_TABLE(i2c, chipone_i2c_id); 769 770 static struct i2c_driver chipone_i2c_driver = { 771 .probe = chipone_i2c_probe, 772 .id_table = chipone_i2c_id, 773 .driver = { 774 .name = "chipone-icn6211-i2c", 775 .of_match_table = chipone_of_match, 776 }, 777 }; 778 779 static int __init chipone_init(void) 780 { 781 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 782 mipi_dsi_driver_register(&chipone_dsi_driver); 783 784 return i2c_add_driver(&chipone_i2c_driver); 785 } 786 module_init(chipone_init); 787 788 static void __exit chipone_exit(void) 789 { 790 i2c_del_driver(&chipone_i2c_driver); 791 792 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 793 mipi_dsi_driver_unregister(&chipone_dsi_driver); 794 } 795 module_exit(chipone_exit); 796 797 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 798 MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge"); 799 MODULE_LICENSE("GPL"); 800