1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2020 Amarula Solutions(India) 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 */ 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_of.h> 9 #include <drm/drm_print.h> 10 #include <drm/drm_mipi_dsi.h> 11 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 20 #define VENDOR_ID 0x00 21 #define DEVICE_ID_H 0x01 22 #define DEVICE_ID_L 0x02 23 #define VERSION_ID 0x03 24 #define FIRMWARE_VERSION 0x08 25 #define CONFIG_FINISH 0x09 26 #define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */ 27 #define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */ 28 #define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */ 29 #define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */ 30 #define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */ 31 #define RGB_TEST_CTRL 0x1e 32 #define ATE_PLL_EN 0x1f 33 #define HACTIVE_LI 0x20 34 #define VACTIVE_LI 0x21 35 #define VACTIVE_HACTIVE_HI 0x22 36 #define HFP_LI 0x23 37 #define HSYNC_LI 0x24 38 #define HBP_LI 0x25 39 #define HFP_HSW_HBP_HI 0x26 40 #define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4) 41 #define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6) 42 #define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8) 43 #define VFP 0x27 44 #define VSYNC 0x28 45 #define VBP 0x29 46 #define BIST_POL 0x2a 47 #define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4) 48 #define BIST_POL_BIST_GEN BIT(3) 49 #define BIST_POL_HSYNC_POL BIT(2) 50 #define BIST_POL_VSYNC_POL BIT(1) 51 #define BIST_POL_DE_POL BIT(0) 52 #define BIST_RED 0x2b 53 #define BIST_GREEN 0x2c 54 #define BIST_BLUE 0x2d 55 #define BIST_CHESS_X 0x2e 56 #define BIST_CHESS_Y 0x2f 57 #define BIST_CHESS_XY_H 0x30 58 #define BIST_FRAME_TIME_L 0x31 59 #define BIST_FRAME_TIME_H 0x32 60 #define FIFO_MAX_ADDR_LOW 0x33 61 #define SYNC_EVENT_DLY 0x34 62 #define HSW_MIN 0x35 63 #define HFP_MIN 0x36 64 #define LOGIC_RST_NUM 0x37 65 #define OSC_CTRL(n) (0x48 + ((n) & 0x7)) /* 0..5 */ 66 #define BG_CTRL 0x4e 67 #define LDO_PLL 0x4f 68 #define PLL_CTRL(n) (0x50 + ((n) & 0xf)) /* 0..15 */ 69 #define PLL_CTRL_6_EXTERNAL 0x90 70 #define PLL_CTRL_6_MIPI_CLK 0x92 71 #define PLL_CTRL_6_INTERNAL 0x93 72 #define PLL_REM(n) (0x60 + ((n) & 0x3)) /* 0..2 */ 73 #define PLL_DIV(n) (0x63 + ((n) & 0x3)) /* 0..2 */ 74 #define PLL_FRAC(n) (0x66 + ((n) & 0x3)) /* 0..2 */ 75 #define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 */ 76 #define PLL_REF_DIV 0x6b 77 #define PLL_REF_DIV_P(n) ((n) & 0xf) 78 #define PLL_REF_DIV_Pe BIT(4) 79 #define PLL_REF_DIV_S(n) (((n) & 0x7) << 5) 80 #define PLL_SSC_P(n) (0x6c + ((n) & 0x3)) /* 0..2 */ 81 #define PLL_SSC_STEP(n) (0x6f + ((n) & 0x3)) /* 0..2 */ 82 #define PLL_SSC_OFFSET(n) (0x72 + ((n) & 0x3)) /* 0..3 */ 83 #define GPIO_OEN 0x79 84 #define MIPI_CFG_PW 0x7a 85 #define MIPI_CFG_PW_CONFIG_DSI 0xc1 86 #define MIPI_CFG_PW_CONFIG_I2C 0x3e 87 #define GPIO_SEL(n) (0x7b + ((n) & 0x1)) /* 0..1 */ 88 #define IRQ_SEL 0x7d 89 #define DBG_SEL 0x7e 90 #define DBG_SIGNAL 0x7f 91 #define MIPI_ERR_VECTOR_L 0x80 92 #define MIPI_ERR_VECTOR_H 0x81 93 #define MIPI_ERR_VECTOR_EN_L 0x82 94 #define MIPI_ERR_VECTOR_EN_H 0x83 95 #define MIPI_MAX_SIZE_L 0x84 96 #define MIPI_MAX_SIZE_H 0x85 97 #define DSI_CTRL 0x86 98 #define DSI_CTRL_UNKNOWN 0x28 99 #define DSI_CTRL_DSI_LANES(n) ((n) & 0x3) 100 #define MIPI_PN_SWAP 0x87 101 #define MIPI_PN_SWAP_CLK BIT(4) 102 #define MIPI_PN_SWAP_D(n) BIT((n) & 0x3) 103 #define MIPI_SOT_SYNC_BIT(n) (0x88 + ((n) & 0x1)) /* 0..1 */ 104 #define MIPI_ULPS_CTRL 0x8a 105 #define MIPI_CLK_CHK_VAR 0x8e 106 #define MIPI_CLK_CHK_INI 0x8f 107 #define MIPI_T_TERM_EN 0x90 108 #define MIPI_T_HS_SETTLE 0x91 109 #define MIPI_T_TA_SURE_PRE 0x92 110 #define MIPI_T_LPX_SET 0x94 111 #define MIPI_T_CLK_MISS 0x95 112 #define MIPI_INIT_TIME_L 0x96 113 #define MIPI_INIT_TIME_H 0x97 114 #define MIPI_T_CLK_TERM_EN 0x99 115 #define MIPI_T_CLK_SETTLE 0x9a 116 #define MIPI_TO_HS_RX_L 0x9e 117 #define MIPI_TO_HS_RX_H 0x9f 118 #define MIPI_PHY(n) (0xa0 + ((n) & 0x7)) /* 0..5 */ 119 #define MIPI_PD_RX 0xb0 120 #define MIPI_PD_TERM 0xb1 121 #define MIPI_PD_HSRX 0xb2 122 #define MIPI_PD_LPTX 0xb3 123 #define MIPI_PD_LPRX 0xb4 124 #define MIPI_PD_CK_LANE 0xb5 125 #define MIPI_FORCE_0 0xb6 126 #define MIPI_RST_CTRL 0xb7 127 #define MIPI_RST_NUM 0xb8 128 #define MIPI_DBG_SET(n) (0xc0 + ((n) & 0xf)) /* 0..9 */ 129 #define MIPI_DBG_SEL 0xe0 130 #define MIPI_DBG_DATA 0xe1 131 #define MIPI_ATE_TEST_SEL 0xe2 132 #define MIPI_ATE_STATUS(n) (0xe3 + ((n) & 0x1)) /* 0..1 */ 133 134 struct chipone { 135 struct device *dev; 136 struct regmap *regmap; 137 struct i2c_client *client; 138 struct drm_bridge bridge; 139 struct drm_display_mode mode; 140 struct drm_bridge *panel_bridge; 141 struct mipi_dsi_device *dsi; 142 struct gpio_desc *enable_gpio; 143 struct regulator *vdd1; 144 struct regulator *vdd2; 145 struct regulator *vdd3; 146 bool interface_i2c; 147 }; 148 149 static const struct regmap_range chipone_dsi_readable_ranges[] = { 150 regmap_reg_range(VENDOR_ID, VERSION_ID), 151 regmap_reg_range(FIRMWARE_VERSION, PLL_SSC_OFFSET(3)), 152 regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL), 153 regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE), 154 regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H), 155 regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE), 156 regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)), 157 regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM), 158 regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)), 159 regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)), 160 }; 161 162 static const struct regmap_access_table chipone_dsi_readable_table = { 163 .yes_ranges = chipone_dsi_readable_ranges, 164 .n_yes_ranges = ARRAY_SIZE(chipone_dsi_readable_ranges), 165 }; 166 167 static const struct regmap_range chipone_dsi_writeable_ranges[] = { 168 regmap_reg_range(CONFIG_FINISH, PLL_SSC_OFFSET(3)), 169 regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL), 170 regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE), 171 regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H), 172 regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE), 173 regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)), 174 regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM), 175 regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)), 176 regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)), 177 }; 178 179 static const struct regmap_access_table chipone_dsi_writeable_table = { 180 .yes_ranges = chipone_dsi_writeable_ranges, 181 .n_yes_ranges = ARRAY_SIZE(chipone_dsi_writeable_ranges), 182 }; 183 184 static const struct regmap_config chipone_regmap_config = { 185 .reg_bits = 8, 186 .val_bits = 8, 187 .rd_table = &chipone_dsi_readable_table, 188 .wr_table = &chipone_dsi_writeable_table, 189 .cache_type = REGCACHE_RBTREE, 190 .max_register = MIPI_ATE_STATUS(1), 191 }; 192 193 static int chipone_dsi_read(void *context, 194 const void *reg, size_t reg_size, 195 void *val, size_t val_size) 196 { 197 struct mipi_dsi_device *dsi = context; 198 const u16 reg16 = (val_size << 8) | *(u8 *)reg; 199 int ret; 200 201 ret = mipi_dsi_generic_read(dsi, ®16, 2, val, val_size); 202 203 return ret == val_size ? 0 : -EINVAL; 204 } 205 206 static int chipone_dsi_write(void *context, const void *data, size_t count) 207 { 208 struct mipi_dsi_device *dsi = context; 209 210 return mipi_dsi_generic_write(dsi, data, 2); 211 } 212 213 static const struct regmap_bus chipone_dsi_regmap_bus = { 214 .read = chipone_dsi_read, 215 .write = chipone_dsi_write, 216 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, 217 .val_format_endian_default = REGMAP_ENDIAN_NATIVE, 218 }; 219 220 static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge) 221 { 222 return container_of(bridge, struct chipone, bridge); 223 } 224 225 static void chipone_readb(struct chipone *icn, u8 reg, u8 *val) 226 { 227 int ret, pval; 228 229 ret = regmap_read(icn->regmap, reg, &pval); 230 231 *val = ret ? 0 : pval & 0xff; 232 } 233 234 static int chipone_writeb(struct chipone *icn, u8 reg, u8 val) 235 { 236 return regmap_write(icn->regmap, reg, val); 237 } 238 239 static void chipone_configure_pll(struct chipone *icn, 240 const struct drm_display_mode *mode) 241 { 242 unsigned int best_p = 0, best_m = 0, best_s = 0; 243 unsigned int mode_clock = mode->clock * 1000; 244 unsigned int delta, min_delta = 0xffffffff; 245 unsigned int freq_p, freq_s, freq_out; 246 unsigned int p_min, p_max; 247 unsigned int p, m, s; 248 unsigned int fin; 249 bool best_p_pot; 250 u8 ref_div; 251 252 /* 253 * DSI byte clock frequency (input into PLL) is calculated as: 254 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 8 255 * 256 * DPI pixel clock frequency (output from PLL) is mode clock. 257 * 258 * The chip contains fractional PLL which works as follows: 259 * DPI_CLK = ((DSI_CLK / P) * M) / S 260 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider 261 * register PLL_REF_DIV[4] is extra 1:2 divider 262 * M is integer multiplier, register PLL_INT(0) is multiplier 263 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider 264 * 265 * It seems the PLL input clock after applying P pre-divider have 266 * to be lower than 20 MHz. 267 */ 268 fin = mode_clock * mipi_dsi_pixel_format_to_bpp(icn->dsi->format) / 269 icn->dsi->lanes / 8; /* in Hz */ 270 271 /* Minimum value of P predivider for PLL input in 5..20 MHz */ 272 p_min = clamp(DIV_ROUND_UP(fin, 20000000), 1U, 31U); 273 p_max = clamp(fin / 5000000, 1U, 31U); 274 275 for (p = p_min; p < p_max; p++) { /* PLL_REF_DIV[4,3:0] */ 276 if (p > 16 && p & 1) /* P > 16 uses extra /2 */ 277 continue; 278 freq_p = fin / p; 279 if (freq_p == 0) /* Divider too high */ 280 break; 281 282 for (s = 0; s < 0x7; s++) { /* PLL_REF_DIV[7:5] */ 283 freq_s = freq_p / BIT(s + 1); 284 if (freq_s == 0) /* Divider too high */ 285 break; 286 287 m = mode_clock / freq_s; 288 289 /* Multiplier is 8 bit */ 290 if (m > 0xff) 291 continue; 292 293 /* Limit PLL VCO frequency to 1 GHz */ 294 freq_out = (fin * m) / p; 295 if (freq_out > 1000000000) 296 continue; 297 298 /* Apply post-divider */ 299 freq_out /= BIT(s + 1); 300 301 delta = abs(mode_clock - freq_out); 302 if (delta < min_delta) { 303 best_p = p; 304 best_m = m; 305 best_s = s; 306 min_delta = delta; 307 } 308 } 309 } 310 311 best_p_pot = !(best_p & 1); 312 313 dev_dbg(icn->dev, 314 "PLL: P[3:0]=%d P[4]=2*%d M=%d S[7:5]=2^%d delta=%d => DSI f_in=%d Hz ; DPI f_out=%d Hz\n", 315 best_p >> best_p_pot, best_p_pot, best_m, best_s + 1, 316 min_delta, fin, (fin * best_m) / (best_p << (best_s + 1))); 317 318 ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s); 319 if (best_p_pot) /* Prefer /2 pre-divider */ 320 ref_div |= PLL_REF_DIV_Pe; 321 322 /* Clock source selection fixed to MIPI DSI clock lane */ 323 chipone_writeb(icn, PLL_CTRL(6), PLL_CTRL_6_MIPI_CLK); 324 chipone_writeb(icn, PLL_REF_DIV, ref_div); 325 chipone_writeb(icn, PLL_INT(0), best_m); 326 } 327 328 static void chipone_atomic_enable(struct drm_bridge *bridge, 329 struct drm_bridge_state *old_bridge_state) 330 { 331 struct chipone *icn = bridge_to_chipone(bridge); 332 struct drm_atomic_state *state = old_bridge_state->base.state; 333 struct drm_display_mode *mode = &icn->mode; 334 const struct drm_bridge_state *bridge_state; 335 u16 hfp, hbp, hsync; 336 u32 bus_flags; 337 u8 pol, id[4]; 338 339 chipone_readb(icn, VENDOR_ID, id); 340 chipone_readb(icn, DEVICE_ID_H, id + 1); 341 chipone_readb(icn, DEVICE_ID_L, id + 2); 342 chipone_readb(icn, VERSION_ID, id + 3); 343 344 dev_dbg(icn->dev, 345 "Chip IDs: Vendor=0x%02x Device=0x%02x:0x%02x Version=0x%02x\n", 346 id[0], id[1], id[2], id[3]); 347 348 if (id[0] != 0xc1 || id[1] != 0x62 || id[2] != 0x11) { 349 dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n"); 350 return; 351 } 352 353 /* Get the DPI flags from the bridge state. */ 354 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 355 bus_flags = bridge_state->output_bus_cfg.flags; 356 357 if (icn->interface_i2c) 358 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C); 359 else 360 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI); 361 362 chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff); 363 364 chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff); 365 366 /* 367 * lsb nibble: 2nd nibble of hdisplay 368 * msb nibble: 2nd nibble of vdisplay 369 */ 370 chipone_writeb(icn, VACTIVE_HACTIVE_HI, 371 ((mode->hdisplay >> 8) & 0xf) | 372 (((mode->vdisplay >> 8) & 0xf) << 4)); 373 374 hfp = mode->hsync_start - mode->hdisplay; 375 hsync = mode->hsync_end - mode->hsync_start; 376 hbp = mode->htotal - mode->hsync_end; 377 378 chipone_writeb(icn, HFP_LI, hfp & 0xff); 379 chipone_writeb(icn, HSYNC_LI, hsync & 0xff); 380 chipone_writeb(icn, HBP_LI, hbp & 0xff); 381 /* Top two bits of Horizontal Front porch/Sync/Back porch */ 382 chipone_writeb(icn, HFP_HSW_HBP_HI, 383 HFP_HSW_HBP_HI_HFP(hfp) | 384 HFP_HSW_HBP_HI_HS(hsync) | 385 HFP_HSW_HBP_HI_HBP(hbp)); 386 387 chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay); 388 389 chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start); 390 391 chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end); 392 393 /* dsi specific sequence */ 394 chipone_writeb(icn, SYNC_EVENT_DLY, 0x80); 395 chipone_writeb(icn, HFP_MIN, hfp & 0xff); 396 397 /* DSI data lane count */ 398 chipone_writeb(icn, DSI_CTRL, 399 DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1)); 400 401 chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0); 402 chipone_writeb(icn, PLL_CTRL(12), 0xff); 403 chipone_writeb(icn, MIPI_PN_SWAP, 0x00); 404 405 /* DPI HS/VS/DE polarity */ 406 pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) | 407 ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) | 408 ((bus_flags & DRM_BUS_FLAG_DE_HIGH) ? BIST_POL_DE_POL : 0); 409 chipone_writeb(icn, BIST_POL, pol); 410 411 /* Configure PLL settings */ 412 chipone_configure_pll(icn, mode); 413 414 chipone_writeb(icn, SYS_CTRL(0), 0x40); 415 chipone_writeb(icn, SYS_CTRL(1), 0x88); 416 417 /* icn6211 specific sequence */ 418 chipone_writeb(icn, MIPI_FORCE_0, 0x20); 419 chipone_writeb(icn, PLL_CTRL(1), 0x20); 420 chipone_writeb(icn, CONFIG_FINISH, 0x10); 421 422 usleep_range(10000, 11000); 423 } 424 425 static void chipone_atomic_pre_enable(struct drm_bridge *bridge, 426 struct drm_bridge_state *old_bridge_state) 427 { 428 struct chipone *icn = bridge_to_chipone(bridge); 429 int ret; 430 431 if (icn->vdd1) { 432 ret = regulator_enable(icn->vdd1); 433 if (ret) 434 DRM_DEV_ERROR(icn->dev, 435 "failed to enable VDD1 regulator: %d\n", ret); 436 } 437 438 if (icn->vdd2) { 439 ret = regulator_enable(icn->vdd2); 440 if (ret) 441 DRM_DEV_ERROR(icn->dev, 442 "failed to enable VDD2 regulator: %d\n", ret); 443 } 444 445 if (icn->vdd3) { 446 ret = regulator_enable(icn->vdd3); 447 if (ret) 448 DRM_DEV_ERROR(icn->dev, 449 "failed to enable VDD3 regulator: %d\n", ret); 450 } 451 452 gpiod_set_value(icn->enable_gpio, 1); 453 454 usleep_range(10000, 11000); 455 } 456 457 static void chipone_atomic_post_disable(struct drm_bridge *bridge, 458 struct drm_bridge_state *old_bridge_state) 459 { 460 struct chipone *icn = bridge_to_chipone(bridge); 461 462 if (icn->vdd1) 463 regulator_disable(icn->vdd1); 464 465 if (icn->vdd2) 466 regulator_disable(icn->vdd2); 467 468 if (icn->vdd3) 469 regulator_disable(icn->vdd3); 470 471 gpiod_set_value(icn->enable_gpio, 0); 472 } 473 474 static void chipone_mode_set(struct drm_bridge *bridge, 475 const struct drm_display_mode *mode, 476 const struct drm_display_mode *adjusted_mode) 477 { 478 struct chipone *icn = bridge_to_chipone(bridge); 479 480 drm_mode_copy(&icn->mode, adjusted_mode); 481 }; 482 483 static int chipone_dsi_attach(struct chipone *icn) 484 { 485 struct mipi_dsi_device *dsi = icn->dsi; 486 struct device *dev = icn->dev; 487 struct device_node *endpoint; 488 int dsi_lanes, ret; 489 490 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 491 dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 492 of_node_put(endpoint); 493 494 /* 495 * If the 'data-lanes' property does not exist in DT or is invalid, 496 * default to previously hard-coded behavior, which was 4 data lanes. 497 */ 498 if (dsi_lanes >= 1 && dsi_lanes <= 4) 499 icn->dsi->lanes = dsi_lanes; 500 else 501 icn->dsi->lanes = 4; 502 503 dsi->format = MIPI_DSI_FMT_RGB888; 504 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 505 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET; 506 507 ret = mipi_dsi_attach(dsi); 508 if (ret < 0) 509 dev_err(icn->dev, "failed to attach dsi\n"); 510 511 return ret; 512 } 513 514 static int chipone_dsi_host_attach(struct chipone *icn) 515 { 516 struct device *dev = icn->dev; 517 struct device_node *host_node; 518 struct device_node *endpoint; 519 struct mipi_dsi_device *dsi; 520 struct mipi_dsi_host *host; 521 int ret = 0; 522 523 const struct mipi_dsi_device_info info = { 524 .type = "chipone", 525 .channel = 0, 526 .node = NULL, 527 }; 528 529 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 530 host_node = of_graph_get_remote_port_parent(endpoint); 531 of_node_put(endpoint); 532 533 if (!host_node) 534 return -EINVAL; 535 536 host = of_find_mipi_dsi_host_by_node(host_node); 537 of_node_put(host_node); 538 if (!host) { 539 dev_err(dev, "failed to find dsi host\n"); 540 return -EPROBE_DEFER; 541 } 542 543 dsi = mipi_dsi_device_register_full(host, &info); 544 if (IS_ERR(dsi)) { 545 return dev_err_probe(dev, PTR_ERR(dsi), 546 "failed to create dsi device\n"); 547 } 548 549 icn->dsi = dsi; 550 551 ret = chipone_dsi_attach(icn); 552 if (ret < 0) 553 mipi_dsi_device_unregister(dsi); 554 555 return ret; 556 } 557 558 static int chipone_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) 559 { 560 struct chipone *icn = bridge_to_chipone(bridge); 561 562 return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags); 563 } 564 565 #define MAX_INPUT_SEL_FORMATS 1 566 567 static u32 * 568 chipone_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 569 struct drm_bridge_state *bridge_state, 570 struct drm_crtc_state *crtc_state, 571 struct drm_connector_state *conn_state, 572 u32 output_fmt, 573 unsigned int *num_input_fmts) 574 { 575 u32 *input_fmts; 576 577 *num_input_fmts = 0; 578 579 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 580 GFP_KERNEL); 581 if (!input_fmts) 582 return NULL; 583 584 /* This is the DSI-end bus format */ 585 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 586 *num_input_fmts = 1; 587 588 return input_fmts; 589 } 590 591 static const struct drm_bridge_funcs chipone_bridge_funcs = { 592 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 593 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 594 .atomic_reset = drm_atomic_helper_bridge_reset, 595 .atomic_pre_enable = chipone_atomic_pre_enable, 596 .atomic_enable = chipone_atomic_enable, 597 .atomic_post_disable = chipone_atomic_post_disable, 598 .mode_set = chipone_mode_set, 599 .attach = chipone_attach, 600 .atomic_get_input_bus_fmts = chipone_atomic_get_input_bus_fmts, 601 }; 602 603 static int chipone_parse_dt(struct chipone *icn) 604 { 605 struct device *dev = icn->dev; 606 int ret; 607 608 icn->vdd1 = devm_regulator_get_optional(dev, "vdd1"); 609 if (IS_ERR(icn->vdd1)) { 610 ret = PTR_ERR(icn->vdd1); 611 if (ret == -EPROBE_DEFER) 612 return -EPROBE_DEFER; 613 icn->vdd1 = NULL; 614 DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret); 615 } 616 617 icn->vdd2 = devm_regulator_get_optional(dev, "vdd2"); 618 if (IS_ERR(icn->vdd2)) { 619 ret = PTR_ERR(icn->vdd2); 620 if (ret == -EPROBE_DEFER) 621 return -EPROBE_DEFER; 622 icn->vdd2 = NULL; 623 DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret); 624 } 625 626 icn->vdd3 = devm_regulator_get_optional(dev, "vdd3"); 627 if (IS_ERR(icn->vdd3)) { 628 ret = PTR_ERR(icn->vdd3); 629 if (ret == -EPROBE_DEFER) 630 return -EPROBE_DEFER; 631 icn->vdd3 = NULL; 632 DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret); 633 } 634 635 icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); 636 if (IS_ERR(icn->enable_gpio)) { 637 DRM_DEV_ERROR(dev, "failed to get enable GPIO\n"); 638 return PTR_ERR(icn->enable_gpio); 639 } 640 641 icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); 642 if (IS_ERR(icn->panel_bridge)) 643 return PTR_ERR(icn->panel_bridge); 644 645 return 0; 646 } 647 648 static int chipone_common_probe(struct device *dev, struct chipone **icnr) 649 { 650 struct chipone *icn; 651 int ret; 652 653 icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL); 654 if (!icn) 655 return -ENOMEM; 656 657 icn->dev = dev; 658 659 ret = chipone_parse_dt(icn); 660 if (ret) 661 return ret; 662 663 icn->bridge.funcs = &chipone_bridge_funcs; 664 icn->bridge.type = DRM_MODE_CONNECTOR_DPI; 665 icn->bridge.of_node = dev->of_node; 666 667 *icnr = icn; 668 669 return ret; 670 } 671 672 static int chipone_dsi_probe(struct mipi_dsi_device *dsi) 673 { 674 struct device *dev = &dsi->dev; 675 struct chipone *icn; 676 int ret; 677 678 ret = chipone_common_probe(dev, &icn); 679 if (ret) 680 return ret; 681 682 icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus, 683 dsi, &chipone_regmap_config); 684 if (IS_ERR(icn->regmap)) 685 return PTR_ERR(icn->regmap); 686 687 icn->interface_i2c = false; 688 icn->dsi = dsi; 689 690 mipi_dsi_set_drvdata(dsi, icn); 691 692 drm_bridge_add(&icn->bridge); 693 694 ret = chipone_dsi_attach(icn); 695 if (ret) 696 drm_bridge_remove(&icn->bridge); 697 698 return ret; 699 } 700 701 static int chipone_i2c_probe(struct i2c_client *client, 702 const struct i2c_device_id *id) 703 { 704 struct device *dev = &client->dev; 705 struct chipone *icn; 706 int ret; 707 708 ret = chipone_common_probe(dev, &icn); 709 if (ret) 710 return ret; 711 712 icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config); 713 if (IS_ERR(icn->regmap)) 714 return PTR_ERR(icn->regmap); 715 716 icn->interface_i2c = true; 717 icn->client = client; 718 dev_set_drvdata(dev, icn); 719 i2c_set_clientdata(client, icn); 720 721 drm_bridge_add(&icn->bridge); 722 723 return chipone_dsi_host_attach(icn); 724 } 725 726 static int chipone_dsi_remove(struct mipi_dsi_device *dsi) 727 { 728 struct chipone *icn = mipi_dsi_get_drvdata(dsi); 729 730 mipi_dsi_detach(dsi); 731 drm_bridge_remove(&icn->bridge); 732 733 return 0; 734 } 735 736 static const struct of_device_id chipone_of_match[] = { 737 { .compatible = "chipone,icn6211", }, 738 { /* sentinel */ } 739 }; 740 MODULE_DEVICE_TABLE(of, chipone_of_match); 741 742 static struct mipi_dsi_driver chipone_dsi_driver = { 743 .probe = chipone_dsi_probe, 744 .remove = chipone_dsi_remove, 745 .driver = { 746 .name = "chipone-icn6211", 747 .owner = THIS_MODULE, 748 .of_match_table = chipone_of_match, 749 }, 750 }; 751 752 static struct i2c_device_id chipone_i2c_id[] = { 753 { "chipone,icn6211" }, 754 {}, 755 }; 756 MODULE_DEVICE_TABLE(i2c, chipone_i2c_id); 757 758 static struct i2c_driver chipone_i2c_driver = { 759 .probe = chipone_i2c_probe, 760 .id_table = chipone_i2c_id, 761 .driver = { 762 .name = "chipone-icn6211-i2c", 763 .of_match_table = chipone_of_match, 764 }, 765 }; 766 767 static int __init chipone_init(void) 768 { 769 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 770 mipi_dsi_driver_register(&chipone_dsi_driver); 771 772 return i2c_add_driver(&chipone_i2c_driver); 773 } 774 module_init(chipone_init); 775 776 static void __exit chipone_exit(void) 777 { 778 i2c_del_driver(&chipone_i2c_driver); 779 780 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 781 mipi_dsi_driver_unregister(&chipone_dsi_driver); 782 } 783 module_exit(chipone_exit); 784 785 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 786 MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge"); 787 MODULE_LICENSE("GPL"); 788