1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright(c) 2020, Analogix Semiconductor. All rights reserved.
4  *
5  */
6 
7 #ifndef __ANX7625_H__
8 #define __ANX7625_H__
9 
10 #define ANX7625_DRV_VERSION "0.1.04"
11 
12 /* Loading OCM re-trying times */
13 #define OCM_LOADING_TIME 10
14 
15 /*********  ANX7625 Register  **********/
16 #define TX_P0_ADDR				0x70
17 #define TX_P1_ADDR				0x7A
18 #define TX_P2_ADDR				0x72
19 
20 #define RX_P0_ADDR				0x7e
21 #define RX_P1_ADDR				0x84
22 #define RX_P2_ADDR				0x54
23 
24 #define RSVD_00_ADDR				0x00
25 #define RSVD_D1_ADDR				0xD1
26 #define RSVD_60_ADDR				0x60
27 #define RSVD_39_ADDR				0x39
28 #define RSVD_7F_ADDR				0x7F
29 
30 #define TCPC_INTERFACE_ADDR			0x58
31 
32 /* Clock frequency in Hz */
33 #define XTAL_FRQ        (27 * 1000000)
34 
35 #define  POST_DIVIDER_MIN	1
36 #define  POST_DIVIDER_MAX	16
37 #define  PLL_OUT_FREQ_MIN	520000000UL
38 #define  PLL_OUT_FREQ_MAX	730000000UL
39 #define  PLL_OUT_FREQ_ABS_MIN	300000000UL
40 #define  PLL_OUT_FREQ_ABS_MAX	800000000UL
41 #define  MAX_UNSIGNED_24BIT	16777215UL
42 
43 /***************************************************************/
44 /* Register definition of device address 0x58 */
45 
46 #define PRODUCT_ID_L 0x02
47 #define PRODUCT_ID_H 0x03
48 
49 #define INTR_ALERT_1  0xCC
50 #define INTR_SOFTWARE_INT BIT(3)
51 #define INTR_RECEIVED_MSG BIT(5)
52 
53 #define SYSTEM_STSTUS 0x45
54 #define INTERFACE_CHANGE_INT 0x44
55 #define HPD_STATUS_CHANGE 0x80
56 #define HPD_STATUS 0x80
57 
58 /******** END of I2C Address 0x58 ********/
59 
60 /***************************************************************/
61 /* Register definition of device address 0x70 */
62 #define TX_HDCP_CTRL0			0x01
63 #define STORE_AN			BIT(7)
64 #define RX_REPEATER			BIT(6)
65 #define RE_AUTHEN			BIT(5)
66 #define SW_AUTH_OK			BIT(4)
67 #define HARD_AUTH_EN			BIT(3)
68 #define ENC_EN				BIT(2)
69 #define BKSV_SRM_PASS			BIT(1)
70 #define KSVLIST_VLD			BIT(0)
71 
72 #define SP_TX_WAIT_R0_TIME		0x40
73 #define SP_TX_WAIT_KSVR_TIME		0x42
74 #define SP_TX_SYS_CTRL1_REG		0x80
75 #define HDCP2TX_FW_EN			BIT(4)
76 
77 #define SP_TX_LINK_BW_SET_REG		0xA0
78 #define SP_TX_LANE_COUNT_SET_REG	0xA1
79 
80 #define M_VID_0 0xC0
81 #define M_VID_1 0xC1
82 #define M_VID_2 0xC2
83 #define N_VID_0 0xC3
84 #define N_VID_1 0xC4
85 #define N_VID_2 0xC5
86 
87 #define KEY_START_ADDR			0x9000
88 #define KEY_RESERVED			416
89 
90 #define HDCP14KEY_START_ADDR		(KEY_START_ADDR + KEY_RESERVED)
91 #define HDCP14KEY_SIZE			624
92 
93 /***************************************************************/
94 /* Register definition of device address 0x72 */
95 #define AUX_RST	0x04
96 #define RST_CTRL2 0x07
97 
98 #define SP_TX_TOTAL_LINE_STA_L 0x24
99 #define SP_TX_TOTAL_LINE_STA_H 0x25
100 #define SP_TX_ACT_LINE_STA_L 0x26
101 #define SP_TX_ACT_LINE_STA_H 0x27
102 #define SP_TX_V_F_PORCH_STA 0x28
103 #define SP_TX_V_SYNC_STA 0x29
104 #define SP_TX_V_B_PORCH_STA 0x2A
105 #define SP_TX_TOTAL_PIXEL_STA_L 0x2B
106 #define SP_TX_TOTAL_PIXEL_STA_H 0x2C
107 #define SP_TX_ACT_PIXEL_STA_L 0x2D
108 #define SP_TX_ACT_PIXEL_STA_H 0x2E
109 #define SP_TX_H_F_PORCH_STA_L 0x2F
110 #define SP_TX_H_F_PORCH_STA_H 0x30
111 #define SP_TX_H_SYNC_STA_L 0x31
112 #define SP_TX_H_SYNC_STA_H 0x32
113 #define SP_TX_H_B_PORCH_STA_L 0x33
114 #define SP_TX_H_B_PORCH_STA_H 0x34
115 
116 #define SP_TX_VID_CTRL 0x84
117 #define SP_TX_BPC_MASK 0xE0
118 #define SP_TX_BPC_6    0x00
119 #define SP_TX_BPC_8    0x20
120 #define SP_TX_BPC_10   0x40
121 #define SP_TX_BPC_12   0x60
122 
123 #define VIDEO_BIT_MATRIX_12 0x4c
124 
125 #define AUDIO_CHANNEL_STATUS_1 0xd0
126 #define AUDIO_CHANNEL_STATUS_2 0xd1
127 #define AUDIO_CHANNEL_STATUS_3 0xd2
128 #define AUDIO_CHANNEL_STATUS_4 0xd3
129 #define AUDIO_CHANNEL_STATUS_5 0xd4
130 #define AUDIO_CHANNEL_STATUS_6 0xd5
131 #define TDM_SLAVE_MODE 0x10
132 #define I2S_SLAVE_MODE 0x08
133 #define AUDIO_LAYOUT   0x01
134 
135 #define HPD_DET_TIMER_BIT0_7   0xea
136 #define HPD_DET_TIMER_BIT8_15  0xeb
137 #define HPD_DET_TIMER_BIT16_23 0xec
138 /* HPD debounce time 2ms for 27M clock */
139 #define HPD_TIME               54000
140 
141 #define AUDIO_CONTROL_REGISTER 0xe6
142 #define TDM_TIMING_MODE 0x08
143 
144 #define I2C_ADDR_72_DPTX              0x72
145 
146 #define HP_MIN			8
147 #define HBLANKING_MIN		80
148 #define SYNC_LEN_DEF		32
149 #define HFP_HBP_DEF		((HBLANKING_MIN - SYNC_LEN_DEF) / 2)
150 #define VIDEO_CONTROL_0	0x08
151 
152 #define  ACTIVE_LINES_L         0x14
153 #define  ACTIVE_LINES_H         0x15  /* Bit[7:6] are reserved */
154 #define  VERTICAL_FRONT_PORCH   0x16
155 #define  VERTICAL_SYNC_WIDTH    0x17
156 #define  VERTICAL_BACK_PORCH    0x18
157 
158 #define  HORIZONTAL_TOTAL_PIXELS_L    0x19
159 #define  HORIZONTAL_TOTAL_PIXELS_H    0x1A  /* Bit[7:6] are reserved */
160 #define  HORIZONTAL_ACTIVE_PIXELS_L   0x1B
161 #define  HORIZONTAL_ACTIVE_PIXELS_H   0x1C  /* Bit[7:6] are reserved */
162 #define  HORIZONTAL_FRONT_PORCH_L     0x1D
163 #define  HORIZONTAL_FRONT_PORCH_H     0x1E  /* Bit[7:4] are reserved */
164 #define  HORIZONTAL_SYNC_WIDTH_L      0x1F
165 #define  HORIZONTAL_SYNC_WIDTH_H      0x20  /* Bit[7:4] are reserved */
166 #define  HORIZONTAL_BACK_PORCH_L      0x21
167 #define  HORIZONTAL_BACK_PORCH_H      0x22  /* Bit[7:4] are reserved */
168 
169 /******** END of I2C Address 0x72 *********/
170 
171 /***************************************************************/
172 /* Register definition of device address 0x7a */
173 #define DP_TX_SWING_REG_CNT		0x14
174 #define DP_TX_LANE0_SWING_REG0		0x00
175 #define DP_TX_LANE1_SWING_REG0		0x14
176 /******** END of I2C Address 0x7a *********/
177 
178 /***************************************************************/
179 /* Register definition of device address 0x7e */
180 
181 #define  I2C_ADDR_7E_FLASH_CONTROLLER  0x7E
182 
183 #define R_BOOT_RETRY		0x00
184 #define R_RAM_ADDR_H		0x01
185 #define R_RAM_ADDR_L		0x02
186 #define R_RAM_LEN_H		0x03
187 #define R_RAM_LEN_L		0x04
188 #define FLASH_LOAD_STA          0x05
189 #define FLASH_LOAD_STA_CHK	BIT(7)
190 
191 #define R_RAM_CTRL              0x05
192 /* bit positions */
193 #define FLASH_DONE              BIT(7)
194 #define BOOT_LOAD_DONE          BIT(6)
195 #define CRC_OK                  BIT(5)
196 #define LOAD_DONE               BIT(4)
197 #define O_RW_DONE               BIT(3)
198 #define FUSE_BUSY               BIT(2)
199 #define DECRYPT_EN              BIT(1)
200 #define LOAD_START              BIT(0)
201 
202 #define FLASH_ADDR_HIGH         0x0F
203 #define FLASH_ADDR_LOW          0x10
204 #define FLASH_LEN_HIGH          0x31
205 #define FLASH_LEN_LOW           0x32
206 #define R_FLASH_RW_CTRL         0x33
207 /* bit positions */
208 #define READ_DELAY_SELECT       BIT(7)
209 #define GENERAL_INSTRUCTION_EN  BIT(6)
210 #define FLASH_ERASE_EN          BIT(5)
211 #define RDID_READ_EN            BIT(4)
212 #define REMS_READ_EN            BIT(3)
213 #define WRITE_STATUS_EN         BIT(2)
214 #define FLASH_READ              BIT(1)
215 #define FLASH_WRITE             BIT(0)
216 
217 #define FLASH_BUF_BASE_ADDR     0x60
218 #define FLASH_BUF_LEN           0x20
219 
220 #define  XTAL_FRQ_SEL    0x3F
221 /* bit field positions */
222 #define  XTAL_FRQ_SEL_POS    5
223 /* bit field values */
224 #define  XTAL_FRQ_19M2   (0 << XTAL_FRQ_SEL_POS)
225 #define  XTAL_FRQ_27M    (4 << XTAL_FRQ_SEL_POS)
226 
227 #define  R_DSC_CTRL_0    0x40
228 #define  READ_STATUS_EN  7
229 #define  CLK_1MEG_RB     6  /* 1MHz clock reset; 0=reset, 0=reset release */
230 #define  DSC_BIST_DONE   1  /* Bit[5:1]: 1=DSC MBIST pass */
231 #define  DSC_EN          0x01  /* 1=DSC enabled, 0=DSC disabled */
232 
233 #define OCM_FW_VERSION   0x31
234 #define OCM_FW_REVERSION 0x32
235 
236 #define AP_AUX_ADDR_7_0   0x11
237 #define AP_AUX_ADDR_15_8  0x12
238 #define AP_AUX_ADDR_19_16 0x13
239 
240 /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */
241 #define AP_AUX_CTRL_STATUS 0x14
242 #define AP_AUX_CTRL_OP_EN 0x10
243 #define AP_AUX_CTRL_ADDRONLY 0x20
244 
245 #define AP_AUX_BUFF_START 0x15
246 #define PIXEL_CLOCK_L	0x25
247 #define PIXEL_CLOCK_H	0x26
248 
249 #define AP_AUX_COMMAND	0x27  /* com+len */
250 #define LENGTH_SHIFT	4
251 #define DPCD_CMD(len, cmd)	((((len) - 1) << LENGTH_SHIFT) | (cmd))
252 
253 /* Bit 0&1: 3D video structure */
254 /* 0x01: frame packing,  0x02:Line alternative, 0x03:Side-by-side(full) */
255 #define AP_AV_STATUS 0x28
256 #define AP_VIDEO_CHG  BIT(2)
257 #define AP_AUDIO_CHG  BIT(3)
258 #define AP_MIPI_MUTE  BIT(4) /* 1:MIPI input mute, 0: ummute */
259 #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in  0: no RX in */
260 #define AP_DISABLE_PD BIT(6)
261 #define AP_DISABLE_DISPLAY BIT(7)
262 /***************************************************************/
263 /* Register definition of device address 0x84 */
264 #define  MIPI_PHY_CONTROL_3            0x03
265 #define  MIPI_HS_PWD_CLK               7
266 #define  MIPI_HS_RT_CLK                6
267 #define  MIPI_PD_CLK                   5
268 #define  MIPI_CLK_RT_MANUAL_PD_EN      4
269 #define  MIPI_CLK_HS_MANUAL_PD_EN      3
270 #define  MIPI_CLK_DET_DET_BYPASS       2
271 #define  MIPI_CLK_MISS_CTRL            1
272 #define  MIPI_PD_LPTX_CH_MANUAL_PD_EN  0
273 
274 #define  MIPI_LANE_CTRL_0		0x05
275 #define  MIPI_TIME_HS_PRPR		0x08
276 
277 /*
278  * After MIPI RX protocol layer received video frames,
279  * Protocol layer starts to reconstruct video stream from PHY
280  */
281 #define  MIPI_VIDEO_STABLE_CNT           0x0A
282 
283 #define  MIPI_LANE_CTRL_10               0x0F
284 #define  MIPI_DIGITAL_ADJ_1     0x1B
285 #define  IVO_MID0               0x26
286 #define  IVO_MID1               0xCF
287 
288 #define  MIPI_PLL_M_NUM_23_16   0x1E
289 #define  MIPI_PLL_M_NUM_15_8    0x1F
290 #define  MIPI_PLL_M_NUM_7_0     0x20
291 #define  MIPI_PLL_N_NUM_23_16   0x21
292 #define  MIPI_PLL_N_NUM_15_8    0x22
293 #define  MIPI_PLL_N_NUM_7_0     0x23
294 
295 #define  MIPI_DIGITAL_PLL_6     0x2A
296 /* Bit[7:6]: VCO band control, only effective */
297 #define  MIPI_M_NUM_READY        0x10
298 #define  MIPI_N_NUM_READY        0x08
299 #define  STABLE_INTEGER_CNT_EN   0x04
300 #define  MIPI_PLL_TEST_BIT       0
301 /* Bit[1:0]: test point output select - */
302 /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */
303 
304 #define  MIPI_DIGITAL_PLL_7      0x2B
305 #define  MIPI_PLL_FORCE_N_EN     7
306 #define  MIPI_PLL_FORCE_BAND_EN  6
307 
308 #define  MIPI_PLL_VCO_TUNE_REG   4
309 /* Bit[5:4]: VCO metal capacitance - */
310 /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */
311 #define  MIPI_PLL_VCO_TUNE_REG_VAL   0x30
312 
313 #define  MIPI_PLL_PLL_LDO_BIT    2
314 /* Bit[3:2]: vco_v2i power - */
315 /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */
316 #define  MIPI_PLL_RESET_N        0x02
317 #define  MIPI_FRQ_FORCE_NDET     0
318 
319 #define  MIPI_ALERT_CLR_0        0x2D
320 #define  HS_link_error_clear     7
321 /* This bit itself is S/C, and it clears 0x84:0x31[7] */
322 
323 #define  MIPI_ALERT_OUT_0        0x31
324 #define  check_sum_err_hs_sync   7
325 /* This bit is cleared by 0x84:0x2D[7] */
326 
327 #define  MIPI_DIGITAL_PLL_8    0x33
328 #define  MIPI_POST_DIV_VAL     4
329 /* N means divided by (n+1), n = 0~15 */
330 #define  MIPI_EN_LOCK_FRZ      3
331 #define  MIPI_FRQ_COUNTER_RST  2
332 #define  MIPI_FRQ_SET_REG_8    1
333 /* Bit 0 is reserved */
334 
335 #define  MIPI_DIGITAL_PLL_9    0x34
336 
337 #define  MIPI_DIGITAL_PLL_16   0x3B
338 #define  MIPI_FRQ_FREEZE_NDET          7
339 #define  MIPI_FRQ_REG_SET_ENABLE       6
340 #define  MIPI_REG_FORCE_SEL_EN         5
341 #define  MIPI_REG_SEL_DIV_REG          4
342 #define  MIPI_REG_FORCE_PRE_DIV_EN     3
343 /* Bit 2 is reserved */
344 #define  MIPI_FREF_D_IND               1
345 #define  REF_CLK_27000KHZ    1
346 #define  REF_CLK_19200KHZ    0
347 #define  MIPI_REG_PLL_PLL_TEST_ENABLE  0
348 
349 #define  MIPI_DIGITAL_PLL_18  0x3D
350 #define  FRQ_COUNT_RB_SEL       7
351 #define  REG_FORCE_POST_DIV_EN  6
352 #define  MIPI_DPI_SELECT        5
353 #define  SELECT_DSI  1
354 #define  SELECT_DPI  0
355 #define  REG_BAUD_DIV_RATIO     0
356 
357 #define  H_BLANK_L            0x3E
358 /* For DSC only */
359 #define  H_BLANK_H            0x3F
360 /* For DSC only; note: bit[7:6] are reserved */
361 #define  MIPI_SWAP  0x4A
362 #define  MIPI_SWAP_CH0    7
363 #define  MIPI_SWAP_CH1    6
364 #define  MIPI_SWAP_CH2    5
365 #define  MIPI_SWAP_CH3    4
366 #define  MIPI_SWAP_CLK    3
367 /* Bit[2:0] are reserved */
368 
369 /******** END of I2C Address 0x84 *********/
370 
371 /* DPCD regs */
372 #define DPCD_DPCD_REV                  0x00
373 #define DPCD_MAX_LINK_RATE             0x01
374 #define DPCD_MAX_LANE_COUNT            0x02
375 
376 /*********  ANX7625 Register End  **********/
377 
378 /***************** Display *****************/
379 enum audio_fs {
380 	AUDIO_FS_441K  = 0x00,
381 	AUDIO_FS_48K   = 0x02,
382 	AUDIO_FS_32K   = 0x03,
383 	AUDIO_FS_882K  = 0x08,
384 	AUDIO_FS_96K   = 0x0a,
385 	AUDIO_FS_1764K = 0x0c,
386 	AUDIO_FS_192K  = 0x0e
387 };
388 
389 enum audio_wd_len {
390 	AUDIO_W_LEN_16_20MAX = 0x02,
391 	AUDIO_W_LEN_18_20MAX = 0x04,
392 	AUDIO_W_LEN_17_20MAX = 0x0c,
393 	AUDIO_W_LEN_19_20MAX = 0x08,
394 	AUDIO_W_LEN_20_20MAX = 0x0a,
395 	AUDIO_W_LEN_20_24MAX = 0x03,
396 	AUDIO_W_LEN_22_24MAX = 0x05,
397 	AUDIO_W_LEN_21_24MAX = 0x0d,
398 	AUDIO_W_LEN_23_24MAX = 0x09,
399 	AUDIO_W_LEN_24_24MAX = 0x0b
400 };
401 
402 #define I2S_CH_2	0x01
403 #define TDM_CH_4	0x03
404 #define TDM_CH_6	0x05
405 #define TDM_CH_8	0x07
406 
407 #define MAX_DPCD_BUFFER_SIZE	16
408 
409 #define ONE_BLOCK_SIZE      128
410 #define FOUR_BLOCK_SIZE     (128 * 4)
411 
412 #define MAX_EDID_BLOCK	3
413 #define EDID_TRY_CNT	3
414 #define SUPPORT_PIXEL_CLOCK	300000
415 
416 struct s_edid_data {
417 	int edid_block_num;
418 	u8 edid_raw_data[FOUR_BLOCK_SIZE];
419 };
420 
421 /***************** Display End *****************/
422 
423 #define MAX_LANES_SUPPORT	4
424 
425 struct anx7625_platform_data {
426 	struct gpio_desc *gpio_p_on;
427 	struct gpio_desc *gpio_reset;
428 	struct regulator_bulk_data supplies[3];
429 	struct drm_bridge *panel_bridge;
430 	int intp_irq;
431 	int is_dpi;
432 	int mipi_lanes;
433 	int audio_en;
434 	int dp_lane0_swing_reg_cnt;
435 	u8 lane0_reg_data[DP_TX_SWING_REG_CNT];
436 	int dp_lane1_swing_reg_cnt;
437 	u8 lane1_reg_data[DP_TX_SWING_REG_CNT];
438 	u32 low_power_mode;
439 	struct device_node *mipi_host_node;
440 };
441 
442 struct anx7625_i2c_client {
443 	struct i2c_client *tx_p0_client;
444 	struct i2c_client *tx_p1_client;
445 	struct i2c_client *tx_p2_client;
446 	struct i2c_client *rx_p0_client;
447 	struct i2c_client *rx_p1_client;
448 	struct i2c_client *rx_p2_client;
449 	struct i2c_client *tcpc_client;
450 };
451 
452 struct anx7625_data {
453 	struct anx7625_platform_data pdata;
454 	struct platform_device *audio_pdev;
455 	int hpd_status;
456 	int hpd_high_cnt;
457 	int dp_en;
458 	int hdcp_cp;
459 	/* Lock for work queue */
460 	struct mutex lock;
461 	struct i2c_client *client;
462 	struct anx7625_i2c_client i2c;
463 	struct i2c_client *last_client;
464 	struct timer_list hdcp_timer;
465 	struct s_edid_data slimport_edid_p;
466 	struct device *codec_dev;
467 	hdmi_codec_plugged_cb plugged_cb;
468 	struct work_struct work;
469 	struct workqueue_struct *workqueue;
470 	struct delayed_work hdcp_work;
471 	struct workqueue_struct *hdcp_workqueue;
472 	/* Lock for hdcp work queue */
473 	struct mutex hdcp_wq_lock;
474 	char edid_block;
475 	struct display_timing dt;
476 	u8 display_timing_valid;
477 	struct drm_bridge bridge;
478 	u8 bridge_attached;
479 	struct drm_connector *connector;
480 	struct mipi_dsi_device *dsi;
481 	struct drm_dp_aux aux;
482 };
483 
484 #endif  /* __ANX7625_H__ */
485