1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 7 #ifndef __ANX7625_H__ 8 #define __ANX7625_H__ 9 10 #define ANX7625_DRV_VERSION "0.1.04" 11 12 /* Loading OCM re-trying times */ 13 #define OCM_LOADING_TIME 10 14 15 /********* ANX7625 Register **********/ 16 #define TX_P0_ADDR 0x70 17 #define TX_P1_ADDR 0x7A 18 #define TX_P2_ADDR 0x72 19 20 #define RX_P0_ADDR 0x7e 21 #define RX_P1_ADDR 0x84 22 #define RX_P2_ADDR 0x54 23 24 #define RSVD_00_ADDR 0x00 25 #define RSVD_D1_ADDR 0xD1 26 #define RSVD_60_ADDR 0x60 27 #define RSVD_39_ADDR 0x39 28 #define RSVD_7F_ADDR 0x7F 29 30 #define TCPC_INTERFACE_ADDR 0x58 31 32 /* Clock frequency in Hz */ 33 #define XTAL_FRQ (27 * 1000000) 34 35 #define POST_DIVIDER_MIN 1 36 #define POST_DIVIDER_MAX 16 37 #define PLL_OUT_FREQ_MIN 520000000UL 38 #define PLL_OUT_FREQ_MAX 730000000UL 39 #define PLL_OUT_FREQ_ABS_MIN 300000000UL 40 #define PLL_OUT_FREQ_ABS_MAX 800000000UL 41 #define MAX_UNSIGNED_24BIT 16777215UL 42 43 /***************************************************************/ 44 /* Register definition of device address 0x58 */ 45 46 #define PRODUCT_ID_L 0x02 47 #define PRODUCT_ID_H 0x03 48 49 #define INTR_ALERT_1 0xCC 50 #define INTR_SOFTWARE_INT BIT(3) 51 #define INTR_RECEIVED_MSG BIT(5) 52 53 #define SYSTEM_STSTUS 0x45 54 #define INTERFACE_CHANGE_INT 0x44 55 #define HPD_STATUS_CHANGE 0x80 56 #define HPD_STATUS 0x80 57 58 /******** END of I2C Address 0x58 ********/ 59 60 /***************************************************************/ 61 /* Register definition of device address 0x70 */ 62 #define I2C_ADDR_70_DPTX 0x70 63 64 #define SP_TX_LINK_BW_SET_REG 0xA0 65 #define SP_TX_LANE_COUNT_SET_REG 0xA1 66 67 #define M_VID_0 0xC0 68 #define M_VID_1 0xC1 69 #define M_VID_2 0xC2 70 #define N_VID_0 0xC3 71 #define N_VID_1 0xC4 72 #define N_VID_2 0xC5 73 74 /***************************************************************/ 75 /* Register definition of device address 0x72 */ 76 #define AUX_RST 0x04 77 #define RST_CTRL2 0x07 78 79 #define SP_TX_TOTAL_LINE_STA_L 0x24 80 #define SP_TX_TOTAL_LINE_STA_H 0x25 81 #define SP_TX_ACT_LINE_STA_L 0x26 82 #define SP_TX_ACT_LINE_STA_H 0x27 83 #define SP_TX_V_F_PORCH_STA 0x28 84 #define SP_TX_V_SYNC_STA 0x29 85 #define SP_TX_V_B_PORCH_STA 0x2A 86 #define SP_TX_TOTAL_PIXEL_STA_L 0x2B 87 #define SP_TX_TOTAL_PIXEL_STA_H 0x2C 88 #define SP_TX_ACT_PIXEL_STA_L 0x2D 89 #define SP_TX_ACT_PIXEL_STA_H 0x2E 90 #define SP_TX_H_F_PORCH_STA_L 0x2F 91 #define SP_TX_H_F_PORCH_STA_H 0x30 92 #define SP_TX_H_SYNC_STA_L 0x31 93 #define SP_TX_H_SYNC_STA_H 0x32 94 #define SP_TX_H_B_PORCH_STA_L 0x33 95 #define SP_TX_H_B_PORCH_STA_H 0x34 96 97 #define SP_TX_VID_CTRL 0x84 98 #define SP_TX_BPC_MASK 0xE0 99 #define SP_TX_BPC_6 0x00 100 #define SP_TX_BPC_8 0x20 101 #define SP_TX_BPC_10 0x40 102 #define SP_TX_BPC_12 0x60 103 104 #define VIDEO_BIT_MATRIX_12 0x4c 105 106 #define AUDIO_CHANNEL_STATUS_1 0xd0 107 #define AUDIO_CHANNEL_STATUS_2 0xd1 108 #define AUDIO_CHANNEL_STATUS_3 0xd2 109 #define AUDIO_CHANNEL_STATUS_4 0xd3 110 #define AUDIO_CHANNEL_STATUS_5 0xd4 111 #define AUDIO_CHANNEL_STATUS_6 0xd5 112 #define TDM_SLAVE_MODE 0x10 113 #define I2S_SLAVE_MODE 0x08 114 115 #define AUDIO_CONTROL_REGISTER 0xe6 116 #define TDM_TIMING_MODE 0x08 117 118 #define I2C_ADDR_72_DPTX 0x72 119 120 #define HP_MIN 8 121 #define HBLANKING_MIN 80 122 #define SYNC_LEN_DEF 32 123 #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2) 124 #define VIDEO_CONTROL_0 0x08 125 126 #define ACTIVE_LINES_L 0x14 127 #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */ 128 #define VERTICAL_FRONT_PORCH 0x16 129 #define VERTICAL_SYNC_WIDTH 0x17 130 #define VERTICAL_BACK_PORCH 0x18 131 132 #define HORIZONTAL_TOTAL_PIXELS_L 0x19 133 #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */ 134 #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 135 #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */ 136 #define HORIZONTAL_FRONT_PORCH_L 0x1D 137 #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */ 138 #define HORIZONTAL_SYNC_WIDTH_L 0x1F 139 #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */ 140 #define HORIZONTAL_BACK_PORCH_L 0x21 141 #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */ 142 143 /******** END of I2C Address 0x72 *********/ 144 /***************************************************************/ 145 /* Register definition of device address 0x7e */ 146 147 #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 148 149 #define FLASH_LOAD_STA 0x05 150 #define FLASH_LOAD_STA_CHK BIT(7) 151 152 #define XTAL_FRQ_SEL 0x3F 153 /* bit field positions */ 154 #define XTAL_FRQ_SEL_POS 5 155 /* bit field values */ 156 #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 157 #define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 158 159 #define R_DSC_CTRL_0 0x40 160 #define READ_STATUS_EN 7 161 #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 162 #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */ 163 #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 164 165 #define OCM_FW_VERSION 0x31 166 #define OCM_FW_REVERSION 0x32 167 168 #define AP_AUX_ADDR_7_0 0x11 169 #define AP_AUX_ADDR_15_8 0x12 170 #define AP_AUX_ADDR_19_16 0x13 171 172 /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 173 #define AP_AUX_CTRL_STATUS 0x14 174 #define AP_AUX_CTRL_OP_EN 0x10 175 #define AP_AUX_CTRL_ADDRONLY 0x20 176 177 #define AP_AUX_BUFF_START 0x15 178 #define PIXEL_CLOCK_L 0x25 179 #define PIXEL_CLOCK_H 0x26 180 181 #define AP_AUX_COMMAND 0x27 /* com+len */ 182 /* Bit 0&1: 3D video structure */ 183 /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 184 #define AP_AV_STATUS 0x28 185 #define AP_VIDEO_CHG BIT(2) 186 #define AP_AUDIO_CHG BIT(3) 187 #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */ 188 #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */ 189 #define AP_DISABLE_PD BIT(6) 190 #define AP_DISABLE_DISPLAY BIT(7) 191 /***************************************************************/ 192 /* Register definition of device address 0x84 */ 193 #define MIPI_PHY_CONTROL_3 0x03 194 #define MIPI_HS_PWD_CLK 7 195 #define MIPI_HS_RT_CLK 6 196 #define MIPI_PD_CLK 5 197 #define MIPI_CLK_RT_MANUAL_PD_EN 4 198 #define MIPI_CLK_HS_MANUAL_PD_EN 3 199 #define MIPI_CLK_DET_DET_BYPASS 2 200 #define MIPI_CLK_MISS_CTRL 1 201 #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 202 203 #define MIPI_LANE_CTRL_0 0x05 204 #define MIPI_TIME_HS_PRPR 0x08 205 206 /* 207 * After MIPI RX protocol layer received video frames, 208 * Protocol layer starts to reconstruct video stream from PHY 209 */ 210 #define MIPI_VIDEO_STABLE_CNT 0x0A 211 212 #define MIPI_LANE_CTRL_10 0x0F 213 #define MIPI_DIGITAL_ADJ_1 0x1B 214 215 #define MIPI_PLL_M_NUM_23_16 0x1E 216 #define MIPI_PLL_M_NUM_15_8 0x1F 217 #define MIPI_PLL_M_NUM_7_0 0x20 218 #define MIPI_PLL_N_NUM_23_16 0x21 219 #define MIPI_PLL_N_NUM_15_8 0x22 220 #define MIPI_PLL_N_NUM_7_0 0x23 221 222 #define MIPI_DIGITAL_PLL_6 0x2A 223 /* Bit[7:6]: VCO band control, only effective */ 224 #define MIPI_M_NUM_READY 0x10 225 #define MIPI_N_NUM_READY 0x08 226 #define STABLE_INTEGER_CNT_EN 0x04 227 #define MIPI_PLL_TEST_BIT 0 228 /* Bit[1:0]: test point output select - */ 229 /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 230 231 #define MIPI_DIGITAL_PLL_7 0x2B 232 #define MIPI_PLL_FORCE_N_EN 7 233 #define MIPI_PLL_FORCE_BAND_EN 6 234 235 #define MIPI_PLL_VCO_TUNE_REG 4 236 /* Bit[5:4]: VCO metal capacitance - */ 237 /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 238 #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 239 240 #define MIPI_PLL_PLL_LDO_BIT 2 241 /* Bit[3:2]: vco_v2i power - */ 242 /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 243 #define MIPI_PLL_RESET_N 0x02 244 #define MIPI_FRQ_FORCE_NDET 0 245 246 #define MIPI_ALERT_CLR_0 0x2D 247 #define HS_link_error_clear 7 248 /* This bit itself is S/C, and it clears 0x84:0x31[7] */ 249 250 #define MIPI_ALERT_OUT_0 0x31 251 #define check_sum_err_hs_sync 7 252 /* This bit is cleared by 0x84:0x2D[7] */ 253 254 #define MIPI_DIGITAL_PLL_8 0x33 255 #define MIPI_POST_DIV_VAL 4 256 /* N means divided by (n+1), n = 0~15 */ 257 #define MIPI_EN_LOCK_FRZ 3 258 #define MIPI_FRQ_COUNTER_RST 2 259 #define MIPI_FRQ_SET_REG_8 1 260 /* Bit 0 is reserved */ 261 262 #define MIPI_DIGITAL_PLL_9 0x34 263 264 #define MIPI_DIGITAL_PLL_16 0x3B 265 #define MIPI_FRQ_FREEZE_NDET 7 266 #define MIPI_FRQ_REG_SET_ENABLE 6 267 #define MIPI_REG_FORCE_SEL_EN 5 268 #define MIPI_REG_SEL_DIV_REG 4 269 #define MIPI_REG_FORCE_PRE_DIV_EN 3 270 /* Bit 2 is reserved */ 271 #define MIPI_FREF_D_IND 1 272 #define REF_CLK_27000KHZ 1 273 #define REF_CLK_19200KHZ 0 274 #define MIPI_REG_PLL_PLL_TEST_ENABLE 0 275 276 #define MIPI_DIGITAL_PLL_18 0x3D 277 #define FRQ_COUNT_RB_SEL 7 278 #define REG_FORCE_POST_DIV_EN 6 279 #define MIPI_DPI_SELECT 5 280 #define SELECT_DSI 1 281 #define SELECT_DPI 0 282 #define REG_BAUD_DIV_RATIO 0 283 284 #define H_BLANK_L 0x3E 285 /* For DSC only */ 286 #define H_BLANK_H 0x3F 287 /* For DSC only; note: bit[7:6] are reserved */ 288 #define MIPI_SWAP 0x4A 289 #define MIPI_SWAP_CH0 7 290 #define MIPI_SWAP_CH1 6 291 #define MIPI_SWAP_CH2 5 292 #define MIPI_SWAP_CH3 4 293 #define MIPI_SWAP_CLK 3 294 /* Bit[2:0] are reserved */ 295 296 /******** END of I2C Address 0x84 *********/ 297 298 /* DPCD regs */ 299 #define DPCD_DPCD_REV 0x00 300 #define DPCD_MAX_LINK_RATE 0x01 301 #define DPCD_MAX_LANE_COUNT 0x02 302 303 /********* ANX7625 Register End **********/ 304 305 /***************** Display *****************/ 306 enum audio_fs { 307 AUDIO_FS_441K = 0x00, 308 AUDIO_FS_48K = 0x02, 309 AUDIO_FS_32K = 0x03, 310 AUDIO_FS_882K = 0x08, 311 AUDIO_FS_96K = 0x0a, 312 AUDIO_FS_1764K = 0x0c, 313 AUDIO_FS_192K = 0x0e 314 }; 315 316 enum audio_wd_len { 317 AUDIO_W_LEN_16_20MAX = 0x02, 318 AUDIO_W_LEN_18_20MAX = 0x04, 319 AUDIO_W_LEN_17_20MAX = 0x0c, 320 AUDIO_W_LEN_19_20MAX = 0x08, 321 AUDIO_W_LEN_20_20MAX = 0x0a, 322 AUDIO_W_LEN_20_24MAX = 0x03, 323 AUDIO_W_LEN_22_24MAX = 0x05, 324 AUDIO_W_LEN_21_24MAX = 0x0d, 325 AUDIO_W_LEN_23_24MAX = 0x09, 326 AUDIO_W_LEN_24_24MAX = 0x0b 327 }; 328 329 #define I2S_CH_2 0x01 330 #define TDM_CH_4 0x03 331 #define TDM_CH_6 0x05 332 #define TDM_CH_8 0x07 333 334 #define MAX_DPCD_BUFFER_SIZE 16 335 336 #define ONE_BLOCK_SIZE 128 337 #define FOUR_BLOCK_SIZE (128 * 4) 338 339 #define MAX_EDID_BLOCK 3 340 #define EDID_TRY_CNT 3 341 #define SUPPORT_PIXEL_CLOCK 300000 342 343 struct s_edid_data { 344 int edid_block_num; 345 u8 edid_raw_data[FOUR_BLOCK_SIZE]; 346 }; 347 348 /***************** Display End *****************/ 349 350 struct anx7625_platform_data { 351 struct gpio_desc *gpio_p_on; 352 struct gpio_desc *gpio_reset; 353 struct regulator_bulk_data supplies[3]; 354 struct drm_bridge *panel_bridge; 355 int intp_irq; 356 u32 low_power_mode; 357 struct device_node *mipi_host_node; 358 }; 359 360 struct anx7625_i2c_client { 361 struct i2c_client *tx_p0_client; 362 struct i2c_client *tx_p1_client; 363 struct i2c_client *tx_p2_client; 364 struct i2c_client *rx_p0_client; 365 struct i2c_client *rx_p1_client; 366 struct i2c_client *rx_p2_client; 367 struct i2c_client *tcpc_client; 368 }; 369 370 struct anx7625_data { 371 struct anx7625_platform_data pdata; 372 atomic_t power_status; 373 int hpd_status; 374 int hpd_high_cnt; 375 /* Lock for work queue */ 376 struct mutex lock; 377 struct i2c_client *client; 378 struct anx7625_i2c_client i2c; 379 struct i2c_client *last_client; 380 struct s_edid_data slimport_edid_p; 381 struct work_struct work; 382 struct workqueue_struct *workqueue; 383 char edid_block; 384 struct display_timing dt; 385 u8 display_timing_valid; 386 struct drm_bridge bridge; 387 u8 bridge_attached; 388 struct mipi_dsi_device *dsi; 389 }; 390 391 #endif /* __ANX7625_H__ */ 392