1*8bdfc5daSXin Ji /* SPDX-License-Identifier: GPL-2.0-only */ 2*8bdfc5daSXin Ji /* 3*8bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4*8bdfc5daSXin Ji * 5*8bdfc5daSXin Ji */ 6*8bdfc5daSXin Ji 7*8bdfc5daSXin Ji #ifndef __ANX7625_H__ 8*8bdfc5daSXin Ji #define __ANX7625_H__ 9*8bdfc5daSXin Ji 10*8bdfc5daSXin Ji #define ANX7625_DRV_VERSION "0.1.04" 11*8bdfc5daSXin Ji 12*8bdfc5daSXin Ji /* Loading OCM re-trying times */ 13*8bdfc5daSXin Ji #define OCM_LOADING_TIME 10 14*8bdfc5daSXin Ji 15*8bdfc5daSXin Ji /********* ANX7625 Register **********/ 16*8bdfc5daSXin Ji #define TX_P0_ADDR 0x70 17*8bdfc5daSXin Ji #define TX_P1_ADDR 0x7A 18*8bdfc5daSXin Ji #define TX_P2_ADDR 0x72 19*8bdfc5daSXin Ji 20*8bdfc5daSXin Ji #define RX_P0_ADDR 0x7e 21*8bdfc5daSXin Ji #define RX_P1_ADDR 0x84 22*8bdfc5daSXin Ji #define RX_P2_ADDR 0x54 23*8bdfc5daSXin Ji 24*8bdfc5daSXin Ji #define RSVD_00_ADDR 0x00 25*8bdfc5daSXin Ji #define RSVD_D1_ADDR 0xD1 26*8bdfc5daSXin Ji #define RSVD_60_ADDR 0x60 27*8bdfc5daSXin Ji #define RSVD_39_ADDR 0x39 28*8bdfc5daSXin Ji #define RSVD_7F_ADDR 0x7F 29*8bdfc5daSXin Ji 30*8bdfc5daSXin Ji #define TCPC_INTERFACE_ADDR 0x58 31*8bdfc5daSXin Ji 32*8bdfc5daSXin Ji /* Clock frequency in Hz */ 33*8bdfc5daSXin Ji #define XTAL_FRQ (27 * 1000000) 34*8bdfc5daSXin Ji 35*8bdfc5daSXin Ji #define POST_DIVIDER_MIN 1 36*8bdfc5daSXin Ji #define POST_DIVIDER_MAX 16 37*8bdfc5daSXin Ji #define PLL_OUT_FREQ_MIN 520000000UL 38*8bdfc5daSXin Ji #define PLL_OUT_FREQ_MAX 730000000UL 39*8bdfc5daSXin Ji #define PLL_OUT_FREQ_ABS_MIN 300000000UL 40*8bdfc5daSXin Ji #define PLL_OUT_FREQ_ABS_MAX 800000000UL 41*8bdfc5daSXin Ji #define MAX_UNSIGNED_24BIT 16777215UL 42*8bdfc5daSXin Ji 43*8bdfc5daSXin Ji /***************************************************************/ 44*8bdfc5daSXin Ji /* Register definition of device address 0x58 */ 45*8bdfc5daSXin Ji 46*8bdfc5daSXin Ji #define PRODUCT_ID_L 0x02 47*8bdfc5daSXin Ji #define PRODUCT_ID_H 0x03 48*8bdfc5daSXin Ji 49*8bdfc5daSXin Ji #define INTR_ALERT_1 0xCC 50*8bdfc5daSXin Ji #define INTR_SOFTWARE_INT BIT(3) 51*8bdfc5daSXin Ji #define INTR_RECEIVED_MSG BIT(5) 52*8bdfc5daSXin Ji 53*8bdfc5daSXin Ji #define SYSTEM_STSTUS 0x45 54*8bdfc5daSXin Ji #define INTERFACE_CHANGE_INT 0x44 55*8bdfc5daSXin Ji #define HPD_STATUS_CHANGE 0x80 56*8bdfc5daSXin Ji #define HPD_STATUS 0x80 57*8bdfc5daSXin Ji 58*8bdfc5daSXin Ji /******** END of I2C Address 0x58 ********/ 59*8bdfc5daSXin Ji 60*8bdfc5daSXin Ji /***************************************************************/ 61*8bdfc5daSXin Ji /* Register definition of device address 0x70 */ 62*8bdfc5daSXin Ji #define I2C_ADDR_70_DPTX 0x70 63*8bdfc5daSXin Ji 64*8bdfc5daSXin Ji #define SP_TX_LINK_BW_SET_REG 0xA0 65*8bdfc5daSXin Ji #define SP_TX_LANE_COUNT_SET_REG 0xA1 66*8bdfc5daSXin Ji 67*8bdfc5daSXin Ji #define M_VID_0 0xC0 68*8bdfc5daSXin Ji #define M_VID_1 0xC1 69*8bdfc5daSXin Ji #define M_VID_2 0xC2 70*8bdfc5daSXin Ji #define N_VID_0 0xC3 71*8bdfc5daSXin Ji #define N_VID_1 0xC4 72*8bdfc5daSXin Ji #define N_VID_2 0xC5 73*8bdfc5daSXin Ji 74*8bdfc5daSXin Ji /***************************************************************/ 75*8bdfc5daSXin Ji /* Register definition of device address 0x72 */ 76*8bdfc5daSXin Ji #define AUX_RST 0x04 77*8bdfc5daSXin Ji #define RST_CTRL2 0x07 78*8bdfc5daSXin Ji 79*8bdfc5daSXin Ji #define SP_TX_TOTAL_LINE_STA_L 0x24 80*8bdfc5daSXin Ji #define SP_TX_TOTAL_LINE_STA_H 0x25 81*8bdfc5daSXin Ji #define SP_TX_ACT_LINE_STA_L 0x26 82*8bdfc5daSXin Ji #define SP_TX_ACT_LINE_STA_H 0x27 83*8bdfc5daSXin Ji #define SP_TX_V_F_PORCH_STA 0x28 84*8bdfc5daSXin Ji #define SP_TX_V_SYNC_STA 0x29 85*8bdfc5daSXin Ji #define SP_TX_V_B_PORCH_STA 0x2A 86*8bdfc5daSXin Ji #define SP_TX_TOTAL_PIXEL_STA_L 0x2B 87*8bdfc5daSXin Ji #define SP_TX_TOTAL_PIXEL_STA_H 0x2C 88*8bdfc5daSXin Ji #define SP_TX_ACT_PIXEL_STA_L 0x2D 89*8bdfc5daSXin Ji #define SP_TX_ACT_PIXEL_STA_H 0x2E 90*8bdfc5daSXin Ji #define SP_TX_H_F_PORCH_STA_L 0x2F 91*8bdfc5daSXin Ji #define SP_TX_H_F_PORCH_STA_H 0x30 92*8bdfc5daSXin Ji #define SP_TX_H_SYNC_STA_L 0x31 93*8bdfc5daSXin Ji #define SP_TX_H_SYNC_STA_H 0x32 94*8bdfc5daSXin Ji #define SP_TX_H_B_PORCH_STA_L 0x33 95*8bdfc5daSXin Ji #define SP_TX_H_B_PORCH_STA_H 0x34 96*8bdfc5daSXin Ji 97*8bdfc5daSXin Ji #define SP_TX_VID_CTRL 0x84 98*8bdfc5daSXin Ji #define SP_TX_BPC_MASK 0xE0 99*8bdfc5daSXin Ji #define SP_TX_BPC_6 0x00 100*8bdfc5daSXin Ji #define SP_TX_BPC_8 0x20 101*8bdfc5daSXin Ji #define SP_TX_BPC_10 0x40 102*8bdfc5daSXin Ji #define SP_TX_BPC_12 0x60 103*8bdfc5daSXin Ji 104*8bdfc5daSXin Ji #define VIDEO_BIT_MATRIX_12 0x4c 105*8bdfc5daSXin Ji 106*8bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_1 0xd0 107*8bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_2 0xd1 108*8bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_3 0xd2 109*8bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_4 0xd3 110*8bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_5 0xd4 111*8bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_6 0xd5 112*8bdfc5daSXin Ji #define TDM_SLAVE_MODE 0x10 113*8bdfc5daSXin Ji #define I2S_SLAVE_MODE 0x08 114*8bdfc5daSXin Ji 115*8bdfc5daSXin Ji #define AUDIO_CONTROL_REGISTER 0xe6 116*8bdfc5daSXin Ji #define TDM_TIMING_MODE 0x08 117*8bdfc5daSXin Ji 118*8bdfc5daSXin Ji #define I2C_ADDR_72_DPTX 0x72 119*8bdfc5daSXin Ji 120*8bdfc5daSXin Ji #define HP_MIN 8 121*8bdfc5daSXin Ji #define HBLANKING_MIN 80 122*8bdfc5daSXin Ji #define SYNC_LEN_DEF 32 123*8bdfc5daSXin Ji #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2) 124*8bdfc5daSXin Ji #define VIDEO_CONTROL_0 0x08 125*8bdfc5daSXin Ji 126*8bdfc5daSXin Ji #define ACTIVE_LINES_L 0x14 127*8bdfc5daSXin Ji #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */ 128*8bdfc5daSXin Ji #define VERTICAL_FRONT_PORCH 0x16 129*8bdfc5daSXin Ji #define VERTICAL_SYNC_WIDTH 0x17 130*8bdfc5daSXin Ji #define VERTICAL_BACK_PORCH 0x18 131*8bdfc5daSXin Ji 132*8bdfc5daSXin Ji #define HORIZONTAL_TOTAL_PIXELS_L 0x19 133*8bdfc5daSXin Ji #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */ 134*8bdfc5daSXin Ji #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 135*8bdfc5daSXin Ji #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */ 136*8bdfc5daSXin Ji #define HORIZONTAL_FRONT_PORCH_L 0x1D 137*8bdfc5daSXin Ji #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */ 138*8bdfc5daSXin Ji #define HORIZONTAL_SYNC_WIDTH_L 0x1F 139*8bdfc5daSXin Ji #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */ 140*8bdfc5daSXin Ji #define HORIZONTAL_BACK_PORCH_L 0x21 141*8bdfc5daSXin Ji #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */ 142*8bdfc5daSXin Ji 143*8bdfc5daSXin Ji /******** END of I2C Address 0x72 *********/ 144*8bdfc5daSXin Ji /***************************************************************/ 145*8bdfc5daSXin Ji /* Register definition of device address 0x7e */ 146*8bdfc5daSXin Ji 147*8bdfc5daSXin Ji #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 148*8bdfc5daSXin Ji 149*8bdfc5daSXin Ji #define FLASH_LOAD_STA 0x05 150*8bdfc5daSXin Ji #define FLASH_LOAD_STA_CHK BIT(7) 151*8bdfc5daSXin Ji 152*8bdfc5daSXin Ji #define XTAL_FRQ_SEL 0x3F 153*8bdfc5daSXin Ji /* bit field positions */ 154*8bdfc5daSXin Ji #define XTAL_FRQ_SEL_POS 5 155*8bdfc5daSXin Ji /* bit field values */ 156*8bdfc5daSXin Ji #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 157*8bdfc5daSXin Ji #define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 158*8bdfc5daSXin Ji 159*8bdfc5daSXin Ji #define R_DSC_CTRL_0 0x40 160*8bdfc5daSXin Ji #define READ_STATUS_EN 7 161*8bdfc5daSXin Ji #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 162*8bdfc5daSXin Ji #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */ 163*8bdfc5daSXin Ji #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 164*8bdfc5daSXin Ji 165*8bdfc5daSXin Ji #define OCM_FW_VERSION 0x31 166*8bdfc5daSXin Ji #define OCM_FW_REVERSION 0x32 167*8bdfc5daSXin Ji 168*8bdfc5daSXin Ji #define AP_AUX_ADDR_7_0 0x11 169*8bdfc5daSXin Ji #define AP_AUX_ADDR_15_8 0x12 170*8bdfc5daSXin Ji #define AP_AUX_ADDR_19_16 0x13 171*8bdfc5daSXin Ji 172*8bdfc5daSXin Ji /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 173*8bdfc5daSXin Ji #define AP_AUX_CTRL_STATUS 0x14 174*8bdfc5daSXin Ji #define AP_AUX_CTRL_OP_EN 0x10 175*8bdfc5daSXin Ji #define AP_AUX_CTRL_ADDRONLY 0x20 176*8bdfc5daSXin Ji 177*8bdfc5daSXin Ji #define AP_AUX_BUFF_START 0x15 178*8bdfc5daSXin Ji #define PIXEL_CLOCK_L 0x25 179*8bdfc5daSXin Ji #define PIXEL_CLOCK_H 0x26 180*8bdfc5daSXin Ji 181*8bdfc5daSXin Ji #define AP_AUX_COMMAND 0x27 /* com+len */ 182*8bdfc5daSXin Ji /* Bit 0&1: 3D video structure */ 183*8bdfc5daSXin Ji /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 184*8bdfc5daSXin Ji #define AP_AV_STATUS 0x28 185*8bdfc5daSXin Ji #define AP_VIDEO_CHG BIT(2) 186*8bdfc5daSXin Ji #define AP_AUDIO_CHG BIT(3) 187*8bdfc5daSXin Ji #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */ 188*8bdfc5daSXin Ji #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */ 189*8bdfc5daSXin Ji #define AP_DISABLE_PD BIT(6) 190*8bdfc5daSXin Ji #define AP_DISABLE_DISPLAY BIT(7) 191*8bdfc5daSXin Ji /***************************************************************/ 192*8bdfc5daSXin Ji /* Register definition of device address 0x84 */ 193*8bdfc5daSXin Ji #define MIPI_PHY_CONTROL_3 0x03 194*8bdfc5daSXin Ji #define MIPI_HS_PWD_CLK 7 195*8bdfc5daSXin Ji #define MIPI_HS_RT_CLK 6 196*8bdfc5daSXin Ji #define MIPI_PD_CLK 5 197*8bdfc5daSXin Ji #define MIPI_CLK_RT_MANUAL_PD_EN 4 198*8bdfc5daSXin Ji #define MIPI_CLK_HS_MANUAL_PD_EN 3 199*8bdfc5daSXin Ji #define MIPI_CLK_DET_DET_BYPASS 2 200*8bdfc5daSXin Ji #define MIPI_CLK_MISS_CTRL 1 201*8bdfc5daSXin Ji #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 202*8bdfc5daSXin Ji 203*8bdfc5daSXin Ji #define MIPI_LANE_CTRL_0 0x05 204*8bdfc5daSXin Ji #define MIPI_TIME_HS_PRPR 0x08 205*8bdfc5daSXin Ji 206*8bdfc5daSXin Ji /* 207*8bdfc5daSXin Ji * After MIPI RX protocol layer received video frames, 208*8bdfc5daSXin Ji * Protocol layer starts to reconstruct video stream from PHY 209*8bdfc5daSXin Ji */ 210*8bdfc5daSXin Ji #define MIPI_VIDEO_STABLE_CNT 0x0A 211*8bdfc5daSXin Ji 212*8bdfc5daSXin Ji #define MIPI_LANE_CTRL_10 0x0F 213*8bdfc5daSXin Ji #define MIPI_DIGITAL_ADJ_1 0x1B 214*8bdfc5daSXin Ji 215*8bdfc5daSXin Ji #define MIPI_PLL_M_NUM_23_16 0x1E 216*8bdfc5daSXin Ji #define MIPI_PLL_M_NUM_15_8 0x1F 217*8bdfc5daSXin Ji #define MIPI_PLL_M_NUM_7_0 0x20 218*8bdfc5daSXin Ji #define MIPI_PLL_N_NUM_23_16 0x21 219*8bdfc5daSXin Ji #define MIPI_PLL_N_NUM_15_8 0x22 220*8bdfc5daSXin Ji #define MIPI_PLL_N_NUM_7_0 0x23 221*8bdfc5daSXin Ji 222*8bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_6 0x2A 223*8bdfc5daSXin Ji /* Bit[7:6]: VCO band control, only effective */ 224*8bdfc5daSXin Ji #define MIPI_M_NUM_READY 0x10 225*8bdfc5daSXin Ji #define MIPI_N_NUM_READY 0x08 226*8bdfc5daSXin Ji #define STABLE_INTEGER_CNT_EN 0x04 227*8bdfc5daSXin Ji #define MIPI_PLL_TEST_BIT 0 228*8bdfc5daSXin Ji /* Bit[1:0]: test point output select - */ 229*8bdfc5daSXin Ji /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 230*8bdfc5daSXin Ji 231*8bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_7 0x2B 232*8bdfc5daSXin Ji #define MIPI_PLL_FORCE_N_EN 7 233*8bdfc5daSXin Ji #define MIPI_PLL_FORCE_BAND_EN 6 234*8bdfc5daSXin Ji 235*8bdfc5daSXin Ji #define MIPI_PLL_VCO_TUNE_REG 4 236*8bdfc5daSXin Ji /* Bit[5:4]: VCO metal capacitance - */ 237*8bdfc5daSXin Ji /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 238*8bdfc5daSXin Ji #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 239*8bdfc5daSXin Ji 240*8bdfc5daSXin Ji #define MIPI_PLL_PLL_LDO_BIT 2 241*8bdfc5daSXin Ji /* Bit[3:2]: vco_v2i power - */ 242*8bdfc5daSXin Ji /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 243*8bdfc5daSXin Ji #define MIPI_PLL_RESET_N 0x02 244*8bdfc5daSXin Ji #define MIPI_FRQ_FORCE_NDET 0 245*8bdfc5daSXin Ji 246*8bdfc5daSXin Ji #define MIPI_ALERT_CLR_0 0x2D 247*8bdfc5daSXin Ji #define HS_link_error_clear 7 248*8bdfc5daSXin Ji /* This bit itself is S/C, and it clears 0x84:0x31[7] */ 249*8bdfc5daSXin Ji 250*8bdfc5daSXin Ji #define MIPI_ALERT_OUT_0 0x31 251*8bdfc5daSXin Ji #define check_sum_err_hs_sync 7 252*8bdfc5daSXin Ji /* This bit is cleared by 0x84:0x2D[7] */ 253*8bdfc5daSXin Ji 254*8bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_8 0x33 255*8bdfc5daSXin Ji #define MIPI_POST_DIV_VAL 4 256*8bdfc5daSXin Ji /* N means divided by (n+1), n = 0~15 */ 257*8bdfc5daSXin Ji #define MIPI_EN_LOCK_FRZ 3 258*8bdfc5daSXin Ji #define MIPI_FRQ_COUNTER_RST 2 259*8bdfc5daSXin Ji #define MIPI_FRQ_SET_REG_8 1 260*8bdfc5daSXin Ji /* Bit 0 is reserved */ 261*8bdfc5daSXin Ji 262*8bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_9 0x34 263*8bdfc5daSXin Ji 264*8bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_16 0x3B 265*8bdfc5daSXin Ji #define MIPI_FRQ_FREEZE_NDET 7 266*8bdfc5daSXin Ji #define MIPI_FRQ_REG_SET_ENABLE 6 267*8bdfc5daSXin Ji #define MIPI_REG_FORCE_SEL_EN 5 268*8bdfc5daSXin Ji #define MIPI_REG_SEL_DIV_REG 4 269*8bdfc5daSXin Ji #define MIPI_REG_FORCE_PRE_DIV_EN 3 270*8bdfc5daSXin Ji /* Bit 2 is reserved */ 271*8bdfc5daSXin Ji #define MIPI_FREF_D_IND 1 272*8bdfc5daSXin Ji #define REF_CLK_27000KHZ 1 273*8bdfc5daSXin Ji #define REF_CLK_19200KHZ 0 274*8bdfc5daSXin Ji #define MIPI_REG_PLL_PLL_TEST_ENABLE 0 275*8bdfc5daSXin Ji 276*8bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_18 0x3D 277*8bdfc5daSXin Ji #define FRQ_COUNT_RB_SEL 7 278*8bdfc5daSXin Ji #define REG_FORCE_POST_DIV_EN 6 279*8bdfc5daSXin Ji #define MIPI_DPI_SELECT 5 280*8bdfc5daSXin Ji #define SELECT_DSI 1 281*8bdfc5daSXin Ji #define SELECT_DPI 0 282*8bdfc5daSXin Ji #define REG_BAUD_DIV_RATIO 0 283*8bdfc5daSXin Ji 284*8bdfc5daSXin Ji #define H_BLANK_L 0x3E 285*8bdfc5daSXin Ji /* For DSC only */ 286*8bdfc5daSXin Ji #define H_BLANK_H 0x3F 287*8bdfc5daSXin Ji /* For DSC only; note: bit[7:6] are reserved */ 288*8bdfc5daSXin Ji #define MIPI_SWAP 0x4A 289*8bdfc5daSXin Ji #define MIPI_SWAP_CH0 7 290*8bdfc5daSXin Ji #define MIPI_SWAP_CH1 6 291*8bdfc5daSXin Ji #define MIPI_SWAP_CH2 5 292*8bdfc5daSXin Ji #define MIPI_SWAP_CH3 4 293*8bdfc5daSXin Ji #define MIPI_SWAP_CLK 3 294*8bdfc5daSXin Ji /* Bit[2:0] are reserved */ 295*8bdfc5daSXin Ji 296*8bdfc5daSXin Ji /******** END of I2C Address 0x84 *********/ 297*8bdfc5daSXin Ji 298*8bdfc5daSXin Ji /* DPCD regs */ 299*8bdfc5daSXin Ji #define DPCD_DPCD_REV 0x00 300*8bdfc5daSXin Ji #define DPCD_MAX_LINK_RATE 0x01 301*8bdfc5daSXin Ji #define DPCD_MAX_LANE_COUNT 0x02 302*8bdfc5daSXin Ji 303*8bdfc5daSXin Ji /********* ANX7625 Register End **********/ 304*8bdfc5daSXin Ji 305*8bdfc5daSXin Ji /***************** Display *****************/ 306*8bdfc5daSXin Ji enum audio_fs { 307*8bdfc5daSXin Ji AUDIO_FS_441K = 0x00, 308*8bdfc5daSXin Ji AUDIO_FS_48K = 0x02, 309*8bdfc5daSXin Ji AUDIO_FS_32K = 0x03, 310*8bdfc5daSXin Ji AUDIO_FS_882K = 0x08, 311*8bdfc5daSXin Ji AUDIO_FS_96K = 0x0a, 312*8bdfc5daSXin Ji AUDIO_FS_1764K = 0x0c, 313*8bdfc5daSXin Ji AUDIO_FS_192K = 0x0e 314*8bdfc5daSXin Ji }; 315*8bdfc5daSXin Ji 316*8bdfc5daSXin Ji enum audio_wd_len { 317*8bdfc5daSXin Ji AUDIO_W_LEN_16_20MAX = 0x02, 318*8bdfc5daSXin Ji AUDIO_W_LEN_18_20MAX = 0x04, 319*8bdfc5daSXin Ji AUDIO_W_LEN_17_20MAX = 0x0c, 320*8bdfc5daSXin Ji AUDIO_W_LEN_19_20MAX = 0x08, 321*8bdfc5daSXin Ji AUDIO_W_LEN_20_20MAX = 0x0a, 322*8bdfc5daSXin Ji AUDIO_W_LEN_20_24MAX = 0x03, 323*8bdfc5daSXin Ji AUDIO_W_LEN_22_24MAX = 0x05, 324*8bdfc5daSXin Ji AUDIO_W_LEN_21_24MAX = 0x0d, 325*8bdfc5daSXin Ji AUDIO_W_LEN_23_24MAX = 0x09, 326*8bdfc5daSXin Ji AUDIO_W_LEN_24_24MAX = 0x0b 327*8bdfc5daSXin Ji }; 328*8bdfc5daSXin Ji 329*8bdfc5daSXin Ji #define I2S_CH_2 0x01 330*8bdfc5daSXin Ji #define TDM_CH_4 0x03 331*8bdfc5daSXin Ji #define TDM_CH_6 0x05 332*8bdfc5daSXin Ji #define TDM_CH_8 0x07 333*8bdfc5daSXin Ji 334*8bdfc5daSXin Ji #define MAX_DPCD_BUFFER_SIZE 16 335*8bdfc5daSXin Ji 336*8bdfc5daSXin Ji #define ONE_BLOCK_SIZE 128 337*8bdfc5daSXin Ji #define FOUR_BLOCK_SIZE (128 * 4) 338*8bdfc5daSXin Ji 339*8bdfc5daSXin Ji #define MAX_EDID_BLOCK 3 340*8bdfc5daSXin Ji #define EDID_TRY_CNT 3 341*8bdfc5daSXin Ji #define SUPPORT_PIXEL_CLOCK 300000 342*8bdfc5daSXin Ji 343*8bdfc5daSXin Ji struct s_edid_data { 344*8bdfc5daSXin Ji int edid_block_num; 345*8bdfc5daSXin Ji u8 edid_raw_data[FOUR_BLOCK_SIZE]; 346*8bdfc5daSXin Ji }; 347*8bdfc5daSXin Ji 348*8bdfc5daSXin Ji /***************** Display End *****************/ 349*8bdfc5daSXin Ji 350*8bdfc5daSXin Ji struct anx7625_platform_data { 351*8bdfc5daSXin Ji struct gpio_desc *gpio_p_on; 352*8bdfc5daSXin Ji struct gpio_desc *gpio_reset; 353*8bdfc5daSXin Ji struct drm_bridge *panel_bridge; 354*8bdfc5daSXin Ji int intp_irq; 355*8bdfc5daSXin Ji u32 low_power_mode; 356*8bdfc5daSXin Ji struct device_node *mipi_host_node; 357*8bdfc5daSXin Ji }; 358*8bdfc5daSXin Ji 359*8bdfc5daSXin Ji struct anx7625_i2c_client { 360*8bdfc5daSXin Ji struct i2c_client *tx_p0_client; 361*8bdfc5daSXin Ji struct i2c_client *tx_p1_client; 362*8bdfc5daSXin Ji struct i2c_client *tx_p2_client; 363*8bdfc5daSXin Ji struct i2c_client *rx_p0_client; 364*8bdfc5daSXin Ji struct i2c_client *rx_p1_client; 365*8bdfc5daSXin Ji struct i2c_client *rx_p2_client; 366*8bdfc5daSXin Ji struct i2c_client *tcpc_client; 367*8bdfc5daSXin Ji }; 368*8bdfc5daSXin Ji 369*8bdfc5daSXin Ji struct anx7625_data { 370*8bdfc5daSXin Ji struct anx7625_platform_data pdata; 371*8bdfc5daSXin Ji atomic_t power_status; 372*8bdfc5daSXin Ji int hpd_status; 373*8bdfc5daSXin Ji int hpd_high_cnt; 374*8bdfc5daSXin Ji /* Lock for work queue */ 375*8bdfc5daSXin Ji struct mutex lock; 376*8bdfc5daSXin Ji struct i2c_client *client; 377*8bdfc5daSXin Ji struct anx7625_i2c_client i2c; 378*8bdfc5daSXin Ji struct i2c_client *last_client; 379*8bdfc5daSXin Ji struct s_edid_data slimport_edid_p; 380*8bdfc5daSXin Ji struct work_struct work; 381*8bdfc5daSXin Ji struct workqueue_struct *workqueue; 382*8bdfc5daSXin Ji char edid_block; 383*8bdfc5daSXin Ji struct display_timing dt; 384*8bdfc5daSXin Ji u8 display_timing_valid; 385*8bdfc5daSXin Ji struct drm_bridge bridge; 386*8bdfc5daSXin Ji u8 bridge_attached; 387*8bdfc5daSXin Ji struct mipi_dsi_device *dsi; 388*8bdfc5daSXin Ji }; 389*8bdfc5daSXin Ji 390*8bdfc5daSXin Ji #endif /* __ANX7625_H__ */ 391