18bdfc5daSXin Ji /* SPDX-License-Identifier: GPL-2.0-only */ 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji 78bdfc5daSXin Ji #ifndef __ANX7625_H__ 88bdfc5daSXin Ji #define __ANX7625_H__ 98bdfc5daSXin Ji 108bdfc5daSXin Ji #define ANX7625_DRV_VERSION "0.1.04" 118bdfc5daSXin Ji 128bdfc5daSXin Ji /* Loading OCM re-trying times */ 138bdfc5daSXin Ji #define OCM_LOADING_TIME 10 148bdfc5daSXin Ji 158bdfc5daSXin Ji /********* ANX7625 Register **********/ 168bdfc5daSXin Ji #define TX_P0_ADDR 0x70 178bdfc5daSXin Ji #define TX_P1_ADDR 0x7A 188bdfc5daSXin Ji #define TX_P2_ADDR 0x72 198bdfc5daSXin Ji 208bdfc5daSXin Ji #define RX_P0_ADDR 0x7e 218bdfc5daSXin Ji #define RX_P1_ADDR 0x84 228bdfc5daSXin Ji #define RX_P2_ADDR 0x54 238bdfc5daSXin Ji 248bdfc5daSXin Ji #define RSVD_00_ADDR 0x00 258bdfc5daSXin Ji #define RSVD_D1_ADDR 0xD1 268bdfc5daSXin Ji #define RSVD_60_ADDR 0x60 278bdfc5daSXin Ji #define RSVD_39_ADDR 0x39 288bdfc5daSXin Ji #define RSVD_7F_ADDR 0x7F 298bdfc5daSXin Ji 308bdfc5daSXin Ji #define TCPC_INTERFACE_ADDR 0x58 318bdfc5daSXin Ji 328bdfc5daSXin Ji /* Clock frequency in Hz */ 338bdfc5daSXin Ji #define XTAL_FRQ (27 * 1000000) 348bdfc5daSXin Ji 358bdfc5daSXin Ji #define POST_DIVIDER_MIN 1 368bdfc5daSXin Ji #define POST_DIVIDER_MAX 16 378bdfc5daSXin Ji #define PLL_OUT_FREQ_MIN 520000000UL 388bdfc5daSXin Ji #define PLL_OUT_FREQ_MAX 730000000UL 398bdfc5daSXin Ji #define PLL_OUT_FREQ_ABS_MIN 300000000UL 408bdfc5daSXin Ji #define PLL_OUT_FREQ_ABS_MAX 800000000UL 418bdfc5daSXin Ji #define MAX_UNSIGNED_24BIT 16777215UL 428bdfc5daSXin Ji 438bdfc5daSXin Ji /***************************************************************/ 448bdfc5daSXin Ji /* Register definition of device address 0x58 */ 458bdfc5daSXin Ji 468bdfc5daSXin Ji #define PRODUCT_ID_L 0x02 478bdfc5daSXin Ji #define PRODUCT_ID_H 0x03 488bdfc5daSXin Ji 498bdfc5daSXin Ji #define INTR_ALERT_1 0xCC 508bdfc5daSXin Ji #define INTR_SOFTWARE_INT BIT(3) 518bdfc5daSXin Ji #define INTR_RECEIVED_MSG BIT(5) 528bdfc5daSXin Ji 538bdfc5daSXin Ji #define SYSTEM_STSTUS 0x45 548bdfc5daSXin Ji #define INTERFACE_CHANGE_INT 0x44 558bdfc5daSXin Ji #define HPD_STATUS_CHANGE 0x80 568bdfc5daSXin Ji #define HPD_STATUS 0x80 578bdfc5daSXin Ji 588bdfc5daSXin Ji /******** END of I2C Address 0x58 ********/ 598bdfc5daSXin Ji 608bdfc5daSXin Ji /***************************************************************/ 618bdfc5daSXin Ji /* Register definition of device address 0x70 */ 628bdfc5daSXin Ji #define I2C_ADDR_70_DPTX 0x70 638bdfc5daSXin Ji 648bdfc5daSXin Ji #define SP_TX_LINK_BW_SET_REG 0xA0 658bdfc5daSXin Ji #define SP_TX_LANE_COUNT_SET_REG 0xA1 668bdfc5daSXin Ji 678bdfc5daSXin Ji #define M_VID_0 0xC0 688bdfc5daSXin Ji #define M_VID_1 0xC1 698bdfc5daSXin Ji #define M_VID_2 0xC2 708bdfc5daSXin Ji #define N_VID_0 0xC3 718bdfc5daSXin Ji #define N_VID_1 0xC4 728bdfc5daSXin Ji #define N_VID_2 0xC5 738bdfc5daSXin Ji 748bdfc5daSXin Ji /***************************************************************/ 758bdfc5daSXin Ji /* Register definition of device address 0x72 */ 768bdfc5daSXin Ji #define AUX_RST 0x04 778bdfc5daSXin Ji #define RST_CTRL2 0x07 788bdfc5daSXin Ji 798bdfc5daSXin Ji #define SP_TX_TOTAL_LINE_STA_L 0x24 808bdfc5daSXin Ji #define SP_TX_TOTAL_LINE_STA_H 0x25 818bdfc5daSXin Ji #define SP_TX_ACT_LINE_STA_L 0x26 828bdfc5daSXin Ji #define SP_TX_ACT_LINE_STA_H 0x27 838bdfc5daSXin Ji #define SP_TX_V_F_PORCH_STA 0x28 848bdfc5daSXin Ji #define SP_TX_V_SYNC_STA 0x29 858bdfc5daSXin Ji #define SP_TX_V_B_PORCH_STA 0x2A 868bdfc5daSXin Ji #define SP_TX_TOTAL_PIXEL_STA_L 0x2B 878bdfc5daSXin Ji #define SP_TX_TOTAL_PIXEL_STA_H 0x2C 888bdfc5daSXin Ji #define SP_TX_ACT_PIXEL_STA_L 0x2D 898bdfc5daSXin Ji #define SP_TX_ACT_PIXEL_STA_H 0x2E 908bdfc5daSXin Ji #define SP_TX_H_F_PORCH_STA_L 0x2F 918bdfc5daSXin Ji #define SP_TX_H_F_PORCH_STA_H 0x30 928bdfc5daSXin Ji #define SP_TX_H_SYNC_STA_L 0x31 938bdfc5daSXin Ji #define SP_TX_H_SYNC_STA_H 0x32 948bdfc5daSXin Ji #define SP_TX_H_B_PORCH_STA_L 0x33 958bdfc5daSXin Ji #define SP_TX_H_B_PORCH_STA_H 0x34 968bdfc5daSXin Ji 978bdfc5daSXin Ji #define SP_TX_VID_CTRL 0x84 988bdfc5daSXin Ji #define SP_TX_BPC_MASK 0xE0 998bdfc5daSXin Ji #define SP_TX_BPC_6 0x00 1008bdfc5daSXin Ji #define SP_TX_BPC_8 0x20 1018bdfc5daSXin Ji #define SP_TX_BPC_10 0x40 1028bdfc5daSXin Ji #define SP_TX_BPC_12 0x60 1038bdfc5daSXin Ji 1048bdfc5daSXin Ji #define VIDEO_BIT_MATRIX_12 0x4c 1058bdfc5daSXin Ji 1068bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_1 0xd0 1078bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_2 0xd1 1088bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_3 0xd2 1098bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_4 0xd3 1108bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_5 0xd4 1118bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_6 0xd5 1128bdfc5daSXin Ji #define TDM_SLAVE_MODE 0x10 1138bdfc5daSXin Ji #define I2S_SLAVE_MODE 0x08 114*566fef12SXin Ji #define AUDIO_LAYOUT 0x01 1158bdfc5daSXin Ji 1168bdfc5daSXin Ji #define AUDIO_CONTROL_REGISTER 0xe6 1178bdfc5daSXin Ji #define TDM_TIMING_MODE 0x08 1188bdfc5daSXin Ji 1198bdfc5daSXin Ji #define I2C_ADDR_72_DPTX 0x72 1208bdfc5daSXin Ji 1218bdfc5daSXin Ji #define HP_MIN 8 1228bdfc5daSXin Ji #define HBLANKING_MIN 80 1238bdfc5daSXin Ji #define SYNC_LEN_DEF 32 1248bdfc5daSXin Ji #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2) 1258bdfc5daSXin Ji #define VIDEO_CONTROL_0 0x08 1268bdfc5daSXin Ji 1278bdfc5daSXin Ji #define ACTIVE_LINES_L 0x14 1288bdfc5daSXin Ji #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */ 1298bdfc5daSXin Ji #define VERTICAL_FRONT_PORCH 0x16 1308bdfc5daSXin Ji #define VERTICAL_SYNC_WIDTH 0x17 1318bdfc5daSXin Ji #define VERTICAL_BACK_PORCH 0x18 1328bdfc5daSXin Ji 1338bdfc5daSXin Ji #define HORIZONTAL_TOTAL_PIXELS_L 0x19 1348bdfc5daSXin Ji #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */ 1358bdfc5daSXin Ji #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 1368bdfc5daSXin Ji #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */ 1378bdfc5daSXin Ji #define HORIZONTAL_FRONT_PORCH_L 0x1D 1388bdfc5daSXin Ji #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */ 1398bdfc5daSXin Ji #define HORIZONTAL_SYNC_WIDTH_L 0x1F 1408bdfc5daSXin Ji #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */ 1418bdfc5daSXin Ji #define HORIZONTAL_BACK_PORCH_L 0x21 1428bdfc5daSXin Ji #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */ 1438bdfc5daSXin Ji 1448bdfc5daSXin Ji /******** END of I2C Address 0x72 *********/ 145fd0310b6SXin Ji 146fd0310b6SXin Ji /***************************************************************/ 147fd0310b6SXin Ji /* Register definition of device address 0x7a */ 148fd0310b6SXin Ji #define DP_TX_SWING_REG_CNT 0x14 149fd0310b6SXin Ji #define DP_TX_LANE0_SWING_REG0 0x00 150fd0310b6SXin Ji #define DP_TX_LANE1_SWING_REG0 0x14 151fd0310b6SXin Ji /******** END of I2C Address 0x7a *********/ 152fd0310b6SXin Ji 1538bdfc5daSXin Ji /***************************************************************/ 1548bdfc5daSXin Ji /* Register definition of device address 0x7e */ 1558bdfc5daSXin Ji 1568bdfc5daSXin Ji #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 1578bdfc5daSXin Ji 1588bdfc5daSXin Ji #define FLASH_LOAD_STA 0x05 1598bdfc5daSXin Ji #define FLASH_LOAD_STA_CHK BIT(7) 1608bdfc5daSXin Ji 1618bdfc5daSXin Ji #define XTAL_FRQ_SEL 0x3F 1628bdfc5daSXin Ji /* bit field positions */ 1638bdfc5daSXin Ji #define XTAL_FRQ_SEL_POS 5 1648bdfc5daSXin Ji /* bit field values */ 1658bdfc5daSXin Ji #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 1668bdfc5daSXin Ji #define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 1678bdfc5daSXin Ji 1688bdfc5daSXin Ji #define R_DSC_CTRL_0 0x40 1698bdfc5daSXin Ji #define READ_STATUS_EN 7 1708bdfc5daSXin Ji #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 1718bdfc5daSXin Ji #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */ 1728bdfc5daSXin Ji #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 1738bdfc5daSXin Ji 1748bdfc5daSXin Ji #define OCM_FW_VERSION 0x31 1758bdfc5daSXin Ji #define OCM_FW_REVERSION 0x32 1768bdfc5daSXin Ji 1778bdfc5daSXin Ji #define AP_AUX_ADDR_7_0 0x11 1788bdfc5daSXin Ji #define AP_AUX_ADDR_15_8 0x12 1798bdfc5daSXin Ji #define AP_AUX_ADDR_19_16 0x13 1808bdfc5daSXin Ji 1818bdfc5daSXin Ji /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 1828bdfc5daSXin Ji #define AP_AUX_CTRL_STATUS 0x14 1838bdfc5daSXin Ji #define AP_AUX_CTRL_OP_EN 0x10 1848bdfc5daSXin Ji #define AP_AUX_CTRL_ADDRONLY 0x20 1858bdfc5daSXin Ji 1868bdfc5daSXin Ji #define AP_AUX_BUFF_START 0x15 1878bdfc5daSXin Ji #define PIXEL_CLOCK_L 0x25 1888bdfc5daSXin Ji #define PIXEL_CLOCK_H 0x26 1898bdfc5daSXin Ji 1908bdfc5daSXin Ji #define AP_AUX_COMMAND 0x27 /* com+len */ 1918bdfc5daSXin Ji /* Bit 0&1: 3D video structure */ 1928bdfc5daSXin Ji /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 1938bdfc5daSXin Ji #define AP_AV_STATUS 0x28 1948bdfc5daSXin Ji #define AP_VIDEO_CHG BIT(2) 1958bdfc5daSXin Ji #define AP_AUDIO_CHG BIT(3) 1968bdfc5daSXin Ji #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */ 1978bdfc5daSXin Ji #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */ 1988bdfc5daSXin Ji #define AP_DISABLE_PD BIT(6) 1998bdfc5daSXin Ji #define AP_DISABLE_DISPLAY BIT(7) 2008bdfc5daSXin Ji /***************************************************************/ 2018bdfc5daSXin Ji /* Register definition of device address 0x84 */ 2028bdfc5daSXin Ji #define MIPI_PHY_CONTROL_3 0x03 2038bdfc5daSXin Ji #define MIPI_HS_PWD_CLK 7 2048bdfc5daSXin Ji #define MIPI_HS_RT_CLK 6 2058bdfc5daSXin Ji #define MIPI_PD_CLK 5 2068bdfc5daSXin Ji #define MIPI_CLK_RT_MANUAL_PD_EN 4 2078bdfc5daSXin Ji #define MIPI_CLK_HS_MANUAL_PD_EN 3 2088bdfc5daSXin Ji #define MIPI_CLK_DET_DET_BYPASS 2 2098bdfc5daSXin Ji #define MIPI_CLK_MISS_CTRL 1 2108bdfc5daSXin Ji #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 2118bdfc5daSXin Ji 2128bdfc5daSXin Ji #define MIPI_LANE_CTRL_0 0x05 2138bdfc5daSXin Ji #define MIPI_TIME_HS_PRPR 0x08 2148bdfc5daSXin Ji 2158bdfc5daSXin Ji /* 2168bdfc5daSXin Ji * After MIPI RX protocol layer received video frames, 2178bdfc5daSXin Ji * Protocol layer starts to reconstruct video stream from PHY 2188bdfc5daSXin Ji */ 2198bdfc5daSXin Ji #define MIPI_VIDEO_STABLE_CNT 0x0A 2208bdfc5daSXin Ji 2218bdfc5daSXin Ji #define MIPI_LANE_CTRL_10 0x0F 2228bdfc5daSXin Ji #define MIPI_DIGITAL_ADJ_1 0x1B 2237d066dc7SXin Ji #define IVO_MID0 0x26 2247d066dc7SXin Ji #define IVO_MID1 0xCF 2258bdfc5daSXin Ji 2268bdfc5daSXin Ji #define MIPI_PLL_M_NUM_23_16 0x1E 2278bdfc5daSXin Ji #define MIPI_PLL_M_NUM_15_8 0x1F 2288bdfc5daSXin Ji #define MIPI_PLL_M_NUM_7_0 0x20 2298bdfc5daSXin Ji #define MIPI_PLL_N_NUM_23_16 0x21 2308bdfc5daSXin Ji #define MIPI_PLL_N_NUM_15_8 0x22 2318bdfc5daSXin Ji #define MIPI_PLL_N_NUM_7_0 0x23 2328bdfc5daSXin Ji 2338bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_6 0x2A 2348bdfc5daSXin Ji /* Bit[7:6]: VCO band control, only effective */ 2358bdfc5daSXin Ji #define MIPI_M_NUM_READY 0x10 2368bdfc5daSXin Ji #define MIPI_N_NUM_READY 0x08 2378bdfc5daSXin Ji #define STABLE_INTEGER_CNT_EN 0x04 2388bdfc5daSXin Ji #define MIPI_PLL_TEST_BIT 0 2398bdfc5daSXin Ji /* Bit[1:0]: test point output select - */ 2408bdfc5daSXin Ji /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 2418bdfc5daSXin Ji 2428bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_7 0x2B 2438bdfc5daSXin Ji #define MIPI_PLL_FORCE_N_EN 7 2448bdfc5daSXin Ji #define MIPI_PLL_FORCE_BAND_EN 6 2458bdfc5daSXin Ji 2468bdfc5daSXin Ji #define MIPI_PLL_VCO_TUNE_REG 4 2478bdfc5daSXin Ji /* Bit[5:4]: VCO metal capacitance - */ 2488bdfc5daSXin Ji /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 2498bdfc5daSXin Ji #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 2508bdfc5daSXin Ji 2518bdfc5daSXin Ji #define MIPI_PLL_PLL_LDO_BIT 2 2528bdfc5daSXin Ji /* Bit[3:2]: vco_v2i power - */ 2538bdfc5daSXin Ji /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 2548bdfc5daSXin Ji #define MIPI_PLL_RESET_N 0x02 2558bdfc5daSXin Ji #define MIPI_FRQ_FORCE_NDET 0 2568bdfc5daSXin Ji 2578bdfc5daSXin Ji #define MIPI_ALERT_CLR_0 0x2D 2588bdfc5daSXin Ji #define HS_link_error_clear 7 2598bdfc5daSXin Ji /* This bit itself is S/C, and it clears 0x84:0x31[7] */ 2608bdfc5daSXin Ji 2618bdfc5daSXin Ji #define MIPI_ALERT_OUT_0 0x31 2628bdfc5daSXin Ji #define check_sum_err_hs_sync 7 2638bdfc5daSXin Ji /* This bit is cleared by 0x84:0x2D[7] */ 2648bdfc5daSXin Ji 2658bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_8 0x33 2668bdfc5daSXin Ji #define MIPI_POST_DIV_VAL 4 2678bdfc5daSXin Ji /* N means divided by (n+1), n = 0~15 */ 2688bdfc5daSXin Ji #define MIPI_EN_LOCK_FRZ 3 2698bdfc5daSXin Ji #define MIPI_FRQ_COUNTER_RST 2 2708bdfc5daSXin Ji #define MIPI_FRQ_SET_REG_8 1 2718bdfc5daSXin Ji /* Bit 0 is reserved */ 2728bdfc5daSXin Ji 2738bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_9 0x34 2748bdfc5daSXin Ji 2758bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_16 0x3B 2768bdfc5daSXin Ji #define MIPI_FRQ_FREEZE_NDET 7 2778bdfc5daSXin Ji #define MIPI_FRQ_REG_SET_ENABLE 6 2788bdfc5daSXin Ji #define MIPI_REG_FORCE_SEL_EN 5 2798bdfc5daSXin Ji #define MIPI_REG_SEL_DIV_REG 4 2808bdfc5daSXin Ji #define MIPI_REG_FORCE_PRE_DIV_EN 3 2818bdfc5daSXin Ji /* Bit 2 is reserved */ 2828bdfc5daSXin Ji #define MIPI_FREF_D_IND 1 2838bdfc5daSXin Ji #define REF_CLK_27000KHZ 1 2848bdfc5daSXin Ji #define REF_CLK_19200KHZ 0 2858bdfc5daSXin Ji #define MIPI_REG_PLL_PLL_TEST_ENABLE 0 2868bdfc5daSXin Ji 2878bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_18 0x3D 2888bdfc5daSXin Ji #define FRQ_COUNT_RB_SEL 7 2898bdfc5daSXin Ji #define REG_FORCE_POST_DIV_EN 6 2908bdfc5daSXin Ji #define MIPI_DPI_SELECT 5 2918bdfc5daSXin Ji #define SELECT_DSI 1 2928bdfc5daSXin Ji #define SELECT_DPI 0 2938bdfc5daSXin Ji #define REG_BAUD_DIV_RATIO 0 2948bdfc5daSXin Ji 2958bdfc5daSXin Ji #define H_BLANK_L 0x3E 2968bdfc5daSXin Ji /* For DSC only */ 2978bdfc5daSXin Ji #define H_BLANK_H 0x3F 2988bdfc5daSXin Ji /* For DSC only; note: bit[7:6] are reserved */ 2998bdfc5daSXin Ji #define MIPI_SWAP 0x4A 3008bdfc5daSXin Ji #define MIPI_SWAP_CH0 7 3018bdfc5daSXin Ji #define MIPI_SWAP_CH1 6 3028bdfc5daSXin Ji #define MIPI_SWAP_CH2 5 3038bdfc5daSXin Ji #define MIPI_SWAP_CH3 4 3048bdfc5daSXin Ji #define MIPI_SWAP_CLK 3 3058bdfc5daSXin Ji /* Bit[2:0] are reserved */ 3068bdfc5daSXin Ji 3078bdfc5daSXin Ji /******** END of I2C Address 0x84 *********/ 3088bdfc5daSXin Ji 3098bdfc5daSXin Ji /* DPCD regs */ 3108bdfc5daSXin Ji #define DPCD_DPCD_REV 0x00 3118bdfc5daSXin Ji #define DPCD_MAX_LINK_RATE 0x01 3128bdfc5daSXin Ji #define DPCD_MAX_LANE_COUNT 0x02 3138bdfc5daSXin Ji 3148bdfc5daSXin Ji /********* ANX7625 Register End **********/ 3158bdfc5daSXin Ji 3168bdfc5daSXin Ji /***************** Display *****************/ 3178bdfc5daSXin Ji enum audio_fs { 3188bdfc5daSXin Ji AUDIO_FS_441K = 0x00, 3198bdfc5daSXin Ji AUDIO_FS_48K = 0x02, 3208bdfc5daSXin Ji AUDIO_FS_32K = 0x03, 3218bdfc5daSXin Ji AUDIO_FS_882K = 0x08, 3228bdfc5daSXin Ji AUDIO_FS_96K = 0x0a, 3238bdfc5daSXin Ji AUDIO_FS_1764K = 0x0c, 3248bdfc5daSXin Ji AUDIO_FS_192K = 0x0e 3258bdfc5daSXin Ji }; 3268bdfc5daSXin Ji 3278bdfc5daSXin Ji enum audio_wd_len { 3288bdfc5daSXin Ji AUDIO_W_LEN_16_20MAX = 0x02, 3298bdfc5daSXin Ji AUDIO_W_LEN_18_20MAX = 0x04, 3308bdfc5daSXin Ji AUDIO_W_LEN_17_20MAX = 0x0c, 3318bdfc5daSXin Ji AUDIO_W_LEN_19_20MAX = 0x08, 3328bdfc5daSXin Ji AUDIO_W_LEN_20_20MAX = 0x0a, 3338bdfc5daSXin Ji AUDIO_W_LEN_20_24MAX = 0x03, 3348bdfc5daSXin Ji AUDIO_W_LEN_22_24MAX = 0x05, 3358bdfc5daSXin Ji AUDIO_W_LEN_21_24MAX = 0x0d, 3368bdfc5daSXin Ji AUDIO_W_LEN_23_24MAX = 0x09, 3378bdfc5daSXin Ji AUDIO_W_LEN_24_24MAX = 0x0b 3388bdfc5daSXin Ji }; 3398bdfc5daSXin Ji 3408bdfc5daSXin Ji #define I2S_CH_2 0x01 3418bdfc5daSXin Ji #define TDM_CH_4 0x03 3428bdfc5daSXin Ji #define TDM_CH_6 0x05 3438bdfc5daSXin Ji #define TDM_CH_8 0x07 3448bdfc5daSXin Ji 3458bdfc5daSXin Ji #define MAX_DPCD_BUFFER_SIZE 16 3468bdfc5daSXin Ji 3478bdfc5daSXin Ji #define ONE_BLOCK_SIZE 128 3488bdfc5daSXin Ji #define FOUR_BLOCK_SIZE (128 * 4) 3498bdfc5daSXin Ji 3508bdfc5daSXin Ji #define MAX_EDID_BLOCK 3 3518bdfc5daSXin Ji #define EDID_TRY_CNT 3 3528bdfc5daSXin Ji #define SUPPORT_PIXEL_CLOCK 300000 3538bdfc5daSXin Ji 3548bdfc5daSXin Ji struct s_edid_data { 3558bdfc5daSXin Ji int edid_block_num; 3568bdfc5daSXin Ji u8 edid_raw_data[FOUR_BLOCK_SIZE]; 3578bdfc5daSXin Ji }; 3588bdfc5daSXin Ji 3598bdfc5daSXin Ji /***************** Display End *****************/ 3608bdfc5daSXin Ji 361fd0310b6SXin Ji #define MAX_LANES_SUPPORT 4 362fd0310b6SXin Ji 3638bdfc5daSXin Ji struct anx7625_platform_data { 3648bdfc5daSXin Ji struct gpio_desc *gpio_p_on; 3658bdfc5daSXin Ji struct gpio_desc *gpio_reset; 3666c744983SHsin-Yi Wang struct regulator_bulk_data supplies[3]; 3678bdfc5daSXin Ji struct drm_bridge *panel_bridge; 3688bdfc5daSXin Ji int intp_irq; 369fd0310b6SXin Ji int is_dpi; 370fd0310b6SXin Ji int mipi_lanes; 371*566fef12SXin Ji int audio_en; 372fd0310b6SXin Ji int dp_lane0_swing_reg_cnt; 373fd0310b6SXin Ji int lane0_reg_data[DP_TX_SWING_REG_CNT]; 374fd0310b6SXin Ji int dp_lane1_swing_reg_cnt; 375fd0310b6SXin Ji int lane1_reg_data[DP_TX_SWING_REG_CNT]; 3768bdfc5daSXin Ji u32 low_power_mode; 3778bdfc5daSXin Ji struct device_node *mipi_host_node; 3788bdfc5daSXin Ji }; 3798bdfc5daSXin Ji 3808bdfc5daSXin Ji struct anx7625_i2c_client { 3818bdfc5daSXin Ji struct i2c_client *tx_p0_client; 3828bdfc5daSXin Ji struct i2c_client *tx_p1_client; 3838bdfc5daSXin Ji struct i2c_client *tx_p2_client; 3848bdfc5daSXin Ji struct i2c_client *rx_p0_client; 3858bdfc5daSXin Ji struct i2c_client *rx_p1_client; 3868bdfc5daSXin Ji struct i2c_client *rx_p2_client; 3878bdfc5daSXin Ji struct i2c_client *tcpc_client; 3888bdfc5daSXin Ji }; 3898bdfc5daSXin Ji 3908bdfc5daSXin Ji struct anx7625_data { 3918bdfc5daSXin Ji struct anx7625_platform_data pdata; 392*566fef12SXin Ji struct platform_device *audio_pdev; 3938bdfc5daSXin Ji int hpd_status; 3948bdfc5daSXin Ji int hpd_high_cnt; 3958bdfc5daSXin Ji /* Lock for work queue */ 3968bdfc5daSXin Ji struct mutex lock; 3978bdfc5daSXin Ji struct i2c_client *client; 3988bdfc5daSXin Ji struct anx7625_i2c_client i2c; 3998bdfc5daSXin Ji struct i2c_client *last_client; 4008bdfc5daSXin Ji struct s_edid_data slimport_edid_p; 401*566fef12SXin Ji struct device *codec_dev; 402*566fef12SXin Ji hdmi_codec_plugged_cb plugged_cb; 4038bdfc5daSXin Ji struct work_struct work; 4048bdfc5daSXin Ji struct workqueue_struct *workqueue; 4058bdfc5daSXin Ji char edid_block; 4068bdfc5daSXin Ji struct display_timing dt; 4078bdfc5daSXin Ji u8 display_timing_valid; 4088bdfc5daSXin Ji struct drm_bridge bridge; 4098bdfc5daSXin Ji u8 bridge_attached; 4108bdfc5daSXin Ji struct mipi_dsi_device *dsi; 4118bdfc5daSXin Ji }; 4128bdfc5daSXin Ji 4138bdfc5daSXin Ji #endif /* __ANX7625_H__ */ 414