18bdfc5daSXin Ji /* SPDX-License-Identifier: GPL-2.0-only */ 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji 78bdfc5daSXin Ji #ifndef __ANX7625_H__ 88bdfc5daSXin Ji #define __ANX7625_H__ 98bdfc5daSXin Ji 108bdfc5daSXin Ji #define ANX7625_DRV_VERSION "0.1.04" 118bdfc5daSXin Ji 128bdfc5daSXin Ji /* Loading OCM re-trying times */ 138bdfc5daSXin Ji #define OCM_LOADING_TIME 10 148bdfc5daSXin Ji 158bdfc5daSXin Ji /********* ANX7625 Register **********/ 168bdfc5daSXin Ji #define TX_P0_ADDR 0x70 178bdfc5daSXin Ji #define TX_P1_ADDR 0x7A 188bdfc5daSXin Ji #define TX_P2_ADDR 0x72 198bdfc5daSXin Ji 208bdfc5daSXin Ji #define RX_P0_ADDR 0x7e 218bdfc5daSXin Ji #define RX_P1_ADDR 0x84 228bdfc5daSXin Ji #define RX_P2_ADDR 0x54 238bdfc5daSXin Ji 248bdfc5daSXin Ji #define RSVD_00_ADDR 0x00 258bdfc5daSXin Ji #define RSVD_D1_ADDR 0xD1 268bdfc5daSXin Ji #define RSVD_60_ADDR 0x60 278bdfc5daSXin Ji #define RSVD_39_ADDR 0x39 288bdfc5daSXin Ji #define RSVD_7F_ADDR 0x7F 298bdfc5daSXin Ji 308bdfc5daSXin Ji #define TCPC_INTERFACE_ADDR 0x58 318bdfc5daSXin Ji 328bdfc5daSXin Ji /* Clock frequency in Hz */ 338bdfc5daSXin Ji #define XTAL_FRQ (27 * 1000000) 348bdfc5daSXin Ji 358bdfc5daSXin Ji #define POST_DIVIDER_MIN 1 368bdfc5daSXin Ji #define POST_DIVIDER_MAX 16 378bdfc5daSXin Ji #define PLL_OUT_FREQ_MIN 520000000UL 388bdfc5daSXin Ji #define PLL_OUT_FREQ_MAX 730000000UL 398bdfc5daSXin Ji #define PLL_OUT_FREQ_ABS_MIN 300000000UL 408bdfc5daSXin Ji #define PLL_OUT_FREQ_ABS_MAX 800000000UL 418bdfc5daSXin Ji #define MAX_UNSIGNED_24BIT 16777215UL 428bdfc5daSXin Ji 438bdfc5daSXin Ji /***************************************************************/ 448bdfc5daSXin Ji /* Register definition of device address 0x58 */ 458bdfc5daSXin Ji 468bdfc5daSXin Ji #define PRODUCT_ID_L 0x02 478bdfc5daSXin Ji #define PRODUCT_ID_H 0x03 488bdfc5daSXin Ji 498bdfc5daSXin Ji #define INTR_ALERT_1 0xCC 508bdfc5daSXin Ji #define INTR_SOFTWARE_INT BIT(3) 518bdfc5daSXin Ji #define INTR_RECEIVED_MSG BIT(5) 528bdfc5daSXin Ji 538bdfc5daSXin Ji #define SYSTEM_STSTUS 0x45 548bdfc5daSXin Ji #define INTERFACE_CHANGE_INT 0x44 558bdfc5daSXin Ji #define HPD_STATUS_CHANGE 0x80 568bdfc5daSXin Ji #define HPD_STATUS 0x80 578bdfc5daSXin Ji 588bdfc5daSXin Ji /******** END of I2C Address 0x58 ********/ 598bdfc5daSXin Ji 608bdfc5daSXin Ji /***************************************************************/ 618bdfc5daSXin Ji /* Register definition of device address 0x70 */ 62cd1637c7SXin Ji #define TX_HDCP_CTRL0 0x01 63cd1637c7SXin Ji #define STORE_AN BIT(7) 64cd1637c7SXin Ji #define RX_REPEATER BIT(6) 65cd1637c7SXin Ji #define RE_AUTHEN BIT(5) 66cd1637c7SXin Ji #define SW_AUTH_OK BIT(4) 67cd1637c7SXin Ji #define HARD_AUTH_EN BIT(3) 68cd1637c7SXin Ji #define ENC_EN BIT(2) 69cd1637c7SXin Ji #define BKSV_SRM_PASS BIT(1) 70cd1637c7SXin Ji #define KSVLIST_VLD BIT(0) 71cd1637c7SXin Ji 72cd1637c7SXin Ji #define SP_TX_WAIT_R0_TIME 0x40 73cd1637c7SXin Ji #define SP_TX_WAIT_KSVR_TIME 0x42 74cd1637c7SXin Ji #define SP_TX_SYS_CTRL1_REG 0x80 75cd1637c7SXin Ji #define HDCP2TX_FW_EN BIT(4) 768bdfc5daSXin Ji 778bdfc5daSXin Ji #define SP_TX_LINK_BW_SET_REG 0xA0 788bdfc5daSXin Ji #define SP_TX_LANE_COUNT_SET_REG 0xA1 798bdfc5daSXin Ji 808bdfc5daSXin Ji #define M_VID_0 0xC0 818bdfc5daSXin Ji #define M_VID_1 0xC1 828bdfc5daSXin Ji #define M_VID_2 0xC2 838bdfc5daSXin Ji #define N_VID_0 0xC3 848bdfc5daSXin Ji #define N_VID_1 0xC4 858bdfc5daSXin Ji #define N_VID_2 0xC5 868bdfc5daSXin Ji 87cd1637c7SXin Ji #define KEY_START_ADDR 0x9000 88cd1637c7SXin Ji #define KEY_RESERVED 416 89cd1637c7SXin Ji 90cd1637c7SXin Ji #define HDCP14KEY_START_ADDR (KEY_START_ADDR + KEY_RESERVED) 91cd1637c7SXin Ji #define HDCP14KEY_SIZE 624 92cd1637c7SXin Ji 938bdfc5daSXin Ji /***************************************************************/ 948bdfc5daSXin Ji /* Register definition of device address 0x72 */ 958bdfc5daSXin Ji #define AUX_RST 0x04 968bdfc5daSXin Ji #define RST_CTRL2 0x07 978bdfc5daSXin Ji 988bdfc5daSXin Ji #define SP_TX_TOTAL_LINE_STA_L 0x24 998bdfc5daSXin Ji #define SP_TX_TOTAL_LINE_STA_H 0x25 1008bdfc5daSXin Ji #define SP_TX_ACT_LINE_STA_L 0x26 1018bdfc5daSXin Ji #define SP_TX_ACT_LINE_STA_H 0x27 1028bdfc5daSXin Ji #define SP_TX_V_F_PORCH_STA 0x28 1038bdfc5daSXin Ji #define SP_TX_V_SYNC_STA 0x29 1048bdfc5daSXin Ji #define SP_TX_V_B_PORCH_STA 0x2A 1058bdfc5daSXin Ji #define SP_TX_TOTAL_PIXEL_STA_L 0x2B 1068bdfc5daSXin Ji #define SP_TX_TOTAL_PIXEL_STA_H 0x2C 1078bdfc5daSXin Ji #define SP_TX_ACT_PIXEL_STA_L 0x2D 1088bdfc5daSXin Ji #define SP_TX_ACT_PIXEL_STA_H 0x2E 1098bdfc5daSXin Ji #define SP_TX_H_F_PORCH_STA_L 0x2F 1108bdfc5daSXin Ji #define SP_TX_H_F_PORCH_STA_H 0x30 1118bdfc5daSXin Ji #define SP_TX_H_SYNC_STA_L 0x31 1128bdfc5daSXin Ji #define SP_TX_H_SYNC_STA_H 0x32 1138bdfc5daSXin Ji #define SP_TX_H_B_PORCH_STA_L 0x33 1148bdfc5daSXin Ji #define SP_TX_H_B_PORCH_STA_H 0x34 1158bdfc5daSXin Ji 1168bdfc5daSXin Ji #define SP_TX_VID_CTRL 0x84 1178bdfc5daSXin Ji #define SP_TX_BPC_MASK 0xE0 1188bdfc5daSXin Ji #define SP_TX_BPC_6 0x00 1198bdfc5daSXin Ji #define SP_TX_BPC_8 0x20 1208bdfc5daSXin Ji #define SP_TX_BPC_10 0x40 1218bdfc5daSXin Ji #define SP_TX_BPC_12 0x60 1228bdfc5daSXin Ji 1238bdfc5daSXin Ji #define VIDEO_BIT_MATRIX_12 0x4c 1248bdfc5daSXin Ji 1258bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_1 0xd0 1268bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_2 0xd1 1278bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_3 0xd2 1288bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_4 0xd3 1298bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_5 0xd4 1308bdfc5daSXin Ji #define AUDIO_CHANNEL_STATUS_6 0xd5 1318bdfc5daSXin Ji #define TDM_SLAVE_MODE 0x10 1328bdfc5daSXin Ji #define I2S_SLAVE_MODE 0x08 133566fef12SXin Ji #define AUDIO_LAYOUT 0x01 1348bdfc5daSXin Ji 1358e3d857cSXin Ji #define HPD_DET_TIMER_BIT0_7 0xea 1368e3d857cSXin Ji #define HPD_DET_TIMER_BIT8_15 0xeb 1378e3d857cSXin Ji #define HPD_DET_TIMER_BIT16_23 0xec 1388e3d857cSXin Ji /* HPD debounce time 2ms for 27M clock */ 1398e3d857cSXin Ji #define HPD_TIME 54000 1408e3d857cSXin Ji 1418bdfc5daSXin Ji #define AUDIO_CONTROL_REGISTER 0xe6 1428bdfc5daSXin Ji #define TDM_TIMING_MODE 0x08 1438bdfc5daSXin Ji 1448bdfc5daSXin Ji #define I2C_ADDR_72_DPTX 0x72 1458bdfc5daSXin Ji 1468bdfc5daSXin Ji #define HP_MIN 8 1478bdfc5daSXin Ji #define HBLANKING_MIN 80 1488bdfc5daSXin Ji #define SYNC_LEN_DEF 32 1498bdfc5daSXin Ji #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2) 1508bdfc5daSXin Ji #define VIDEO_CONTROL_0 0x08 1518bdfc5daSXin Ji 1528bdfc5daSXin Ji #define ACTIVE_LINES_L 0x14 1538bdfc5daSXin Ji #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */ 1548bdfc5daSXin Ji #define VERTICAL_FRONT_PORCH 0x16 1558bdfc5daSXin Ji #define VERTICAL_SYNC_WIDTH 0x17 1568bdfc5daSXin Ji #define VERTICAL_BACK_PORCH 0x18 1578bdfc5daSXin Ji 1588bdfc5daSXin Ji #define HORIZONTAL_TOTAL_PIXELS_L 0x19 1598bdfc5daSXin Ji #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */ 1608bdfc5daSXin Ji #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 1618bdfc5daSXin Ji #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */ 1628bdfc5daSXin Ji #define HORIZONTAL_FRONT_PORCH_L 0x1D 1638bdfc5daSXin Ji #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */ 1648bdfc5daSXin Ji #define HORIZONTAL_SYNC_WIDTH_L 0x1F 1658bdfc5daSXin Ji #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */ 1668bdfc5daSXin Ji #define HORIZONTAL_BACK_PORCH_L 0x21 1678bdfc5daSXin Ji #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */ 1688bdfc5daSXin Ji 1698bdfc5daSXin Ji /******** END of I2C Address 0x72 *********/ 170fd0310b6SXin Ji 171fd0310b6SXin Ji /***************************************************************/ 172fd0310b6SXin Ji /* Register definition of device address 0x7a */ 173fd0310b6SXin Ji #define DP_TX_SWING_REG_CNT 0x14 174fd0310b6SXin Ji #define DP_TX_LANE0_SWING_REG0 0x00 175fd0310b6SXin Ji #define DP_TX_LANE1_SWING_REG0 0x14 176fd0310b6SXin Ji /******** END of I2C Address 0x7a *********/ 177fd0310b6SXin Ji 1788bdfc5daSXin Ji /***************************************************************/ 1798bdfc5daSXin Ji /* Register definition of device address 0x7e */ 1808bdfc5daSXin Ji 1818bdfc5daSXin Ji #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 1828bdfc5daSXin Ji 183cd1637c7SXin Ji #define R_BOOT_RETRY 0x00 184cd1637c7SXin Ji #define R_RAM_ADDR_H 0x01 185cd1637c7SXin Ji #define R_RAM_ADDR_L 0x02 186cd1637c7SXin Ji #define R_RAM_LEN_H 0x03 187cd1637c7SXin Ji #define R_RAM_LEN_L 0x04 1888bdfc5daSXin Ji #define FLASH_LOAD_STA 0x05 1898bdfc5daSXin Ji #define FLASH_LOAD_STA_CHK BIT(7) 1908bdfc5daSXin Ji 191cd1637c7SXin Ji #define R_RAM_CTRL 0x05 192cd1637c7SXin Ji /* bit positions */ 193cd1637c7SXin Ji #define FLASH_DONE BIT(7) 194cd1637c7SXin Ji #define BOOT_LOAD_DONE BIT(6) 195cd1637c7SXin Ji #define CRC_OK BIT(5) 196cd1637c7SXin Ji #define LOAD_DONE BIT(4) 197cd1637c7SXin Ji #define O_RW_DONE BIT(3) 198cd1637c7SXin Ji #define FUSE_BUSY BIT(2) 199cd1637c7SXin Ji #define DECRYPT_EN BIT(1) 200cd1637c7SXin Ji #define LOAD_START BIT(0) 201cd1637c7SXin Ji 202cd1637c7SXin Ji #define FLASH_ADDR_HIGH 0x0F 203cd1637c7SXin Ji #define FLASH_ADDR_LOW 0x10 204cd1637c7SXin Ji #define FLASH_LEN_HIGH 0x31 205cd1637c7SXin Ji #define FLASH_LEN_LOW 0x32 206cd1637c7SXin Ji #define R_FLASH_RW_CTRL 0x33 207cd1637c7SXin Ji /* bit positions */ 208cd1637c7SXin Ji #define READ_DELAY_SELECT BIT(7) 209cd1637c7SXin Ji #define GENERAL_INSTRUCTION_EN BIT(6) 210cd1637c7SXin Ji #define FLASH_ERASE_EN BIT(5) 211cd1637c7SXin Ji #define RDID_READ_EN BIT(4) 212cd1637c7SXin Ji #define REMS_READ_EN BIT(3) 213cd1637c7SXin Ji #define WRITE_STATUS_EN BIT(2) 214cd1637c7SXin Ji #define FLASH_READ BIT(1) 215cd1637c7SXin Ji #define FLASH_WRITE BIT(0) 216cd1637c7SXin Ji 217cd1637c7SXin Ji #define FLASH_BUF_BASE_ADDR 0x60 218cd1637c7SXin Ji #define FLASH_BUF_LEN 0x20 219cd1637c7SXin Ji 2208bdfc5daSXin Ji #define XTAL_FRQ_SEL 0x3F 2218bdfc5daSXin Ji /* bit field positions */ 2228bdfc5daSXin Ji #define XTAL_FRQ_SEL_POS 5 2238bdfc5daSXin Ji /* bit field values */ 2248bdfc5daSXin Ji #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 2258bdfc5daSXin Ji #define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 2268bdfc5daSXin Ji 2278bdfc5daSXin Ji #define R_DSC_CTRL_0 0x40 2288bdfc5daSXin Ji #define READ_STATUS_EN 7 2298bdfc5daSXin Ji #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 2308bdfc5daSXin Ji #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */ 2318bdfc5daSXin Ji #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 2328bdfc5daSXin Ji 2338bdfc5daSXin Ji #define OCM_FW_VERSION 0x31 2348bdfc5daSXin Ji #define OCM_FW_REVERSION 0x32 2358bdfc5daSXin Ji 2368bdfc5daSXin Ji #define AP_AUX_ADDR_7_0 0x11 2378bdfc5daSXin Ji #define AP_AUX_ADDR_15_8 0x12 2388bdfc5daSXin Ji #define AP_AUX_ADDR_19_16 0x13 2398bdfc5daSXin Ji 2408bdfc5daSXin Ji /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 2418bdfc5daSXin Ji #define AP_AUX_CTRL_STATUS 0x14 2428bdfc5daSXin Ji #define AP_AUX_CTRL_OP_EN 0x10 2438bdfc5daSXin Ji #define AP_AUX_CTRL_ADDRONLY 0x20 2448bdfc5daSXin Ji 2458bdfc5daSXin Ji #define AP_AUX_BUFF_START 0x15 2468bdfc5daSXin Ji #define PIXEL_CLOCK_L 0x25 2478bdfc5daSXin Ji #define PIXEL_CLOCK_H 0x26 2488bdfc5daSXin Ji 2498bdfc5daSXin Ji #define AP_AUX_COMMAND 0x27 /* com+len */ 250cd1637c7SXin Ji #define LENGTH_SHIFT 4 251cd1637c7SXin Ji #define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd)) 252cd1637c7SXin Ji 2538bdfc5daSXin Ji /* Bit 0&1: 3D video structure */ 2548bdfc5daSXin Ji /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 2558bdfc5daSXin Ji #define AP_AV_STATUS 0x28 2568bdfc5daSXin Ji #define AP_VIDEO_CHG BIT(2) 2578bdfc5daSXin Ji #define AP_AUDIO_CHG BIT(3) 2588bdfc5daSXin Ji #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */ 2598bdfc5daSXin Ji #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */ 2608bdfc5daSXin Ji #define AP_DISABLE_PD BIT(6) 2618bdfc5daSXin Ji #define AP_DISABLE_DISPLAY BIT(7) 262*1e0635bcSXin Ji 263*1e0635bcSXin Ji #define GPIO_CTRL_2 0x49 264*1e0635bcSXin Ji #define HPD_SOURCE BIT(6) 265*1e0635bcSXin Ji 2668bdfc5daSXin Ji /***************************************************************/ 2678bdfc5daSXin Ji /* Register definition of device address 0x84 */ 2688bdfc5daSXin Ji #define MIPI_PHY_CONTROL_3 0x03 2698bdfc5daSXin Ji #define MIPI_HS_PWD_CLK 7 2708bdfc5daSXin Ji #define MIPI_HS_RT_CLK 6 2718bdfc5daSXin Ji #define MIPI_PD_CLK 5 2728bdfc5daSXin Ji #define MIPI_CLK_RT_MANUAL_PD_EN 4 2738bdfc5daSXin Ji #define MIPI_CLK_HS_MANUAL_PD_EN 3 2748bdfc5daSXin Ji #define MIPI_CLK_DET_DET_BYPASS 2 2758bdfc5daSXin Ji #define MIPI_CLK_MISS_CTRL 1 2768bdfc5daSXin Ji #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 2778bdfc5daSXin Ji 2788bdfc5daSXin Ji #define MIPI_LANE_CTRL_0 0x05 2798bdfc5daSXin Ji #define MIPI_TIME_HS_PRPR 0x08 2808bdfc5daSXin Ji 2818bdfc5daSXin Ji /* 2828bdfc5daSXin Ji * After MIPI RX protocol layer received video frames, 2838bdfc5daSXin Ji * Protocol layer starts to reconstruct video stream from PHY 2848bdfc5daSXin Ji */ 2858bdfc5daSXin Ji #define MIPI_VIDEO_STABLE_CNT 0x0A 2868bdfc5daSXin Ji 2878bdfc5daSXin Ji #define MIPI_LANE_CTRL_10 0x0F 2888bdfc5daSXin Ji #define MIPI_DIGITAL_ADJ_1 0x1B 2897d066dc7SXin Ji #define IVO_MID0 0x26 2907d066dc7SXin Ji #define IVO_MID1 0xCF 2918bdfc5daSXin Ji 2928bdfc5daSXin Ji #define MIPI_PLL_M_NUM_23_16 0x1E 2938bdfc5daSXin Ji #define MIPI_PLL_M_NUM_15_8 0x1F 2948bdfc5daSXin Ji #define MIPI_PLL_M_NUM_7_0 0x20 2958bdfc5daSXin Ji #define MIPI_PLL_N_NUM_23_16 0x21 2968bdfc5daSXin Ji #define MIPI_PLL_N_NUM_15_8 0x22 2978bdfc5daSXin Ji #define MIPI_PLL_N_NUM_7_0 0x23 2988bdfc5daSXin Ji 2998bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_6 0x2A 3008bdfc5daSXin Ji /* Bit[7:6]: VCO band control, only effective */ 3018bdfc5daSXin Ji #define MIPI_M_NUM_READY 0x10 3028bdfc5daSXin Ji #define MIPI_N_NUM_READY 0x08 3038bdfc5daSXin Ji #define STABLE_INTEGER_CNT_EN 0x04 3048bdfc5daSXin Ji #define MIPI_PLL_TEST_BIT 0 3058bdfc5daSXin Ji /* Bit[1:0]: test point output select - */ 3068bdfc5daSXin Ji /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 3078bdfc5daSXin Ji 3088bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_7 0x2B 3098bdfc5daSXin Ji #define MIPI_PLL_FORCE_N_EN 7 3108bdfc5daSXin Ji #define MIPI_PLL_FORCE_BAND_EN 6 3118bdfc5daSXin Ji 3128bdfc5daSXin Ji #define MIPI_PLL_VCO_TUNE_REG 4 3138bdfc5daSXin Ji /* Bit[5:4]: VCO metal capacitance - */ 3148bdfc5daSXin Ji /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 3158bdfc5daSXin Ji #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 3168bdfc5daSXin Ji 3178bdfc5daSXin Ji #define MIPI_PLL_PLL_LDO_BIT 2 3188bdfc5daSXin Ji /* Bit[3:2]: vco_v2i power - */ 3198bdfc5daSXin Ji /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 3208bdfc5daSXin Ji #define MIPI_PLL_RESET_N 0x02 3218bdfc5daSXin Ji #define MIPI_FRQ_FORCE_NDET 0 3228bdfc5daSXin Ji 3238bdfc5daSXin Ji #define MIPI_ALERT_CLR_0 0x2D 3248bdfc5daSXin Ji #define HS_link_error_clear 7 3258bdfc5daSXin Ji /* This bit itself is S/C, and it clears 0x84:0x31[7] */ 3268bdfc5daSXin Ji 3278bdfc5daSXin Ji #define MIPI_ALERT_OUT_0 0x31 3288bdfc5daSXin Ji #define check_sum_err_hs_sync 7 3298bdfc5daSXin Ji /* This bit is cleared by 0x84:0x2D[7] */ 3308bdfc5daSXin Ji 3318bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_8 0x33 3328bdfc5daSXin Ji #define MIPI_POST_DIV_VAL 4 3338bdfc5daSXin Ji /* N means divided by (n+1), n = 0~15 */ 3348bdfc5daSXin Ji #define MIPI_EN_LOCK_FRZ 3 3358bdfc5daSXin Ji #define MIPI_FRQ_COUNTER_RST 2 3368bdfc5daSXin Ji #define MIPI_FRQ_SET_REG_8 1 3378bdfc5daSXin Ji /* Bit 0 is reserved */ 3388bdfc5daSXin Ji 3398bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_9 0x34 3408bdfc5daSXin Ji 3418bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_16 0x3B 3428bdfc5daSXin Ji #define MIPI_FRQ_FREEZE_NDET 7 3438bdfc5daSXin Ji #define MIPI_FRQ_REG_SET_ENABLE 6 3448bdfc5daSXin Ji #define MIPI_REG_FORCE_SEL_EN 5 3458bdfc5daSXin Ji #define MIPI_REG_SEL_DIV_REG 4 3468bdfc5daSXin Ji #define MIPI_REG_FORCE_PRE_DIV_EN 3 3478bdfc5daSXin Ji /* Bit 2 is reserved */ 3488bdfc5daSXin Ji #define MIPI_FREF_D_IND 1 3498bdfc5daSXin Ji #define REF_CLK_27000KHZ 1 3508bdfc5daSXin Ji #define REF_CLK_19200KHZ 0 3518bdfc5daSXin Ji #define MIPI_REG_PLL_PLL_TEST_ENABLE 0 3528bdfc5daSXin Ji 3538bdfc5daSXin Ji #define MIPI_DIGITAL_PLL_18 0x3D 3548bdfc5daSXin Ji #define FRQ_COUNT_RB_SEL 7 3558bdfc5daSXin Ji #define REG_FORCE_POST_DIV_EN 6 3568bdfc5daSXin Ji #define MIPI_DPI_SELECT 5 3578bdfc5daSXin Ji #define SELECT_DSI 1 3588bdfc5daSXin Ji #define SELECT_DPI 0 3598bdfc5daSXin Ji #define REG_BAUD_DIV_RATIO 0 3608bdfc5daSXin Ji 3618bdfc5daSXin Ji #define H_BLANK_L 0x3E 3628bdfc5daSXin Ji /* For DSC only */ 3638bdfc5daSXin Ji #define H_BLANK_H 0x3F 3648bdfc5daSXin Ji /* For DSC only; note: bit[7:6] are reserved */ 3658bdfc5daSXin Ji #define MIPI_SWAP 0x4A 3668bdfc5daSXin Ji #define MIPI_SWAP_CH0 7 3678bdfc5daSXin Ji #define MIPI_SWAP_CH1 6 3688bdfc5daSXin Ji #define MIPI_SWAP_CH2 5 3698bdfc5daSXin Ji #define MIPI_SWAP_CH3 4 3708bdfc5daSXin Ji #define MIPI_SWAP_CLK 3 3718bdfc5daSXin Ji /* Bit[2:0] are reserved */ 3728bdfc5daSXin Ji 3738bdfc5daSXin Ji /******** END of I2C Address 0x84 *********/ 3748bdfc5daSXin Ji 3758bdfc5daSXin Ji /* DPCD regs */ 3768bdfc5daSXin Ji #define DPCD_DPCD_REV 0x00 3778bdfc5daSXin Ji #define DPCD_MAX_LINK_RATE 0x01 3788bdfc5daSXin Ji #define DPCD_MAX_LANE_COUNT 0x02 3798bdfc5daSXin Ji 3808bdfc5daSXin Ji /********* ANX7625 Register End **********/ 3818bdfc5daSXin Ji 3828bdfc5daSXin Ji /***************** Display *****************/ 3838bdfc5daSXin Ji enum audio_fs { 3848bdfc5daSXin Ji AUDIO_FS_441K = 0x00, 3858bdfc5daSXin Ji AUDIO_FS_48K = 0x02, 3868bdfc5daSXin Ji AUDIO_FS_32K = 0x03, 3878bdfc5daSXin Ji AUDIO_FS_882K = 0x08, 3888bdfc5daSXin Ji AUDIO_FS_96K = 0x0a, 3898bdfc5daSXin Ji AUDIO_FS_1764K = 0x0c, 3908bdfc5daSXin Ji AUDIO_FS_192K = 0x0e 3918bdfc5daSXin Ji }; 3928bdfc5daSXin Ji 3938bdfc5daSXin Ji enum audio_wd_len { 3948bdfc5daSXin Ji AUDIO_W_LEN_16_20MAX = 0x02, 3958bdfc5daSXin Ji AUDIO_W_LEN_18_20MAX = 0x04, 3968bdfc5daSXin Ji AUDIO_W_LEN_17_20MAX = 0x0c, 3978bdfc5daSXin Ji AUDIO_W_LEN_19_20MAX = 0x08, 3988bdfc5daSXin Ji AUDIO_W_LEN_20_20MAX = 0x0a, 3998bdfc5daSXin Ji AUDIO_W_LEN_20_24MAX = 0x03, 4008bdfc5daSXin Ji AUDIO_W_LEN_22_24MAX = 0x05, 4018bdfc5daSXin Ji AUDIO_W_LEN_21_24MAX = 0x0d, 4028bdfc5daSXin Ji AUDIO_W_LEN_23_24MAX = 0x09, 4038bdfc5daSXin Ji AUDIO_W_LEN_24_24MAX = 0x0b 4048bdfc5daSXin Ji }; 4058bdfc5daSXin Ji 4068bdfc5daSXin Ji #define I2S_CH_2 0x01 4078bdfc5daSXin Ji #define TDM_CH_4 0x03 4088bdfc5daSXin Ji #define TDM_CH_6 0x05 4098bdfc5daSXin Ji #define TDM_CH_8 0x07 4108bdfc5daSXin Ji 4118bdfc5daSXin Ji #define MAX_DPCD_BUFFER_SIZE 16 4128bdfc5daSXin Ji 4138bdfc5daSXin Ji #define ONE_BLOCK_SIZE 128 4148bdfc5daSXin Ji #define FOUR_BLOCK_SIZE (128 * 4) 4158bdfc5daSXin Ji 4168bdfc5daSXin Ji #define MAX_EDID_BLOCK 3 4178bdfc5daSXin Ji #define EDID_TRY_CNT 3 4188bdfc5daSXin Ji #define SUPPORT_PIXEL_CLOCK 300000 4198bdfc5daSXin Ji 4208bdfc5daSXin Ji struct s_edid_data { 4218bdfc5daSXin Ji int edid_block_num; 4228bdfc5daSXin Ji u8 edid_raw_data[FOUR_BLOCK_SIZE]; 4238bdfc5daSXin Ji }; 4248bdfc5daSXin Ji 4258bdfc5daSXin Ji /***************** Display End *****************/ 4268bdfc5daSXin Ji 427fd0310b6SXin Ji #define MAX_LANES_SUPPORT 4 428fd0310b6SXin Ji 4298bdfc5daSXin Ji struct anx7625_platform_data { 4308bdfc5daSXin Ji struct gpio_desc *gpio_p_on; 4318bdfc5daSXin Ji struct gpio_desc *gpio_reset; 4326c744983SHsin-Yi Wang struct regulator_bulk_data supplies[3]; 4338bdfc5daSXin Ji struct drm_bridge *panel_bridge; 4348bdfc5daSXin Ji int intp_irq; 435fd0310b6SXin Ji int is_dpi; 436fd0310b6SXin Ji int mipi_lanes; 437566fef12SXin Ji int audio_en; 438fd0310b6SXin Ji int dp_lane0_swing_reg_cnt; 439fb8da7f3SNícolas F. R. A. Prado u8 lane0_reg_data[DP_TX_SWING_REG_CNT]; 440fd0310b6SXin Ji int dp_lane1_swing_reg_cnt; 441fb8da7f3SNícolas F. R. A. Prado u8 lane1_reg_data[DP_TX_SWING_REG_CNT]; 4428bdfc5daSXin Ji u32 low_power_mode; 4438bdfc5daSXin Ji struct device_node *mipi_host_node; 4448bdfc5daSXin Ji }; 4458bdfc5daSXin Ji 4468bdfc5daSXin Ji struct anx7625_i2c_client { 4478bdfc5daSXin Ji struct i2c_client *tx_p0_client; 4488bdfc5daSXin Ji struct i2c_client *tx_p1_client; 4498bdfc5daSXin Ji struct i2c_client *tx_p2_client; 4508bdfc5daSXin Ji struct i2c_client *rx_p0_client; 4518bdfc5daSXin Ji struct i2c_client *rx_p1_client; 4528bdfc5daSXin Ji struct i2c_client *rx_p2_client; 4538bdfc5daSXin Ji struct i2c_client *tcpc_client; 4548bdfc5daSXin Ji }; 4558bdfc5daSXin Ji 4568bdfc5daSXin Ji struct anx7625_data { 4578bdfc5daSXin Ji struct anx7625_platform_data pdata; 458566fef12SXin Ji struct platform_device *audio_pdev; 4598bdfc5daSXin Ji int hpd_status; 4608bdfc5daSXin Ji int hpd_high_cnt; 461cd1637c7SXin Ji int dp_en; 462cd1637c7SXin Ji int hdcp_cp; 4638bdfc5daSXin Ji /* Lock for work queue */ 4648bdfc5daSXin Ji struct mutex lock; 465d65feac2SPin-yen Lin struct device *dev; 4668bdfc5daSXin Ji struct anx7625_i2c_client i2c; 4678bdfc5daSXin Ji struct i2c_client *last_client; 468cd1637c7SXin Ji struct timer_list hdcp_timer; 4698bdfc5daSXin Ji struct s_edid_data slimport_edid_p; 470566fef12SXin Ji struct device *codec_dev; 471566fef12SXin Ji hdmi_codec_plugged_cb plugged_cb; 4728bdfc5daSXin Ji struct work_struct work; 4738bdfc5daSXin Ji struct workqueue_struct *workqueue; 474cd1637c7SXin Ji struct delayed_work hdcp_work; 475cd1637c7SXin Ji struct workqueue_struct *hdcp_workqueue; 476cd1637c7SXin Ji /* Lock for hdcp work queue */ 477cd1637c7SXin Ji struct mutex hdcp_wq_lock; 478ee4a2ef1SHsin-Yi Wang /* Lock for aux transfer and disable */ 479ee4a2ef1SHsin-Yi Wang struct mutex aux_lock; 4808bdfc5daSXin Ji char edid_block; 4818bdfc5daSXin Ji struct display_timing dt; 4828bdfc5daSXin Ji u8 display_timing_valid; 4838bdfc5daSXin Ji struct drm_bridge bridge; 4848bdfc5daSXin Ji u8 bridge_attached; 485191be002SXin Ji struct drm_connector *connector; 4868bdfc5daSXin Ji struct mipi_dsi_device *dsi; 487adca62ecSHsin-Yi Wang struct drm_dp_aux aux; 4888bdfc5daSXin Ji }; 4898bdfc5daSXin Ji 4908bdfc5daSXin Ji #endif /* __ANX7625_H__ */ 491