1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_dp_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_mipi_dsi.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_panel.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 35 #include <video/display_timing.h> 36 37 #include "anx7625.h" 38 39 /* 40 * There is a sync issue while access I2C register between AP(CPU) and 41 * internal firmware(OCM), to avoid the race condition, AP should access 42 * the reserved slave address before slave address occurs changes. 43 */ 44 static int i2c_access_workaround(struct anx7625_data *ctx, 45 struct i2c_client *client) 46 { 47 u8 offset; 48 struct device *dev = &client->dev; 49 int ret; 50 51 if (client == ctx->last_client) 52 return 0; 53 54 ctx->last_client = client; 55 56 if (client == ctx->i2c.tcpc_client) 57 offset = RSVD_00_ADDR; 58 else if (client == ctx->i2c.tx_p0_client) 59 offset = RSVD_D1_ADDR; 60 else if (client == ctx->i2c.tx_p1_client) 61 offset = RSVD_60_ADDR; 62 else if (client == ctx->i2c.rx_p0_client) 63 offset = RSVD_39_ADDR; 64 else if (client == ctx->i2c.rx_p1_client) 65 offset = RSVD_7F_ADDR; 66 else 67 offset = RSVD_00_ADDR; 68 69 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 70 if (ret < 0) 71 DRM_DEV_ERROR(dev, 72 "fail to access i2c id=%x\n:%x", 73 client->addr, offset); 74 75 return ret; 76 } 77 78 static int anx7625_reg_read(struct anx7625_data *ctx, 79 struct i2c_client *client, u8 reg_addr) 80 { 81 int ret; 82 struct device *dev = &client->dev; 83 84 i2c_access_workaround(ctx, client); 85 86 ret = i2c_smbus_read_byte_data(client, reg_addr); 87 if (ret < 0) 88 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 89 client->addr, reg_addr); 90 91 return ret; 92 } 93 94 static int anx7625_reg_block_read(struct anx7625_data *ctx, 95 struct i2c_client *client, 96 u8 reg_addr, u8 len, u8 *buf) 97 { 98 int ret; 99 struct device *dev = &client->dev; 100 101 i2c_access_workaround(ctx, client); 102 103 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 104 if (ret < 0) 105 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 106 client->addr, reg_addr); 107 108 return ret; 109 } 110 111 static int anx7625_reg_write(struct anx7625_data *ctx, 112 struct i2c_client *client, 113 u8 reg_addr, u8 reg_val) 114 { 115 int ret; 116 struct device *dev = &client->dev; 117 118 i2c_access_workaround(ctx, client); 119 120 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 121 122 if (ret < 0) 123 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 124 client->addr, reg_addr); 125 126 return ret; 127 } 128 129 static int anx7625_write_or(struct anx7625_data *ctx, 130 struct i2c_client *client, 131 u8 offset, u8 mask) 132 { 133 int val; 134 135 val = anx7625_reg_read(ctx, client, offset); 136 if (val < 0) 137 return val; 138 139 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 140 } 141 142 static int anx7625_write_and(struct anx7625_data *ctx, 143 struct i2c_client *client, 144 u8 offset, u8 mask) 145 { 146 int val; 147 148 val = anx7625_reg_read(ctx, client, offset); 149 if (val < 0) 150 return val; 151 152 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 153 } 154 155 static int anx7625_write_and_or(struct anx7625_data *ctx, 156 struct i2c_client *client, 157 u8 offset, u8 and_mask, u8 or_mask) 158 { 159 int val; 160 161 val = anx7625_reg_read(ctx, client, offset); 162 if (val < 0) 163 return val; 164 165 return anx7625_reg_write(ctx, client, 166 offset, (val & and_mask) | (or_mask)); 167 } 168 169 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 170 { 171 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 172 } 173 174 static int wait_aux_op_finish(struct anx7625_data *ctx) 175 { 176 struct device *dev = &ctx->client->dev; 177 int val; 178 int ret; 179 180 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 181 ctx, val, 182 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 183 2000, 184 2000 * 150); 185 if (ret) { 186 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 187 return -EIO; 188 } 189 190 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 191 AP_AUX_CTRL_STATUS); 192 if (val < 0 || (val & 0x0F)) { 193 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 194 val = -EIO; 195 } 196 197 return val; 198 } 199 200 static int anx7625_video_mute_control(struct anx7625_data *ctx, 201 u8 status) 202 { 203 int ret; 204 205 if (status) { 206 /* Set mute on flag */ 207 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 208 AP_AV_STATUS, AP_MIPI_MUTE); 209 /* Clear mipi RX en */ 210 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 211 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 212 } else { 213 /* Mute off flag */ 214 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 215 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 216 /* Set MIPI RX EN */ 217 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 218 AP_AV_STATUS, AP_MIPI_RX_EN); 219 } 220 221 return ret; 222 } 223 224 static int anx7625_config_audio_input(struct anx7625_data *ctx) 225 { 226 struct device *dev = &ctx->client->dev; 227 int ret; 228 229 /* Channel num */ 230 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 231 AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5); 232 233 /* FS */ 234 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 235 AUDIO_CHANNEL_STATUS_4, 236 0xf0, AUDIO_FS_48K); 237 /* Word length */ 238 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 239 AUDIO_CHANNEL_STATUS_5, 240 0xf0, AUDIO_W_LEN_24_24MAX); 241 /* I2S */ 242 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 243 AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE); 244 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 245 AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE); 246 /* Audio change flag */ 247 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 248 AP_AV_STATUS, AP_AUDIO_CHG); 249 250 if (ret < 0) 251 DRM_DEV_ERROR(dev, "fail to config audio.\n"); 252 253 return ret; 254 } 255 256 /* Reduction of fraction a/b */ 257 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 258 { 259 unsigned long gcd_num; 260 unsigned long tmp_a, tmp_b; 261 u32 i = 1; 262 263 gcd_num = gcd(*a, *b); 264 *a /= gcd_num; 265 *b /= gcd_num; 266 267 tmp_a = *a; 268 tmp_b = *b; 269 270 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 271 i++; 272 *a = tmp_a / i; 273 *b = tmp_b / i; 274 } 275 276 /* 277 * In the end, make a, b larger to have higher ODFC PLL 278 * output frequency accuracy 279 */ 280 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 281 *a <<= 1; 282 *b <<= 1; 283 } 284 285 *a >>= 1; 286 *b >>= 1; 287 } 288 289 static int anx7625_calculate_m_n(u32 pixelclock, 290 unsigned long *m, 291 unsigned long *n, 292 u8 *post_divider) 293 { 294 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 295 /* Pixel clock frequency is too high */ 296 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 297 pixelclock, 298 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 299 return -EINVAL; 300 } 301 302 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 303 /* Pixel clock frequency is too low */ 304 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 305 pixelclock, 306 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 307 return -EINVAL; 308 } 309 310 for (*post_divider = 1; 311 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 312 *post_divider += 1; 313 314 if (*post_divider > POST_DIVIDER_MAX) { 315 for (*post_divider = 1; 316 (pixelclock < 317 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 318 *post_divider += 1; 319 320 if (*post_divider > POST_DIVIDER_MAX) { 321 DRM_ERROR("cannot find property post_divider(%d)\n", 322 *post_divider); 323 return -EDOM; 324 } 325 } 326 327 /* Patch to improve the accuracy */ 328 if (*post_divider == 7) { 329 /* 27,000,000 is not divisible by 7 */ 330 *post_divider = 8; 331 } else if (*post_divider == 11) { 332 /* 27,000,000 is not divisible by 11 */ 333 *post_divider = 12; 334 } else if ((*post_divider == 13) || (*post_divider == 14)) { 335 /* 27,000,000 is not divisible by 13 or 14 */ 336 *post_divider = 15; 337 } 338 339 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 340 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 341 pixelclock * (*post_divider), 342 PLL_OUT_FREQ_ABS_MAX); 343 return -EDOM; 344 } 345 346 *m = pixelclock; 347 *n = XTAL_FRQ / (*post_divider); 348 349 anx7625_reduction_of_a_fraction(m, n); 350 351 return 0; 352 } 353 354 static int anx7625_odfc_config(struct anx7625_data *ctx, 355 u8 post_divider) 356 { 357 int ret; 358 struct device *dev = &ctx->client->dev; 359 360 /* Config input reference clock frequency 27MHz/19.2MHz */ 361 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 362 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 363 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 364 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 365 /* Post divider */ 366 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 367 MIPI_DIGITAL_PLL_8, 0x0f); 368 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 369 post_divider << 4); 370 371 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 372 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 373 ~MIPI_PLL_VCO_TUNE_REG_VAL); 374 375 /* Reset ODFC PLL */ 376 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 377 ~MIPI_PLL_RESET_N); 378 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 379 MIPI_PLL_RESET_N); 380 381 if (ret < 0) 382 DRM_DEV_ERROR(dev, "IO error.\n"); 383 384 return ret; 385 } 386 387 /* 388 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 389 * anx7625 defined K ratio for matching MIPI input video clock and 390 * DP output video clock. Increase K value can match bigger video data 391 * variation. IVO panel has small variation than DP CTS spec, need 392 * decrease the K value. 393 */ 394 static int anx7625_set_k_value(struct anx7625_data *ctx) 395 { 396 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 397 398 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 399 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 400 MIPI_DIGITAL_ADJ_1, 0x3B); 401 402 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 403 MIPI_DIGITAL_ADJ_1, 0x3D); 404 } 405 406 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 407 { 408 struct device *dev = &ctx->client->dev; 409 unsigned long m, n; 410 u16 htotal; 411 int ret; 412 u8 post_divider = 0; 413 414 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 415 &m, &n, &post_divider); 416 417 if (ret) { 418 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 419 return ret; 420 } 421 422 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 423 m, n, post_divider); 424 425 /* Configure pixel clock */ 426 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 427 (ctx->dt.pixelclock.min / 1000) & 0xFF); 428 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 429 (ctx->dt.pixelclock.min / 1000) >> 8); 430 /* Lane count */ 431 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 432 MIPI_LANE_CTRL_0, 0xfc); 433 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 434 MIPI_LANE_CTRL_0, 3); 435 436 /* Htotal */ 437 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 438 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 439 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 440 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 441 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 442 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 443 /* Hactive */ 444 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 445 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 446 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 447 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 448 /* HFP */ 449 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 450 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 451 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 452 HORIZONTAL_FRONT_PORCH_H, 453 ctx->dt.hfront_porch.min >> 8); 454 /* HWS */ 455 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 456 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 457 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 458 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 459 /* HBP */ 460 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 461 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 462 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 463 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 464 /* Vactive */ 465 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 466 ctx->dt.vactive.min); 467 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 468 ctx->dt.vactive.min >> 8); 469 /* VFP */ 470 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 471 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 472 /* VWS */ 473 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 474 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 475 /* VBP */ 476 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 477 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 478 /* M value */ 479 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 480 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 481 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 482 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 483 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 484 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 485 /* N value */ 486 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 487 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 488 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 489 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 490 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 491 (n & 0xff)); 492 493 anx7625_set_k_value(ctx); 494 495 ret |= anx7625_odfc_config(ctx, post_divider - 1); 496 497 if (ret < 0) 498 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 499 500 return ret; 501 } 502 503 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 504 { 505 int val; 506 struct device *dev = &ctx->client->dev; 507 508 /* Swap MIPI-DSI data lane 3 P and N */ 509 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 510 if (val < 0) { 511 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 512 return -EIO; 513 } 514 515 val |= (1 << MIPI_SWAP_CH3); 516 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 517 } 518 519 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 520 521 { 522 int val, ret; 523 struct device *dev = &ctx->client->dev; 524 525 /* Swap MIPI-DSI data lane 3 P and N */ 526 ret = anx7625_swap_dsi_lane3(ctx); 527 if (ret < 0) { 528 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 529 return ret; 530 } 531 532 /* DSI clock settings */ 533 val = (0 << MIPI_HS_PWD_CLK) | 534 (0 << MIPI_HS_RT_CLK) | 535 (0 << MIPI_PD_CLK) | 536 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 537 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 538 (0 << MIPI_CLK_DET_DET_BYPASS) | 539 (0 << MIPI_CLK_MISS_CTRL) | 540 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 541 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 542 MIPI_PHY_CONTROL_3, val); 543 544 /* 545 * Decreased HS prepare timing delay from 160ns to 80ns work with 546 * a) Dragon board 810 series (Qualcomm AP) 547 * b) Moving Pixel DSI source (PG3A pattern generator + 548 * P332 D-PHY Probe) default D-PHY timing 549 * 5ns/step 550 */ 551 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 552 MIPI_TIME_HS_PRPR, 0x10); 553 554 /* Enable DSI mode*/ 555 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 556 SELECT_DSI << MIPI_DPI_SELECT); 557 558 ret |= anx7625_dsi_video_timing_config(ctx); 559 if (ret < 0) { 560 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 561 return ret; 562 } 563 564 /* Toggle m, n ready */ 565 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 566 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 567 usleep_range(1000, 1100); 568 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 569 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 570 571 /* Configure integer stable register */ 572 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 573 MIPI_VIDEO_STABLE_CNT, 0x02); 574 /* Power on MIPI RX */ 575 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 576 MIPI_LANE_CTRL_10, 0x00); 577 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 578 MIPI_LANE_CTRL_10, 0x80); 579 580 if (ret < 0) 581 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 582 583 return ret; 584 } 585 586 static int anx7625_dsi_config(struct anx7625_data *ctx) 587 { 588 struct device *dev = &ctx->client->dev; 589 int ret; 590 591 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 592 593 /* DSC disable */ 594 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 595 R_DSC_CTRL_0, ~DSC_EN); 596 597 ret |= anx7625_api_dsi_config(ctx); 598 599 if (ret < 0) { 600 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 601 return ret; 602 } 603 604 /* Set MIPI RX EN */ 605 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 606 AP_AV_STATUS, AP_MIPI_RX_EN); 607 /* Clear mute flag */ 608 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 609 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 610 if (ret < 0) 611 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 612 else 613 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 614 615 return ret; 616 } 617 618 static void anx7625_dp_start(struct anx7625_data *ctx) 619 { 620 int ret; 621 struct device *dev = &ctx->client->dev; 622 623 if (!ctx->display_timing_valid) { 624 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 625 return; 626 } 627 628 anx7625_config_audio_input(ctx); 629 630 ret = anx7625_dsi_config(ctx); 631 632 if (ret < 0) 633 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 634 } 635 636 static void anx7625_dp_stop(struct anx7625_data *ctx) 637 { 638 struct device *dev = &ctx->client->dev; 639 int ret; 640 641 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 642 643 /* 644 * Video disable: 0x72:08 bit 7 = 0; 645 * Audio disable: 0x70:87 bit 0 = 0; 646 */ 647 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 648 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 649 650 ret |= anx7625_video_mute_control(ctx, 1); 651 if (ret < 0) 652 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 653 } 654 655 static int sp_tx_rst_aux(struct anx7625_data *ctx) 656 { 657 int ret; 658 659 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 660 AUX_RST); 661 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 662 ~AUX_RST); 663 return ret; 664 } 665 666 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 667 { 668 int ret; 669 670 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 671 AP_AUX_BUFF_START, offset); 672 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 673 AP_AUX_COMMAND, 0x04); 674 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 675 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 676 return (ret | wait_aux_op_finish(ctx)); 677 } 678 679 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 680 { 681 int ret; 682 683 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 684 AP_AUX_COMMAND, len_cmd); 685 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 686 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 687 return (ret | wait_aux_op_finish(ctx)); 688 } 689 690 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 691 { 692 int c = 0; 693 struct device *dev = &ctx->client->dev; 694 695 sp_tx_aux_wr(ctx, 0x7e); 696 sp_tx_aux_rd(ctx, 0x01); 697 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 698 if (c < 0) { 699 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 700 return -EIO; 701 } 702 703 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 704 705 if (c > MAX_EDID_BLOCK) 706 c = 1; 707 708 return c; 709 } 710 711 static int edid_read(struct anx7625_data *ctx, 712 u8 offset, u8 *pblock_buf) 713 { 714 int ret, cnt; 715 struct device *dev = &ctx->client->dev; 716 717 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 718 sp_tx_aux_wr(ctx, offset); 719 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 720 ret = sp_tx_aux_rd(ctx, 0xf1); 721 722 if (ret) { 723 sp_tx_rst_aux(ctx); 724 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 725 } else { 726 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 727 AP_AUX_BUFF_START, 728 MAX_DPCD_BUFFER_SIZE, 729 pblock_buf); 730 if (ret > 0) 731 break; 732 } 733 } 734 735 if (cnt > EDID_TRY_CNT) 736 return -EIO; 737 738 return 0; 739 } 740 741 static int segments_edid_read(struct anx7625_data *ctx, 742 u8 segment, u8 *buf, u8 offset) 743 { 744 u8 cnt; 745 int ret; 746 struct device *dev = &ctx->client->dev; 747 748 /* Write address only */ 749 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 750 AP_AUX_ADDR_7_0, 0x30); 751 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 752 AP_AUX_COMMAND, 0x04); 753 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 754 AP_AUX_CTRL_STATUS, 755 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 756 757 ret |= wait_aux_op_finish(ctx); 758 /* Write segment address */ 759 ret |= sp_tx_aux_wr(ctx, segment); 760 /* Data read */ 761 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 762 AP_AUX_ADDR_7_0, 0x50); 763 if (ret) { 764 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 765 return ret; 766 } 767 768 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 769 sp_tx_aux_wr(ctx, offset); 770 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 771 ret = sp_tx_aux_rd(ctx, 0xf1); 772 773 if (ret) { 774 ret = sp_tx_rst_aux(ctx); 775 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 776 } else { 777 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 778 AP_AUX_BUFF_START, 779 MAX_DPCD_BUFFER_SIZE, buf); 780 if (ret > 0) 781 break; 782 } 783 } 784 785 if (cnt > EDID_TRY_CNT) 786 return -EIO; 787 788 return 0; 789 } 790 791 static int sp_tx_edid_read(struct anx7625_data *ctx, 792 u8 *pedid_blocks_buf) 793 { 794 u8 offset, edid_pos; 795 int count, blocks_num; 796 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 797 u8 i, j; 798 u8 g_edid_break = 0; 799 int ret; 800 struct device *dev = &ctx->client->dev; 801 802 /* Address initial */ 803 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 804 AP_AUX_ADDR_7_0, 0x50); 805 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 806 AP_AUX_ADDR_15_8, 0); 807 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 808 AP_AUX_ADDR_19_16, 0xf0); 809 if (ret < 0) { 810 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 811 return -EIO; 812 } 813 814 blocks_num = sp_tx_get_edid_block(ctx); 815 if (blocks_num < 0) 816 return blocks_num; 817 818 count = 0; 819 820 do { 821 switch (count) { 822 case 0: 823 case 1: 824 for (i = 0; i < 8; i++) { 825 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 826 g_edid_break = edid_read(ctx, offset, 827 pblock_buf); 828 829 if (g_edid_break) 830 break; 831 832 memcpy(&pedid_blocks_buf[offset], 833 pblock_buf, 834 MAX_DPCD_BUFFER_SIZE); 835 } 836 837 break; 838 case 2: 839 offset = 0x00; 840 841 for (j = 0; j < 8; j++) { 842 edid_pos = (j + count * 8) * 843 MAX_DPCD_BUFFER_SIZE; 844 845 if (g_edid_break == 1) 846 break; 847 848 segments_edid_read(ctx, count / 2, 849 pblock_buf, offset); 850 memcpy(&pedid_blocks_buf[edid_pos], 851 pblock_buf, 852 MAX_DPCD_BUFFER_SIZE); 853 offset = offset + 0x10; 854 } 855 856 break; 857 case 3: 858 offset = 0x80; 859 860 for (j = 0; j < 8; j++) { 861 edid_pos = (j + count * 8) * 862 MAX_DPCD_BUFFER_SIZE; 863 if (g_edid_break == 1) 864 break; 865 866 segments_edid_read(ctx, count / 2, 867 pblock_buf, offset); 868 memcpy(&pedid_blocks_buf[edid_pos], 869 pblock_buf, 870 MAX_DPCD_BUFFER_SIZE); 871 offset = offset + 0x10; 872 } 873 874 break; 875 default: 876 break; 877 } 878 879 count++; 880 881 } while (blocks_num >= count); 882 883 /* Check edid data */ 884 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 885 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 886 return -EINVAL; 887 } 888 889 /* Reset aux channel */ 890 sp_tx_rst_aux(ctx); 891 892 return (blocks_num + 1); 893 } 894 895 static void anx7625_power_on(struct anx7625_data *ctx) 896 { 897 struct device *dev = &ctx->client->dev; 898 int ret, i; 899 900 if (!ctx->pdata.low_power_mode) { 901 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 902 return; 903 } 904 905 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 906 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 907 if (ret < 0) { 908 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 909 i, ret); 910 goto reg_err; 911 } 912 usleep_range(2000, 2100); 913 } 914 915 usleep_range(11000, 12000); 916 917 /* Power on pin enable */ 918 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 919 usleep_range(10000, 11000); 920 /* Power reset pin enable */ 921 gpiod_set_value(ctx->pdata.gpio_reset, 1); 922 usleep_range(10000, 11000); 923 924 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 925 return; 926 reg_err: 927 for (--i; i >= 0; i--) 928 regulator_disable(ctx->pdata.supplies[i].consumer); 929 } 930 931 static void anx7625_power_standby(struct anx7625_data *ctx) 932 { 933 struct device *dev = &ctx->client->dev; 934 int ret; 935 936 if (!ctx->pdata.low_power_mode) { 937 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 938 return; 939 } 940 941 gpiod_set_value(ctx->pdata.gpio_reset, 0); 942 usleep_range(1000, 1100); 943 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 944 usleep_range(1000, 1100); 945 946 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 947 ctx->pdata.supplies); 948 if (ret < 0) 949 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 950 951 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 952 } 953 954 /* Basic configurations of ANX7625 */ 955 static void anx7625_config(struct anx7625_data *ctx) 956 { 957 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 958 XTAL_FRQ_SEL, XTAL_FRQ_27M); 959 } 960 961 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 962 { 963 struct device *dev = &ctx->client->dev; 964 int ret; 965 966 /* Reset main ocm */ 967 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 968 /* Disable PD */ 969 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 970 AP_AV_STATUS, AP_DISABLE_PD); 971 /* Release main ocm */ 972 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 973 974 if (ret < 0) 975 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 976 else 977 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 978 } 979 980 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 981 { 982 int ret; 983 struct device *dev = &ctx->client->dev; 984 985 /* Check interface workable */ 986 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 987 FLASH_LOAD_STA); 988 if (ret < 0) { 989 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 990 return ret; 991 } 992 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 993 return -ENODEV; 994 995 anx7625_disable_pd_protocol(ctx); 996 997 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 998 anx7625_reg_read(ctx, 999 ctx->i2c.rx_p0_client, 1000 OCM_FW_VERSION), 1001 anx7625_reg_read(ctx, 1002 ctx->i2c.rx_p0_client, 1003 OCM_FW_REVERSION)); 1004 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1005 ANX7625_DRV_VERSION); 1006 1007 return 0; 1008 } 1009 1010 static void anx7625_power_on_init(struct anx7625_data *ctx) 1011 { 1012 int retry_count, i; 1013 1014 for (retry_count = 0; retry_count < 3; retry_count++) { 1015 anx7625_power_on(ctx); 1016 anx7625_config(ctx); 1017 1018 for (i = 0; i < OCM_LOADING_TIME; i++) { 1019 if (!anx7625_ocm_loading_check(ctx)) 1020 return; 1021 usleep_range(1000, 1100); 1022 } 1023 anx7625_power_standby(ctx); 1024 } 1025 } 1026 1027 static void anx7625_init_gpio(struct anx7625_data *platform) 1028 { 1029 struct device *dev = &platform->client->dev; 1030 1031 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1032 1033 /* Gpio for chip power enable */ 1034 platform->pdata.gpio_p_on = 1035 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1036 /* Gpio for chip reset */ 1037 platform->pdata.gpio_reset = 1038 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1039 1040 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1041 platform->pdata.low_power_mode = 1; 1042 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1043 desc_to_gpio(platform->pdata.gpio_p_on), 1044 desc_to_gpio(platform->pdata.gpio_reset)); 1045 } else { 1046 platform->pdata.low_power_mode = 0; 1047 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1048 } 1049 } 1050 1051 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1052 { 1053 ctx->hpd_status = 0; 1054 ctx->hpd_high_cnt = 0; 1055 ctx->display_timing_valid = 0; 1056 } 1057 1058 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1059 { 1060 int ret; 1061 struct device *dev = &ctx->client->dev; 1062 1063 if (ctx->hpd_high_cnt >= 2) { 1064 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1065 return; 1066 } 1067 1068 ctx->hpd_high_cnt++; 1069 1070 /* Not support HDCP */ 1071 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1072 1073 /* Try auth flag */ 1074 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1075 /* Interrupt for DRM */ 1076 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1077 if (ret < 0) 1078 return; 1079 1080 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1081 if (ret < 0) 1082 return; 1083 1084 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1085 } 1086 1087 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1088 { 1089 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1090 } 1091 1092 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1093 { 1094 int ret, val; 1095 struct device *dev = &ctx->client->dev; 1096 1097 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1098 ctx, val, 1099 ((val & HPD_STATUS) || (val < 0)), 1100 5000, 1101 5000 * 100); 1102 if (ret) { 1103 DRM_DEV_ERROR(dev, "no hpd.\n"); 1104 return; 1105 } 1106 1107 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1108 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1109 INTR_ALERT_1, 0xFF); 1110 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1111 INTERFACE_CHANGE_INT, 0); 1112 1113 anx7625_start_dp_work(ctx); 1114 1115 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1116 drm_helper_hpd_irq_event(ctx->bridge.dev); 1117 } 1118 1119 static void anx7625_remove_edid(struct anx7625_data *ctx) 1120 { 1121 ctx->slimport_edid_p.edid_block_num = -1; 1122 } 1123 1124 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1125 { 1126 struct device *dev = &ctx->client->dev; 1127 1128 /* HPD changed */ 1129 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1130 (u32)on); 1131 1132 if (on == 0) { 1133 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1134 anx7625_remove_edid(ctx); 1135 anx7625_stop_dp_work(ctx); 1136 } else { 1137 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1138 anx7625_start_dp_work(ctx); 1139 } 1140 1141 ctx->hpd_status = 1; 1142 } 1143 1144 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1145 { 1146 int intr_vector, status; 1147 struct device *dev = &ctx->client->dev; 1148 1149 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1150 INTR_ALERT_1, 0xFF); 1151 if (status < 0) { 1152 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1153 return status; 1154 } 1155 1156 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1157 INTERFACE_CHANGE_INT); 1158 if (intr_vector < 0) { 1159 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1160 return intr_vector; 1161 } 1162 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1163 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1164 INTERFACE_CHANGE_INT, 1165 intr_vector & (~intr_vector)); 1166 if (status < 0) { 1167 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1168 return status; 1169 } 1170 1171 if (!(intr_vector & HPD_STATUS_CHANGE)) 1172 return -ENOENT; 1173 1174 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1175 SYSTEM_STSTUS); 1176 if (status < 0) { 1177 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1178 return status; 1179 } 1180 1181 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1182 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1183 1184 return 0; 1185 } 1186 1187 static void anx7625_work_func(struct work_struct *work) 1188 { 1189 int event; 1190 struct anx7625_data *ctx = container_of(work, 1191 struct anx7625_data, work); 1192 1193 mutex_lock(&ctx->lock); 1194 1195 if (pm_runtime_suspended(&ctx->client->dev)) 1196 goto unlock; 1197 1198 event = anx7625_hpd_change_detect(ctx); 1199 if (event < 0) 1200 goto unlock; 1201 1202 if (ctx->bridge_attached) 1203 drm_helper_hpd_irq_event(ctx->bridge.dev); 1204 1205 unlock: 1206 mutex_unlock(&ctx->lock); 1207 } 1208 1209 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1210 { 1211 struct anx7625_data *ctx = (struct anx7625_data *)data; 1212 1213 queue_work(ctx->workqueue, &ctx->work); 1214 1215 return IRQ_HANDLED; 1216 } 1217 1218 static int anx7625_parse_dt(struct device *dev, 1219 struct anx7625_platform_data *pdata) 1220 { 1221 struct device_node *np = dev->of_node; 1222 struct drm_panel *panel; 1223 int ret; 1224 1225 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1226 if (!pdata->mipi_host_node) { 1227 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1228 return -ENODEV; 1229 } 1230 1231 DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n"); 1232 1233 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1234 if (ret < 0) { 1235 if (ret == -ENODEV) 1236 return 0; 1237 return ret; 1238 } 1239 if (!panel) 1240 return -ENODEV; 1241 1242 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1243 if (IS_ERR(pdata->panel_bridge)) 1244 return PTR_ERR(pdata->panel_bridge); 1245 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1246 1247 return 0; 1248 } 1249 1250 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1251 { 1252 return container_of(bridge, struct anx7625_data, bridge); 1253 } 1254 1255 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1256 { 1257 struct device *dev = &ctx->client->dev; 1258 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1259 int edid_num; 1260 u8 *edid; 1261 1262 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1263 if (!edid) { 1264 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1265 return NULL; 1266 } 1267 1268 if (ctx->slimport_edid_p.edid_block_num > 0) { 1269 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1270 FOUR_BLOCK_SIZE); 1271 return (struct edid *)edid; 1272 } 1273 1274 pm_runtime_get_sync(dev); 1275 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1276 pm_runtime_put_sync(dev); 1277 1278 if (edid_num < 1) { 1279 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1280 kfree(edid); 1281 return NULL; 1282 } 1283 1284 p_edid->edid_block_num = edid_num; 1285 1286 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1287 return (struct edid *)edid; 1288 } 1289 1290 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1291 { 1292 struct device *dev = &ctx->client->dev; 1293 1294 DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n"); 1295 1296 return connector_status_connected; 1297 } 1298 1299 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1300 { 1301 struct mipi_dsi_device *dsi; 1302 struct device *dev = &ctx->client->dev; 1303 struct mipi_dsi_host *host; 1304 const struct mipi_dsi_device_info info = { 1305 .type = "anx7625", 1306 .channel = 0, 1307 .node = NULL, 1308 }; 1309 1310 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1311 1312 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1313 if (!host) { 1314 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1315 return -EINVAL; 1316 } 1317 1318 dsi = mipi_dsi_device_register_full(host, &info); 1319 if (IS_ERR(dsi)) { 1320 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 1321 return -EINVAL; 1322 } 1323 1324 dsi->lanes = 4; 1325 dsi->format = MIPI_DSI_FMT_RGB888; 1326 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1327 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1328 MIPI_DSI_MODE_NO_EOT_PACKET | 1329 MIPI_DSI_MODE_VIDEO_HSE; 1330 1331 if (mipi_dsi_attach(dsi) < 0) { 1332 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 1333 mipi_dsi_device_unregister(dsi); 1334 return -EINVAL; 1335 } 1336 1337 ctx->dsi = dsi; 1338 1339 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 1340 1341 return 0; 1342 } 1343 1344 static void anx7625_bridge_detach(struct drm_bridge *bridge) 1345 { 1346 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1347 1348 if (ctx->dsi) { 1349 mipi_dsi_detach(ctx->dsi); 1350 mipi_dsi_device_unregister(ctx->dsi); 1351 } 1352 } 1353 1354 static int anx7625_bridge_attach(struct drm_bridge *bridge, 1355 enum drm_bridge_attach_flags flags) 1356 { 1357 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1358 int err; 1359 struct device *dev = &ctx->client->dev; 1360 1361 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 1362 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 1363 return -EINVAL; 1364 1365 if (!bridge->encoder) { 1366 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 1367 return -ENODEV; 1368 } 1369 1370 err = anx7625_attach_dsi(ctx); 1371 if (err) { 1372 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); 1373 return err; 1374 } 1375 1376 if (ctx->pdata.panel_bridge) { 1377 err = drm_bridge_attach(bridge->encoder, 1378 ctx->pdata.panel_bridge, 1379 &ctx->bridge, flags); 1380 if (err) 1381 return err; 1382 } 1383 1384 ctx->bridge_attached = 1; 1385 1386 return 0; 1387 } 1388 1389 static enum drm_mode_status 1390 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 1391 const struct drm_display_info *info, 1392 const struct drm_display_mode *mode) 1393 { 1394 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1395 struct device *dev = &ctx->client->dev; 1396 1397 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 1398 1399 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 1400 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 1401 DRM_DEV_DEBUG_DRIVER(dev, 1402 "drm mode invalid, pixelclock too high.\n"); 1403 return MODE_CLOCK_HIGH; 1404 } 1405 1406 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 1407 1408 return MODE_OK; 1409 } 1410 1411 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 1412 const struct drm_display_mode *old_mode, 1413 const struct drm_display_mode *mode) 1414 { 1415 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1416 struct device *dev = &ctx->client->dev; 1417 1418 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 1419 1420 ctx->dt.pixelclock.min = mode->clock; 1421 ctx->dt.hactive.min = mode->hdisplay; 1422 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 1423 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 1424 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 1425 ctx->dt.vactive.min = mode->vdisplay; 1426 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 1427 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 1428 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 1429 1430 ctx->display_timing_valid = 1; 1431 1432 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 1433 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 1434 ctx->dt.hactive.min, 1435 ctx->dt.hsync_len.min, 1436 ctx->dt.hfront_porch.min, 1437 ctx->dt.hback_porch.min); 1438 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 1439 ctx->dt.vactive.min, 1440 ctx->dt.vsync_len.min, 1441 ctx->dt.vfront_porch.min, 1442 ctx->dt.vback_porch.min); 1443 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 1444 mode->hdisplay, 1445 mode->hsync_start); 1446 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 1447 mode->hsync_end, 1448 mode->htotal); 1449 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 1450 mode->vdisplay, 1451 mode->vsync_start); 1452 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 1453 mode->vsync_end, 1454 mode->vtotal); 1455 } 1456 1457 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 1458 const struct drm_display_mode *mode, 1459 struct drm_display_mode *adj) 1460 { 1461 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1462 struct device *dev = &ctx->client->dev; 1463 u32 hsync, hfp, hbp, hblanking; 1464 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 1465 u32 vref, adj_clock; 1466 1467 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 1468 1469 hsync = mode->hsync_end - mode->hsync_start; 1470 hfp = mode->hsync_start - mode->hdisplay; 1471 hbp = mode->htotal - mode->hsync_end; 1472 hblanking = mode->htotal - mode->hdisplay; 1473 1474 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 1475 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1476 hsync, hfp, hbp, adj->clock); 1477 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1478 adj->hsync_start, adj->hsync_end, adj->htotal); 1479 1480 adj_hfp = hfp; 1481 adj_hsync = hsync; 1482 adj_hbp = hbp; 1483 adj_hblanking = hblanking; 1484 1485 /* HFP needs to be even */ 1486 if (hfp & 0x1) { 1487 adj_hfp += 1; 1488 adj_hblanking += 1; 1489 } 1490 1491 /* HBP needs to be even */ 1492 if (hbp & 0x1) { 1493 adj_hbp -= 1; 1494 adj_hblanking -= 1; 1495 } 1496 1497 /* HSYNC needs to be even */ 1498 if (hsync & 0x1) { 1499 if (adj_hblanking < hblanking) 1500 adj_hsync += 1; 1501 else 1502 adj_hsync -= 1; 1503 } 1504 1505 /* 1506 * Once illegal timing detected, use default HFP, HSYNC, HBP 1507 * This adjusting made for built-in eDP panel, for the externel 1508 * DP monitor, may need return false. 1509 */ 1510 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 1511 adj_hsync = SYNC_LEN_DEF; 1512 adj_hfp = HFP_HBP_DEF; 1513 adj_hbp = HFP_HBP_DEF; 1514 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 1515 if (hblanking < HBLANKING_MIN) { 1516 delta_adj = HBLANKING_MIN - hblanking; 1517 adj_clock = vref * delta_adj * adj->vtotal; 1518 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 1519 } else { 1520 delta_adj = hblanking - HBLANKING_MIN; 1521 adj_clock = vref * delta_adj * adj->vtotal; 1522 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 1523 } 1524 1525 DRM_WARN("illegal hblanking timing, use default.\n"); 1526 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 1527 } else if (adj_hfp < HP_MIN) { 1528 /* Adjust hfp if hfp less than HP_MIN */ 1529 delta_adj = HP_MIN - adj_hfp; 1530 adj_hfp = HP_MIN; 1531 1532 /* 1533 * Balance total HBlanking pixel, if HBP does not have enough 1534 * space, adjust HSYNC length, otherwise adjust HBP 1535 */ 1536 if ((adj_hbp - delta_adj) < HP_MIN) 1537 /* HBP not enough space */ 1538 adj_hsync -= delta_adj; 1539 else 1540 adj_hbp -= delta_adj; 1541 } else if (adj_hbp < HP_MIN) { 1542 delta_adj = HP_MIN - adj_hbp; 1543 adj_hbp = HP_MIN; 1544 1545 /* 1546 * Balance total HBlanking pixel, if HBP hasn't enough space, 1547 * adjust HSYNC length, otherwize adjust HBP 1548 */ 1549 if ((adj_hfp - delta_adj) < HP_MIN) 1550 /* HFP not enough space */ 1551 adj_hsync -= delta_adj; 1552 else 1553 adj_hfp -= delta_adj; 1554 } 1555 1556 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 1557 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1558 adj_hsync, adj_hfp, adj_hbp, adj->clock); 1559 1560 /* Reconstruct timing */ 1561 adj->hsync_start = adj->hdisplay + adj_hfp; 1562 adj->hsync_end = adj->hsync_start + adj_hsync; 1563 adj->htotal = adj->hsync_end + adj_hbp; 1564 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1565 adj->hsync_start, adj->hsync_end, adj->htotal); 1566 1567 return true; 1568 } 1569 1570 static void anx7625_bridge_enable(struct drm_bridge *bridge) 1571 { 1572 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1573 struct device *dev = &ctx->client->dev; 1574 1575 DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 1576 1577 pm_runtime_get_sync(dev); 1578 1579 anx7625_dp_start(ctx); 1580 } 1581 1582 static void anx7625_bridge_disable(struct drm_bridge *bridge) 1583 { 1584 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1585 struct device *dev = &ctx->client->dev; 1586 1587 DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 1588 1589 anx7625_dp_stop(ctx); 1590 1591 pm_runtime_put_sync(dev); 1592 } 1593 1594 static enum drm_connector_status 1595 anx7625_bridge_detect(struct drm_bridge *bridge) 1596 { 1597 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1598 struct device *dev = &ctx->client->dev; 1599 1600 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 1601 1602 return anx7625_sink_detect(ctx); 1603 } 1604 1605 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 1606 struct drm_connector *connector) 1607 { 1608 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1609 struct device *dev = &ctx->client->dev; 1610 1611 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 1612 1613 return anx7625_get_edid(ctx); 1614 } 1615 1616 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 1617 .attach = anx7625_bridge_attach, 1618 .detach = anx7625_bridge_detach, 1619 .disable = anx7625_bridge_disable, 1620 .mode_valid = anx7625_bridge_mode_valid, 1621 .mode_set = anx7625_bridge_mode_set, 1622 .mode_fixup = anx7625_bridge_mode_fixup, 1623 .enable = anx7625_bridge_enable, 1624 .detect = anx7625_bridge_detect, 1625 .get_edid = anx7625_bridge_get_edid, 1626 }; 1627 1628 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 1629 struct i2c_client *client) 1630 { 1631 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 1632 TX_P0_ADDR >> 1); 1633 if (!ctx->i2c.tx_p0_client) 1634 return -ENOMEM; 1635 1636 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 1637 TX_P1_ADDR >> 1); 1638 if (!ctx->i2c.tx_p1_client) 1639 goto free_tx_p0; 1640 1641 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 1642 TX_P2_ADDR >> 1); 1643 if (!ctx->i2c.tx_p2_client) 1644 goto free_tx_p1; 1645 1646 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 1647 RX_P0_ADDR >> 1); 1648 if (!ctx->i2c.rx_p0_client) 1649 goto free_tx_p2; 1650 1651 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 1652 RX_P1_ADDR >> 1); 1653 if (!ctx->i2c.rx_p1_client) 1654 goto free_rx_p0; 1655 1656 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 1657 RX_P2_ADDR >> 1); 1658 if (!ctx->i2c.rx_p2_client) 1659 goto free_rx_p1; 1660 1661 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 1662 TCPC_INTERFACE_ADDR >> 1); 1663 if (!ctx->i2c.tcpc_client) 1664 goto free_rx_p2; 1665 1666 return 0; 1667 1668 free_rx_p2: 1669 i2c_unregister_device(ctx->i2c.rx_p2_client); 1670 free_rx_p1: 1671 i2c_unregister_device(ctx->i2c.rx_p1_client); 1672 free_rx_p0: 1673 i2c_unregister_device(ctx->i2c.rx_p0_client); 1674 free_tx_p2: 1675 i2c_unregister_device(ctx->i2c.tx_p2_client); 1676 free_tx_p1: 1677 i2c_unregister_device(ctx->i2c.tx_p1_client); 1678 free_tx_p0: 1679 i2c_unregister_device(ctx->i2c.tx_p0_client); 1680 1681 return -ENOMEM; 1682 } 1683 1684 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 1685 { 1686 i2c_unregister_device(ctx->i2c.tx_p0_client); 1687 i2c_unregister_device(ctx->i2c.tx_p1_client); 1688 i2c_unregister_device(ctx->i2c.tx_p2_client); 1689 i2c_unregister_device(ctx->i2c.rx_p0_client); 1690 i2c_unregister_device(ctx->i2c.rx_p1_client); 1691 i2c_unregister_device(ctx->i2c.rx_p2_client); 1692 i2c_unregister_device(ctx->i2c.tcpc_client); 1693 } 1694 1695 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 1696 { 1697 struct anx7625_data *ctx = dev_get_drvdata(dev); 1698 1699 mutex_lock(&ctx->lock); 1700 1701 anx7625_stop_dp_work(ctx); 1702 anx7625_power_standby(ctx); 1703 1704 mutex_unlock(&ctx->lock); 1705 1706 return 0; 1707 } 1708 1709 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 1710 { 1711 struct anx7625_data *ctx = dev_get_drvdata(dev); 1712 1713 mutex_lock(&ctx->lock); 1714 1715 anx7625_power_on_init(ctx); 1716 anx7625_hpd_polling(ctx); 1717 1718 mutex_unlock(&ctx->lock); 1719 1720 return 0; 1721 } 1722 1723 static int __maybe_unused anx7625_resume(struct device *dev) 1724 { 1725 struct anx7625_data *ctx = dev_get_drvdata(dev); 1726 1727 if (!ctx->pdata.intp_irq) 1728 return 0; 1729 1730 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1731 enable_irq(ctx->pdata.intp_irq); 1732 anx7625_runtime_pm_resume(dev); 1733 } 1734 1735 return 0; 1736 } 1737 1738 static int __maybe_unused anx7625_suspend(struct device *dev) 1739 { 1740 struct anx7625_data *ctx = dev_get_drvdata(dev); 1741 1742 if (!ctx->pdata.intp_irq) 1743 return 0; 1744 1745 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1746 anx7625_runtime_pm_suspend(dev); 1747 disable_irq(ctx->pdata.intp_irq); 1748 } 1749 1750 return 0; 1751 } 1752 1753 static const struct dev_pm_ops anx7625_pm_ops = { 1754 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 1755 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 1756 anx7625_runtime_pm_resume, NULL) 1757 }; 1758 1759 static int anx7625_i2c_probe(struct i2c_client *client, 1760 const struct i2c_device_id *id) 1761 { 1762 struct anx7625_data *platform; 1763 struct anx7625_platform_data *pdata; 1764 int ret = 0; 1765 struct device *dev = &client->dev; 1766 1767 if (!i2c_check_functionality(client->adapter, 1768 I2C_FUNC_SMBUS_I2C_BLOCK)) { 1769 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 1770 return -ENODEV; 1771 } 1772 1773 platform = kzalloc(sizeof(*platform), GFP_KERNEL); 1774 if (!platform) { 1775 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 1776 return -ENOMEM; 1777 } 1778 1779 pdata = &platform->pdata; 1780 1781 ret = anx7625_parse_dt(dev, pdata); 1782 if (ret) { 1783 if (ret != -EPROBE_DEFER) 1784 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 1785 goto free_platform; 1786 } 1787 1788 platform->client = client; 1789 i2c_set_clientdata(client, platform); 1790 1791 pdata->supplies[0].supply = "vdd10"; 1792 pdata->supplies[1].supply = "vdd18"; 1793 pdata->supplies[2].supply = "vdd33"; 1794 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 1795 pdata->supplies); 1796 if (ret) { 1797 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 1798 return ret; 1799 } 1800 anx7625_init_gpio(platform); 1801 1802 mutex_init(&platform->lock); 1803 1804 platform->pdata.intp_irq = client->irq; 1805 if (platform->pdata.intp_irq) { 1806 INIT_WORK(&platform->work, anx7625_work_func); 1807 platform->workqueue = alloc_workqueue("anx7625_work", 1808 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 1809 if (!platform->workqueue) { 1810 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 1811 ret = -ENOMEM; 1812 goto free_platform; 1813 } 1814 1815 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 1816 NULL, anx7625_intr_hpd_isr, 1817 IRQF_TRIGGER_FALLING | 1818 IRQF_ONESHOT, 1819 "anx7625-intp", platform); 1820 if (ret) { 1821 DRM_DEV_ERROR(dev, "fail to request irq\n"); 1822 goto free_wq; 1823 } 1824 } 1825 1826 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 1827 ret = -ENOMEM; 1828 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 1829 goto free_wq; 1830 } 1831 1832 pm_runtime_enable(dev); 1833 1834 if (!platform->pdata.low_power_mode) { 1835 anx7625_disable_pd_protocol(platform); 1836 pm_runtime_get_sync(dev); 1837 } 1838 1839 /* Add work function */ 1840 if (platform->pdata.intp_irq) 1841 queue_work(platform->workqueue, &platform->work); 1842 1843 platform->bridge.funcs = &anx7625_bridge_funcs; 1844 platform->bridge.of_node = client->dev.of_node; 1845 platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 1846 platform->bridge.type = DRM_MODE_CONNECTOR_eDP; 1847 drm_bridge_add(&platform->bridge); 1848 1849 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 1850 1851 return 0; 1852 1853 free_wq: 1854 if (platform->workqueue) 1855 destroy_workqueue(platform->workqueue); 1856 1857 free_platform: 1858 kfree(platform); 1859 1860 return ret; 1861 } 1862 1863 static int anx7625_i2c_remove(struct i2c_client *client) 1864 { 1865 struct anx7625_data *platform = i2c_get_clientdata(client); 1866 1867 drm_bridge_remove(&platform->bridge); 1868 1869 if (platform->pdata.intp_irq) 1870 destroy_workqueue(platform->workqueue); 1871 1872 if (!platform->pdata.low_power_mode) 1873 pm_runtime_put_sync_suspend(&client->dev); 1874 1875 anx7625_unregister_i2c_dummy_clients(platform); 1876 1877 kfree(platform); 1878 return 0; 1879 } 1880 1881 static const struct i2c_device_id anx7625_id[] = { 1882 {"anx7625", 0}, 1883 {} 1884 }; 1885 1886 MODULE_DEVICE_TABLE(i2c, anx7625_id); 1887 1888 static const struct of_device_id anx_match_table[] = { 1889 {.compatible = "analogix,anx7625",}, 1890 {}, 1891 }; 1892 MODULE_DEVICE_TABLE(of, anx_match_table); 1893 1894 static struct i2c_driver anx7625_driver = { 1895 .driver = { 1896 .name = "anx7625", 1897 .of_match_table = anx_match_table, 1898 .pm = &anx7625_pm_ops, 1899 }, 1900 .probe = anx7625_i2c_probe, 1901 .remove = anx7625_i2c_remove, 1902 1903 .id_table = anx7625_id, 1904 }; 1905 1906 module_i2c_driver(anx7625_driver); 1907 1908 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 1909 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 1910 MODULE_LICENSE("GPL v2"); 1911 MODULE_VERSION(ANX7625_DRV_VERSION); 1912