1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/dp/drm_dp_aux_bus.h> 28 #include <drm/dp/drm_dp_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_hdcp.h> 31 #include <drm/drm_mipi_dsi.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_panel.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include <media/v4l2-fwnode.h> 38 #include <sound/hdmi-codec.h> 39 #include <video/display_timing.h> 40 41 #include "anx7625.h" 42 43 /* 44 * There is a sync issue while access I2C register between AP(CPU) and 45 * internal firmware(OCM), to avoid the race condition, AP should access 46 * the reserved slave address before slave address occurs changes. 47 */ 48 static int i2c_access_workaround(struct anx7625_data *ctx, 49 struct i2c_client *client) 50 { 51 u8 offset; 52 struct device *dev = &client->dev; 53 int ret; 54 55 if (client == ctx->last_client) 56 return 0; 57 58 ctx->last_client = client; 59 60 if (client == ctx->i2c.tcpc_client) 61 offset = RSVD_00_ADDR; 62 else if (client == ctx->i2c.tx_p0_client) 63 offset = RSVD_D1_ADDR; 64 else if (client == ctx->i2c.tx_p1_client) 65 offset = RSVD_60_ADDR; 66 else if (client == ctx->i2c.rx_p0_client) 67 offset = RSVD_39_ADDR; 68 else if (client == ctx->i2c.rx_p1_client) 69 offset = RSVD_7F_ADDR; 70 else 71 offset = RSVD_00_ADDR; 72 73 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 74 if (ret < 0) 75 DRM_DEV_ERROR(dev, 76 "fail to access i2c id=%x\n:%x", 77 client->addr, offset); 78 79 return ret; 80 } 81 82 static int anx7625_reg_read(struct anx7625_data *ctx, 83 struct i2c_client *client, u8 reg_addr) 84 { 85 int ret; 86 struct device *dev = &client->dev; 87 88 i2c_access_workaround(ctx, client); 89 90 ret = i2c_smbus_read_byte_data(client, reg_addr); 91 if (ret < 0) 92 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 93 client->addr, reg_addr); 94 95 return ret; 96 } 97 98 static int anx7625_reg_block_read(struct anx7625_data *ctx, 99 struct i2c_client *client, 100 u8 reg_addr, u8 len, u8 *buf) 101 { 102 int ret; 103 struct device *dev = &client->dev; 104 105 i2c_access_workaround(ctx, client); 106 107 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 108 if (ret < 0) 109 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 110 client->addr, reg_addr); 111 112 return ret; 113 } 114 115 static int anx7625_reg_write(struct anx7625_data *ctx, 116 struct i2c_client *client, 117 u8 reg_addr, u8 reg_val) 118 { 119 int ret; 120 struct device *dev = &client->dev; 121 122 i2c_access_workaround(ctx, client); 123 124 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 125 126 if (ret < 0) 127 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 128 client->addr, reg_addr); 129 130 return ret; 131 } 132 133 static int anx7625_reg_block_write(struct anx7625_data *ctx, 134 struct i2c_client *client, 135 u8 reg_addr, u8 len, u8 *buf) 136 { 137 int ret; 138 struct device *dev = &client->dev; 139 140 i2c_access_workaround(ctx, client); 141 142 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 143 if (ret < 0) 144 dev_err(dev, "write i2c block failed id=%x\n:%x", 145 client->addr, reg_addr); 146 147 return ret; 148 } 149 150 static int anx7625_write_or(struct anx7625_data *ctx, 151 struct i2c_client *client, 152 u8 offset, u8 mask) 153 { 154 int val; 155 156 val = anx7625_reg_read(ctx, client, offset); 157 if (val < 0) 158 return val; 159 160 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 161 } 162 163 static int anx7625_write_and(struct anx7625_data *ctx, 164 struct i2c_client *client, 165 u8 offset, u8 mask) 166 { 167 int val; 168 169 val = anx7625_reg_read(ctx, client, offset); 170 if (val < 0) 171 return val; 172 173 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 174 } 175 176 static int anx7625_write_and_or(struct anx7625_data *ctx, 177 struct i2c_client *client, 178 u8 offset, u8 and_mask, u8 or_mask) 179 { 180 int val; 181 182 val = anx7625_reg_read(ctx, client, offset); 183 if (val < 0) 184 return val; 185 186 return anx7625_reg_write(ctx, client, 187 offset, (val & and_mask) | (or_mask)); 188 } 189 190 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 191 { 192 int i, ret; 193 194 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 195 AUDIO_CONTROL_REGISTER, 0x80); 196 for (i = 0; i < 13; i++) 197 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 198 VIDEO_BIT_MATRIX_12 + i, 199 0x18 + i); 200 201 return ret; 202 } 203 204 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 205 { 206 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 207 } 208 209 static int wait_aux_op_finish(struct anx7625_data *ctx) 210 { 211 struct device *dev = &ctx->client->dev; 212 int val; 213 int ret; 214 215 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 216 ctx, val, 217 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 218 2000, 219 2000 * 150); 220 if (ret) { 221 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 222 return -EIO; 223 } 224 225 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 226 AP_AUX_CTRL_STATUS); 227 if (val < 0 || (val & 0x0F)) { 228 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 229 return -EIO; 230 } 231 232 return 0; 233 } 234 235 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 236 u8 len, u8 *buf) 237 { 238 struct device *dev = &ctx->client->dev; 239 int ret; 240 u8 addrh, addrm, addrl; 241 u8 cmd; 242 bool is_write = !(op & DP_AUX_I2C_READ); 243 244 if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 245 dev_err(dev, "exceed aux buffer len.\n"); 246 return -EINVAL; 247 } 248 249 if (!len) 250 return len; 251 252 addrl = address & 0xFF; 253 addrm = (address >> 8) & 0xFF; 254 addrh = (address >> 16) & 0xFF; 255 256 if (!is_write) 257 op &= ~DP_AUX_I2C_MOT; 258 cmd = DPCD_CMD(len, op); 259 260 /* Set command and length */ 261 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 262 AP_AUX_COMMAND, cmd); 263 264 /* Set aux access address */ 265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 266 AP_AUX_ADDR_7_0, addrl); 267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 268 AP_AUX_ADDR_15_8, addrm); 269 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 270 AP_AUX_ADDR_19_16, addrh); 271 272 if (is_write) 273 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 274 AP_AUX_BUFF_START, len, buf); 275 /* Enable aux access */ 276 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 277 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 278 279 if (ret < 0) { 280 dev_err(dev, "cannot access aux related register.\n"); 281 return -EIO; 282 } 283 284 ret = wait_aux_op_finish(ctx); 285 if (ret < 0) { 286 dev_err(dev, "aux IO error: wait aux op finish.\n"); 287 return ret; 288 } 289 290 /* Write done */ 291 if (is_write) 292 return len; 293 294 /* Read done, read out dpcd data */ 295 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 296 AP_AUX_BUFF_START, len, buf); 297 if (ret < 0) { 298 dev_err(dev, "read dpcd register failed\n"); 299 return -EIO; 300 } 301 302 return len; 303 } 304 305 static int anx7625_video_mute_control(struct anx7625_data *ctx, 306 u8 status) 307 { 308 int ret; 309 310 if (status) { 311 /* Set mute on flag */ 312 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 313 AP_AV_STATUS, AP_MIPI_MUTE); 314 /* Clear mipi RX en */ 315 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 316 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 317 } else { 318 /* Mute off flag */ 319 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 320 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 321 /* Set MIPI RX EN */ 322 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 323 AP_AV_STATUS, AP_MIPI_RX_EN); 324 } 325 326 return ret; 327 } 328 329 /* Reduction of fraction a/b */ 330 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 331 { 332 unsigned long gcd_num; 333 unsigned long tmp_a, tmp_b; 334 u32 i = 1; 335 336 gcd_num = gcd(*a, *b); 337 *a /= gcd_num; 338 *b /= gcd_num; 339 340 tmp_a = *a; 341 tmp_b = *b; 342 343 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 344 i++; 345 *a = tmp_a / i; 346 *b = tmp_b / i; 347 } 348 349 /* 350 * In the end, make a, b larger to have higher ODFC PLL 351 * output frequency accuracy 352 */ 353 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 354 *a <<= 1; 355 *b <<= 1; 356 } 357 358 *a >>= 1; 359 *b >>= 1; 360 } 361 362 static int anx7625_calculate_m_n(u32 pixelclock, 363 unsigned long *m, 364 unsigned long *n, 365 u8 *post_divider) 366 { 367 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 368 /* Pixel clock frequency is too high */ 369 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 370 pixelclock, 371 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 372 return -EINVAL; 373 } 374 375 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 376 /* Pixel clock frequency is too low */ 377 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 378 pixelclock, 379 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 380 return -EINVAL; 381 } 382 383 for (*post_divider = 1; 384 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 385 *post_divider += 1; 386 387 if (*post_divider > POST_DIVIDER_MAX) { 388 for (*post_divider = 1; 389 (pixelclock < 390 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 391 *post_divider += 1; 392 393 if (*post_divider > POST_DIVIDER_MAX) { 394 DRM_ERROR("cannot find property post_divider(%d)\n", 395 *post_divider); 396 return -EDOM; 397 } 398 } 399 400 /* Patch to improve the accuracy */ 401 if (*post_divider == 7) { 402 /* 27,000,000 is not divisible by 7 */ 403 *post_divider = 8; 404 } else if (*post_divider == 11) { 405 /* 27,000,000 is not divisible by 11 */ 406 *post_divider = 12; 407 } else if ((*post_divider == 13) || (*post_divider == 14)) { 408 /* 27,000,000 is not divisible by 13 or 14 */ 409 *post_divider = 15; 410 } 411 412 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 413 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 414 pixelclock * (*post_divider), 415 PLL_OUT_FREQ_ABS_MAX); 416 return -EDOM; 417 } 418 419 *m = pixelclock; 420 *n = XTAL_FRQ / (*post_divider); 421 422 anx7625_reduction_of_a_fraction(m, n); 423 424 return 0; 425 } 426 427 static int anx7625_odfc_config(struct anx7625_data *ctx, 428 u8 post_divider) 429 { 430 int ret; 431 struct device *dev = &ctx->client->dev; 432 433 /* Config input reference clock frequency 27MHz/19.2MHz */ 434 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 435 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 436 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 437 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 438 /* Post divider */ 439 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 440 MIPI_DIGITAL_PLL_8, 0x0f); 441 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 442 post_divider << 4); 443 444 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 445 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 446 ~MIPI_PLL_VCO_TUNE_REG_VAL); 447 448 /* Reset ODFC PLL */ 449 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 450 ~MIPI_PLL_RESET_N); 451 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 452 MIPI_PLL_RESET_N); 453 454 if (ret < 0) 455 DRM_DEV_ERROR(dev, "IO error.\n"); 456 457 return ret; 458 } 459 460 /* 461 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 462 * anx7625 defined K ratio for matching MIPI input video clock and 463 * DP output video clock. Increase K value can match bigger video data 464 * variation. IVO panel has small variation than DP CTS spec, need 465 * decrease the K value. 466 */ 467 static int anx7625_set_k_value(struct anx7625_data *ctx) 468 { 469 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 470 471 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 472 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 473 MIPI_DIGITAL_ADJ_1, 0x3B); 474 475 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 476 MIPI_DIGITAL_ADJ_1, 0x3D); 477 } 478 479 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 480 { 481 struct device *dev = &ctx->client->dev; 482 unsigned long m, n; 483 u16 htotal; 484 int ret; 485 u8 post_divider = 0; 486 487 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 488 &m, &n, &post_divider); 489 490 if (ret) { 491 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 492 return ret; 493 } 494 495 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 496 m, n, post_divider); 497 498 /* Configure pixel clock */ 499 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 500 (ctx->dt.pixelclock.min / 1000) & 0xFF); 501 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 502 (ctx->dt.pixelclock.min / 1000) >> 8); 503 /* Lane count */ 504 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 505 MIPI_LANE_CTRL_0, 0xfc); 506 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 507 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 508 509 /* Htotal */ 510 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 511 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 513 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 514 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 515 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 516 /* Hactive */ 517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 518 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 519 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 520 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 521 /* HFP */ 522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 523 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 524 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 525 HORIZONTAL_FRONT_PORCH_H, 526 ctx->dt.hfront_porch.min >> 8); 527 /* HWS */ 528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 529 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 530 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 531 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 532 /* HBP */ 533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 534 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 535 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 536 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 537 /* Vactive */ 538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 539 ctx->dt.vactive.min); 540 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 541 ctx->dt.vactive.min >> 8); 542 /* VFP */ 543 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 544 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 545 /* VWS */ 546 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 547 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 548 /* VBP */ 549 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 550 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 551 /* M value */ 552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 553 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 555 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 556 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 557 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 558 /* N value */ 559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 560 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 562 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 563 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 564 (n & 0xff)); 565 566 anx7625_set_k_value(ctx); 567 568 ret |= anx7625_odfc_config(ctx, post_divider - 1); 569 570 if (ret < 0) 571 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 572 573 return ret; 574 } 575 576 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 577 { 578 int val; 579 struct device *dev = &ctx->client->dev; 580 581 /* Swap MIPI-DSI data lane 3 P and N */ 582 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 583 if (val < 0) { 584 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 585 return -EIO; 586 } 587 588 val |= (1 << MIPI_SWAP_CH3); 589 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 590 } 591 592 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 593 594 { 595 int val, ret; 596 struct device *dev = &ctx->client->dev; 597 598 /* Swap MIPI-DSI data lane 3 P and N */ 599 ret = anx7625_swap_dsi_lane3(ctx); 600 if (ret < 0) { 601 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 602 return ret; 603 } 604 605 /* DSI clock settings */ 606 val = (0 << MIPI_HS_PWD_CLK) | 607 (0 << MIPI_HS_RT_CLK) | 608 (0 << MIPI_PD_CLK) | 609 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 610 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 611 (0 << MIPI_CLK_DET_DET_BYPASS) | 612 (0 << MIPI_CLK_MISS_CTRL) | 613 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 614 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 615 MIPI_PHY_CONTROL_3, val); 616 617 /* 618 * Decreased HS prepare timing delay from 160ns to 80ns work with 619 * a) Dragon board 810 series (Qualcomm AP) 620 * b) Moving Pixel DSI source (PG3A pattern generator + 621 * P332 D-PHY Probe) default D-PHY timing 622 * 5ns/step 623 */ 624 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 625 MIPI_TIME_HS_PRPR, 0x10); 626 627 /* Enable DSI mode*/ 628 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 629 SELECT_DSI << MIPI_DPI_SELECT); 630 631 ret |= anx7625_dsi_video_timing_config(ctx); 632 if (ret < 0) { 633 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 634 return ret; 635 } 636 637 /* Toggle m, n ready */ 638 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 639 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 640 usleep_range(1000, 1100); 641 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 642 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 643 644 /* Configure integer stable register */ 645 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 646 MIPI_VIDEO_STABLE_CNT, 0x02); 647 /* Power on MIPI RX */ 648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 649 MIPI_LANE_CTRL_10, 0x00); 650 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 651 MIPI_LANE_CTRL_10, 0x80); 652 653 if (ret < 0) 654 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 655 656 return ret; 657 } 658 659 static int anx7625_dsi_config(struct anx7625_data *ctx) 660 { 661 struct device *dev = &ctx->client->dev; 662 int ret; 663 664 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 665 666 /* DSC disable */ 667 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 668 R_DSC_CTRL_0, ~DSC_EN); 669 670 ret |= anx7625_api_dsi_config(ctx); 671 672 if (ret < 0) { 673 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 674 return ret; 675 } 676 677 /* Set MIPI RX EN */ 678 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 679 AP_AV_STATUS, AP_MIPI_RX_EN); 680 /* Clear mute flag */ 681 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 682 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 683 if (ret < 0) 684 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 685 else 686 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 687 688 return ret; 689 } 690 691 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 692 { 693 struct device *dev = &ctx->client->dev; 694 u16 freq = ctx->dt.pixelclock.min / 1000; 695 int ret; 696 697 /* configure pixel clock */ 698 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 699 PIXEL_CLOCK_L, freq & 0xFF); 700 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 701 PIXEL_CLOCK_H, (freq >> 8)); 702 703 /* set DPI mode */ 704 /* set to DPI PLL module sel */ 705 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 706 MIPI_DIGITAL_PLL_9, 0x20); 707 /* power down MIPI */ 708 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 709 MIPI_LANE_CTRL_10, 0x08); 710 /* enable DPI mode */ 711 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 712 MIPI_DIGITAL_PLL_18, 0x1C); 713 /* set first edge */ 714 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 715 VIDEO_CONTROL_0, 0x06); 716 if (ret < 0) 717 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 718 719 return ret; 720 } 721 722 static int anx7625_dpi_config(struct anx7625_data *ctx) 723 { 724 struct device *dev = &ctx->client->dev; 725 int ret; 726 727 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 728 729 /* DSC disable */ 730 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 731 R_DSC_CTRL_0, ~DSC_EN); 732 if (ret < 0) { 733 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 734 return ret; 735 } 736 737 ret = anx7625_config_bit_matrix(ctx); 738 if (ret < 0) { 739 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 740 return ret; 741 } 742 743 ret = anx7625_api_dpi_config(ctx); 744 if (ret < 0) { 745 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 746 return ret; 747 } 748 749 /* set MIPI RX EN */ 750 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 751 AP_AV_STATUS, AP_MIPI_RX_EN); 752 /* clear mute flag */ 753 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 754 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 755 if (ret < 0) 756 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 757 758 return ret; 759 } 760 761 static int anx7625_read_flash_status(struct anx7625_data *ctx) 762 { 763 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 764 } 765 766 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 767 { 768 int ret, val; 769 struct device *dev = &ctx->client->dev; 770 u8 ident[FLASH_BUF_LEN]; 771 772 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 773 FLASH_ADDR_HIGH, 0x91); 774 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 775 FLASH_ADDR_LOW, 0xA0); 776 if (ret < 0) { 777 dev_err(dev, "IO error : set key flash address.\n"); 778 return ret; 779 } 780 781 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 782 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 783 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 784 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 785 if (ret < 0) { 786 dev_err(dev, "IO error : set key flash len.\n"); 787 return ret; 788 } 789 790 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 791 R_FLASH_RW_CTRL, FLASH_READ); 792 ret |= readx_poll_timeout(anx7625_read_flash_status, 793 ctx, val, 794 ((val & FLASH_DONE) || (val < 0)), 795 2000, 796 2000 * 150); 797 if (ret) { 798 dev_err(dev, "flash read access fail!\n"); 799 return -EIO; 800 } 801 802 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 803 FLASH_BUF_BASE_ADDR, 804 FLASH_BUF_LEN, ident); 805 if (ret < 0) { 806 dev_err(dev, "read flash data fail!\n"); 807 return -EIO; 808 } 809 810 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 811 return -EINVAL; 812 813 return 0; 814 } 815 816 static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 817 { 818 int ret; 819 struct device *dev = &ctx->client->dev; 820 821 /* Select HDCP 1.4 KEY */ 822 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 823 R_BOOT_RETRY, 0x12); 824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 825 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 830 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 831 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 832 833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 834 R_RAM_ADDR_H, 0); 835 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 836 R_RAM_ADDR_L, 0); 837 /* Enable HDCP 1.4 KEY load */ 838 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 839 R_RAM_CTRL, DECRYPT_EN | LOAD_START); 840 dev_dbg(dev, "load HDCP 1.4 key done\n"); 841 return ret; 842 } 843 844 static int anx7625_hdcp_disable(struct anx7625_data *ctx) 845 { 846 int ret; 847 struct device *dev = &ctx->client->dev; 848 849 dev_dbg(dev, "disable HDCP 1.4\n"); 850 851 /* Disable HDCP */ 852 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 853 /* Try auth flag */ 854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 855 /* Interrupt for DRM */ 856 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 857 if (ret < 0) 858 dev_err(dev, "fail to disable HDCP\n"); 859 860 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 861 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 862 } 863 864 static int anx7625_hdcp_enable(struct anx7625_data *ctx) 865 { 866 u8 bcap; 867 int ret; 868 struct device *dev = &ctx->client->dev; 869 870 ret = anx7625_hdcp_key_probe(ctx); 871 if (ret) { 872 dev_dbg(dev, "no key found, not to do hdcp\n"); 873 return ret; 874 } 875 876 /* Read downstream capability */ 877 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap); 878 if (ret < 0) 879 return ret; 880 881 if (!(bcap & 0x01)) { 882 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 883 return 0; 884 } 885 886 dev_dbg(dev, "enable HDCP 1.4\n"); 887 888 /* First clear HDCP state */ 889 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 890 TX_HDCP_CTRL0, 891 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 892 usleep_range(1000, 1100); 893 /* Second clear HDCP state */ 894 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 895 TX_HDCP_CTRL0, 896 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 897 898 /* Set time for waiting KSVR */ 899 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 900 SP_TX_WAIT_KSVR_TIME, 0xc8); 901 /* Set time for waiting R0 */ 902 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 903 SP_TX_WAIT_R0_TIME, 0xb0); 904 ret |= anx7625_hdcp_key_load(ctx); 905 if (ret) { 906 pr_warn("prepare HDCP key failed.\n"); 907 return ret; 908 } 909 910 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 911 912 /* Try auth flag */ 913 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 914 /* Interrupt for DRM */ 915 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 916 if (ret < 0) 917 dev_err(dev, "fail to enable HDCP\n"); 918 919 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 920 TX_HDCP_CTRL0, HARD_AUTH_EN); 921 } 922 923 static void anx7625_dp_start(struct anx7625_data *ctx) 924 { 925 int ret; 926 struct device *dev = &ctx->client->dev; 927 928 if (!ctx->display_timing_valid) { 929 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 930 return; 931 } 932 933 /* Disable HDCP */ 934 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 935 936 if (ctx->pdata.is_dpi) 937 ret = anx7625_dpi_config(ctx); 938 else 939 ret = anx7625_dsi_config(ctx); 940 941 if (ret < 0) 942 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 943 944 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 945 946 ctx->dp_en = 1; 947 } 948 949 static void anx7625_dp_stop(struct anx7625_data *ctx) 950 { 951 struct device *dev = &ctx->client->dev; 952 int ret; 953 u8 data; 954 955 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 956 957 /* 958 * Video disable: 0x72:08 bit 7 = 0; 959 * Audio disable: 0x70:87 bit 0 = 0; 960 */ 961 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 962 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 963 964 ret |= anx7625_video_mute_control(ctx, 1); 965 966 dev_dbg(dev, "notify downstream enter into standby\n"); 967 /* Downstream monitor enter into standby mode */ 968 data = 2; 969 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data); 970 if (ret < 0) 971 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 972 973 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 974 975 ctx->dp_en = 0; 976 } 977 978 static int sp_tx_rst_aux(struct anx7625_data *ctx) 979 { 980 int ret; 981 982 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 983 AUX_RST); 984 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 985 ~AUX_RST); 986 return ret; 987 } 988 989 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 990 { 991 int ret; 992 993 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 994 AP_AUX_BUFF_START, offset); 995 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 996 AP_AUX_COMMAND, 0x04); 997 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 998 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 999 return (ret | wait_aux_op_finish(ctx)); 1000 } 1001 1002 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 1003 { 1004 int ret; 1005 1006 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1007 AP_AUX_COMMAND, len_cmd); 1008 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1009 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1010 return (ret | wait_aux_op_finish(ctx)); 1011 } 1012 1013 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 1014 { 1015 int c = 0; 1016 struct device *dev = &ctx->client->dev; 1017 1018 sp_tx_aux_wr(ctx, 0x7e); 1019 sp_tx_aux_rd(ctx, 0x01); 1020 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 1021 if (c < 0) { 1022 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 1023 return -EIO; 1024 } 1025 1026 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 1027 1028 if (c > MAX_EDID_BLOCK) 1029 c = 1; 1030 1031 return c; 1032 } 1033 1034 static int edid_read(struct anx7625_data *ctx, 1035 u8 offset, u8 *pblock_buf) 1036 { 1037 int ret, cnt; 1038 struct device *dev = &ctx->client->dev; 1039 1040 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1041 sp_tx_aux_wr(ctx, offset); 1042 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1043 ret = sp_tx_aux_rd(ctx, 0xf1); 1044 1045 if (ret) { 1046 ret = sp_tx_rst_aux(ctx); 1047 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 1048 } else { 1049 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1050 AP_AUX_BUFF_START, 1051 MAX_DPCD_BUFFER_SIZE, 1052 pblock_buf); 1053 if (ret > 0) 1054 break; 1055 } 1056 } 1057 1058 if (cnt > EDID_TRY_CNT) 1059 return -EIO; 1060 1061 return ret; 1062 } 1063 1064 static int segments_edid_read(struct anx7625_data *ctx, 1065 u8 segment, u8 *buf, u8 offset) 1066 { 1067 u8 cnt; 1068 int ret; 1069 struct device *dev = &ctx->client->dev; 1070 1071 /* Write address only */ 1072 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1073 AP_AUX_ADDR_7_0, 0x30); 1074 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1075 AP_AUX_COMMAND, 0x04); 1076 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1077 AP_AUX_CTRL_STATUS, 1078 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 1079 1080 ret |= wait_aux_op_finish(ctx); 1081 /* Write segment address */ 1082 ret |= sp_tx_aux_wr(ctx, segment); 1083 /* Data read */ 1084 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1085 AP_AUX_ADDR_7_0, 0x50); 1086 if (ret) { 1087 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 1088 return ret; 1089 } 1090 1091 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1092 sp_tx_aux_wr(ctx, offset); 1093 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1094 ret = sp_tx_aux_rd(ctx, 0xf1); 1095 1096 if (ret) { 1097 ret = sp_tx_rst_aux(ctx); 1098 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 1099 } else { 1100 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1101 AP_AUX_BUFF_START, 1102 MAX_DPCD_BUFFER_SIZE, buf); 1103 if (ret > 0) 1104 break; 1105 } 1106 } 1107 1108 if (cnt > EDID_TRY_CNT) 1109 return -EIO; 1110 1111 return ret; 1112 } 1113 1114 static int sp_tx_edid_read(struct anx7625_data *ctx, 1115 u8 *pedid_blocks_buf) 1116 { 1117 u8 offset; 1118 int edid_pos; 1119 int count, blocks_num; 1120 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 1121 u8 i, j; 1122 int g_edid_break = 0; 1123 int ret; 1124 struct device *dev = &ctx->client->dev; 1125 1126 /* Address initial */ 1127 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1128 AP_AUX_ADDR_7_0, 0x50); 1129 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1130 AP_AUX_ADDR_15_8, 0); 1131 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 1132 AP_AUX_ADDR_19_16, 0xf0); 1133 if (ret < 0) { 1134 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 1135 return -EIO; 1136 } 1137 1138 blocks_num = sp_tx_get_edid_block(ctx); 1139 if (blocks_num < 0) 1140 return blocks_num; 1141 1142 count = 0; 1143 1144 do { 1145 switch (count) { 1146 case 0: 1147 case 1: 1148 for (i = 0; i < 8; i++) { 1149 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 1150 g_edid_break = edid_read(ctx, offset, 1151 pblock_buf); 1152 1153 if (g_edid_break < 0) 1154 break; 1155 1156 memcpy(&pedid_blocks_buf[offset], 1157 pblock_buf, 1158 MAX_DPCD_BUFFER_SIZE); 1159 } 1160 1161 break; 1162 case 2: 1163 offset = 0x00; 1164 1165 for (j = 0; j < 8; j++) { 1166 edid_pos = (j + count * 8) * 1167 MAX_DPCD_BUFFER_SIZE; 1168 1169 if (g_edid_break == 1) 1170 break; 1171 1172 ret = segments_edid_read(ctx, count / 2, 1173 pblock_buf, offset); 1174 if (ret < 0) 1175 return ret; 1176 1177 memcpy(&pedid_blocks_buf[edid_pos], 1178 pblock_buf, 1179 MAX_DPCD_BUFFER_SIZE); 1180 offset = offset + 0x10; 1181 } 1182 1183 break; 1184 case 3: 1185 offset = 0x80; 1186 1187 for (j = 0; j < 8; j++) { 1188 edid_pos = (j + count * 8) * 1189 MAX_DPCD_BUFFER_SIZE; 1190 if (g_edid_break == 1) 1191 break; 1192 1193 ret = segments_edid_read(ctx, count / 2, 1194 pblock_buf, offset); 1195 if (ret < 0) 1196 return ret; 1197 1198 memcpy(&pedid_blocks_buf[edid_pos], 1199 pblock_buf, 1200 MAX_DPCD_BUFFER_SIZE); 1201 offset = offset + 0x10; 1202 } 1203 1204 break; 1205 default: 1206 break; 1207 } 1208 1209 count++; 1210 1211 } while (blocks_num >= count); 1212 1213 /* Check edid data */ 1214 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 1215 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 1216 return -EINVAL; 1217 } 1218 1219 /* Reset aux channel */ 1220 ret = sp_tx_rst_aux(ctx); 1221 if (ret < 0) { 1222 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 1223 return ret; 1224 } 1225 1226 return (blocks_num + 1); 1227 } 1228 1229 static void anx7625_power_on(struct anx7625_data *ctx) 1230 { 1231 struct device *dev = &ctx->client->dev; 1232 int ret, i; 1233 1234 if (!ctx->pdata.low_power_mode) { 1235 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1236 return; 1237 } 1238 1239 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 1240 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 1241 if (ret < 0) { 1242 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 1243 i, ret); 1244 goto reg_err; 1245 } 1246 usleep_range(2000, 2100); 1247 } 1248 1249 usleep_range(11000, 12000); 1250 1251 /* Power on pin enable */ 1252 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 1253 usleep_range(10000, 11000); 1254 /* Power reset pin enable */ 1255 gpiod_set_value(ctx->pdata.gpio_reset, 1); 1256 usleep_range(10000, 11000); 1257 1258 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 1259 return; 1260 reg_err: 1261 for (--i; i >= 0; i--) 1262 regulator_disable(ctx->pdata.supplies[i].consumer); 1263 } 1264 1265 static void anx7625_power_standby(struct anx7625_data *ctx) 1266 { 1267 struct device *dev = &ctx->client->dev; 1268 int ret; 1269 1270 if (!ctx->pdata.low_power_mode) { 1271 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1272 return; 1273 } 1274 1275 gpiod_set_value(ctx->pdata.gpio_reset, 0); 1276 usleep_range(1000, 1100); 1277 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 1278 usleep_range(1000, 1100); 1279 1280 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1281 ctx->pdata.supplies); 1282 if (ret < 0) 1283 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1284 1285 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1286 } 1287 1288 /* Basic configurations of ANX7625 */ 1289 static void anx7625_config(struct anx7625_data *ctx) 1290 { 1291 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1292 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1293 } 1294 1295 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1296 { 1297 struct device *dev = &ctx->client->dev; 1298 int ret; 1299 1300 /* Reset main ocm */ 1301 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1302 /* Disable PD */ 1303 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1304 AP_AV_STATUS, AP_DISABLE_PD); 1305 /* Release main ocm */ 1306 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1307 1308 if (ret < 0) 1309 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1310 else 1311 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1312 } 1313 1314 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1315 { 1316 int ret; 1317 struct device *dev = &ctx->client->dev; 1318 1319 /* Check interface workable */ 1320 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1321 FLASH_LOAD_STA); 1322 if (ret < 0) { 1323 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1324 return ret; 1325 } 1326 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1327 return -ENODEV; 1328 1329 anx7625_disable_pd_protocol(ctx); 1330 1331 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1332 anx7625_reg_read(ctx, 1333 ctx->i2c.rx_p0_client, 1334 OCM_FW_VERSION), 1335 anx7625_reg_read(ctx, 1336 ctx->i2c.rx_p0_client, 1337 OCM_FW_REVERSION)); 1338 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1339 ANX7625_DRV_VERSION); 1340 1341 return 0; 1342 } 1343 1344 static void anx7625_power_on_init(struct anx7625_data *ctx) 1345 { 1346 int retry_count, i; 1347 1348 for (retry_count = 0; retry_count < 3; retry_count++) { 1349 anx7625_power_on(ctx); 1350 anx7625_config(ctx); 1351 1352 for (i = 0; i < OCM_LOADING_TIME; i++) { 1353 if (!anx7625_ocm_loading_check(ctx)) 1354 return; 1355 usleep_range(1000, 1100); 1356 } 1357 anx7625_power_standby(ctx); 1358 } 1359 } 1360 1361 static void anx7625_init_gpio(struct anx7625_data *platform) 1362 { 1363 struct device *dev = &platform->client->dev; 1364 1365 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1366 1367 /* Gpio for chip power enable */ 1368 platform->pdata.gpio_p_on = 1369 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1370 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 1371 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 1372 platform->pdata.gpio_p_on = NULL; 1373 } 1374 1375 /* Gpio for chip reset */ 1376 platform->pdata.gpio_reset = 1377 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1378 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 1379 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 1380 platform->pdata.gpio_reset = NULL; 1381 } 1382 1383 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1384 platform->pdata.low_power_mode = 1; 1385 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1386 desc_to_gpio(platform->pdata.gpio_p_on), 1387 desc_to_gpio(platform->pdata.gpio_reset)); 1388 } else { 1389 platform->pdata.low_power_mode = 0; 1390 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1391 } 1392 } 1393 1394 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1395 { 1396 ctx->hpd_status = 0; 1397 ctx->hpd_high_cnt = 0; 1398 ctx->display_timing_valid = 0; 1399 } 1400 1401 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1402 { 1403 int ret; 1404 struct device *dev = &ctx->client->dev; 1405 1406 if (ctx->hpd_high_cnt >= 2) { 1407 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1408 return; 1409 } 1410 1411 ctx->hpd_status = 1; 1412 ctx->hpd_high_cnt++; 1413 1414 /* Not support HDCP */ 1415 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1416 1417 /* Try auth flag */ 1418 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1419 /* Interrupt for DRM */ 1420 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1421 if (ret < 0) { 1422 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1423 return; 1424 } 1425 1426 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1427 if (ret < 0) 1428 return; 1429 1430 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1431 } 1432 1433 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1434 { 1435 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1436 } 1437 1438 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1439 { 1440 int ret, val; 1441 struct device *dev = &ctx->client->dev; 1442 1443 /* Interrupt mode, no need poll HPD status, just return */ 1444 if (ctx->pdata.intp_irq) 1445 return; 1446 1447 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1448 ctx, val, 1449 ((val & HPD_STATUS) || (val < 0)), 1450 5000, 1451 5000 * 100); 1452 if (ret) { 1453 DRM_DEV_ERROR(dev, "no hpd.\n"); 1454 return; 1455 } 1456 1457 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1458 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1459 INTR_ALERT_1, 0xFF); 1460 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1461 INTERFACE_CHANGE_INT, 0); 1462 1463 anx7625_start_dp_work(ctx); 1464 1465 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1466 drm_helper_hpd_irq_event(ctx->bridge.dev); 1467 } 1468 1469 static void anx7625_remove_edid(struct anx7625_data *ctx) 1470 { 1471 ctx->slimport_edid_p.edid_block_num = -1; 1472 } 1473 1474 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1475 { 1476 int i; 1477 1478 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1479 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1480 DP_TX_LANE0_SWING_REG0 + i, 1481 ctx->pdata.lane0_reg_data[i] & 0xFF); 1482 1483 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1484 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1485 DP_TX_LANE1_SWING_REG0 + i, 1486 ctx->pdata.lane1_reg_data[i] & 0xFF); 1487 } 1488 1489 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1490 { 1491 struct device *dev = &ctx->client->dev; 1492 1493 /* HPD changed */ 1494 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1495 (u32)on); 1496 1497 if (on == 0) { 1498 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1499 anx7625_remove_edid(ctx); 1500 anx7625_stop_dp_work(ctx); 1501 } else { 1502 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1503 anx7625_start_dp_work(ctx); 1504 anx7625_dp_adjust_swing(ctx); 1505 } 1506 } 1507 1508 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1509 { 1510 int intr_vector, status; 1511 struct device *dev = &ctx->client->dev; 1512 1513 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1514 INTR_ALERT_1, 0xFF); 1515 if (status < 0) { 1516 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1517 return status; 1518 } 1519 1520 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1521 INTERFACE_CHANGE_INT); 1522 if (intr_vector < 0) { 1523 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1524 return intr_vector; 1525 } 1526 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1527 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1528 INTERFACE_CHANGE_INT, 1529 intr_vector & (~intr_vector)); 1530 if (status < 0) { 1531 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1532 return status; 1533 } 1534 1535 if (!(intr_vector & HPD_STATUS_CHANGE)) 1536 return -ENOENT; 1537 1538 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1539 SYSTEM_STSTUS); 1540 if (status < 0) { 1541 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1542 return status; 1543 } 1544 1545 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1546 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1547 1548 return 0; 1549 } 1550 1551 static void anx7625_work_func(struct work_struct *work) 1552 { 1553 int event; 1554 struct anx7625_data *ctx = container_of(work, 1555 struct anx7625_data, work); 1556 1557 mutex_lock(&ctx->lock); 1558 1559 if (pm_runtime_suspended(&ctx->client->dev)) 1560 goto unlock; 1561 1562 event = anx7625_hpd_change_detect(ctx); 1563 if (event < 0) 1564 goto unlock; 1565 1566 if (ctx->bridge_attached) 1567 drm_helper_hpd_irq_event(ctx->bridge.dev); 1568 1569 unlock: 1570 mutex_unlock(&ctx->lock); 1571 } 1572 1573 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1574 { 1575 struct anx7625_data *ctx = (struct anx7625_data *)data; 1576 1577 queue_work(ctx->workqueue, &ctx->work); 1578 1579 return IRQ_HANDLED; 1580 } 1581 1582 static int anx7625_get_swing_setting(struct device *dev, 1583 struct anx7625_platform_data *pdata) 1584 { 1585 int num_regs; 1586 1587 if (of_get_property(dev->of_node, 1588 "analogix,lane0-swing", &num_regs)) { 1589 if (num_regs > DP_TX_SWING_REG_CNT) 1590 num_regs = DP_TX_SWING_REG_CNT; 1591 1592 pdata->dp_lane0_swing_reg_cnt = num_regs; 1593 of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1594 pdata->lane0_reg_data, num_regs); 1595 } 1596 1597 if (of_get_property(dev->of_node, 1598 "analogix,lane1-swing", &num_regs)) { 1599 if (num_regs > DP_TX_SWING_REG_CNT) 1600 num_regs = DP_TX_SWING_REG_CNT; 1601 1602 pdata->dp_lane1_swing_reg_cnt = num_regs; 1603 of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1604 pdata->lane1_reg_data, num_regs); 1605 } 1606 1607 return 0; 1608 } 1609 1610 static int anx7625_parse_dt(struct device *dev, 1611 struct anx7625_platform_data *pdata) 1612 { 1613 struct device_node *np = dev->of_node, *ep0; 1614 int bus_type, mipi_lanes; 1615 1616 anx7625_get_swing_setting(dev, pdata); 1617 1618 pdata->is_dpi = 1; /* default dpi mode */ 1619 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1620 if (!pdata->mipi_host_node) { 1621 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1622 return -ENODEV; 1623 } 1624 1625 bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1626 mipi_lanes = MAX_LANES_SUPPORT; 1627 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1628 if (ep0) { 1629 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1630 bus_type = 0; 1631 1632 mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1633 } 1634 1635 if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1636 pdata->is_dpi = 0; 1637 1638 pdata->mipi_lanes = mipi_lanes; 1639 if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1640 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1641 1642 if (pdata->is_dpi) 1643 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1644 else 1645 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1646 1647 if (of_property_read_bool(np, "analogix,audio-enable")) 1648 pdata->audio_en = 1; 1649 1650 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); 1651 if (IS_ERR(pdata->panel_bridge)) { 1652 if (PTR_ERR(pdata->panel_bridge) == -ENODEV) 1653 return 0; 1654 1655 return PTR_ERR(pdata->panel_bridge); 1656 } 1657 1658 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1659 1660 return 0; 1661 } 1662 1663 static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1664 { 1665 struct device_node *bus, *panel; 1666 1667 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1668 if (!bus) 1669 return false; 1670 1671 panel = of_get_child_by_name(bus, "panel"); 1672 of_node_put(bus); 1673 if (!panel) 1674 return false; 1675 of_node_put(panel); 1676 1677 return true; 1678 } 1679 1680 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1681 { 1682 return container_of(bridge, struct anx7625_data, bridge); 1683 } 1684 1685 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1686 struct drm_dp_aux_msg *msg) 1687 { 1688 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1689 struct device *dev = &ctx->client->dev; 1690 u8 request = msg->request & ~DP_AUX_I2C_MOT; 1691 int ret = 0; 1692 1693 pm_runtime_get_sync(dev); 1694 msg->reply = 0; 1695 switch (request) { 1696 case DP_AUX_NATIVE_WRITE: 1697 case DP_AUX_I2C_WRITE: 1698 case DP_AUX_NATIVE_READ: 1699 case DP_AUX_I2C_READ: 1700 break; 1701 default: 1702 ret = -EINVAL; 1703 } 1704 if (!ret) 1705 ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1706 msg->size, msg->buffer); 1707 pm_runtime_mark_last_busy(dev); 1708 pm_runtime_put_autosuspend(dev); 1709 1710 return ret; 1711 } 1712 1713 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1714 { 1715 struct device *dev = &ctx->client->dev; 1716 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1717 int edid_num; 1718 u8 *edid; 1719 1720 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1721 if (!edid) { 1722 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1723 return NULL; 1724 } 1725 1726 if (ctx->slimport_edid_p.edid_block_num > 0) { 1727 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1728 FOUR_BLOCK_SIZE); 1729 return (struct edid *)edid; 1730 } 1731 1732 pm_runtime_get_sync(dev); 1733 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1734 pm_runtime_put_sync(dev); 1735 1736 if (edid_num < 1) { 1737 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1738 kfree(edid); 1739 return NULL; 1740 } 1741 1742 p_edid->edid_block_num = edid_num; 1743 1744 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1745 return (struct edid *)edid; 1746 } 1747 1748 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1749 { 1750 struct device *dev = &ctx->client->dev; 1751 1752 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1753 1754 if (ctx->pdata.panel_bridge) 1755 return connector_status_connected; 1756 1757 return ctx->hpd_status ? connector_status_connected : 1758 connector_status_disconnected; 1759 } 1760 1761 static int anx7625_audio_hw_params(struct device *dev, void *data, 1762 struct hdmi_codec_daifmt *fmt, 1763 struct hdmi_codec_params *params) 1764 { 1765 struct anx7625_data *ctx = dev_get_drvdata(dev); 1766 int wl, ch, rate; 1767 int ret = 0; 1768 1769 if (fmt->fmt != HDMI_DSP_A) { 1770 DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1771 return -EINVAL; 1772 } 1773 1774 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1775 params->sample_rate, params->sample_width, 1776 params->cea.channels); 1777 1778 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1779 AUDIO_CHANNEL_STATUS_6, 1780 ~I2S_SLAVE_MODE, 1781 TDM_SLAVE_MODE); 1782 1783 /* Word length */ 1784 switch (params->sample_width) { 1785 case 16: 1786 wl = AUDIO_W_LEN_16_20MAX; 1787 break; 1788 case 18: 1789 wl = AUDIO_W_LEN_18_20MAX; 1790 break; 1791 case 20: 1792 wl = AUDIO_W_LEN_20_20MAX; 1793 break; 1794 case 24: 1795 wl = AUDIO_W_LEN_24_24MAX; 1796 break; 1797 default: 1798 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1799 params->sample_width); 1800 return -EINVAL; 1801 } 1802 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1803 AUDIO_CHANNEL_STATUS_5, 1804 0xf0, wl); 1805 1806 /* Channel num */ 1807 switch (params->cea.channels) { 1808 case 2: 1809 ch = I2S_CH_2; 1810 break; 1811 case 4: 1812 ch = TDM_CH_4; 1813 break; 1814 case 6: 1815 ch = TDM_CH_6; 1816 break; 1817 case 8: 1818 ch = TDM_CH_8; 1819 break; 1820 default: 1821 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1822 params->cea.channels); 1823 return -EINVAL; 1824 } 1825 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1826 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1827 if (ch > I2S_CH_2) 1828 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1829 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1830 else 1831 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1832 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1833 1834 /* FS */ 1835 switch (params->sample_rate) { 1836 case 32000: 1837 rate = AUDIO_FS_32K; 1838 break; 1839 case 44100: 1840 rate = AUDIO_FS_441K; 1841 break; 1842 case 48000: 1843 rate = AUDIO_FS_48K; 1844 break; 1845 case 88200: 1846 rate = AUDIO_FS_882K; 1847 break; 1848 case 96000: 1849 rate = AUDIO_FS_96K; 1850 break; 1851 case 176400: 1852 rate = AUDIO_FS_1764K; 1853 break; 1854 case 192000: 1855 rate = AUDIO_FS_192K; 1856 break; 1857 default: 1858 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1859 params->sample_rate); 1860 return -EINVAL; 1861 } 1862 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1863 AUDIO_CHANNEL_STATUS_4, 1864 0xf0, rate); 1865 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1866 AP_AV_STATUS, AP_AUDIO_CHG); 1867 if (ret < 0) { 1868 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1869 return -EIO; 1870 } 1871 1872 return 0; 1873 } 1874 1875 static void anx7625_audio_shutdown(struct device *dev, void *data) 1876 { 1877 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1878 } 1879 1880 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1881 struct device_node *endpoint) 1882 { 1883 struct of_endpoint of_ep; 1884 int ret; 1885 1886 ret = of_graph_parse_endpoint(endpoint, &of_ep); 1887 if (ret < 0) 1888 return ret; 1889 1890 /* 1891 * HDMI sound should be located at external DPI port 1892 * Didn't have good way to check where is internal(DSI) 1893 * or external(DPI) bridge 1894 */ 1895 return 0; 1896 } 1897 1898 static void 1899 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1900 enum drm_connector_status status) 1901 { 1902 if (ctx->plugged_cb && ctx->codec_dev) { 1903 ctx->plugged_cb(ctx->codec_dev, 1904 status == connector_status_connected); 1905 } 1906 } 1907 1908 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1909 hdmi_codec_plugged_cb fn, 1910 struct device *codec_dev) 1911 { 1912 struct anx7625_data *ctx = data; 1913 1914 ctx->plugged_cb = fn; 1915 ctx->codec_dev = codec_dev; 1916 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1917 1918 return 0; 1919 } 1920 1921 static int anx7625_audio_get_eld(struct device *dev, void *data, 1922 u8 *buf, size_t len) 1923 { 1924 struct anx7625_data *ctx = dev_get_drvdata(dev); 1925 1926 if (!ctx->connector) { 1927 dev_err(dev, "connector not initial\n"); 1928 return -EINVAL; 1929 } 1930 1931 dev_dbg(dev, "audio copy eld\n"); 1932 memcpy(buf, ctx->connector->eld, 1933 min(sizeof(ctx->connector->eld), len)); 1934 1935 return 0; 1936 } 1937 1938 static const struct hdmi_codec_ops anx7625_codec_ops = { 1939 .hw_params = anx7625_audio_hw_params, 1940 .audio_shutdown = anx7625_audio_shutdown, 1941 .get_eld = anx7625_audio_get_eld, 1942 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1943 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1944 }; 1945 1946 static void anx7625_unregister_audio(struct anx7625_data *ctx) 1947 { 1948 struct device *dev = &ctx->client->dev; 1949 1950 if (ctx->audio_pdev) { 1951 platform_device_unregister(ctx->audio_pdev); 1952 ctx->audio_pdev = NULL; 1953 } 1954 1955 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1956 } 1957 1958 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1959 { 1960 struct hdmi_codec_pdata codec_data = { 1961 .ops = &anx7625_codec_ops, 1962 .max_i2s_channels = 8, 1963 .i2s = 1, 1964 .data = ctx, 1965 }; 1966 1967 ctx->audio_pdev = platform_device_register_data(dev, 1968 HDMI_CODEC_DRV_NAME, 1969 PLATFORM_DEVID_AUTO, 1970 &codec_data, 1971 sizeof(codec_data)); 1972 1973 if (IS_ERR(ctx->audio_pdev)) 1974 return PTR_ERR(ctx->audio_pdev); 1975 1976 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1977 1978 return 0; 1979 } 1980 1981 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1982 { 1983 struct mipi_dsi_device *dsi; 1984 struct device *dev = &ctx->client->dev; 1985 struct mipi_dsi_host *host; 1986 const struct mipi_dsi_device_info info = { 1987 .type = "anx7625", 1988 .channel = 0, 1989 .node = NULL, 1990 }; 1991 int ret; 1992 1993 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1994 1995 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1996 if (!host) { 1997 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1998 return -EPROBE_DEFER; 1999 } 2000 2001 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2002 if (IS_ERR(dsi)) { 2003 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 2004 return -EINVAL; 2005 } 2006 2007 dsi->lanes = ctx->pdata.mipi_lanes; 2008 dsi->format = MIPI_DSI_FMT_RGB888; 2009 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 2010 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2011 MIPI_DSI_MODE_VIDEO_HSE | 2012 MIPI_DSI_HS_PKT_END_ALIGNED; 2013 2014 ret = devm_mipi_dsi_attach(dev, dsi); 2015 if (ret) { 2016 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 2017 return ret; 2018 } 2019 2020 ctx->dsi = dsi; 2021 2022 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 2023 2024 return 0; 2025 } 2026 2027 static void hdcp_check_work_func(struct work_struct *work) 2028 { 2029 u8 status; 2030 struct delayed_work *dwork; 2031 struct anx7625_data *ctx; 2032 struct device *dev; 2033 struct drm_device *drm_dev; 2034 2035 dwork = to_delayed_work(work); 2036 ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2037 dev = &ctx->client->dev; 2038 2039 if (!ctx->connector) { 2040 dev_err(dev, "HDCP connector is null!"); 2041 return; 2042 } 2043 2044 drm_dev = ctx->connector->dev; 2045 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2046 mutex_lock(&ctx->hdcp_wq_lock); 2047 2048 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2049 dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2050 if (status & BIT(1)) { 2051 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2052 drm_hdcp_update_content_protection(ctx->connector, 2053 ctx->hdcp_cp); 2054 dev_dbg(dev, "update CP to ENABLE\n"); 2055 } 2056 2057 mutex_unlock(&ctx->hdcp_wq_lock); 2058 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2059 } 2060 2061 static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2062 struct drm_connector_state *state) 2063 { 2064 struct device *dev = &ctx->client->dev; 2065 int cp; 2066 2067 dev_dbg(dev, "hdcp state check\n"); 2068 cp = state->content_protection; 2069 2070 if (cp == ctx->hdcp_cp) 2071 return 0; 2072 2073 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2074 if (ctx->dp_en) { 2075 dev_dbg(dev, "enable HDCP\n"); 2076 anx7625_hdcp_enable(ctx); 2077 2078 queue_delayed_work(ctx->hdcp_workqueue, 2079 &ctx->hdcp_work, 2080 msecs_to_jiffies(2000)); 2081 } 2082 } 2083 2084 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2085 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2086 dev_err(dev, "current CP is not ENABLED\n"); 2087 return -EINVAL; 2088 } 2089 anx7625_hdcp_disable(ctx); 2090 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2091 drm_hdcp_update_content_protection(ctx->connector, 2092 ctx->hdcp_cp); 2093 dev_dbg(dev, "update CP to UNDESIRE\n"); 2094 } 2095 2096 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2097 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2098 return -EINVAL; 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int anx7625_bridge_attach(struct drm_bridge *bridge, 2105 enum drm_bridge_attach_flags flags) 2106 { 2107 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2108 int err; 2109 struct device *dev = &ctx->client->dev; 2110 2111 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 2112 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 2113 return -EINVAL; 2114 2115 if (!bridge->encoder) { 2116 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 2117 return -ENODEV; 2118 } 2119 2120 ctx->aux.drm_dev = bridge->dev; 2121 err = drm_dp_aux_register(&ctx->aux); 2122 if (err) { 2123 dev_err(dev, "failed to register aux channel: %d\n", err); 2124 return err; 2125 } 2126 2127 if (ctx->pdata.panel_bridge) { 2128 err = drm_bridge_attach(bridge->encoder, 2129 ctx->pdata.panel_bridge, 2130 &ctx->bridge, flags); 2131 if (err) 2132 return err; 2133 } 2134 2135 ctx->bridge_attached = 1; 2136 2137 return 0; 2138 } 2139 2140 static void anx7625_bridge_detach(struct drm_bridge *bridge) 2141 { 2142 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2143 2144 drm_dp_aux_unregister(&ctx->aux); 2145 } 2146 2147 static enum drm_mode_status 2148 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 2149 const struct drm_display_info *info, 2150 const struct drm_display_mode *mode) 2151 { 2152 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2153 struct device *dev = &ctx->client->dev; 2154 2155 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 2156 2157 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 2158 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 2159 DRM_DEV_DEBUG_DRIVER(dev, 2160 "drm mode invalid, pixelclock too high.\n"); 2161 return MODE_CLOCK_HIGH; 2162 } 2163 2164 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 2165 2166 return MODE_OK; 2167 } 2168 2169 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 2170 const struct drm_display_mode *old_mode, 2171 const struct drm_display_mode *mode) 2172 { 2173 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2174 struct device *dev = &ctx->client->dev; 2175 2176 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 2177 2178 ctx->dt.pixelclock.min = mode->clock; 2179 ctx->dt.hactive.min = mode->hdisplay; 2180 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 2181 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 2182 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 2183 ctx->dt.vactive.min = mode->vdisplay; 2184 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 2185 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 2186 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 2187 2188 ctx->display_timing_valid = 1; 2189 2190 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 2191 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 2192 ctx->dt.hactive.min, 2193 ctx->dt.hsync_len.min, 2194 ctx->dt.hfront_porch.min, 2195 ctx->dt.hback_porch.min); 2196 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 2197 ctx->dt.vactive.min, 2198 ctx->dt.vsync_len.min, 2199 ctx->dt.vfront_porch.min, 2200 ctx->dt.vback_porch.min); 2201 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 2202 mode->hdisplay, 2203 mode->hsync_start); 2204 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 2205 mode->hsync_end, 2206 mode->htotal); 2207 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 2208 mode->vdisplay, 2209 mode->vsync_start); 2210 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 2211 mode->vsync_end, 2212 mode->vtotal); 2213 } 2214 2215 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 2216 const struct drm_display_mode *mode, 2217 struct drm_display_mode *adj) 2218 { 2219 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2220 struct device *dev = &ctx->client->dev; 2221 u32 hsync, hfp, hbp, hblanking; 2222 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 2223 u32 vref, adj_clock; 2224 2225 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 2226 2227 /* No need fixup for external monitor */ 2228 if (!ctx->pdata.panel_bridge) 2229 return true; 2230 2231 hsync = mode->hsync_end - mode->hsync_start; 2232 hfp = mode->hsync_start - mode->hdisplay; 2233 hbp = mode->htotal - mode->hsync_end; 2234 hblanking = mode->htotal - mode->hdisplay; 2235 2236 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 2237 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2238 hsync, hfp, hbp, adj->clock); 2239 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2240 adj->hsync_start, adj->hsync_end, adj->htotal); 2241 2242 adj_hfp = hfp; 2243 adj_hsync = hsync; 2244 adj_hbp = hbp; 2245 adj_hblanking = hblanking; 2246 2247 /* HFP needs to be even */ 2248 if (hfp & 0x1) { 2249 adj_hfp += 1; 2250 adj_hblanking += 1; 2251 } 2252 2253 /* HBP needs to be even */ 2254 if (hbp & 0x1) { 2255 adj_hbp -= 1; 2256 adj_hblanking -= 1; 2257 } 2258 2259 /* HSYNC needs to be even */ 2260 if (hsync & 0x1) { 2261 if (adj_hblanking < hblanking) 2262 adj_hsync += 1; 2263 else 2264 adj_hsync -= 1; 2265 } 2266 2267 /* 2268 * Once illegal timing detected, use default HFP, HSYNC, HBP 2269 * This adjusting made for built-in eDP panel, for the externel 2270 * DP monitor, may need return false. 2271 */ 2272 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 2273 adj_hsync = SYNC_LEN_DEF; 2274 adj_hfp = HFP_HBP_DEF; 2275 adj_hbp = HFP_HBP_DEF; 2276 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 2277 if (hblanking < HBLANKING_MIN) { 2278 delta_adj = HBLANKING_MIN - hblanking; 2279 adj_clock = vref * delta_adj * adj->vtotal; 2280 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 2281 } else { 2282 delta_adj = hblanking - HBLANKING_MIN; 2283 adj_clock = vref * delta_adj * adj->vtotal; 2284 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 2285 } 2286 2287 DRM_WARN("illegal hblanking timing, use default.\n"); 2288 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 2289 } else if (adj_hfp < HP_MIN) { 2290 /* Adjust hfp if hfp less than HP_MIN */ 2291 delta_adj = HP_MIN - adj_hfp; 2292 adj_hfp = HP_MIN; 2293 2294 /* 2295 * Balance total HBlanking pixel, if HBP does not have enough 2296 * space, adjust HSYNC length, otherwise adjust HBP 2297 */ 2298 if ((adj_hbp - delta_adj) < HP_MIN) 2299 /* HBP not enough space */ 2300 adj_hsync -= delta_adj; 2301 else 2302 adj_hbp -= delta_adj; 2303 } else if (adj_hbp < HP_MIN) { 2304 delta_adj = HP_MIN - adj_hbp; 2305 adj_hbp = HP_MIN; 2306 2307 /* 2308 * Balance total HBlanking pixel, if HBP hasn't enough space, 2309 * adjust HSYNC length, otherwize adjust HBP 2310 */ 2311 if ((adj_hfp - delta_adj) < HP_MIN) 2312 /* HFP not enough space */ 2313 adj_hsync -= delta_adj; 2314 else 2315 adj_hfp -= delta_adj; 2316 } 2317 2318 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 2319 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2320 adj_hsync, adj_hfp, adj_hbp, adj->clock); 2321 2322 /* Reconstruct timing */ 2323 adj->hsync_start = adj->hdisplay + adj_hfp; 2324 adj->hsync_end = adj->hsync_start + adj_hsync; 2325 adj->htotal = adj->hsync_end + adj_hbp; 2326 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2327 adj->hsync_start, adj->hsync_end, adj->htotal); 2328 2329 return true; 2330 } 2331 2332 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2333 struct drm_bridge_state *bridge_state, 2334 struct drm_crtc_state *crtc_state, 2335 struct drm_connector_state *conn_state) 2336 { 2337 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2338 struct device *dev = &ctx->client->dev; 2339 2340 dev_dbg(dev, "drm bridge atomic check\n"); 2341 2342 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2343 &crtc_state->adjusted_mode); 2344 2345 return anx7625_connector_atomic_check(ctx, conn_state); 2346 } 2347 2348 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2349 struct drm_bridge_state *state) 2350 { 2351 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2352 struct device *dev = &ctx->client->dev; 2353 struct drm_connector *connector; 2354 2355 dev_dbg(dev, "drm atomic enable\n"); 2356 2357 if (!bridge->encoder) { 2358 dev_err(dev, "Parent encoder object not found"); 2359 return; 2360 } 2361 2362 connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2363 bridge->encoder); 2364 if (!connector) 2365 return; 2366 2367 ctx->connector = connector; 2368 2369 pm_runtime_get_sync(dev); 2370 2371 anx7625_dp_start(ctx); 2372 } 2373 2374 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2375 struct drm_bridge_state *old) 2376 { 2377 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2378 struct device *dev = &ctx->client->dev; 2379 2380 dev_dbg(dev, "drm atomic disable\n"); 2381 2382 ctx->connector = NULL; 2383 anx7625_dp_stop(ctx); 2384 2385 pm_runtime_put_sync(dev); 2386 } 2387 2388 static enum drm_connector_status 2389 anx7625_bridge_detect(struct drm_bridge *bridge) 2390 { 2391 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2392 struct device *dev = &ctx->client->dev; 2393 2394 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 2395 2396 return anx7625_sink_detect(ctx); 2397 } 2398 2399 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 2400 struct drm_connector *connector) 2401 { 2402 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2403 struct device *dev = &ctx->client->dev; 2404 2405 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 2406 2407 return anx7625_get_edid(ctx); 2408 } 2409 2410 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 2411 .attach = anx7625_bridge_attach, 2412 .detach = anx7625_bridge_detach, 2413 .mode_valid = anx7625_bridge_mode_valid, 2414 .mode_set = anx7625_bridge_mode_set, 2415 .atomic_check = anx7625_bridge_atomic_check, 2416 .atomic_enable = anx7625_bridge_atomic_enable, 2417 .atomic_disable = anx7625_bridge_atomic_disable, 2418 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2419 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2420 .atomic_reset = drm_atomic_helper_bridge_reset, 2421 .detect = anx7625_bridge_detect, 2422 .get_edid = anx7625_bridge_get_edid, 2423 }; 2424 2425 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 2426 struct i2c_client *client) 2427 { 2428 int err = 0; 2429 2430 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 2431 TX_P0_ADDR >> 1); 2432 if (IS_ERR(ctx->i2c.tx_p0_client)) 2433 return PTR_ERR(ctx->i2c.tx_p0_client); 2434 2435 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 2436 TX_P1_ADDR >> 1); 2437 if (IS_ERR(ctx->i2c.tx_p1_client)) { 2438 err = PTR_ERR(ctx->i2c.tx_p1_client); 2439 goto free_tx_p0; 2440 } 2441 2442 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 2443 TX_P2_ADDR >> 1); 2444 if (IS_ERR(ctx->i2c.tx_p2_client)) { 2445 err = PTR_ERR(ctx->i2c.tx_p2_client); 2446 goto free_tx_p1; 2447 } 2448 2449 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 2450 RX_P0_ADDR >> 1); 2451 if (IS_ERR(ctx->i2c.rx_p0_client)) { 2452 err = PTR_ERR(ctx->i2c.rx_p0_client); 2453 goto free_tx_p2; 2454 } 2455 2456 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 2457 RX_P1_ADDR >> 1); 2458 if (IS_ERR(ctx->i2c.rx_p1_client)) { 2459 err = PTR_ERR(ctx->i2c.rx_p1_client); 2460 goto free_rx_p0; 2461 } 2462 2463 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 2464 RX_P2_ADDR >> 1); 2465 if (IS_ERR(ctx->i2c.rx_p2_client)) { 2466 err = PTR_ERR(ctx->i2c.rx_p2_client); 2467 goto free_rx_p1; 2468 } 2469 2470 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 2471 TCPC_INTERFACE_ADDR >> 1); 2472 if (IS_ERR(ctx->i2c.tcpc_client)) { 2473 err = PTR_ERR(ctx->i2c.tcpc_client); 2474 goto free_rx_p2; 2475 } 2476 2477 return 0; 2478 2479 free_rx_p2: 2480 i2c_unregister_device(ctx->i2c.rx_p2_client); 2481 free_rx_p1: 2482 i2c_unregister_device(ctx->i2c.rx_p1_client); 2483 free_rx_p0: 2484 i2c_unregister_device(ctx->i2c.rx_p0_client); 2485 free_tx_p2: 2486 i2c_unregister_device(ctx->i2c.tx_p2_client); 2487 free_tx_p1: 2488 i2c_unregister_device(ctx->i2c.tx_p1_client); 2489 free_tx_p0: 2490 i2c_unregister_device(ctx->i2c.tx_p0_client); 2491 2492 return err; 2493 } 2494 2495 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 2496 { 2497 i2c_unregister_device(ctx->i2c.tx_p0_client); 2498 i2c_unregister_device(ctx->i2c.tx_p1_client); 2499 i2c_unregister_device(ctx->i2c.tx_p2_client); 2500 i2c_unregister_device(ctx->i2c.rx_p0_client); 2501 i2c_unregister_device(ctx->i2c.rx_p1_client); 2502 i2c_unregister_device(ctx->i2c.rx_p2_client); 2503 i2c_unregister_device(ctx->i2c.tcpc_client); 2504 } 2505 2506 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2507 { 2508 struct anx7625_data *ctx = dev_get_drvdata(dev); 2509 2510 mutex_lock(&ctx->lock); 2511 2512 anx7625_stop_dp_work(ctx); 2513 anx7625_power_standby(ctx); 2514 2515 mutex_unlock(&ctx->lock); 2516 2517 return 0; 2518 } 2519 2520 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2521 { 2522 struct anx7625_data *ctx = dev_get_drvdata(dev); 2523 2524 mutex_lock(&ctx->lock); 2525 2526 anx7625_power_on_init(ctx); 2527 anx7625_hpd_polling(ctx); 2528 2529 mutex_unlock(&ctx->lock); 2530 2531 return 0; 2532 } 2533 2534 static int __maybe_unused anx7625_resume(struct device *dev) 2535 { 2536 struct anx7625_data *ctx = dev_get_drvdata(dev); 2537 2538 if (!ctx->pdata.intp_irq) 2539 return 0; 2540 2541 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2542 enable_irq(ctx->pdata.intp_irq); 2543 anx7625_runtime_pm_resume(dev); 2544 } 2545 2546 return 0; 2547 } 2548 2549 static int __maybe_unused anx7625_suspend(struct device *dev) 2550 { 2551 struct anx7625_data *ctx = dev_get_drvdata(dev); 2552 2553 if (!ctx->pdata.intp_irq) 2554 return 0; 2555 2556 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2557 anx7625_runtime_pm_suspend(dev); 2558 disable_irq(ctx->pdata.intp_irq); 2559 } 2560 2561 return 0; 2562 } 2563 2564 static const struct dev_pm_ops anx7625_pm_ops = { 2565 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 2566 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2567 anx7625_runtime_pm_resume, NULL) 2568 }; 2569 2570 static void anx7625_runtime_disable(void *data) 2571 { 2572 pm_runtime_dont_use_autosuspend(data); 2573 pm_runtime_disable(data); 2574 } 2575 2576 static int anx7625_i2c_probe(struct i2c_client *client, 2577 const struct i2c_device_id *id) 2578 { 2579 struct anx7625_data *platform; 2580 struct anx7625_platform_data *pdata; 2581 int ret = 0; 2582 struct device *dev = &client->dev; 2583 2584 if (!i2c_check_functionality(client->adapter, 2585 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2586 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2587 return -ENODEV; 2588 } 2589 2590 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL); 2591 if (!platform) { 2592 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2593 return -ENOMEM; 2594 } 2595 2596 pdata = &platform->pdata; 2597 2598 platform->client = client; 2599 i2c_set_clientdata(client, platform); 2600 2601 pdata->supplies[0].supply = "vdd10"; 2602 pdata->supplies[1].supply = "vdd18"; 2603 pdata->supplies[2].supply = "vdd33"; 2604 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2605 pdata->supplies); 2606 if (ret) { 2607 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2608 return ret; 2609 } 2610 anx7625_init_gpio(platform); 2611 2612 mutex_init(&platform->lock); 2613 mutex_init(&platform->hdcp_wq_lock); 2614 2615 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2616 platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2617 if (!platform->hdcp_workqueue) { 2618 dev_err(dev, "fail to create work queue\n"); 2619 ret = -ENOMEM; 2620 return ret; 2621 } 2622 2623 platform->pdata.intp_irq = client->irq; 2624 if (platform->pdata.intp_irq) { 2625 INIT_WORK(&platform->work, anx7625_work_func); 2626 platform->workqueue = alloc_workqueue("anx7625_work", 2627 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2628 if (!platform->workqueue) { 2629 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2630 ret = -ENOMEM; 2631 goto free_hdcp_wq; 2632 } 2633 2634 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2635 NULL, anx7625_intr_hpd_isr, 2636 IRQF_TRIGGER_FALLING | 2637 IRQF_ONESHOT, 2638 "anx7625-intp", platform); 2639 if (ret) { 2640 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2641 goto free_wq; 2642 } 2643 } 2644 2645 platform->aux.name = "anx7625-aux"; 2646 platform->aux.dev = dev; 2647 platform->aux.transfer = anx7625_aux_transfer; 2648 drm_dp_aux_init(&platform->aux); 2649 devm_of_dp_aux_populate_ep_devices(&platform->aux); 2650 2651 ret = anx7625_parse_dt(dev, pdata); 2652 if (ret) { 2653 if (ret != -EPROBE_DEFER) 2654 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2655 return ret; 2656 } 2657 2658 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2659 ret = -ENOMEM; 2660 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2661 goto free_wq; 2662 } 2663 2664 pm_runtime_enable(dev); 2665 pm_runtime_set_autosuspend_delay(dev, 1000); 2666 pm_runtime_use_autosuspend(dev); 2667 pm_suspend_ignore_children(dev, true); 2668 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev); 2669 if (ret) 2670 return ret; 2671 2672 if (!platform->pdata.low_power_mode) { 2673 anx7625_disable_pd_protocol(platform); 2674 pm_runtime_get_sync(dev); 2675 } 2676 2677 /* Add work function */ 2678 if (platform->pdata.intp_irq) 2679 queue_work(platform->workqueue, &platform->work); 2680 2681 platform->bridge.funcs = &anx7625_bridge_funcs; 2682 platform->bridge.of_node = client->dev.of_node; 2683 if (!anx7625_of_panel_on_aux_bus(&client->dev)) 2684 platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 2685 if (!platform->pdata.panel_bridge) 2686 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2687 DRM_BRIDGE_OP_DETECT; 2688 platform->bridge.type = platform->pdata.panel_bridge ? 2689 DRM_MODE_CONNECTOR_eDP : 2690 DRM_MODE_CONNECTOR_DisplayPort; 2691 2692 drm_bridge_add(&platform->bridge); 2693 2694 if (!platform->pdata.is_dpi) { 2695 ret = anx7625_attach_dsi(platform); 2696 if (ret) { 2697 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 2698 goto unregister_bridge; 2699 } 2700 } 2701 2702 if (platform->pdata.audio_en) 2703 anx7625_register_audio(dev, platform); 2704 2705 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2706 2707 return 0; 2708 2709 unregister_bridge: 2710 drm_bridge_remove(&platform->bridge); 2711 2712 if (!platform->pdata.low_power_mode) 2713 pm_runtime_put_sync_suspend(&client->dev); 2714 2715 anx7625_unregister_i2c_dummy_clients(platform); 2716 2717 free_wq: 2718 if (platform->workqueue) 2719 destroy_workqueue(platform->workqueue); 2720 2721 free_hdcp_wq: 2722 if (platform->hdcp_workqueue) 2723 destroy_workqueue(platform->hdcp_workqueue); 2724 2725 return ret; 2726 } 2727 2728 static int anx7625_i2c_remove(struct i2c_client *client) 2729 { 2730 struct anx7625_data *platform = i2c_get_clientdata(client); 2731 2732 drm_bridge_remove(&platform->bridge); 2733 2734 if (platform->pdata.intp_irq) 2735 destroy_workqueue(platform->workqueue); 2736 2737 if (platform->hdcp_workqueue) { 2738 cancel_delayed_work(&platform->hdcp_work); 2739 flush_workqueue(platform->hdcp_workqueue); 2740 destroy_workqueue(platform->hdcp_workqueue); 2741 } 2742 2743 if (!platform->pdata.low_power_mode) 2744 pm_runtime_put_sync_suspend(&client->dev); 2745 2746 anx7625_unregister_i2c_dummy_clients(platform); 2747 2748 if (platform->pdata.audio_en) 2749 anx7625_unregister_audio(platform); 2750 2751 return 0; 2752 } 2753 2754 static const struct i2c_device_id anx7625_id[] = { 2755 {"anx7625", 0}, 2756 {} 2757 }; 2758 2759 MODULE_DEVICE_TABLE(i2c, anx7625_id); 2760 2761 static const struct of_device_id anx_match_table[] = { 2762 {.compatible = "analogix,anx7625",}, 2763 {}, 2764 }; 2765 MODULE_DEVICE_TABLE(of, anx_match_table); 2766 2767 static struct i2c_driver anx7625_driver = { 2768 .driver = { 2769 .name = "anx7625", 2770 .of_match_table = anx_match_table, 2771 .pm = &anx7625_pm_ops, 2772 }, 2773 .probe = anx7625_i2c_probe, 2774 .remove = anx7625_i2c_remove, 2775 2776 .id_table = anx7625_id, 2777 }; 2778 2779 module_i2c_driver(anx7625_driver); 2780 2781 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 2782 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 2783 MODULE_LICENSE("GPL v2"); 2784 MODULE_VERSION(ANX7625_DRV_VERSION); 2785