1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/dp/drm_dp_aux_bus.h> 28 #include <drm/dp/drm_dp_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_hdcp.h> 31 #include <drm/drm_mipi_dsi.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_panel.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include <media/v4l2-fwnode.h> 38 #include <sound/hdmi-codec.h> 39 #include <video/display_timing.h> 40 41 #include "anx7625.h" 42 43 /* 44 * There is a sync issue while access I2C register between AP(CPU) and 45 * internal firmware(OCM), to avoid the race condition, AP should access 46 * the reserved slave address before slave address occurs changes. 47 */ 48 static int i2c_access_workaround(struct anx7625_data *ctx, 49 struct i2c_client *client) 50 { 51 u8 offset; 52 struct device *dev = &client->dev; 53 int ret; 54 55 if (client == ctx->last_client) 56 return 0; 57 58 ctx->last_client = client; 59 60 if (client == ctx->i2c.tcpc_client) 61 offset = RSVD_00_ADDR; 62 else if (client == ctx->i2c.tx_p0_client) 63 offset = RSVD_D1_ADDR; 64 else if (client == ctx->i2c.tx_p1_client) 65 offset = RSVD_60_ADDR; 66 else if (client == ctx->i2c.rx_p0_client) 67 offset = RSVD_39_ADDR; 68 else if (client == ctx->i2c.rx_p1_client) 69 offset = RSVD_7F_ADDR; 70 else 71 offset = RSVD_00_ADDR; 72 73 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 74 if (ret < 0) 75 DRM_DEV_ERROR(dev, 76 "fail to access i2c id=%x\n:%x", 77 client->addr, offset); 78 79 return ret; 80 } 81 82 static int anx7625_reg_read(struct anx7625_data *ctx, 83 struct i2c_client *client, u8 reg_addr) 84 { 85 int ret; 86 struct device *dev = &client->dev; 87 88 i2c_access_workaround(ctx, client); 89 90 ret = i2c_smbus_read_byte_data(client, reg_addr); 91 if (ret < 0) 92 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 93 client->addr, reg_addr); 94 95 return ret; 96 } 97 98 static int anx7625_reg_block_read(struct anx7625_data *ctx, 99 struct i2c_client *client, 100 u8 reg_addr, u8 len, u8 *buf) 101 { 102 int ret; 103 struct device *dev = &client->dev; 104 105 i2c_access_workaround(ctx, client); 106 107 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 108 if (ret < 0) 109 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 110 client->addr, reg_addr); 111 112 return ret; 113 } 114 115 static int anx7625_reg_write(struct anx7625_data *ctx, 116 struct i2c_client *client, 117 u8 reg_addr, u8 reg_val) 118 { 119 int ret; 120 struct device *dev = &client->dev; 121 122 i2c_access_workaround(ctx, client); 123 124 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 125 126 if (ret < 0) 127 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 128 client->addr, reg_addr); 129 130 return ret; 131 } 132 133 static int anx7625_reg_block_write(struct anx7625_data *ctx, 134 struct i2c_client *client, 135 u8 reg_addr, u8 len, u8 *buf) 136 { 137 int ret; 138 struct device *dev = &client->dev; 139 140 i2c_access_workaround(ctx, client); 141 142 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 143 if (ret < 0) 144 dev_err(dev, "write i2c block failed id=%x\n:%x", 145 client->addr, reg_addr); 146 147 return ret; 148 } 149 150 static int anx7625_write_or(struct anx7625_data *ctx, 151 struct i2c_client *client, 152 u8 offset, u8 mask) 153 { 154 int val; 155 156 val = anx7625_reg_read(ctx, client, offset); 157 if (val < 0) 158 return val; 159 160 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 161 } 162 163 static int anx7625_write_and(struct anx7625_data *ctx, 164 struct i2c_client *client, 165 u8 offset, u8 mask) 166 { 167 int val; 168 169 val = anx7625_reg_read(ctx, client, offset); 170 if (val < 0) 171 return val; 172 173 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 174 } 175 176 static int anx7625_write_and_or(struct anx7625_data *ctx, 177 struct i2c_client *client, 178 u8 offset, u8 and_mask, u8 or_mask) 179 { 180 int val; 181 182 val = anx7625_reg_read(ctx, client, offset); 183 if (val < 0) 184 return val; 185 186 return anx7625_reg_write(ctx, client, 187 offset, (val & and_mask) | (or_mask)); 188 } 189 190 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 191 { 192 int i, ret; 193 194 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 195 AUDIO_CONTROL_REGISTER, 0x80); 196 for (i = 0; i < 13; i++) 197 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 198 VIDEO_BIT_MATRIX_12 + i, 199 0x18 + i); 200 201 return ret; 202 } 203 204 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 205 { 206 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 207 } 208 209 static int wait_aux_op_finish(struct anx7625_data *ctx) 210 { 211 struct device *dev = &ctx->client->dev; 212 int val; 213 int ret; 214 215 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 216 ctx, val, 217 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 218 2000, 219 2000 * 150); 220 if (ret) { 221 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 222 return -EIO; 223 } 224 225 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 226 AP_AUX_CTRL_STATUS); 227 if (val < 0 || (val & 0x0F)) { 228 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 229 return -EIO; 230 } 231 232 return 0; 233 } 234 235 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 236 u8 len, u8 *buf) 237 { 238 struct device *dev = &ctx->client->dev; 239 int ret; 240 u8 addrh, addrm, addrl; 241 u8 cmd; 242 bool is_write = !(op & DP_AUX_I2C_READ); 243 244 if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 245 dev_err(dev, "exceed aux buffer len.\n"); 246 return -EINVAL; 247 } 248 249 if (!len) 250 return len; 251 252 addrl = address & 0xFF; 253 addrm = (address >> 8) & 0xFF; 254 addrh = (address >> 16) & 0xFF; 255 256 if (!is_write) 257 op &= ~DP_AUX_I2C_MOT; 258 cmd = DPCD_CMD(len, op); 259 260 /* Set command and length */ 261 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 262 AP_AUX_COMMAND, cmd); 263 264 /* Set aux access address */ 265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 266 AP_AUX_ADDR_7_0, addrl); 267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 268 AP_AUX_ADDR_15_8, addrm); 269 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 270 AP_AUX_ADDR_19_16, addrh); 271 272 if (is_write) 273 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 274 AP_AUX_BUFF_START, len, buf); 275 /* Enable aux access */ 276 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 277 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 278 279 if (ret < 0) { 280 dev_err(dev, "cannot access aux related register.\n"); 281 return -EIO; 282 } 283 284 ret = wait_aux_op_finish(ctx); 285 if (ret < 0) { 286 dev_err(dev, "aux IO error: wait aux op finish.\n"); 287 return ret; 288 } 289 290 /* Write done */ 291 if (is_write) 292 return len; 293 294 /* Read done, read out dpcd data */ 295 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 296 AP_AUX_BUFF_START, len, buf); 297 if (ret < 0) { 298 dev_err(dev, "read dpcd register failed\n"); 299 return -EIO; 300 } 301 302 return len; 303 } 304 305 static int anx7625_video_mute_control(struct anx7625_data *ctx, 306 u8 status) 307 { 308 int ret; 309 310 if (status) { 311 /* Set mute on flag */ 312 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 313 AP_AV_STATUS, AP_MIPI_MUTE); 314 /* Clear mipi RX en */ 315 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 316 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 317 } else { 318 /* Mute off flag */ 319 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 320 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 321 /* Set MIPI RX EN */ 322 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 323 AP_AV_STATUS, AP_MIPI_RX_EN); 324 } 325 326 return ret; 327 } 328 329 /* Reduction of fraction a/b */ 330 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 331 { 332 unsigned long gcd_num; 333 unsigned long tmp_a, tmp_b; 334 u32 i = 1; 335 336 gcd_num = gcd(*a, *b); 337 *a /= gcd_num; 338 *b /= gcd_num; 339 340 tmp_a = *a; 341 tmp_b = *b; 342 343 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 344 i++; 345 *a = tmp_a / i; 346 *b = tmp_b / i; 347 } 348 349 /* 350 * In the end, make a, b larger to have higher ODFC PLL 351 * output frequency accuracy 352 */ 353 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 354 *a <<= 1; 355 *b <<= 1; 356 } 357 358 *a >>= 1; 359 *b >>= 1; 360 } 361 362 static int anx7625_calculate_m_n(u32 pixelclock, 363 unsigned long *m, 364 unsigned long *n, 365 u8 *post_divider) 366 { 367 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 368 /* Pixel clock frequency is too high */ 369 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 370 pixelclock, 371 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 372 return -EINVAL; 373 } 374 375 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 376 /* Pixel clock frequency is too low */ 377 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 378 pixelclock, 379 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 380 return -EINVAL; 381 } 382 383 for (*post_divider = 1; 384 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 385 *post_divider += 1; 386 387 if (*post_divider > POST_DIVIDER_MAX) { 388 for (*post_divider = 1; 389 (pixelclock < 390 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 391 *post_divider += 1; 392 393 if (*post_divider > POST_DIVIDER_MAX) { 394 DRM_ERROR("cannot find property post_divider(%d)\n", 395 *post_divider); 396 return -EDOM; 397 } 398 } 399 400 /* Patch to improve the accuracy */ 401 if (*post_divider == 7) { 402 /* 27,000,000 is not divisible by 7 */ 403 *post_divider = 8; 404 } else if (*post_divider == 11) { 405 /* 27,000,000 is not divisible by 11 */ 406 *post_divider = 12; 407 } else if ((*post_divider == 13) || (*post_divider == 14)) { 408 /* 27,000,000 is not divisible by 13 or 14 */ 409 *post_divider = 15; 410 } 411 412 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 413 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 414 pixelclock * (*post_divider), 415 PLL_OUT_FREQ_ABS_MAX); 416 return -EDOM; 417 } 418 419 *m = pixelclock; 420 *n = XTAL_FRQ / (*post_divider); 421 422 anx7625_reduction_of_a_fraction(m, n); 423 424 return 0; 425 } 426 427 static int anx7625_odfc_config(struct anx7625_data *ctx, 428 u8 post_divider) 429 { 430 int ret; 431 struct device *dev = &ctx->client->dev; 432 433 /* Config input reference clock frequency 27MHz/19.2MHz */ 434 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 435 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 436 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 437 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 438 /* Post divider */ 439 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 440 MIPI_DIGITAL_PLL_8, 0x0f); 441 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 442 post_divider << 4); 443 444 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 445 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 446 ~MIPI_PLL_VCO_TUNE_REG_VAL); 447 448 /* Reset ODFC PLL */ 449 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 450 ~MIPI_PLL_RESET_N); 451 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 452 MIPI_PLL_RESET_N); 453 454 if (ret < 0) 455 DRM_DEV_ERROR(dev, "IO error.\n"); 456 457 return ret; 458 } 459 460 /* 461 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 462 * anx7625 defined K ratio for matching MIPI input video clock and 463 * DP output video clock. Increase K value can match bigger video data 464 * variation. IVO panel has small variation than DP CTS spec, need 465 * decrease the K value. 466 */ 467 static int anx7625_set_k_value(struct anx7625_data *ctx) 468 { 469 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 470 471 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 472 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 473 MIPI_DIGITAL_ADJ_1, 0x3B); 474 475 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 476 MIPI_DIGITAL_ADJ_1, 0x3D); 477 } 478 479 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 480 { 481 struct device *dev = &ctx->client->dev; 482 unsigned long m, n; 483 u16 htotal; 484 int ret; 485 u8 post_divider = 0; 486 487 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 488 &m, &n, &post_divider); 489 490 if (ret) { 491 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 492 return ret; 493 } 494 495 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 496 m, n, post_divider); 497 498 /* Configure pixel clock */ 499 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 500 (ctx->dt.pixelclock.min / 1000) & 0xFF); 501 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 502 (ctx->dt.pixelclock.min / 1000) >> 8); 503 /* Lane count */ 504 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 505 MIPI_LANE_CTRL_0, 0xfc); 506 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 507 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 508 509 /* Htotal */ 510 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 511 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 513 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 514 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 515 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 516 /* Hactive */ 517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 518 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 519 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 520 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 521 /* HFP */ 522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 523 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 524 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 525 HORIZONTAL_FRONT_PORCH_H, 526 ctx->dt.hfront_porch.min >> 8); 527 /* HWS */ 528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 529 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 530 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 531 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 532 /* HBP */ 533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 534 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 535 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 536 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 537 /* Vactive */ 538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 539 ctx->dt.vactive.min); 540 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 541 ctx->dt.vactive.min >> 8); 542 /* VFP */ 543 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 544 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 545 /* VWS */ 546 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 547 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 548 /* VBP */ 549 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 550 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 551 /* M value */ 552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 553 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 555 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 556 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 557 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 558 /* N value */ 559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 560 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 562 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 563 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 564 (n & 0xff)); 565 566 anx7625_set_k_value(ctx); 567 568 ret |= anx7625_odfc_config(ctx, post_divider - 1); 569 570 if (ret < 0) 571 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 572 573 return ret; 574 } 575 576 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 577 { 578 int val; 579 struct device *dev = &ctx->client->dev; 580 581 /* Swap MIPI-DSI data lane 3 P and N */ 582 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 583 if (val < 0) { 584 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 585 return -EIO; 586 } 587 588 val |= (1 << MIPI_SWAP_CH3); 589 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 590 } 591 592 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 593 594 { 595 int val, ret; 596 struct device *dev = &ctx->client->dev; 597 598 /* Swap MIPI-DSI data lane 3 P and N */ 599 ret = anx7625_swap_dsi_lane3(ctx); 600 if (ret < 0) { 601 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 602 return ret; 603 } 604 605 /* DSI clock settings */ 606 val = (0 << MIPI_HS_PWD_CLK) | 607 (0 << MIPI_HS_RT_CLK) | 608 (0 << MIPI_PD_CLK) | 609 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 610 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 611 (0 << MIPI_CLK_DET_DET_BYPASS) | 612 (0 << MIPI_CLK_MISS_CTRL) | 613 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 614 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 615 MIPI_PHY_CONTROL_3, val); 616 617 /* 618 * Decreased HS prepare timing delay from 160ns to 80ns work with 619 * a) Dragon board 810 series (Qualcomm AP) 620 * b) Moving Pixel DSI source (PG3A pattern generator + 621 * P332 D-PHY Probe) default D-PHY timing 622 * 5ns/step 623 */ 624 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 625 MIPI_TIME_HS_PRPR, 0x10); 626 627 /* Enable DSI mode*/ 628 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 629 SELECT_DSI << MIPI_DPI_SELECT); 630 631 ret |= anx7625_dsi_video_timing_config(ctx); 632 if (ret < 0) { 633 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 634 return ret; 635 } 636 637 /* Toggle m, n ready */ 638 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 639 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 640 usleep_range(1000, 1100); 641 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 642 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 643 644 /* Configure integer stable register */ 645 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 646 MIPI_VIDEO_STABLE_CNT, 0x02); 647 /* Power on MIPI RX */ 648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 649 MIPI_LANE_CTRL_10, 0x00); 650 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 651 MIPI_LANE_CTRL_10, 0x80); 652 653 if (ret < 0) 654 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 655 656 return ret; 657 } 658 659 static int anx7625_dsi_config(struct anx7625_data *ctx) 660 { 661 struct device *dev = &ctx->client->dev; 662 int ret; 663 664 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 665 666 /* DSC disable */ 667 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 668 R_DSC_CTRL_0, ~DSC_EN); 669 670 ret |= anx7625_api_dsi_config(ctx); 671 672 if (ret < 0) { 673 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 674 return ret; 675 } 676 677 /* Set MIPI RX EN */ 678 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 679 AP_AV_STATUS, AP_MIPI_RX_EN); 680 /* Clear mute flag */ 681 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 682 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 683 if (ret < 0) 684 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 685 else 686 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 687 688 return ret; 689 } 690 691 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 692 { 693 struct device *dev = &ctx->client->dev; 694 u16 freq = ctx->dt.pixelclock.min / 1000; 695 int ret; 696 697 /* configure pixel clock */ 698 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 699 PIXEL_CLOCK_L, freq & 0xFF); 700 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 701 PIXEL_CLOCK_H, (freq >> 8)); 702 703 /* set DPI mode */ 704 /* set to DPI PLL module sel */ 705 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 706 MIPI_DIGITAL_PLL_9, 0x20); 707 /* power down MIPI */ 708 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 709 MIPI_LANE_CTRL_10, 0x08); 710 /* enable DPI mode */ 711 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 712 MIPI_DIGITAL_PLL_18, 0x1C); 713 /* set first edge */ 714 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 715 VIDEO_CONTROL_0, 0x06); 716 if (ret < 0) 717 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 718 719 return ret; 720 } 721 722 static int anx7625_dpi_config(struct anx7625_data *ctx) 723 { 724 struct device *dev = &ctx->client->dev; 725 int ret; 726 727 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 728 729 /* DSC disable */ 730 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 731 R_DSC_CTRL_0, ~DSC_EN); 732 if (ret < 0) { 733 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 734 return ret; 735 } 736 737 ret = anx7625_config_bit_matrix(ctx); 738 if (ret < 0) { 739 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 740 return ret; 741 } 742 743 ret = anx7625_api_dpi_config(ctx); 744 if (ret < 0) { 745 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 746 return ret; 747 } 748 749 /* set MIPI RX EN */ 750 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 751 AP_AV_STATUS, AP_MIPI_RX_EN); 752 /* clear mute flag */ 753 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 754 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 755 if (ret < 0) 756 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 757 758 return ret; 759 } 760 761 static int anx7625_read_flash_status(struct anx7625_data *ctx) 762 { 763 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 764 } 765 766 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 767 { 768 int ret, val; 769 struct device *dev = &ctx->client->dev; 770 u8 ident[FLASH_BUF_LEN]; 771 772 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 773 FLASH_ADDR_HIGH, 0x91); 774 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 775 FLASH_ADDR_LOW, 0xA0); 776 if (ret < 0) { 777 dev_err(dev, "IO error : set key flash address.\n"); 778 return ret; 779 } 780 781 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 782 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 783 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 784 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 785 if (ret < 0) { 786 dev_err(dev, "IO error : set key flash len.\n"); 787 return ret; 788 } 789 790 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 791 R_FLASH_RW_CTRL, FLASH_READ); 792 ret |= readx_poll_timeout(anx7625_read_flash_status, 793 ctx, val, 794 ((val & FLASH_DONE) || (val < 0)), 795 2000, 796 2000 * 150); 797 if (ret) { 798 dev_err(dev, "flash read access fail!\n"); 799 return -EIO; 800 } 801 802 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 803 FLASH_BUF_BASE_ADDR, 804 FLASH_BUF_LEN, ident); 805 if (ret < 0) { 806 dev_err(dev, "read flash data fail!\n"); 807 return -EIO; 808 } 809 810 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 811 return -EINVAL; 812 813 return 0; 814 } 815 816 static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 817 { 818 int ret; 819 struct device *dev = &ctx->client->dev; 820 821 /* Select HDCP 1.4 KEY */ 822 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 823 R_BOOT_RETRY, 0x12); 824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 825 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 830 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 831 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 832 833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 834 R_RAM_ADDR_H, 0); 835 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 836 R_RAM_ADDR_L, 0); 837 /* Enable HDCP 1.4 KEY load */ 838 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 839 R_RAM_CTRL, DECRYPT_EN | LOAD_START); 840 dev_dbg(dev, "load HDCP 1.4 key done\n"); 841 return ret; 842 } 843 844 static int anx7625_hdcp_disable(struct anx7625_data *ctx) 845 { 846 int ret; 847 struct device *dev = &ctx->client->dev; 848 849 dev_dbg(dev, "disable HDCP 1.4\n"); 850 851 /* Disable HDCP */ 852 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 853 /* Try auth flag */ 854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 855 /* Interrupt for DRM */ 856 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 857 if (ret < 0) 858 dev_err(dev, "fail to disable HDCP\n"); 859 860 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 861 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 862 } 863 864 static int anx7625_hdcp_enable(struct anx7625_data *ctx) 865 { 866 u8 bcap; 867 int ret; 868 struct device *dev = &ctx->client->dev; 869 870 ret = anx7625_hdcp_key_probe(ctx); 871 if (ret) { 872 dev_dbg(dev, "no key found, not to do hdcp\n"); 873 return ret; 874 } 875 876 /* Read downstream capability */ 877 anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap); 878 if (!(bcap & 0x01)) { 879 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 880 return 0; 881 } 882 883 dev_dbg(dev, "enable HDCP 1.4\n"); 884 885 /* First clear HDCP state */ 886 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 887 TX_HDCP_CTRL0, 888 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 889 usleep_range(1000, 1100); 890 /* Second clear HDCP state */ 891 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 892 TX_HDCP_CTRL0, 893 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 894 895 /* Set time for waiting KSVR */ 896 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 897 SP_TX_WAIT_KSVR_TIME, 0xc8); 898 /* Set time for waiting R0 */ 899 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 900 SP_TX_WAIT_R0_TIME, 0xb0); 901 ret |= anx7625_hdcp_key_load(ctx); 902 if (ret) { 903 pr_warn("prepare HDCP key failed.\n"); 904 return ret; 905 } 906 907 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 908 909 /* Try auth flag */ 910 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 911 /* Interrupt for DRM */ 912 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 913 if (ret < 0) 914 dev_err(dev, "fail to enable HDCP\n"); 915 916 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 917 TX_HDCP_CTRL0, HARD_AUTH_EN); 918 } 919 920 static void anx7625_dp_start(struct anx7625_data *ctx) 921 { 922 int ret; 923 struct device *dev = &ctx->client->dev; 924 925 if (!ctx->display_timing_valid) { 926 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 927 return; 928 } 929 930 /* Disable HDCP */ 931 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 932 933 if (ctx->pdata.is_dpi) 934 ret = anx7625_dpi_config(ctx); 935 else 936 ret = anx7625_dsi_config(ctx); 937 938 if (ret < 0) 939 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 940 941 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 942 943 ctx->dp_en = 1; 944 } 945 946 static void anx7625_dp_stop(struct anx7625_data *ctx) 947 { 948 struct device *dev = &ctx->client->dev; 949 int ret; 950 u8 data; 951 952 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 953 954 /* 955 * Video disable: 0x72:08 bit 7 = 0; 956 * Audio disable: 0x70:87 bit 0 = 0; 957 */ 958 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 959 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 960 961 ret |= anx7625_video_mute_control(ctx, 1); 962 963 dev_dbg(dev, "notify downstream enter into standby\n"); 964 /* Downstream monitor enter into standby mode */ 965 data = 2; 966 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data); 967 if (ret < 0) 968 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 969 970 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 971 972 ctx->dp_en = 0; 973 } 974 975 static int sp_tx_rst_aux(struct anx7625_data *ctx) 976 { 977 int ret; 978 979 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 980 AUX_RST); 981 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 982 ~AUX_RST); 983 return ret; 984 } 985 986 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 987 { 988 int ret; 989 990 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 991 AP_AUX_BUFF_START, offset); 992 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 993 AP_AUX_COMMAND, 0x04); 994 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 995 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 996 return (ret | wait_aux_op_finish(ctx)); 997 } 998 999 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 1000 { 1001 int ret; 1002 1003 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1004 AP_AUX_COMMAND, len_cmd); 1005 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1006 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1007 return (ret | wait_aux_op_finish(ctx)); 1008 } 1009 1010 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 1011 { 1012 int c = 0; 1013 struct device *dev = &ctx->client->dev; 1014 1015 sp_tx_aux_wr(ctx, 0x7e); 1016 sp_tx_aux_rd(ctx, 0x01); 1017 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 1018 if (c < 0) { 1019 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 1020 return -EIO; 1021 } 1022 1023 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 1024 1025 if (c > MAX_EDID_BLOCK) 1026 c = 1; 1027 1028 return c; 1029 } 1030 1031 static int edid_read(struct anx7625_data *ctx, 1032 u8 offset, u8 *pblock_buf) 1033 { 1034 int ret, cnt; 1035 struct device *dev = &ctx->client->dev; 1036 1037 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1038 sp_tx_aux_wr(ctx, offset); 1039 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1040 ret = sp_tx_aux_rd(ctx, 0xf1); 1041 1042 if (ret) { 1043 ret = sp_tx_rst_aux(ctx); 1044 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 1045 } else { 1046 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1047 AP_AUX_BUFF_START, 1048 MAX_DPCD_BUFFER_SIZE, 1049 pblock_buf); 1050 if (ret > 0) 1051 break; 1052 } 1053 } 1054 1055 if (cnt > EDID_TRY_CNT) 1056 return -EIO; 1057 1058 return ret; 1059 } 1060 1061 static int segments_edid_read(struct anx7625_data *ctx, 1062 u8 segment, u8 *buf, u8 offset) 1063 { 1064 u8 cnt; 1065 int ret; 1066 struct device *dev = &ctx->client->dev; 1067 1068 /* Write address only */ 1069 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1070 AP_AUX_ADDR_7_0, 0x30); 1071 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1072 AP_AUX_COMMAND, 0x04); 1073 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1074 AP_AUX_CTRL_STATUS, 1075 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 1076 1077 ret |= wait_aux_op_finish(ctx); 1078 /* Write segment address */ 1079 ret |= sp_tx_aux_wr(ctx, segment); 1080 /* Data read */ 1081 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1082 AP_AUX_ADDR_7_0, 0x50); 1083 if (ret) { 1084 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 1085 return ret; 1086 } 1087 1088 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1089 sp_tx_aux_wr(ctx, offset); 1090 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1091 ret = sp_tx_aux_rd(ctx, 0xf1); 1092 1093 if (ret) { 1094 ret = sp_tx_rst_aux(ctx); 1095 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 1096 } else { 1097 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1098 AP_AUX_BUFF_START, 1099 MAX_DPCD_BUFFER_SIZE, buf); 1100 if (ret > 0) 1101 break; 1102 } 1103 } 1104 1105 if (cnt > EDID_TRY_CNT) 1106 return -EIO; 1107 1108 return ret; 1109 } 1110 1111 static int sp_tx_edid_read(struct anx7625_data *ctx, 1112 u8 *pedid_blocks_buf) 1113 { 1114 u8 offset; 1115 int edid_pos; 1116 int count, blocks_num; 1117 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 1118 u8 i, j; 1119 int g_edid_break = 0; 1120 int ret; 1121 struct device *dev = &ctx->client->dev; 1122 1123 /* Address initial */ 1124 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1125 AP_AUX_ADDR_7_0, 0x50); 1126 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1127 AP_AUX_ADDR_15_8, 0); 1128 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 1129 AP_AUX_ADDR_19_16, 0xf0); 1130 if (ret < 0) { 1131 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 1132 return -EIO; 1133 } 1134 1135 blocks_num = sp_tx_get_edid_block(ctx); 1136 if (blocks_num < 0) 1137 return blocks_num; 1138 1139 count = 0; 1140 1141 do { 1142 switch (count) { 1143 case 0: 1144 case 1: 1145 for (i = 0; i < 8; i++) { 1146 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 1147 g_edid_break = edid_read(ctx, offset, 1148 pblock_buf); 1149 1150 if (g_edid_break < 0) 1151 break; 1152 1153 memcpy(&pedid_blocks_buf[offset], 1154 pblock_buf, 1155 MAX_DPCD_BUFFER_SIZE); 1156 } 1157 1158 break; 1159 case 2: 1160 offset = 0x00; 1161 1162 for (j = 0; j < 8; j++) { 1163 edid_pos = (j + count * 8) * 1164 MAX_DPCD_BUFFER_SIZE; 1165 1166 if (g_edid_break == 1) 1167 break; 1168 1169 ret = segments_edid_read(ctx, count / 2, 1170 pblock_buf, offset); 1171 if (ret < 0) 1172 return ret; 1173 1174 memcpy(&pedid_blocks_buf[edid_pos], 1175 pblock_buf, 1176 MAX_DPCD_BUFFER_SIZE); 1177 offset = offset + 0x10; 1178 } 1179 1180 break; 1181 case 3: 1182 offset = 0x80; 1183 1184 for (j = 0; j < 8; j++) { 1185 edid_pos = (j + count * 8) * 1186 MAX_DPCD_BUFFER_SIZE; 1187 if (g_edid_break == 1) 1188 break; 1189 1190 ret = segments_edid_read(ctx, count / 2, 1191 pblock_buf, offset); 1192 if (ret < 0) 1193 return ret; 1194 1195 memcpy(&pedid_blocks_buf[edid_pos], 1196 pblock_buf, 1197 MAX_DPCD_BUFFER_SIZE); 1198 offset = offset + 0x10; 1199 } 1200 1201 break; 1202 default: 1203 break; 1204 } 1205 1206 count++; 1207 1208 } while (blocks_num >= count); 1209 1210 /* Check edid data */ 1211 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 1212 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 1213 return -EINVAL; 1214 } 1215 1216 /* Reset aux channel */ 1217 ret = sp_tx_rst_aux(ctx); 1218 if (ret < 0) { 1219 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 1220 return ret; 1221 } 1222 1223 return (blocks_num + 1); 1224 } 1225 1226 static void anx7625_power_on(struct anx7625_data *ctx) 1227 { 1228 struct device *dev = &ctx->client->dev; 1229 int ret, i; 1230 1231 if (!ctx->pdata.low_power_mode) { 1232 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1233 return; 1234 } 1235 1236 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 1237 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 1238 if (ret < 0) { 1239 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 1240 i, ret); 1241 goto reg_err; 1242 } 1243 usleep_range(2000, 2100); 1244 } 1245 1246 usleep_range(11000, 12000); 1247 1248 /* Power on pin enable */ 1249 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 1250 usleep_range(10000, 11000); 1251 /* Power reset pin enable */ 1252 gpiod_set_value(ctx->pdata.gpio_reset, 1); 1253 usleep_range(10000, 11000); 1254 1255 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 1256 return; 1257 reg_err: 1258 for (--i; i >= 0; i--) 1259 regulator_disable(ctx->pdata.supplies[i].consumer); 1260 } 1261 1262 static void anx7625_power_standby(struct anx7625_data *ctx) 1263 { 1264 struct device *dev = &ctx->client->dev; 1265 int ret; 1266 1267 if (!ctx->pdata.low_power_mode) { 1268 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1269 return; 1270 } 1271 1272 gpiod_set_value(ctx->pdata.gpio_reset, 0); 1273 usleep_range(1000, 1100); 1274 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 1275 usleep_range(1000, 1100); 1276 1277 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1278 ctx->pdata.supplies); 1279 if (ret < 0) 1280 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1281 1282 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1283 } 1284 1285 /* Basic configurations of ANX7625 */ 1286 static void anx7625_config(struct anx7625_data *ctx) 1287 { 1288 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1289 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1290 } 1291 1292 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1293 { 1294 struct device *dev = &ctx->client->dev; 1295 int ret; 1296 1297 /* Reset main ocm */ 1298 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1299 /* Disable PD */ 1300 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1301 AP_AV_STATUS, AP_DISABLE_PD); 1302 /* Release main ocm */ 1303 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1304 1305 if (ret < 0) 1306 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1307 else 1308 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1309 } 1310 1311 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1312 { 1313 int ret; 1314 struct device *dev = &ctx->client->dev; 1315 1316 /* Check interface workable */ 1317 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1318 FLASH_LOAD_STA); 1319 if (ret < 0) { 1320 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1321 return ret; 1322 } 1323 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1324 return -ENODEV; 1325 1326 anx7625_disable_pd_protocol(ctx); 1327 1328 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1329 anx7625_reg_read(ctx, 1330 ctx->i2c.rx_p0_client, 1331 OCM_FW_VERSION), 1332 anx7625_reg_read(ctx, 1333 ctx->i2c.rx_p0_client, 1334 OCM_FW_REVERSION)); 1335 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1336 ANX7625_DRV_VERSION); 1337 1338 return 0; 1339 } 1340 1341 static void anx7625_power_on_init(struct anx7625_data *ctx) 1342 { 1343 int retry_count, i; 1344 1345 for (retry_count = 0; retry_count < 3; retry_count++) { 1346 anx7625_power_on(ctx); 1347 anx7625_config(ctx); 1348 1349 for (i = 0; i < OCM_LOADING_TIME; i++) { 1350 if (!anx7625_ocm_loading_check(ctx)) 1351 return; 1352 usleep_range(1000, 1100); 1353 } 1354 anx7625_power_standby(ctx); 1355 } 1356 } 1357 1358 static void anx7625_init_gpio(struct anx7625_data *platform) 1359 { 1360 struct device *dev = &platform->client->dev; 1361 1362 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1363 1364 /* Gpio for chip power enable */ 1365 platform->pdata.gpio_p_on = 1366 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1367 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 1368 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 1369 platform->pdata.gpio_p_on = NULL; 1370 } 1371 1372 /* Gpio for chip reset */ 1373 platform->pdata.gpio_reset = 1374 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1375 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 1376 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 1377 platform->pdata.gpio_reset = NULL; 1378 } 1379 1380 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1381 platform->pdata.low_power_mode = 1; 1382 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1383 desc_to_gpio(platform->pdata.gpio_p_on), 1384 desc_to_gpio(platform->pdata.gpio_reset)); 1385 } else { 1386 platform->pdata.low_power_mode = 0; 1387 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1388 } 1389 } 1390 1391 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1392 { 1393 ctx->hpd_status = 0; 1394 ctx->hpd_high_cnt = 0; 1395 ctx->display_timing_valid = 0; 1396 } 1397 1398 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1399 { 1400 int ret; 1401 struct device *dev = &ctx->client->dev; 1402 1403 if (ctx->hpd_high_cnt >= 2) { 1404 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1405 return; 1406 } 1407 1408 ctx->hpd_status = 1; 1409 ctx->hpd_high_cnt++; 1410 1411 /* Not support HDCP */ 1412 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1413 1414 /* Try auth flag */ 1415 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1416 /* Interrupt for DRM */ 1417 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1418 if (ret < 0) { 1419 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1420 return; 1421 } 1422 1423 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1424 if (ret < 0) 1425 return; 1426 1427 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1428 } 1429 1430 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1431 { 1432 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1433 } 1434 1435 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1436 { 1437 int ret, val; 1438 struct device *dev = &ctx->client->dev; 1439 1440 /* Interrupt mode, no need poll HPD status, just return */ 1441 if (ctx->pdata.intp_irq) 1442 return; 1443 1444 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1445 ctx, val, 1446 ((val & HPD_STATUS) || (val < 0)), 1447 5000, 1448 5000 * 100); 1449 if (ret) { 1450 DRM_DEV_ERROR(dev, "no hpd.\n"); 1451 return; 1452 } 1453 1454 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1455 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1456 INTR_ALERT_1, 0xFF); 1457 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1458 INTERFACE_CHANGE_INT, 0); 1459 1460 anx7625_start_dp_work(ctx); 1461 1462 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1463 drm_helper_hpd_irq_event(ctx->bridge.dev); 1464 } 1465 1466 static void anx7625_remove_edid(struct anx7625_data *ctx) 1467 { 1468 ctx->slimport_edid_p.edid_block_num = -1; 1469 } 1470 1471 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1472 { 1473 int i; 1474 1475 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1476 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1477 DP_TX_LANE0_SWING_REG0 + i, 1478 ctx->pdata.lane0_reg_data[i] & 0xFF); 1479 1480 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1481 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1482 DP_TX_LANE1_SWING_REG0 + i, 1483 ctx->pdata.lane1_reg_data[i] & 0xFF); 1484 } 1485 1486 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1487 { 1488 struct device *dev = &ctx->client->dev; 1489 1490 /* HPD changed */ 1491 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1492 (u32)on); 1493 1494 if (on == 0) { 1495 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1496 anx7625_remove_edid(ctx); 1497 anx7625_stop_dp_work(ctx); 1498 } else { 1499 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1500 anx7625_start_dp_work(ctx); 1501 anx7625_dp_adjust_swing(ctx); 1502 } 1503 } 1504 1505 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1506 { 1507 int intr_vector, status; 1508 struct device *dev = &ctx->client->dev; 1509 1510 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1511 INTR_ALERT_1, 0xFF); 1512 if (status < 0) { 1513 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1514 return status; 1515 } 1516 1517 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1518 INTERFACE_CHANGE_INT); 1519 if (intr_vector < 0) { 1520 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1521 return intr_vector; 1522 } 1523 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1524 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1525 INTERFACE_CHANGE_INT, 1526 intr_vector & (~intr_vector)); 1527 if (status < 0) { 1528 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1529 return status; 1530 } 1531 1532 if (!(intr_vector & HPD_STATUS_CHANGE)) 1533 return -ENOENT; 1534 1535 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1536 SYSTEM_STSTUS); 1537 if (status < 0) { 1538 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1539 return status; 1540 } 1541 1542 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1543 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1544 1545 return 0; 1546 } 1547 1548 static void anx7625_work_func(struct work_struct *work) 1549 { 1550 int event; 1551 struct anx7625_data *ctx = container_of(work, 1552 struct anx7625_data, work); 1553 1554 mutex_lock(&ctx->lock); 1555 1556 if (pm_runtime_suspended(&ctx->client->dev)) 1557 goto unlock; 1558 1559 event = anx7625_hpd_change_detect(ctx); 1560 if (event < 0) 1561 goto unlock; 1562 1563 if (ctx->bridge_attached) 1564 drm_helper_hpd_irq_event(ctx->bridge.dev); 1565 1566 unlock: 1567 mutex_unlock(&ctx->lock); 1568 } 1569 1570 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1571 { 1572 struct anx7625_data *ctx = (struct anx7625_data *)data; 1573 1574 queue_work(ctx->workqueue, &ctx->work); 1575 1576 return IRQ_HANDLED; 1577 } 1578 1579 static int anx7625_get_swing_setting(struct device *dev, 1580 struct anx7625_platform_data *pdata) 1581 { 1582 int num_regs; 1583 1584 if (of_get_property(dev->of_node, 1585 "analogix,lane0-swing", &num_regs)) { 1586 if (num_regs > DP_TX_SWING_REG_CNT) 1587 num_regs = DP_TX_SWING_REG_CNT; 1588 1589 pdata->dp_lane0_swing_reg_cnt = num_regs; 1590 of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1591 pdata->lane0_reg_data, num_regs); 1592 } 1593 1594 if (of_get_property(dev->of_node, 1595 "analogix,lane1-swing", &num_regs)) { 1596 if (num_regs > DP_TX_SWING_REG_CNT) 1597 num_regs = DP_TX_SWING_REG_CNT; 1598 1599 pdata->dp_lane1_swing_reg_cnt = num_regs; 1600 of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1601 pdata->lane1_reg_data, num_regs); 1602 } 1603 1604 return 0; 1605 } 1606 1607 static int anx7625_parse_dt(struct device *dev, 1608 struct anx7625_platform_data *pdata) 1609 { 1610 struct device_node *np = dev->of_node, *ep0; 1611 struct drm_panel *panel; 1612 int ret; 1613 int bus_type, mipi_lanes; 1614 1615 anx7625_get_swing_setting(dev, pdata); 1616 1617 pdata->is_dpi = 1; /* default dpi mode */ 1618 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1619 if (!pdata->mipi_host_node) { 1620 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1621 return -ENODEV; 1622 } 1623 1624 bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1625 mipi_lanes = MAX_LANES_SUPPORT; 1626 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1627 if (ep0) { 1628 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1629 bus_type = 0; 1630 1631 mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1632 } 1633 1634 if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1635 pdata->is_dpi = 0; 1636 1637 pdata->mipi_lanes = mipi_lanes; 1638 if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1639 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1640 1641 if (pdata->is_dpi) 1642 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1643 else 1644 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1645 1646 if (of_property_read_bool(np, "analogix,audio-enable")) 1647 pdata->audio_en = 1; 1648 1649 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1650 if (ret < 0) { 1651 if (ret == -ENODEV) 1652 return 0; 1653 return ret; 1654 } 1655 if (!panel) 1656 return -ENODEV; 1657 1658 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1659 if (IS_ERR(pdata->panel_bridge)) 1660 return PTR_ERR(pdata->panel_bridge); 1661 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1662 1663 return 0; 1664 } 1665 1666 static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1667 { 1668 struct device_node *bus, *panel; 1669 1670 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1671 if (!bus) 1672 return false; 1673 1674 panel = of_get_child_by_name(bus, "panel"); 1675 of_node_put(bus); 1676 if (!panel) 1677 return false; 1678 of_node_put(panel); 1679 1680 return true; 1681 } 1682 1683 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1684 { 1685 return container_of(bridge, struct anx7625_data, bridge); 1686 } 1687 1688 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1689 struct drm_dp_aux_msg *msg) 1690 { 1691 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1692 struct device *dev = &ctx->client->dev; 1693 u8 request = msg->request & ~DP_AUX_I2C_MOT; 1694 int ret = 0; 1695 1696 pm_runtime_get_sync(dev); 1697 msg->reply = 0; 1698 switch (request) { 1699 case DP_AUX_NATIVE_WRITE: 1700 case DP_AUX_I2C_WRITE: 1701 case DP_AUX_NATIVE_READ: 1702 case DP_AUX_I2C_READ: 1703 break; 1704 default: 1705 ret = -EINVAL; 1706 } 1707 if (!ret) 1708 ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1709 msg->size, msg->buffer); 1710 pm_runtime_mark_last_busy(dev); 1711 pm_runtime_put_autosuspend(dev); 1712 1713 return ret; 1714 } 1715 1716 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1717 { 1718 struct device *dev = &ctx->client->dev; 1719 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1720 int edid_num; 1721 u8 *edid; 1722 1723 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1724 if (!edid) { 1725 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1726 return NULL; 1727 } 1728 1729 if (ctx->slimport_edid_p.edid_block_num > 0) { 1730 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1731 FOUR_BLOCK_SIZE); 1732 return (struct edid *)edid; 1733 } 1734 1735 pm_runtime_get_sync(dev); 1736 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1737 pm_runtime_put_sync(dev); 1738 1739 if (edid_num < 1) { 1740 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1741 kfree(edid); 1742 return NULL; 1743 } 1744 1745 p_edid->edid_block_num = edid_num; 1746 1747 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1748 return (struct edid *)edid; 1749 } 1750 1751 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1752 { 1753 struct device *dev = &ctx->client->dev; 1754 1755 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1756 1757 if (ctx->pdata.panel_bridge) 1758 return connector_status_connected; 1759 1760 return ctx->hpd_status ? connector_status_connected : 1761 connector_status_disconnected; 1762 } 1763 1764 static int anx7625_audio_hw_params(struct device *dev, void *data, 1765 struct hdmi_codec_daifmt *fmt, 1766 struct hdmi_codec_params *params) 1767 { 1768 struct anx7625_data *ctx = dev_get_drvdata(dev); 1769 int wl, ch, rate; 1770 int ret = 0; 1771 1772 if (fmt->fmt != HDMI_DSP_A) { 1773 DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1774 return -EINVAL; 1775 } 1776 1777 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1778 params->sample_rate, params->sample_width, 1779 params->cea.channels); 1780 1781 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1782 AUDIO_CHANNEL_STATUS_6, 1783 ~I2S_SLAVE_MODE, 1784 TDM_SLAVE_MODE); 1785 1786 /* Word length */ 1787 switch (params->sample_width) { 1788 case 16: 1789 wl = AUDIO_W_LEN_16_20MAX; 1790 break; 1791 case 18: 1792 wl = AUDIO_W_LEN_18_20MAX; 1793 break; 1794 case 20: 1795 wl = AUDIO_W_LEN_20_20MAX; 1796 break; 1797 case 24: 1798 wl = AUDIO_W_LEN_24_24MAX; 1799 break; 1800 default: 1801 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1802 params->sample_width); 1803 return -EINVAL; 1804 } 1805 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1806 AUDIO_CHANNEL_STATUS_5, 1807 0xf0, wl); 1808 1809 /* Channel num */ 1810 switch (params->cea.channels) { 1811 case 2: 1812 ch = I2S_CH_2; 1813 break; 1814 case 4: 1815 ch = TDM_CH_4; 1816 break; 1817 case 6: 1818 ch = TDM_CH_6; 1819 break; 1820 case 8: 1821 ch = TDM_CH_8; 1822 break; 1823 default: 1824 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1825 params->cea.channels); 1826 return -EINVAL; 1827 } 1828 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1829 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1830 if (ch > I2S_CH_2) 1831 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1832 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1833 else 1834 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1835 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1836 1837 /* FS */ 1838 switch (params->sample_rate) { 1839 case 32000: 1840 rate = AUDIO_FS_32K; 1841 break; 1842 case 44100: 1843 rate = AUDIO_FS_441K; 1844 break; 1845 case 48000: 1846 rate = AUDIO_FS_48K; 1847 break; 1848 case 88200: 1849 rate = AUDIO_FS_882K; 1850 break; 1851 case 96000: 1852 rate = AUDIO_FS_96K; 1853 break; 1854 case 176400: 1855 rate = AUDIO_FS_1764K; 1856 break; 1857 case 192000: 1858 rate = AUDIO_FS_192K; 1859 break; 1860 default: 1861 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1862 params->sample_rate); 1863 return -EINVAL; 1864 } 1865 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1866 AUDIO_CHANNEL_STATUS_4, 1867 0xf0, rate); 1868 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1869 AP_AV_STATUS, AP_AUDIO_CHG); 1870 if (ret < 0) { 1871 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1872 return -EIO; 1873 } 1874 1875 return 0; 1876 } 1877 1878 static void anx7625_audio_shutdown(struct device *dev, void *data) 1879 { 1880 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1881 } 1882 1883 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1884 struct device_node *endpoint) 1885 { 1886 struct of_endpoint of_ep; 1887 int ret; 1888 1889 ret = of_graph_parse_endpoint(endpoint, &of_ep); 1890 if (ret < 0) 1891 return ret; 1892 1893 /* 1894 * HDMI sound should be located at external DPI port 1895 * Didn't have good way to check where is internal(DSI) 1896 * or external(DPI) bridge 1897 */ 1898 return 0; 1899 } 1900 1901 static void 1902 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1903 enum drm_connector_status status) 1904 { 1905 if (ctx->plugged_cb && ctx->codec_dev) { 1906 ctx->plugged_cb(ctx->codec_dev, 1907 status == connector_status_connected); 1908 } 1909 } 1910 1911 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1912 hdmi_codec_plugged_cb fn, 1913 struct device *codec_dev) 1914 { 1915 struct anx7625_data *ctx = data; 1916 1917 ctx->plugged_cb = fn; 1918 ctx->codec_dev = codec_dev; 1919 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1920 1921 return 0; 1922 } 1923 1924 static int anx7625_audio_get_eld(struct device *dev, void *data, 1925 u8 *buf, size_t len) 1926 { 1927 struct anx7625_data *ctx = dev_get_drvdata(dev); 1928 1929 if (!ctx->connector) { 1930 dev_err(dev, "connector not initial\n"); 1931 return -EINVAL; 1932 } 1933 1934 dev_dbg(dev, "audio copy eld\n"); 1935 memcpy(buf, ctx->connector->eld, 1936 min(sizeof(ctx->connector->eld), len)); 1937 1938 return 0; 1939 } 1940 1941 static const struct hdmi_codec_ops anx7625_codec_ops = { 1942 .hw_params = anx7625_audio_hw_params, 1943 .audio_shutdown = anx7625_audio_shutdown, 1944 .get_eld = anx7625_audio_get_eld, 1945 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1946 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1947 }; 1948 1949 static void anx7625_unregister_audio(struct anx7625_data *ctx) 1950 { 1951 struct device *dev = &ctx->client->dev; 1952 1953 if (ctx->audio_pdev) { 1954 platform_device_unregister(ctx->audio_pdev); 1955 ctx->audio_pdev = NULL; 1956 } 1957 1958 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1959 } 1960 1961 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1962 { 1963 struct hdmi_codec_pdata codec_data = { 1964 .ops = &anx7625_codec_ops, 1965 .max_i2s_channels = 8, 1966 .i2s = 1, 1967 .data = ctx, 1968 }; 1969 1970 ctx->audio_pdev = platform_device_register_data(dev, 1971 HDMI_CODEC_DRV_NAME, 1972 PLATFORM_DEVID_AUTO, 1973 &codec_data, 1974 sizeof(codec_data)); 1975 1976 if (IS_ERR(ctx->audio_pdev)) 1977 return PTR_ERR(ctx->audio_pdev); 1978 1979 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1980 1981 return 0; 1982 } 1983 1984 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1985 { 1986 struct mipi_dsi_device *dsi; 1987 struct device *dev = &ctx->client->dev; 1988 struct mipi_dsi_host *host; 1989 const struct mipi_dsi_device_info info = { 1990 .type = "anx7625", 1991 .channel = 0, 1992 .node = NULL, 1993 }; 1994 int ret; 1995 1996 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1997 1998 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1999 if (!host) { 2000 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 2001 return -EPROBE_DEFER; 2002 } 2003 2004 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2005 if (IS_ERR(dsi)) { 2006 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 2007 return -EINVAL; 2008 } 2009 2010 dsi->lanes = ctx->pdata.mipi_lanes; 2011 dsi->format = MIPI_DSI_FMT_RGB888; 2012 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 2013 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2014 MIPI_DSI_MODE_VIDEO_HSE; 2015 2016 ret = devm_mipi_dsi_attach(dev, dsi); 2017 if (ret) { 2018 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 2019 return ret; 2020 } 2021 2022 ctx->dsi = dsi; 2023 2024 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 2025 2026 return 0; 2027 } 2028 2029 static void hdcp_check_work_func(struct work_struct *work) 2030 { 2031 u8 status; 2032 struct delayed_work *dwork; 2033 struct anx7625_data *ctx; 2034 struct device *dev; 2035 struct drm_device *drm_dev; 2036 2037 dwork = to_delayed_work(work); 2038 ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2039 dev = &ctx->client->dev; 2040 2041 if (!ctx->connector) { 2042 dev_err(dev, "HDCP connector is null!"); 2043 return; 2044 } 2045 2046 drm_dev = ctx->connector->dev; 2047 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2048 mutex_lock(&ctx->hdcp_wq_lock); 2049 2050 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2051 dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2052 if (status & BIT(1)) { 2053 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2054 drm_hdcp_update_content_protection(ctx->connector, 2055 ctx->hdcp_cp); 2056 dev_dbg(dev, "update CP to ENABLE\n"); 2057 } 2058 2059 mutex_unlock(&ctx->hdcp_wq_lock); 2060 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2061 } 2062 2063 static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2064 struct drm_connector_state *state) 2065 { 2066 struct device *dev = &ctx->client->dev; 2067 int cp; 2068 2069 dev_dbg(dev, "hdcp state check\n"); 2070 cp = state->content_protection; 2071 2072 if (cp == ctx->hdcp_cp) 2073 return 0; 2074 2075 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2076 if (ctx->dp_en) { 2077 dev_dbg(dev, "enable HDCP\n"); 2078 anx7625_hdcp_enable(ctx); 2079 2080 queue_delayed_work(ctx->hdcp_workqueue, 2081 &ctx->hdcp_work, 2082 msecs_to_jiffies(2000)); 2083 } 2084 } 2085 2086 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2087 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2088 dev_err(dev, "current CP is not ENABLED\n"); 2089 return -EINVAL; 2090 } 2091 anx7625_hdcp_disable(ctx); 2092 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2093 drm_hdcp_update_content_protection(ctx->connector, 2094 ctx->hdcp_cp); 2095 dev_dbg(dev, "update CP to UNDESIRE\n"); 2096 } 2097 2098 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2099 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2100 return -EINVAL; 2101 } 2102 2103 return 0; 2104 } 2105 2106 static int anx7625_bridge_attach(struct drm_bridge *bridge, 2107 enum drm_bridge_attach_flags flags) 2108 { 2109 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2110 int err; 2111 struct device *dev = &ctx->client->dev; 2112 2113 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 2114 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 2115 return -EINVAL; 2116 2117 if (!bridge->encoder) { 2118 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 2119 return -ENODEV; 2120 } 2121 2122 ctx->aux.drm_dev = bridge->dev; 2123 err = drm_dp_aux_register(&ctx->aux); 2124 if (err) { 2125 dev_err(dev, "failed to register aux channel: %d\n", err); 2126 return err; 2127 } 2128 2129 if (ctx->pdata.panel_bridge) { 2130 err = drm_bridge_attach(bridge->encoder, 2131 ctx->pdata.panel_bridge, 2132 &ctx->bridge, flags); 2133 if (err) 2134 return err; 2135 } 2136 2137 ctx->bridge_attached = 1; 2138 2139 return 0; 2140 } 2141 2142 static void anx7625_bridge_detach(struct drm_bridge *bridge) 2143 { 2144 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2145 2146 drm_dp_aux_unregister(&ctx->aux); 2147 } 2148 2149 static enum drm_mode_status 2150 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 2151 const struct drm_display_info *info, 2152 const struct drm_display_mode *mode) 2153 { 2154 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2155 struct device *dev = &ctx->client->dev; 2156 2157 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 2158 2159 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 2160 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 2161 DRM_DEV_DEBUG_DRIVER(dev, 2162 "drm mode invalid, pixelclock too high.\n"); 2163 return MODE_CLOCK_HIGH; 2164 } 2165 2166 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 2167 2168 return MODE_OK; 2169 } 2170 2171 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 2172 const struct drm_display_mode *old_mode, 2173 const struct drm_display_mode *mode) 2174 { 2175 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2176 struct device *dev = &ctx->client->dev; 2177 2178 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 2179 2180 ctx->dt.pixelclock.min = mode->clock; 2181 ctx->dt.hactive.min = mode->hdisplay; 2182 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 2183 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 2184 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 2185 ctx->dt.vactive.min = mode->vdisplay; 2186 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 2187 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 2188 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 2189 2190 ctx->display_timing_valid = 1; 2191 2192 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 2193 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 2194 ctx->dt.hactive.min, 2195 ctx->dt.hsync_len.min, 2196 ctx->dt.hfront_porch.min, 2197 ctx->dt.hback_porch.min); 2198 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 2199 ctx->dt.vactive.min, 2200 ctx->dt.vsync_len.min, 2201 ctx->dt.vfront_porch.min, 2202 ctx->dt.vback_porch.min); 2203 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 2204 mode->hdisplay, 2205 mode->hsync_start); 2206 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 2207 mode->hsync_end, 2208 mode->htotal); 2209 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 2210 mode->vdisplay, 2211 mode->vsync_start); 2212 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 2213 mode->vsync_end, 2214 mode->vtotal); 2215 } 2216 2217 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 2218 const struct drm_display_mode *mode, 2219 struct drm_display_mode *adj) 2220 { 2221 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2222 struct device *dev = &ctx->client->dev; 2223 u32 hsync, hfp, hbp, hblanking; 2224 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 2225 u32 vref, adj_clock; 2226 2227 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 2228 2229 /* No need fixup for external monitor */ 2230 if (!ctx->pdata.panel_bridge) 2231 return true; 2232 2233 hsync = mode->hsync_end - mode->hsync_start; 2234 hfp = mode->hsync_start - mode->hdisplay; 2235 hbp = mode->htotal - mode->hsync_end; 2236 hblanking = mode->htotal - mode->hdisplay; 2237 2238 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 2239 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2240 hsync, hfp, hbp, adj->clock); 2241 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2242 adj->hsync_start, adj->hsync_end, adj->htotal); 2243 2244 adj_hfp = hfp; 2245 adj_hsync = hsync; 2246 adj_hbp = hbp; 2247 adj_hblanking = hblanking; 2248 2249 /* HFP needs to be even */ 2250 if (hfp & 0x1) { 2251 adj_hfp += 1; 2252 adj_hblanking += 1; 2253 } 2254 2255 /* HBP needs to be even */ 2256 if (hbp & 0x1) { 2257 adj_hbp -= 1; 2258 adj_hblanking -= 1; 2259 } 2260 2261 /* HSYNC needs to be even */ 2262 if (hsync & 0x1) { 2263 if (adj_hblanking < hblanking) 2264 adj_hsync += 1; 2265 else 2266 adj_hsync -= 1; 2267 } 2268 2269 /* 2270 * Once illegal timing detected, use default HFP, HSYNC, HBP 2271 * This adjusting made for built-in eDP panel, for the externel 2272 * DP monitor, may need return false. 2273 */ 2274 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 2275 adj_hsync = SYNC_LEN_DEF; 2276 adj_hfp = HFP_HBP_DEF; 2277 adj_hbp = HFP_HBP_DEF; 2278 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 2279 if (hblanking < HBLANKING_MIN) { 2280 delta_adj = HBLANKING_MIN - hblanking; 2281 adj_clock = vref * delta_adj * adj->vtotal; 2282 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 2283 } else { 2284 delta_adj = hblanking - HBLANKING_MIN; 2285 adj_clock = vref * delta_adj * adj->vtotal; 2286 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 2287 } 2288 2289 DRM_WARN("illegal hblanking timing, use default.\n"); 2290 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 2291 } else if (adj_hfp < HP_MIN) { 2292 /* Adjust hfp if hfp less than HP_MIN */ 2293 delta_adj = HP_MIN - adj_hfp; 2294 adj_hfp = HP_MIN; 2295 2296 /* 2297 * Balance total HBlanking pixel, if HBP does not have enough 2298 * space, adjust HSYNC length, otherwise adjust HBP 2299 */ 2300 if ((adj_hbp - delta_adj) < HP_MIN) 2301 /* HBP not enough space */ 2302 adj_hsync -= delta_adj; 2303 else 2304 adj_hbp -= delta_adj; 2305 } else if (adj_hbp < HP_MIN) { 2306 delta_adj = HP_MIN - adj_hbp; 2307 adj_hbp = HP_MIN; 2308 2309 /* 2310 * Balance total HBlanking pixel, if HBP hasn't enough space, 2311 * adjust HSYNC length, otherwize adjust HBP 2312 */ 2313 if ((adj_hfp - delta_adj) < HP_MIN) 2314 /* HFP not enough space */ 2315 adj_hsync -= delta_adj; 2316 else 2317 adj_hfp -= delta_adj; 2318 } 2319 2320 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 2321 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2322 adj_hsync, adj_hfp, adj_hbp, adj->clock); 2323 2324 /* Reconstruct timing */ 2325 adj->hsync_start = adj->hdisplay + adj_hfp; 2326 adj->hsync_end = adj->hsync_start + adj_hsync; 2327 adj->htotal = adj->hsync_end + adj_hbp; 2328 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2329 adj->hsync_start, adj->hsync_end, adj->htotal); 2330 2331 return true; 2332 } 2333 2334 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2335 struct drm_bridge_state *bridge_state, 2336 struct drm_crtc_state *crtc_state, 2337 struct drm_connector_state *conn_state) 2338 { 2339 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2340 struct device *dev = &ctx->client->dev; 2341 2342 dev_dbg(dev, "drm bridge atomic check\n"); 2343 2344 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2345 &crtc_state->adjusted_mode); 2346 2347 return anx7625_connector_atomic_check(ctx, conn_state); 2348 } 2349 2350 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2351 struct drm_bridge_state *state) 2352 { 2353 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2354 struct device *dev = &ctx->client->dev; 2355 struct drm_connector *connector; 2356 2357 dev_dbg(dev, "drm atomic enable\n"); 2358 2359 if (!bridge->encoder) { 2360 dev_err(dev, "Parent encoder object not found"); 2361 return; 2362 } 2363 2364 connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2365 bridge->encoder); 2366 if (!connector) 2367 return; 2368 2369 ctx->connector = connector; 2370 2371 pm_runtime_get_sync(dev); 2372 2373 anx7625_dp_start(ctx); 2374 } 2375 2376 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2377 struct drm_bridge_state *old) 2378 { 2379 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2380 struct device *dev = &ctx->client->dev; 2381 2382 dev_dbg(dev, "drm atomic disable\n"); 2383 2384 ctx->connector = NULL; 2385 anx7625_dp_stop(ctx); 2386 2387 pm_runtime_put_sync(dev); 2388 } 2389 2390 static enum drm_connector_status 2391 anx7625_bridge_detect(struct drm_bridge *bridge) 2392 { 2393 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2394 struct device *dev = &ctx->client->dev; 2395 2396 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 2397 2398 return anx7625_sink_detect(ctx); 2399 } 2400 2401 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 2402 struct drm_connector *connector) 2403 { 2404 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2405 struct device *dev = &ctx->client->dev; 2406 2407 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 2408 2409 return anx7625_get_edid(ctx); 2410 } 2411 2412 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 2413 .attach = anx7625_bridge_attach, 2414 .detach = anx7625_bridge_detach, 2415 .mode_valid = anx7625_bridge_mode_valid, 2416 .mode_set = anx7625_bridge_mode_set, 2417 .atomic_check = anx7625_bridge_atomic_check, 2418 .atomic_enable = anx7625_bridge_atomic_enable, 2419 .atomic_disable = anx7625_bridge_atomic_disable, 2420 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2421 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2422 .atomic_reset = drm_atomic_helper_bridge_reset, 2423 .detect = anx7625_bridge_detect, 2424 .get_edid = anx7625_bridge_get_edid, 2425 }; 2426 2427 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 2428 struct i2c_client *client) 2429 { 2430 int err = 0; 2431 2432 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 2433 TX_P0_ADDR >> 1); 2434 if (IS_ERR(ctx->i2c.tx_p0_client)) 2435 return PTR_ERR(ctx->i2c.tx_p0_client); 2436 2437 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 2438 TX_P1_ADDR >> 1); 2439 if (IS_ERR(ctx->i2c.tx_p1_client)) { 2440 err = PTR_ERR(ctx->i2c.tx_p1_client); 2441 goto free_tx_p0; 2442 } 2443 2444 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 2445 TX_P2_ADDR >> 1); 2446 if (IS_ERR(ctx->i2c.tx_p2_client)) { 2447 err = PTR_ERR(ctx->i2c.tx_p2_client); 2448 goto free_tx_p1; 2449 } 2450 2451 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 2452 RX_P0_ADDR >> 1); 2453 if (IS_ERR(ctx->i2c.rx_p0_client)) { 2454 err = PTR_ERR(ctx->i2c.rx_p0_client); 2455 goto free_tx_p2; 2456 } 2457 2458 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 2459 RX_P1_ADDR >> 1); 2460 if (IS_ERR(ctx->i2c.rx_p1_client)) { 2461 err = PTR_ERR(ctx->i2c.rx_p1_client); 2462 goto free_rx_p0; 2463 } 2464 2465 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 2466 RX_P2_ADDR >> 1); 2467 if (IS_ERR(ctx->i2c.rx_p2_client)) { 2468 err = PTR_ERR(ctx->i2c.rx_p2_client); 2469 goto free_rx_p1; 2470 } 2471 2472 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 2473 TCPC_INTERFACE_ADDR >> 1); 2474 if (IS_ERR(ctx->i2c.tcpc_client)) { 2475 err = PTR_ERR(ctx->i2c.tcpc_client); 2476 goto free_rx_p2; 2477 } 2478 2479 return 0; 2480 2481 free_rx_p2: 2482 i2c_unregister_device(ctx->i2c.rx_p2_client); 2483 free_rx_p1: 2484 i2c_unregister_device(ctx->i2c.rx_p1_client); 2485 free_rx_p0: 2486 i2c_unregister_device(ctx->i2c.rx_p0_client); 2487 free_tx_p2: 2488 i2c_unregister_device(ctx->i2c.tx_p2_client); 2489 free_tx_p1: 2490 i2c_unregister_device(ctx->i2c.tx_p1_client); 2491 free_tx_p0: 2492 i2c_unregister_device(ctx->i2c.tx_p0_client); 2493 2494 return err; 2495 } 2496 2497 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 2498 { 2499 i2c_unregister_device(ctx->i2c.tx_p0_client); 2500 i2c_unregister_device(ctx->i2c.tx_p1_client); 2501 i2c_unregister_device(ctx->i2c.tx_p2_client); 2502 i2c_unregister_device(ctx->i2c.rx_p0_client); 2503 i2c_unregister_device(ctx->i2c.rx_p1_client); 2504 i2c_unregister_device(ctx->i2c.rx_p2_client); 2505 i2c_unregister_device(ctx->i2c.tcpc_client); 2506 } 2507 2508 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2509 { 2510 struct anx7625_data *ctx = dev_get_drvdata(dev); 2511 2512 mutex_lock(&ctx->lock); 2513 2514 anx7625_stop_dp_work(ctx); 2515 anx7625_power_standby(ctx); 2516 2517 mutex_unlock(&ctx->lock); 2518 2519 return 0; 2520 } 2521 2522 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2523 { 2524 struct anx7625_data *ctx = dev_get_drvdata(dev); 2525 2526 mutex_lock(&ctx->lock); 2527 2528 anx7625_power_on_init(ctx); 2529 anx7625_hpd_polling(ctx); 2530 2531 mutex_unlock(&ctx->lock); 2532 2533 return 0; 2534 } 2535 2536 static int __maybe_unused anx7625_resume(struct device *dev) 2537 { 2538 struct anx7625_data *ctx = dev_get_drvdata(dev); 2539 2540 if (!ctx->pdata.intp_irq) 2541 return 0; 2542 2543 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2544 enable_irq(ctx->pdata.intp_irq); 2545 anx7625_runtime_pm_resume(dev); 2546 } 2547 2548 return 0; 2549 } 2550 2551 static int __maybe_unused anx7625_suspend(struct device *dev) 2552 { 2553 struct anx7625_data *ctx = dev_get_drvdata(dev); 2554 2555 if (!ctx->pdata.intp_irq) 2556 return 0; 2557 2558 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2559 anx7625_runtime_pm_suspend(dev); 2560 disable_irq(ctx->pdata.intp_irq); 2561 } 2562 2563 return 0; 2564 } 2565 2566 static const struct dev_pm_ops anx7625_pm_ops = { 2567 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 2568 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2569 anx7625_runtime_pm_resume, NULL) 2570 }; 2571 2572 static void anx7625_runtime_disable(void *data) 2573 { 2574 pm_runtime_dont_use_autosuspend(data); 2575 pm_runtime_disable(data); 2576 } 2577 2578 static int anx7625_i2c_probe(struct i2c_client *client, 2579 const struct i2c_device_id *id) 2580 { 2581 struct anx7625_data *platform; 2582 struct anx7625_platform_data *pdata; 2583 int ret = 0; 2584 struct device *dev = &client->dev; 2585 2586 if (!i2c_check_functionality(client->adapter, 2587 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2588 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2589 return -ENODEV; 2590 } 2591 2592 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL); 2593 if (!platform) { 2594 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2595 return -ENOMEM; 2596 } 2597 2598 pdata = &platform->pdata; 2599 2600 platform->client = client; 2601 i2c_set_clientdata(client, platform); 2602 2603 pdata->supplies[0].supply = "vdd10"; 2604 pdata->supplies[1].supply = "vdd18"; 2605 pdata->supplies[2].supply = "vdd33"; 2606 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2607 pdata->supplies); 2608 if (ret) { 2609 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2610 return ret; 2611 } 2612 anx7625_init_gpio(platform); 2613 2614 mutex_init(&platform->lock); 2615 mutex_init(&platform->hdcp_wq_lock); 2616 2617 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2618 platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2619 if (!platform->hdcp_workqueue) { 2620 dev_err(dev, "fail to create work queue\n"); 2621 ret = -ENOMEM; 2622 return ret; 2623 } 2624 2625 platform->pdata.intp_irq = client->irq; 2626 if (platform->pdata.intp_irq) { 2627 INIT_WORK(&platform->work, anx7625_work_func); 2628 platform->workqueue = alloc_workqueue("anx7625_work", 2629 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2630 if (!platform->workqueue) { 2631 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2632 ret = -ENOMEM; 2633 goto free_hdcp_wq; 2634 } 2635 2636 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2637 NULL, anx7625_intr_hpd_isr, 2638 IRQF_TRIGGER_FALLING | 2639 IRQF_ONESHOT, 2640 "anx7625-intp", platform); 2641 if (ret) { 2642 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2643 goto free_wq; 2644 } 2645 } 2646 2647 platform->aux.name = "anx7625-aux"; 2648 platform->aux.dev = dev; 2649 platform->aux.transfer = anx7625_aux_transfer; 2650 drm_dp_aux_init(&platform->aux); 2651 devm_of_dp_aux_populate_ep_devices(&platform->aux); 2652 2653 ret = anx7625_parse_dt(dev, pdata); 2654 if (ret) { 2655 if (ret != -EPROBE_DEFER) 2656 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2657 return ret; 2658 } 2659 2660 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2661 ret = -ENOMEM; 2662 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2663 goto free_wq; 2664 } 2665 2666 pm_runtime_enable(dev); 2667 pm_runtime_set_autosuspend_delay(dev, 1000); 2668 pm_runtime_use_autosuspend(dev); 2669 pm_suspend_ignore_children(dev, true); 2670 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev); 2671 if (ret) 2672 return ret; 2673 2674 if (!platform->pdata.low_power_mode) { 2675 anx7625_disable_pd_protocol(platform); 2676 pm_runtime_get_sync(dev); 2677 } 2678 2679 /* Add work function */ 2680 if (platform->pdata.intp_irq) 2681 queue_work(platform->workqueue, &platform->work); 2682 2683 platform->bridge.funcs = &anx7625_bridge_funcs; 2684 platform->bridge.of_node = client->dev.of_node; 2685 if (!anx7625_of_panel_on_aux_bus(&client->dev)) 2686 platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 2687 if (!platform->pdata.panel_bridge) 2688 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2689 DRM_BRIDGE_OP_DETECT; 2690 platform->bridge.type = platform->pdata.panel_bridge ? 2691 DRM_MODE_CONNECTOR_eDP : 2692 DRM_MODE_CONNECTOR_DisplayPort; 2693 2694 drm_bridge_add(&platform->bridge); 2695 2696 if (!platform->pdata.is_dpi) { 2697 ret = anx7625_attach_dsi(platform); 2698 if (ret) { 2699 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 2700 goto unregister_bridge; 2701 } 2702 } 2703 2704 if (platform->pdata.audio_en) 2705 anx7625_register_audio(dev, platform); 2706 2707 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2708 2709 return 0; 2710 2711 unregister_bridge: 2712 drm_bridge_remove(&platform->bridge); 2713 2714 if (!platform->pdata.low_power_mode) 2715 pm_runtime_put_sync_suspend(&client->dev); 2716 2717 anx7625_unregister_i2c_dummy_clients(platform); 2718 2719 free_wq: 2720 if (platform->workqueue) 2721 destroy_workqueue(platform->workqueue); 2722 2723 free_hdcp_wq: 2724 if (platform->hdcp_workqueue) 2725 destroy_workqueue(platform->hdcp_workqueue); 2726 2727 return ret; 2728 } 2729 2730 static int anx7625_i2c_remove(struct i2c_client *client) 2731 { 2732 struct anx7625_data *platform = i2c_get_clientdata(client); 2733 2734 drm_bridge_remove(&platform->bridge); 2735 2736 if (platform->pdata.intp_irq) 2737 destroy_workqueue(platform->workqueue); 2738 2739 if (platform->hdcp_workqueue) { 2740 cancel_delayed_work(&platform->hdcp_work); 2741 flush_workqueue(platform->hdcp_workqueue); 2742 destroy_workqueue(platform->hdcp_workqueue); 2743 } 2744 2745 if (!platform->pdata.low_power_mode) 2746 pm_runtime_put_sync_suspend(&client->dev); 2747 2748 anx7625_unregister_i2c_dummy_clients(platform); 2749 2750 if (platform->pdata.audio_en) 2751 anx7625_unregister_audio(platform); 2752 2753 return 0; 2754 } 2755 2756 static const struct i2c_device_id anx7625_id[] = { 2757 {"anx7625", 0}, 2758 {} 2759 }; 2760 2761 MODULE_DEVICE_TABLE(i2c, anx7625_id); 2762 2763 static const struct of_device_id anx_match_table[] = { 2764 {.compatible = "analogix,anx7625",}, 2765 {}, 2766 }; 2767 MODULE_DEVICE_TABLE(of, anx_match_table); 2768 2769 static struct i2c_driver anx7625_driver = { 2770 .driver = { 2771 .name = "anx7625", 2772 .of_match_table = anx_match_table, 2773 .pm = &anx7625_pm_ops, 2774 }, 2775 .probe = anx7625_i2c_probe, 2776 .remove = anx7625_i2c_remove, 2777 2778 .id_table = anx7625_id, 2779 }; 2780 2781 module_i2c_driver(anx7625_driver); 2782 2783 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 2784 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 2785 MODULE_LICENSE("GPL v2"); 2786 MODULE_VERSION(ANX7625_DRV_VERSION); 2787