1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/dp/drm_dp_aux_bus.h> 28 #include <drm/dp/drm_dp_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_hdcp.h> 31 #include <drm/drm_mipi_dsi.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_panel.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include <media/v4l2-fwnode.h> 38 #include <sound/hdmi-codec.h> 39 #include <video/display_timing.h> 40 41 #include "anx7625.h" 42 43 /* 44 * There is a sync issue while access I2C register between AP(CPU) and 45 * internal firmware(OCM), to avoid the race condition, AP should access 46 * the reserved slave address before slave address occurs changes. 47 */ 48 static int i2c_access_workaround(struct anx7625_data *ctx, 49 struct i2c_client *client) 50 { 51 u8 offset; 52 struct device *dev = &client->dev; 53 int ret; 54 55 if (client == ctx->last_client) 56 return 0; 57 58 ctx->last_client = client; 59 60 if (client == ctx->i2c.tcpc_client) 61 offset = RSVD_00_ADDR; 62 else if (client == ctx->i2c.tx_p0_client) 63 offset = RSVD_D1_ADDR; 64 else if (client == ctx->i2c.tx_p1_client) 65 offset = RSVD_60_ADDR; 66 else if (client == ctx->i2c.rx_p0_client) 67 offset = RSVD_39_ADDR; 68 else if (client == ctx->i2c.rx_p1_client) 69 offset = RSVD_7F_ADDR; 70 else 71 offset = RSVD_00_ADDR; 72 73 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 74 if (ret < 0) 75 DRM_DEV_ERROR(dev, 76 "fail to access i2c id=%x\n:%x", 77 client->addr, offset); 78 79 return ret; 80 } 81 82 static int anx7625_reg_read(struct anx7625_data *ctx, 83 struct i2c_client *client, u8 reg_addr) 84 { 85 int ret; 86 struct device *dev = &client->dev; 87 88 i2c_access_workaround(ctx, client); 89 90 ret = i2c_smbus_read_byte_data(client, reg_addr); 91 if (ret < 0) 92 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 93 client->addr, reg_addr); 94 95 return ret; 96 } 97 98 static int anx7625_reg_block_read(struct anx7625_data *ctx, 99 struct i2c_client *client, 100 u8 reg_addr, u8 len, u8 *buf) 101 { 102 int ret; 103 struct device *dev = &client->dev; 104 105 i2c_access_workaround(ctx, client); 106 107 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 108 if (ret < 0) 109 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 110 client->addr, reg_addr); 111 112 return ret; 113 } 114 115 static int anx7625_reg_write(struct anx7625_data *ctx, 116 struct i2c_client *client, 117 u8 reg_addr, u8 reg_val) 118 { 119 int ret; 120 struct device *dev = &client->dev; 121 122 i2c_access_workaround(ctx, client); 123 124 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 125 126 if (ret < 0) 127 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 128 client->addr, reg_addr); 129 130 return ret; 131 } 132 133 static int anx7625_reg_block_write(struct anx7625_data *ctx, 134 struct i2c_client *client, 135 u8 reg_addr, u8 len, u8 *buf) 136 { 137 int ret; 138 struct device *dev = &client->dev; 139 140 i2c_access_workaround(ctx, client); 141 142 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 143 if (ret < 0) 144 dev_err(dev, "write i2c block failed id=%x\n:%x", 145 client->addr, reg_addr); 146 147 return ret; 148 } 149 150 static int anx7625_write_or(struct anx7625_data *ctx, 151 struct i2c_client *client, 152 u8 offset, u8 mask) 153 { 154 int val; 155 156 val = anx7625_reg_read(ctx, client, offset); 157 if (val < 0) 158 return val; 159 160 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 161 } 162 163 static int anx7625_write_and(struct anx7625_data *ctx, 164 struct i2c_client *client, 165 u8 offset, u8 mask) 166 { 167 int val; 168 169 val = anx7625_reg_read(ctx, client, offset); 170 if (val < 0) 171 return val; 172 173 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 174 } 175 176 static int anx7625_write_and_or(struct anx7625_data *ctx, 177 struct i2c_client *client, 178 u8 offset, u8 and_mask, u8 or_mask) 179 { 180 int val; 181 182 val = anx7625_reg_read(ctx, client, offset); 183 if (val < 0) 184 return val; 185 186 return anx7625_reg_write(ctx, client, 187 offset, (val & and_mask) | (or_mask)); 188 } 189 190 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 191 { 192 int i, ret; 193 194 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 195 AUDIO_CONTROL_REGISTER, 0x80); 196 for (i = 0; i < 13; i++) 197 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 198 VIDEO_BIT_MATRIX_12 + i, 199 0x18 + i); 200 201 return ret; 202 } 203 204 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 205 { 206 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 207 } 208 209 static int wait_aux_op_finish(struct anx7625_data *ctx) 210 { 211 struct device *dev = &ctx->client->dev; 212 int val; 213 int ret; 214 215 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 216 ctx, val, 217 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 218 2000, 219 2000 * 150); 220 if (ret) { 221 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 222 return -EIO; 223 } 224 225 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 226 AP_AUX_CTRL_STATUS); 227 if (val < 0 || (val & 0x0F)) { 228 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 229 return -EIO; 230 } 231 232 return 0; 233 } 234 235 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 236 u8 len, u8 *buf) 237 { 238 struct device *dev = &ctx->client->dev; 239 int ret; 240 u8 addrh, addrm, addrl; 241 u8 cmd; 242 bool is_write = !(op & DP_AUX_I2C_READ); 243 244 if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 245 dev_err(dev, "exceed aux buffer len.\n"); 246 return -EINVAL; 247 } 248 249 if (!len) 250 return len; 251 252 addrl = address & 0xFF; 253 addrm = (address >> 8) & 0xFF; 254 addrh = (address >> 16) & 0xFF; 255 256 cmd = DPCD_CMD(len, op); 257 258 /* Set command and length */ 259 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 260 AP_AUX_COMMAND, cmd); 261 262 /* Set aux access address */ 263 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 264 AP_AUX_ADDR_7_0, addrl); 265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 266 AP_AUX_ADDR_15_8, addrm); 267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 268 AP_AUX_ADDR_19_16, addrh); 269 270 if (is_write) 271 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 272 AP_AUX_BUFF_START, len, buf); 273 /* Enable aux access */ 274 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 275 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 276 277 if (ret < 0) { 278 dev_err(dev, "cannot access aux related register.\n"); 279 return -EIO; 280 } 281 282 ret = wait_aux_op_finish(ctx); 283 if (ret < 0) { 284 dev_err(dev, "aux IO error: wait aux op finish.\n"); 285 return ret; 286 } 287 288 /* Write done */ 289 if (is_write) 290 return len; 291 292 /* Read done, read out dpcd data */ 293 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 294 AP_AUX_BUFF_START, len, buf); 295 if (ret < 0) { 296 dev_err(dev, "read dpcd register failed\n"); 297 return -EIO; 298 } 299 300 return len; 301 } 302 303 static int anx7625_video_mute_control(struct anx7625_data *ctx, 304 u8 status) 305 { 306 int ret; 307 308 if (status) { 309 /* Set mute on flag */ 310 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 311 AP_AV_STATUS, AP_MIPI_MUTE); 312 /* Clear mipi RX en */ 313 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 314 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 315 } else { 316 /* Mute off flag */ 317 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 318 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 319 /* Set MIPI RX EN */ 320 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 321 AP_AV_STATUS, AP_MIPI_RX_EN); 322 } 323 324 return ret; 325 } 326 327 /* Reduction of fraction a/b */ 328 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 329 { 330 unsigned long gcd_num; 331 unsigned long tmp_a, tmp_b; 332 u32 i = 1; 333 334 gcd_num = gcd(*a, *b); 335 *a /= gcd_num; 336 *b /= gcd_num; 337 338 tmp_a = *a; 339 tmp_b = *b; 340 341 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 342 i++; 343 *a = tmp_a / i; 344 *b = tmp_b / i; 345 } 346 347 /* 348 * In the end, make a, b larger to have higher ODFC PLL 349 * output frequency accuracy 350 */ 351 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 352 *a <<= 1; 353 *b <<= 1; 354 } 355 356 *a >>= 1; 357 *b >>= 1; 358 } 359 360 static int anx7625_calculate_m_n(u32 pixelclock, 361 unsigned long *m, 362 unsigned long *n, 363 u8 *post_divider) 364 { 365 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 366 /* Pixel clock frequency is too high */ 367 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 368 pixelclock, 369 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 370 return -EINVAL; 371 } 372 373 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 374 /* Pixel clock frequency is too low */ 375 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 376 pixelclock, 377 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 378 return -EINVAL; 379 } 380 381 for (*post_divider = 1; 382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 383 *post_divider += 1; 384 385 if (*post_divider > POST_DIVIDER_MAX) { 386 for (*post_divider = 1; 387 (pixelclock < 388 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 389 *post_divider += 1; 390 391 if (*post_divider > POST_DIVIDER_MAX) { 392 DRM_ERROR("cannot find property post_divider(%d)\n", 393 *post_divider); 394 return -EDOM; 395 } 396 } 397 398 /* Patch to improve the accuracy */ 399 if (*post_divider == 7) { 400 /* 27,000,000 is not divisible by 7 */ 401 *post_divider = 8; 402 } else if (*post_divider == 11) { 403 /* 27,000,000 is not divisible by 11 */ 404 *post_divider = 12; 405 } else if ((*post_divider == 13) || (*post_divider == 14)) { 406 /* 27,000,000 is not divisible by 13 or 14 */ 407 *post_divider = 15; 408 } 409 410 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 411 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 412 pixelclock * (*post_divider), 413 PLL_OUT_FREQ_ABS_MAX); 414 return -EDOM; 415 } 416 417 *m = pixelclock; 418 *n = XTAL_FRQ / (*post_divider); 419 420 anx7625_reduction_of_a_fraction(m, n); 421 422 return 0; 423 } 424 425 static int anx7625_odfc_config(struct anx7625_data *ctx, 426 u8 post_divider) 427 { 428 int ret; 429 struct device *dev = &ctx->client->dev; 430 431 /* Config input reference clock frequency 27MHz/19.2MHz */ 432 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 433 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 434 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 435 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 436 /* Post divider */ 437 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 438 MIPI_DIGITAL_PLL_8, 0x0f); 439 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 440 post_divider << 4); 441 442 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 443 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 444 ~MIPI_PLL_VCO_TUNE_REG_VAL); 445 446 /* Reset ODFC PLL */ 447 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 448 ~MIPI_PLL_RESET_N); 449 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 450 MIPI_PLL_RESET_N); 451 452 if (ret < 0) 453 DRM_DEV_ERROR(dev, "IO error.\n"); 454 455 return ret; 456 } 457 458 /* 459 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 460 * anx7625 defined K ratio for matching MIPI input video clock and 461 * DP output video clock. Increase K value can match bigger video data 462 * variation. IVO panel has small variation than DP CTS spec, need 463 * decrease the K value. 464 */ 465 static int anx7625_set_k_value(struct anx7625_data *ctx) 466 { 467 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 468 469 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 470 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 471 MIPI_DIGITAL_ADJ_1, 0x3B); 472 473 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 474 MIPI_DIGITAL_ADJ_1, 0x3D); 475 } 476 477 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 478 { 479 struct device *dev = &ctx->client->dev; 480 unsigned long m, n; 481 u16 htotal; 482 int ret; 483 u8 post_divider = 0; 484 485 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 486 &m, &n, &post_divider); 487 488 if (ret) { 489 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 490 return ret; 491 } 492 493 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 494 m, n, post_divider); 495 496 /* Configure pixel clock */ 497 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 498 (ctx->dt.pixelclock.min / 1000) & 0xFF); 499 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 500 (ctx->dt.pixelclock.min / 1000) >> 8); 501 /* Lane count */ 502 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 503 MIPI_LANE_CTRL_0, 0xfc); 504 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 505 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 506 507 /* Htotal */ 508 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 509 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 510 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 511 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 513 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 514 /* Hactive */ 515 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 516 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 518 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 519 /* HFP */ 520 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 521 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 523 HORIZONTAL_FRONT_PORCH_H, 524 ctx->dt.hfront_porch.min >> 8); 525 /* HWS */ 526 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 527 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 529 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 530 /* HBP */ 531 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 532 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 534 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 535 /* Vactive */ 536 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 537 ctx->dt.vactive.min); 538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 539 ctx->dt.vactive.min >> 8); 540 /* VFP */ 541 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 542 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 543 /* VWS */ 544 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 545 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 546 /* VBP */ 547 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 548 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 549 /* M value */ 550 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 551 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 553 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 555 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 556 /* N value */ 557 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 558 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 560 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 562 (n & 0xff)); 563 564 anx7625_set_k_value(ctx); 565 566 ret |= anx7625_odfc_config(ctx, post_divider - 1); 567 568 if (ret < 0) 569 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 570 571 return ret; 572 } 573 574 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 575 { 576 int val; 577 struct device *dev = &ctx->client->dev; 578 579 /* Swap MIPI-DSI data lane 3 P and N */ 580 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 581 if (val < 0) { 582 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 583 return -EIO; 584 } 585 586 val |= (1 << MIPI_SWAP_CH3); 587 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 588 } 589 590 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 591 592 { 593 int val, ret; 594 struct device *dev = &ctx->client->dev; 595 596 /* Swap MIPI-DSI data lane 3 P and N */ 597 ret = anx7625_swap_dsi_lane3(ctx); 598 if (ret < 0) { 599 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 600 return ret; 601 } 602 603 /* DSI clock settings */ 604 val = (0 << MIPI_HS_PWD_CLK) | 605 (0 << MIPI_HS_RT_CLK) | 606 (0 << MIPI_PD_CLK) | 607 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 608 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 609 (0 << MIPI_CLK_DET_DET_BYPASS) | 610 (0 << MIPI_CLK_MISS_CTRL) | 611 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 612 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 613 MIPI_PHY_CONTROL_3, val); 614 615 /* 616 * Decreased HS prepare timing delay from 160ns to 80ns work with 617 * a) Dragon board 810 series (Qualcomm AP) 618 * b) Moving Pixel DSI source (PG3A pattern generator + 619 * P332 D-PHY Probe) default D-PHY timing 620 * 5ns/step 621 */ 622 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 623 MIPI_TIME_HS_PRPR, 0x10); 624 625 /* Enable DSI mode*/ 626 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 627 SELECT_DSI << MIPI_DPI_SELECT); 628 629 ret |= anx7625_dsi_video_timing_config(ctx); 630 if (ret < 0) { 631 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 632 return ret; 633 } 634 635 /* Toggle m, n ready */ 636 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 637 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 638 usleep_range(1000, 1100); 639 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 640 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 641 642 /* Configure integer stable register */ 643 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 644 MIPI_VIDEO_STABLE_CNT, 0x02); 645 /* Power on MIPI RX */ 646 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 647 MIPI_LANE_CTRL_10, 0x00); 648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 649 MIPI_LANE_CTRL_10, 0x80); 650 651 if (ret < 0) 652 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 653 654 return ret; 655 } 656 657 static int anx7625_dsi_config(struct anx7625_data *ctx) 658 { 659 struct device *dev = &ctx->client->dev; 660 int ret; 661 662 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 663 664 /* DSC disable */ 665 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 666 R_DSC_CTRL_0, ~DSC_EN); 667 668 ret |= anx7625_api_dsi_config(ctx); 669 670 if (ret < 0) { 671 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 672 return ret; 673 } 674 675 /* Set MIPI RX EN */ 676 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 677 AP_AV_STATUS, AP_MIPI_RX_EN); 678 /* Clear mute flag */ 679 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 680 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 681 if (ret < 0) 682 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 683 else 684 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 685 686 return ret; 687 } 688 689 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 690 { 691 struct device *dev = &ctx->client->dev; 692 u16 freq = ctx->dt.pixelclock.min / 1000; 693 int ret; 694 695 /* configure pixel clock */ 696 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 697 PIXEL_CLOCK_L, freq & 0xFF); 698 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 699 PIXEL_CLOCK_H, (freq >> 8)); 700 701 /* set DPI mode */ 702 /* set to DPI PLL module sel */ 703 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 704 MIPI_DIGITAL_PLL_9, 0x20); 705 /* power down MIPI */ 706 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 707 MIPI_LANE_CTRL_10, 0x08); 708 /* enable DPI mode */ 709 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 710 MIPI_DIGITAL_PLL_18, 0x1C); 711 /* set first edge */ 712 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 713 VIDEO_CONTROL_0, 0x06); 714 if (ret < 0) 715 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 716 717 return ret; 718 } 719 720 static int anx7625_dpi_config(struct anx7625_data *ctx) 721 { 722 struct device *dev = &ctx->client->dev; 723 int ret; 724 725 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 726 727 /* DSC disable */ 728 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 729 R_DSC_CTRL_0, ~DSC_EN); 730 if (ret < 0) { 731 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 732 return ret; 733 } 734 735 ret = anx7625_config_bit_matrix(ctx); 736 if (ret < 0) { 737 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 738 return ret; 739 } 740 741 ret = anx7625_api_dpi_config(ctx); 742 if (ret < 0) { 743 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 744 return ret; 745 } 746 747 /* set MIPI RX EN */ 748 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 749 AP_AV_STATUS, AP_MIPI_RX_EN); 750 /* clear mute flag */ 751 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 752 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 753 if (ret < 0) 754 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 755 756 return ret; 757 } 758 759 static int anx7625_read_flash_status(struct anx7625_data *ctx) 760 { 761 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 762 } 763 764 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 765 { 766 int ret, val; 767 struct device *dev = &ctx->client->dev; 768 u8 ident[FLASH_BUF_LEN]; 769 770 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 771 FLASH_ADDR_HIGH, 0x91); 772 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 773 FLASH_ADDR_LOW, 0xA0); 774 if (ret < 0) { 775 dev_err(dev, "IO error : set key flash address.\n"); 776 return ret; 777 } 778 779 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 780 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 781 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 782 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 783 if (ret < 0) { 784 dev_err(dev, "IO error : set key flash len.\n"); 785 return ret; 786 } 787 788 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 789 R_FLASH_RW_CTRL, FLASH_READ); 790 ret |= readx_poll_timeout(anx7625_read_flash_status, 791 ctx, val, 792 ((val & FLASH_DONE) || (val < 0)), 793 2000, 794 2000 * 150); 795 if (ret) { 796 dev_err(dev, "flash read access fail!\n"); 797 return -EIO; 798 } 799 800 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 801 FLASH_BUF_BASE_ADDR, 802 FLASH_BUF_LEN, ident); 803 if (ret < 0) { 804 dev_err(dev, "read flash data fail!\n"); 805 return -EIO; 806 } 807 808 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 809 return -EINVAL; 810 811 return 0; 812 } 813 814 static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 815 { 816 int ret; 817 struct device *dev = &ctx->client->dev; 818 819 /* Select HDCP 1.4 KEY */ 820 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 821 R_BOOT_RETRY, 0x12); 822 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 823 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 825 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 830 831 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 832 R_RAM_ADDR_H, 0); 833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 834 R_RAM_ADDR_L, 0); 835 /* Enable HDCP 1.4 KEY load */ 836 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 837 R_RAM_CTRL, DECRYPT_EN | LOAD_START); 838 dev_dbg(dev, "load HDCP 1.4 key done\n"); 839 return ret; 840 } 841 842 static int anx7625_hdcp_disable(struct anx7625_data *ctx) 843 { 844 int ret; 845 struct device *dev = &ctx->client->dev; 846 847 dev_dbg(dev, "disable HDCP 1.4\n"); 848 849 /* Disable HDCP */ 850 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 851 /* Try auth flag */ 852 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 853 /* Interrupt for DRM */ 854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 855 if (ret < 0) 856 dev_err(dev, "fail to disable HDCP\n"); 857 858 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 859 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 860 } 861 862 static int anx7625_hdcp_enable(struct anx7625_data *ctx) 863 { 864 u8 bcap; 865 int ret; 866 struct device *dev = &ctx->client->dev; 867 868 ret = anx7625_hdcp_key_probe(ctx); 869 if (ret) { 870 dev_dbg(dev, "no key found, not to do hdcp\n"); 871 return ret; 872 } 873 874 /* Read downstream capability */ 875 anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap); 876 if (!(bcap & 0x01)) { 877 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 878 return 0; 879 } 880 881 dev_dbg(dev, "enable HDCP 1.4\n"); 882 883 /* First clear HDCP state */ 884 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 885 TX_HDCP_CTRL0, 886 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 887 usleep_range(1000, 1100); 888 /* Second clear HDCP state */ 889 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 890 TX_HDCP_CTRL0, 891 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 892 893 /* Set time for waiting KSVR */ 894 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 895 SP_TX_WAIT_KSVR_TIME, 0xc8); 896 /* Set time for waiting R0 */ 897 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 898 SP_TX_WAIT_R0_TIME, 0xb0); 899 ret |= anx7625_hdcp_key_load(ctx); 900 if (ret) { 901 pr_warn("prepare HDCP key failed.\n"); 902 return ret; 903 } 904 905 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 906 907 /* Try auth flag */ 908 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 909 /* Interrupt for DRM */ 910 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 911 if (ret < 0) 912 dev_err(dev, "fail to enable HDCP\n"); 913 914 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 915 TX_HDCP_CTRL0, HARD_AUTH_EN); 916 } 917 918 static void anx7625_dp_start(struct anx7625_data *ctx) 919 { 920 int ret; 921 struct device *dev = &ctx->client->dev; 922 923 if (!ctx->display_timing_valid) { 924 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 925 return; 926 } 927 928 /* Disable HDCP */ 929 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 930 931 if (ctx->pdata.is_dpi) 932 ret = anx7625_dpi_config(ctx); 933 else 934 ret = anx7625_dsi_config(ctx); 935 936 if (ret < 0) 937 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 938 939 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 940 941 ctx->dp_en = 1; 942 } 943 944 static void anx7625_dp_stop(struct anx7625_data *ctx) 945 { 946 struct device *dev = &ctx->client->dev; 947 int ret; 948 u8 data; 949 950 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 951 952 /* 953 * Video disable: 0x72:08 bit 7 = 0; 954 * Audio disable: 0x70:87 bit 0 = 0; 955 */ 956 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 957 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 958 959 ret |= anx7625_video_mute_control(ctx, 1); 960 961 dev_dbg(dev, "notify downstream enter into standby\n"); 962 /* Downstream monitor enter into standby mode */ 963 data = 2; 964 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data); 965 if (ret < 0) 966 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 967 968 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 969 970 ctx->dp_en = 0; 971 } 972 973 static int sp_tx_rst_aux(struct anx7625_data *ctx) 974 { 975 int ret; 976 977 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 978 AUX_RST); 979 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 980 ~AUX_RST); 981 return ret; 982 } 983 984 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 985 { 986 int ret; 987 988 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 989 AP_AUX_BUFF_START, offset); 990 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 991 AP_AUX_COMMAND, 0x04); 992 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 993 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 994 return (ret | wait_aux_op_finish(ctx)); 995 } 996 997 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 998 { 999 int ret; 1000 1001 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1002 AP_AUX_COMMAND, len_cmd); 1003 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1004 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1005 return (ret | wait_aux_op_finish(ctx)); 1006 } 1007 1008 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 1009 { 1010 int c = 0; 1011 struct device *dev = &ctx->client->dev; 1012 1013 sp_tx_aux_wr(ctx, 0x7e); 1014 sp_tx_aux_rd(ctx, 0x01); 1015 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 1016 if (c < 0) { 1017 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 1018 return -EIO; 1019 } 1020 1021 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 1022 1023 if (c > MAX_EDID_BLOCK) 1024 c = 1; 1025 1026 return c; 1027 } 1028 1029 static int edid_read(struct anx7625_data *ctx, 1030 u8 offset, u8 *pblock_buf) 1031 { 1032 int ret, cnt; 1033 struct device *dev = &ctx->client->dev; 1034 1035 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1036 sp_tx_aux_wr(ctx, offset); 1037 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1038 ret = sp_tx_aux_rd(ctx, 0xf1); 1039 1040 if (ret) { 1041 ret = sp_tx_rst_aux(ctx); 1042 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 1043 } else { 1044 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1045 AP_AUX_BUFF_START, 1046 MAX_DPCD_BUFFER_SIZE, 1047 pblock_buf); 1048 if (ret > 0) 1049 break; 1050 } 1051 } 1052 1053 if (cnt > EDID_TRY_CNT) 1054 return -EIO; 1055 1056 return ret; 1057 } 1058 1059 static int segments_edid_read(struct anx7625_data *ctx, 1060 u8 segment, u8 *buf, u8 offset) 1061 { 1062 u8 cnt; 1063 int ret; 1064 struct device *dev = &ctx->client->dev; 1065 1066 /* Write address only */ 1067 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1068 AP_AUX_ADDR_7_0, 0x30); 1069 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1070 AP_AUX_COMMAND, 0x04); 1071 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1072 AP_AUX_CTRL_STATUS, 1073 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 1074 1075 ret |= wait_aux_op_finish(ctx); 1076 /* Write segment address */ 1077 ret |= sp_tx_aux_wr(ctx, segment); 1078 /* Data read */ 1079 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1080 AP_AUX_ADDR_7_0, 0x50); 1081 if (ret) { 1082 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 1083 return ret; 1084 } 1085 1086 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1087 sp_tx_aux_wr(ctx, offset); 1088 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1089 ret = sp_tx_aux_rd(ctx, 0xf1); 1090 1091 if (ret) { 1092 ret = sp_tx_rst_aux(ctx); 1093 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 1094 } else { 1095 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1096 AP_AUX_BUFF_START, 1097 MAX_DPCD_BUFFER_SIZE, buf); 1098 if (ret > 0) 1099 break; 1100 } 1101 } 1102 1103 if (cnt > EDID_TRY_CNT) 1104 return -EIO; 1105 1106 return ret; 1107 } 1108 1109 static int sp_tx_edid_read(struct anx7625_data *ctx, 1110 u8 *pedid_blocks_buf) 1111 { 1112 u8 offset, edid_pos; 1113 int count, blocks_num; 1114 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 1115 u8 i, j; 1116 int g_edid_break = 0; 1117 int ret; 1118 struct device *dev = &ctx->client->dev; 1119 1120 /* Address initial */ 1121 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1122 AP_AUX_ADDR_7_0, 0x50); 1123 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1124 AP_AUX_ADDR_15_8, 0); 1125 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 1126 AP_AUX_ADDR_19_16, 0xf0); 1127 if (ret < 0) { 1128 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 1129 return -EIO; 1130 } 1131 1132 blocks_num = sp_tx_get_edid_block(ctx); 1133 if (blocks_num < 0) 1134 return blocks_num; 1135 1136 count = 0; 1137 1138 do { 1139 switch (count) { 1140 case 0: 1141 case 1: 1142 for (i = 0; i < 8; i++) { 1143 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 1144 g_edid_break = edid_read(ctx, offset, 1145 pblock_buf); 1146 1147 if (g_edid_break < 0) 1148 break; 1149 1150 memcpy(&pedid_blocks_buf[offset], 1151 pblock_buf, 1152 MAX_DPCD_BUFFER_SIZE); 1153 } 1154 1155 break; 1156 case 2: 1157 offset = 0x00; 1158 1159 for (j = 0; j < 8; j++) { 1160 edid_pos = (j + count * 8) * 1161 MAX_DPCD_BUFFER_SIZE; 1162 1163 if (g_edid_break == 1) 1164 break; 1165 1166 ret = segments_edid_read(ctx, count / 2, 1167 pblock_buf, offset); 1168 if (ret < 0) 1169 return ret; 1170 1171 memcpy(&pedid_blocks_buf[edid_pos], 1172 pblock_buf, 1173 MAX_DPCD_BUFFER_SIZE); 1174 offset = offset + 0x10; 1175 } 1176 1177 break; 1178 case 3: 1179 offset = 0x80; 1180 1181 for (j = 0; j < 8; j++) { 1182 edid_pos = (j + count * 8) * 1183 MAX_DPCD_BUFFER_SIZE; 1184 if (g_edid_break == 1) 1185 break; 1186 1187 ret = segments_edid_read(ctx, count / 2, 1188 pblock_buf, offset); 1189 if (ret < 0) 1190 return ret; 1191 1192 memcpy(&pedid_blocks_buf[edid_pos], 1193 pblock_buf, 1194 MAX_DPCD_BUFFER_SIZE); 1195 offset = offset + 0x10; 1196 } 1197 1198 break; 1199 default: 1200 break; 1201 } 1202 1203 count++; 1204 1205 } while (blocks_num >= count); 1206 1207 /* Check edid data */ 1208 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 1209 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 1210 return -EINVAL; 1211 } 1212 1213 /* Reset aux channel */ 1214 ret = sp_tx_rst_aux(ctx); 1215 if (ret < 0) { 1216 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 1217 return ret; 1218 } 1219 1220 return (blocks_num + 1); 1221 } 1222 1223 static void anx7625_power_on(struct anx7625_data *ctx) 1224 { 1225 struct device *dev = &ctx->client->dev; 1226 int ret, i; 1227 1228 if (!ctx->pdata.low_power_mode) { 1229 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1230 return; 1231 } 1232 1233 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 1234 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 1235 if (ret < 0) { 1236 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 1237 i, ret); 1238 goto reg_err; 1239 } 1240 usleep_range(2000, 2100); 1241 } 1242 1243 usleep_range(11000, 12000); 1244 1245 /* Power on pin enable */ 1246 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 1247 usleep_range(10000, 11000); 1248 /* Power reset pin enable */ 1249 gpiod_set_value(ctx->pdata.gpio_reset, 1); 1250 usleep_range(10000, 11000); 1251 1252 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 1253 return; 1254 reg_err: 1255 for (--i; i >= 0; i--) 1256 regulator_disable(ctx->pdata.supplies[i].consumer); 1257 } 1258 1259 static void anx7625_power_standby(struct anx7625_data *ctx) 1260 { 1261 struct device *dev = &ctx->client->dev; 1262 int ret; 1263 1264 if (!ctx->pdata.low_power_mode) { 1265 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1266 return; 1267 } 1268 1269 gpiod_set_value(ctx->pdata.gpio_reset, 0); 1270 usleep_range(1000, 1100); 1271 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 1272 usleep_range(1000, 1100); 1273 1274 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1275 ctx->pdata.supplies); 1276 if (ret < 0) 1277 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1278 1279 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1280 } 1281 1282 /* Basic configurations of ANX7625 */ 1283 static void anx7625_config(struct anx7625_data *ctx) 1284 { 1285 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1286 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1287 } 1288 1289 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1290 { 1291 struct device *dev = &ctx->client->dev; 1292 int ret; 1293 1294 /* Reset main ocm */ 1295 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1296 /* Disable PD */ 1297 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1298 AP_AV_STATUS, AP_DISABLE_PD); 1299 /* Release main ocm */ 1300 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1301 1302 if (ret < 0) 1303 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1304 else 1305 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1306 } 1307 1308 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1309 { 1310 int ret; 1311 struct device *dev = &ctx->client->dev; 1312 1313 /* Check interface workable */ 1314 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1315 FLASH_LOAD_STA); 1316 if (ret < 0) { 1317 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1318 return ret; 1319 } 1320 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1321 return -ENODEV; 1322 1323 anx7625_disable_pd_protocol(ctx); 1324 1325 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1326 anx7625_reg_read(ctx, 1327 ctx->i2c.rx_p0_client, 1328 OCM_FW_VERSION), 1329 anx7625_reg_read(ctx, 1330 ctx->i2c.rx_p0_client, 1331 OCM_FW_REVERSION)); 1332 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1333 ANX7625_DRV_VERSION); 1334 1335 return 0; 1336 } 1337 1338 static void anx7625_power_on_init(struct anx7625_data *ctx) 1339 { 1340 int retry_count, i; 1341 1342 for (retry_count = 0; retry_count < 3; retry_count++) { 1343 anx7625_power_on(ctx); 1344 anx7625_config(ctx); 1345 1346 for (i = 0; i < OCM_LOADING_TIME; i++) { 1347 if (!anx7625_ocm_loading_check(ctx)) 1348 return; 1349 usleep_range(1000, 1100); 1350 } 1351 anx7625_power_standby(ctx); 1352 } 1353 } 1354 1355 static void anx7625_init_gpio(struct anx7625_data *platform) 1356 { 1357 struct device *dev = &platform->client->dev; 1358 1359 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1360 1361 /* Gpio for chip power enable */ 1362 platform->pdata.gpio_p_on = 1363 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1364 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 1365 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 1366 platform->pdata.gpio_p_on = NULL; 1367 } 1368 1369 /* Gpio for chip reset */ 1370 platform->pdata.gpio_reset = 1371 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1372 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 1373 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 1374 platform->pdata.gpio_reset = NULL; 1375 } 1376 1377 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1378 platform->pdata.low_power_mode = 1; 1379 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1380 desc_to_gpio(platform->pdata.gpio_p_on), 1381 desc_to_gpio(platform->pdata.gpio_reset)); 1382 } else { 1383 platform->pdata.low_power_mode = 0; 1384 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1385 } 1386 } 1387 1388 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1389 { 1390 ctx->hpd_status = 0; 1391 ctx->hpd_high_cnt = 0; 1392 ctx->display_timing_valid = 0; 1393 } 1394 1395 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1396 { 1397 int ret; 1398 struct device *dev = &ctx->client->dev; 1399 1400 if (ctx->hpd_high_cnt >= 2) { 1401 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1402 return; 1403 } 1404 1405 ctx->hpd_status = 1; 1406 ctx->hpd_high_cnt++; 1407 1408 /* Not support HDCP */ 1409 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1410 1411 /* Try auth flag */ 1412 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1413 /* Interrupt for DRM */ 1414 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1415 if (ret < 0) { 1416 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1417 return; 1418 } 1419 1420 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1421 if (ret < 0) 1422 return; 1423 1424 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1425 } 1426 1427 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1428 { 1429 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1430 } 1431 1432 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1433 { 1434 int ret, val; 1435 struct device *dev = &ctx->client->dev; 1436 1437 /* Interrupt mode, no need poll HPD status, just return */ 1438 if (ctx->pdata.intp_irq) 1439 return; 1440 1441 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1442 ctx, val, 1443 ((val & HPD_STATUS) || (val < 0)), 1444 5000, 1445 5000 * 100); 1446 if (ret) { 1447 DRM_DEV_ERROR(dev, "no hpd.\n"); 1448 return; 1449 } 1450 1451 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1452 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1453 INTR_ALERT_1, 0xFF); 1454 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1455 INTERFACE_CHANGE_INT, 0); 1456 1457 anx7625_start_dp_work(ctx); 1458 1459 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1460 drm_helper_hpd_irq_event(ctx->bridge.dev); 1461 } 1462 1463 static void anx7625_remove_edid(struct anx7625_data *ctx) 1464 { 1465 ctx->slimport_edid_p.edid_block_num = -1; 1466 } 1467 1468 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1469 { 1470 int i; 1471 1472 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1473 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1474 DP_TX_LANE0_SWING_REG0 + i, 1475 ctx->pdata.lane0_reg_data[i] & 0xFF); 1476 1477 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1478 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1479 DP_TX_LANE1_SWING_REG0 + i, 1480 ctx->pdata.lane1_reg_data[i] & 0xFF); 1481 } 1482 1483 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1484 { 1485 struct device *dev = &ctx->client->dev; 1486 1487 /* HPD changed */ 1488 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1489 (u32)on); 1490 1491 if (on == 0) { 1492 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1493 anx7625_remove_edid(ctx); 1494 anx7625_stop_dp_work(ctx); 1495 } else { 1496 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1497 anx7625_start_dp_work(ctx); 1498 anx7625_dp_adjust_swing(ctx); 1499 } 1500 } 1501 1502 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1503 { 1504 int intr_vector, status; 1505 struct device *dev = &ctx->client->dev; 1506 1507 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1508 INTR_ALERT_1, 0xFF); 1509 if (status < 0) { 1510 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1511 return status; 1512 } 1513 1514 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1515 INTERFACE_CHANGE_INT); 1516 if (intr_vector < 0) { 1517 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1518 return intr_vector; 1519 } 1520 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1521 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1522 INTERFACE_CHANGE_INT, 1523 intr_vector & (~intr_vector)); 1524 if (status < 0) { 1525 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1526 return status; 1527 } 1528 1529 if (!(intr_vector & HPD_STATUS_CHANGE)) 1530 return -ENOENT; 1531 1532 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1533 SYSTEM_STSTUS); 1534 if (status < 0) { 1535 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1536 return status; 1537 } 1538 1539 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1540 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1541 1542 return 0; 1543 } 1544 1545 static void anx7625_work_func(struct work_struct *work) 1546 { 1547 int event; 1548 struct anx7625_data *ctx = container_of(work, 1549 struct anx7625_data, work); 1550 1551 mutex_lock(&ctx->lock); 1552 1553 if (pm_runtime_suspended(&ctx->client->dev)) 1554 goto unlock; 1555 1556 event = anx7625_hpd_change_detect(ctx); 1557 if (event < 0) 1558 goto unlock; 1559 1560 if (ctx->bridge_attached) 1561 drm_helper_hpd_irq_event(ctx->bridge.dev); 1562 1563 unlock: 1564 mutex_unlock(&ctx->lock); 1565 } 1566 1567 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1568 { 1569 struct anx7625_data *ctx = (struct anx7625_data *)data; 1570 1571 queue_work(ctx->workqueue, &ctx->work); 1572 1573 return IRQ_HANDLED; 1574 } 1575 1576 static int anx7625_get_swing_setting(struct device *dev, 1577 struct anx7625_platform_data *pdata) 1578 { 1579 int num_regs; 1580 1581 if (of_get_property(dev->of_node, 1582 "analogix,lane0-swing", &num_regs)) { 1583 if (num_regs > DP_TX_SWING_REG_CNT) 1584 num_regs = DP_TX_SWING_REG_CNT; 1585 1586 pdata->dp_lane0_swing_reg_cnt = num_regs; 1587 of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1588 pdata->lane0_reg_data, num_regs); 1589 } 1590 1591 if (of_get_property(dev->of_node, 1592 "analogix,lane1-swing", &num_regs)) { 1593 if (num_regs > DP_TX_SWING_REG_CNT) 1594 num_regs = DP_TX_SWING_REG_CNT; 1595 1596 pdata->dp_lane1_swing_reg_cnt = num_regs; 1597 of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1598 pdata->lane1_reg_data, num_regs); 1599 } 1600 1601 return 0; 1602 } 1603 1604 static int anx7625_parse_dt(struct device *dev, 1605 struct anx7625_platform_data *pdata) 1606 { 1607 struct device_node *np = dev->of_node, *ep0; 1608 struct drm_panel *panel; 1609 int ret; 1610 int bus_type, mipi_lanes; 1611 1612 anx7625_get_swing_setting(dev, pdata); 1613 1614 pdata->is_dpi = 1; /* default dpi mode */ 1615 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1616 if (!pdata->mipi_host_node) { 1617 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1618 return -ENODEV; 1619 } 1620 1621 bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1622 mipi_lanes = MAX_LANES_SUPPORT; 1623 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1624 if (ep0) { 1625 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1626 bus_type = 0; 1627 1628 mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1629 } 1630 1631 if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1632 pdata->is_dpi = 0; 1633 1634 pdata->mipi_lanes = mipi_lanes; 1635 if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1636 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1637 1638 if (pdata->is_dpi) 1639 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1640 else 1641 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1642 1643 if (of_property_read_bool(np, "analogix,audio-enable")) 1644 pdata->audio_en = 1; 1645 1646 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1647 if (ret < 0) { 1648 if (ret == -ENODEV) 1649 return 0; 1650 return ret; 1651 } 1652 if (!panel) 1653 return -ENODEV; 1654 1655 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1656 if (IS_ERR(pdata->panel_bridge)) 1657 return PTR_ERR(pdata->panel_bridge); 1658 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1659 1660 return 0; 1661 } 1662 1663 static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1664 { 1665 struct device_node *bus, *panel; 1666 1667 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1668 if (!bus) 1669 return false; 1670 1671 panel = of_get_child_by_name(bus, "panel"); 1672 of_node_put(bus); 1673 if (!panel) 1674 return false; 1675 of_node_put(panel); 1676 1677 return true; 1678 } 1679 1680 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1681 { 1682 return container_of(bridge, struct anx7625_data, bridge); 1683 } 1684 1685 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1686 struct drm_dp_aux_msg *msg) 1687 { 1688 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1689 struct device *dev = &ctx->client->dev; 1690 u8 request = msg->request & ~DP_AUX_I2C_MOT; 1691 int ret = 0; 1692 1693 pm_runtime_get_sync(dev); 1694 msg->reply = 0; 1695 switch (request) { 1696 case DP_AUX_NATIVE_WRITE: 1697 case DP_AUX_I2C_WRITE: 1698 case DP_AUX_NATIVE_READ: 1699 case DP_AUX_I2C_READ: 1700 break; 1701 default: 1702 ret = -EINVAL; 1703 } 1704 if (!ret) 1705 ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1706 msg->size, msg->buffer); 1707 pm_runtime_mark_last_busy(dev); 1708 pm_runtime_put_autosuspend(dev); 1709 1710 return ret; 1711 } 1712 1713 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1714 { 1715 struct device *dev = &ctx->client->dev; 1716 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1717 int edid_num; 1718 u8 *edid; 1719 1720 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1721 if (!edid) { 1722 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1723 return NULL; 1724 } 1725 1726 if (ctx->slimport_edid_p.edid_block_num > 0) { 1727 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1728 FOUR_BLOCK_SIZE); 1729 return (struct edid *)edid; 1730 } 1731 1732 pm_runtime_get_sync(dev); 1733 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1734 pm_runtime_put_sync(dev); 1735 1736 if (edid_num < 1) { 1737 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1738 kfree(edid); 1739 return NULL; 1740 } 1741 1742 p_edid->edid_block_num = edid_num; 1743 1744 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1745 return (struct edid *)edid; 1746 } 1747 1748 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1749 { 1750 struct device *dev = &ctx->client->dev; 1751 1752 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1753 1754 if (ctx->pdata.panel_bridge) 1755 return connector_status_connected; 1756 1757 return ctx->hpd_status ? connector_status_connected : 1758 connector_status_disconnected; 1759 } 1760 1761 static int anx7625_audio_hw_params(struct device *dev, void *data, 1762 struct hdmi_codec_daifmt *fmt, 1763 struct hdmi_codec_params *params) 1764 { 1765 struct anx7625_data *ctx = dev_get_drvdata(dev); 1766 int wl, ch, rate; 1767 int ret = 0; 1768 1769 if (fmt->fmt != HDMI_DSP_A) { 1770 DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1771 return -EINVAL; 1772 } 1773 1774 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1775 params->sample_rate, params->sample_width, 1776 params->cea.channels); 1777 1778 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1779 AUDIO_CHANNEL_STATUS_6, 1780 ~I2S_SLAVE_MODE, 1781 TDM_SLAVE_MODE); 1782 1783 /* Word length */ 1784 switch (params->sample_width) { 1785 case 16: 1786 wl = AUDIO_W_LEN_16_20MAX; 1787 break; 1788 case 18: 1789 wl = AUDIO_W_LEN_18_20MAX; 1790 break; 1791 case 20: 1792 wl = AUDIO_W_LEN_20_20MAX; 1793 break; 1794 case 24: 1795 wl = AUDIO_W_LEN_24_24MAX; 1796 break; 1797 default: 1798 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1799 params->sample_width); 1800 return -EINVAL; 1801 } 1802 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1803 AUDIO_CHANNEL_STATUS_5, 1804 0xf0, wl); 1805 1806 /* Channel num */ 1807 switch (params->cea.channels) { 1808 case 2: 1809 ch = I2S_CH_2; 1810 break; 1811 case 4: 1812 ch = TDM_CH_4; 1813 break; 1814 case 6: 1815 ch = TDM_CH_6; 1816 break; 1817 case 8: 1818 ch = TDM_CH_8; 1819 break; 1820 default: 1821 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1822 params->cea.channels); 1823 return -EINVAL; 1824 } 1825 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1826 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1827 if (ch > I2S_CH_2) 1828 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1829 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1830 else 1831 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1832 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1833 1834 /* FS */ 1835 switch (params->sample_rate) { 1836 case 32000: 1837 rate = AUDIO_FS_32K; 1838 break; 1839 case 44100: 1840 rate = AUDIO_FS_441K; 1841 break; 1842 case 48000: 1843 rate = AUDIO_FS_48K; 1844 break; 1845 case 88200: 1846 rate = AUDIO_FS_882K; 1847 break; 1848 case 96000: 1849 rate = AUDIO_FS_96K; 1850 break; 1851 case 176400: 1852 rate = AUDIO_FS_1764K; 1853 break; 1854 case 192000: 1855 rate = AUDIO_FS_192K; 1856 break; 1857 default: 1858 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1859 params->sample_rate); 1860 return -EINVAL; 1861 } 1862 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1863 AUDIO_CHANNEL_STATUS_4, 1864 0xf0, rate); 1865 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1866 AP_AV_STATUS, AP_AUDIO_CHG); 1867 if (ret < 0) { 1868 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1869 return -EIO; 1870 } 1871 1872 return 0; 1873 } 1874 1875 static void anx7625_audio_shutdown(struct device *dev, void *data) 1876 { 1877 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1878 } 1879 1880 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1881 struct device_node *endpoint) 1882 { 1883 struct of_endpoint of_ep; 1884 int ret; 1885 1886 ret = of_graph_parse_endpoint(endpoint, &of_ep); 1887 if (ret < 0) 1888 return ret; 1889 1890 /* 1891 * HDMI sound should be located at external DPI port 1892 * Didn't have good way to check where is internal(DSI) 1893 * or external(DPI) bridge 1894 */ 1895 return 0; 1896 } 1897 1898 static void 1899 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1900 enum drm_connector_status status) 1901 { 1902 if (ctx->plugged_cb && ctx->codec_dev) { 1903 ctx->plugged_cb(ctx->codec_dev, 1904 status == connector_status_connected); 1905 } 1906 } 1907 1908 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1909 hdmi_codec_plugged_cb fn, 1910 struct device *codec_dev) 1911 { 1912 struct anx7625_data *ctx = data; 1913 1914 ctx->plugged_cb = fn; 1915 ctx->codec_dev = codec_dev; 1916 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1917 1918 return 0; 1919 } 1920 1921 static int anx7625_audio_get_eld(struct device *dev, void *data, 1922 u8 *buf, size_t len) 1923 { 1924 struct anx7625_data *ctx = dev_get_drvdata(dev); 1925 1926 if (!ctx->connector) { 1927 dev_err(dev, "connector not initial\n"); 1928 return -EINVAL; 1929 } 1930 1931 dev_dbg(dev, "audio copy eld\n"); 1932 memcpy(buf, ctx->connector->eld, 1933 min(sizeof(ctx->connector->eld), len)); 1934 1935 return 0; 1936 } 1937 1938 static const struct hdmi_codec_ops anx7625_codec_ops = { 1939 .hw_params = anx7625_audio_hw_params, 1940 .audio_shutdown = anx7625_audio_shutdown, 1941 .get_eld = anx7625_audio_get_eld, 1942 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1943 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1944 }; 1945 1946 static void anx7625_unregister_audio(struct anx7625_data *ctx) 1947 { 1948 struct device *dev = &ctx->client->dev; 1949 1950 if (ctx->audio_pdev) { 1951 platform_device_unregister(ctx->audio_pdev); 1952 ctx->audio_pdev = NULL; 1953 } 1954 1955 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1956 } 1957 1958 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1959 { 1960 struct hdmi_codec_pdata codec_data = { 1961 .ops = &anx7625_codec_ops, 1962 .max_i2s_channels = 8, 1963 .i2s = 1, 1964 .data = ctx, 1965 }; 1966 1967 ctx->audio_pdev = platform_device_register_data(dev, 1968 HDMI_CODEC_DRV_NAME, 1969 PLATFORM_DEVID_AUTO, 1970 &codec_data, 1971 sizeof(codec_data)); 1972 1973 if (IS_ERR(ctx->audio_pdev)) 1974 return PTR_ERR(ctx->audio_pdev); 1975 1976 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1977 1978 return 0; 1979 } 1980 1981 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1982 { 1983 struct mipi_dsi_device *dsi; 1984 struct device *dev = &ctx->client->dev; 1985 struct mipi_dsi_host *host; 1986 const struct mipi_dsi_device_info info = { 1987 .type = "anx7625", 1988 .channel = 0, 1989 .node = NULL, 1990 }; 1991 int ret; 1992 1993 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1994 1995 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1996 if (!host) { 1997 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1998 return -EPROBE_DEFER; 1999 } 2000 2001 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2002 if (IS_ERR(dsi)) { 2003 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 2004 return -EINVAL; 2005 } 2006 2007 dsi->lanes = ctx->pdata.mipi_lanes; 2008 dsi->format = MIPI_DSI_FMT_RGB888; 2009 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 2010 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2011 MIPI_DSI_MODE_VIDEO_HSE; 2012 2013 ret = devm_mipi_dsi_attach(dev, dsi); 2014 if (ret) { 2015 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 2016 return ret; 2017 } 2018 2019 ctx->dsi = dsi; 2020 2021 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 2022 2023 return 0; 2024 } 2025 2026 static void hdcp_check_work_func(struct work_struct *work) 2027 { 2028 u8 status; 2029 struct delayed_work *dwork; 2030 struct anx7625_data *ctx; 2031 struct device *dev; 2032 struct drm_device *drm_dev; 2033 2034 dwork = to_delayed_work(work); 2035 ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2036 dev = &ctx->client->dev; 2037 2038 if (!ctx->connector) { 2039 dev_err(dev, "HDCP connector is null!"); 2040 return; 2041 } 2042 2043 drm_dev = ctx->connector->dev; 2044 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2045 mutex_lock(&ctx->hdcp_wq_lock); 2046 2047 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2048 dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2049 if (status & BIT(1)) { 2050 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2051 drm_hdcp_update_content_protection(ctx->connector, 2052 ctx->hdcp_cp); 2053 dev_dbg(dev, "update CP to ENABLE\n"); 2054 } 2055 2056 mutex_unlock(&ctx->hdcp_wq_lock); 2057 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2058 } 2059 2060 static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2061 struct drm_connector_state *state) 2062 { 2063 struct device *dev = &ctx->client->dev; 2064 int cp; 2065 2066 dev_dbg(dev, "hdcp state check\n"); 2067 cp = state->content_protection; 2068 2069 if (cp == ctx->hdcp_cp) 2070 return 0; 2071 2072 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2073 if (ctx->dp_en) { 2074 dev_dbg(dev, "enable HDCP\n"); 2075 anx7625_hdcp_enable(ctx); 2076 2077 queue_delayed_work(ctx->hdcp_workqueue, 2078 &ctx->hdcp_work, 2079 msecs_to_jiffies(2000)); 2080 } 2081 } 2082 2083 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2084 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2085 dev_err(dev, "current CP is not ENABLED\n"); 2086 return -EINVAL; 2087 } 2088 anx7625_hdcp_disable(ctx); 2089 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2090 drm_hdcp_update_content_protection(ctx->connector, 2091 ctx->hdcp_cp); 2092 dev_dbg(dev, "update CP to UNDESIRE\n"); 2093 } 2094 2095 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2096 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2097 return -EINVAL; 2098 } 2099 2100 return 0; 2101 } 2102 2103 static int anx7625_bridge_attach(struct drm_bridge *bridge, 2104 enum drm_bridge_attach_flags flags) 2105 { 2106 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2107 int err; 2108 struct device *dev = &ctx->client->dev; 2109 2110 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 2111 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 2112 return -EINVAL; 2113 2114 if (!bridge->encoder) { 2115 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 2116 return -ENODEV; 2117 } 2118 2119 ctx->aux.drm_dev = bridge->dev; 2120 err = drm_dp_aux_register(&ctx->aux); 2121 if (err) { 2122 dev_err(dev, "failed to register aux channel: %d\n", err); 2123 return err; 2124 } 2125 2126 if (ctx->pdata.panel_bridge) { 2127 err = drm_bridge_attach(bridge->encoder, 2128 ctx->pdata.panel_bridge, 2129 &ctx->bridge, flags); 2130 if (err) 2131 return err; 2132 } 2133 2134 ctx->bridge_attached = 1; 2135 2136 return 0; 2137 } 2138 2139 static void anx7625_bridge_detach(struct drm_bridge *bridge) 2140 { 2141 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2142 2143 drm_dp_aux_unregister(&ctx->aux); 2144 } 2145 2146 static enum drm_mode_status 2147 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 2148 const struct drm_display_info *info, 2149 const struct drm_display_mode *mode) 2150 { 2151 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2152 struct device *dev = &ctx->client->dev; 2153 2154 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 2155 2156 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 2157 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 2158 DRM_DEV_DEBUG_DRIVER(dev, 2159 "drm mode invalid, pixelclock too high.\n"); 2160 return MODE_CLOCK_HIGH; 2161 } 2162 2163 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 2164 2165 return MODE_OK; 2166 } 2167 2168 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 2169 const struct drm_display_mode *old_mode, 2170 const struct drm_display_mode *mode) 2171 { 2172 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2173 struct device *dev = &ctx->client->dev; 2174 2175 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 2176 2177 ctx->dt.pixelclock.min = mode->clock; 2178 ctx->dt.hactive.min = mode->hdisplay; 2179 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 2180 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 2181 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 2182 ctx->dt.vactive.min = mode->vdisplay; 2183 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 2184 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 2185 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 2186 2187 ctx->display_timing_valid = 1; 2188 2189 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 2190 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 2191 ctx->dt.hactive.min, 2192 ctx->dt.hsync_len.min, 2193 ctx->dt.hfront_porch.min, 2194 ctx->dt.hback_porch.min); 2195 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 2196 ctx->dt.vactive.min, 2197 ctx->dt.vsync_len.min, 2198 ctx->dt.vfront_porch.min, 2199 ctx->dt.vback_porch.min); 2200 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 2201 mode->hdisplay, 2202 mode->hsync_start); 2203 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 2204 mode->hsync_end, 2205 mode->htotal); 2206 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 2207 mode->vdisplay, 2208 mode->vsync_start); 2209 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 2210 mode->vsync_end, 2211 mode->vtotal); 2212 } 2213 2214 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 2215 const struct drm_display_mode *mode, 2216 struct drm_display_mode *adj) 2217 { 2218 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2219 struct device *dev = &ctx->client->dev; 2220 u32 hsync, hfp, hbp, hblanking; 2221 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 2222 u32 vref, adj_clock; 2223 2224 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 2225 2226 /* No need fixup for external monitor */ 2227 if (!ctx->pdata.panel_bridge) 2228 return true; 2229 2230 hsync = mode->hsync_end - mode->hsync_start; 2231 hfp = mode->hsync_start - mode->hdisplay; 2232 hbp = mode->htotal - mode->hsync_end; 2233 hblanking = mode->htotal - mode->hdisplay; 2234 2235 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 2236 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2237 hsync, hfp, hbp, adj->clock); 2238 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2239 adj->hsync_start, adj->hsync_end, adj->htotal); 2240 2241 adj_hfp = hfp; 2242 adj_hsync = hsync; 2243 adj_hbp = hbp; 2244 adj_hblanking = hblanking; 2245 2246 /* HFP needs to be even */ 2247 if (hfp & 0x1) { 2248 adj_hfp += 1; 2249 adj_hblanking += 1; 2250 } 2251 2252 /* HBP needs to be even */ 2253 if (hbp & 0x1) { 2254 adj_hbp -= 1; 2255 adj_hblanking -= 1; 2256 } 2257 2258 /* HSYNC needs to be even */ 2259 if (hsync & 0x1) { 2260 if (adj_hblanking < hblanking) 2261 adj_hsync += 1; 2262 else 2263 adj_hsync -= 1; 2264 } 2265 2266 /* 2267 * Once illegal timing detected, use default HFP, HSYNC, HBP 2268 * This adjusting made for built-in eDP panel, for the externel 2269 * DP monitor, may need return false. 2270 */ 2271 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 2272 adj_hsync = SYNC_LEN_DEF; 2273 adj_hfp = HFP_HBP_DEF; 2274 adj_hbp = HFP_HBP_DEF; 2275 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 2276 if (hblanking < HBLANKING_MIN) { 2277 delta_adj = HBLANKING_MIN - hblanking; 2278 adj_clock = vref * delta_adj * adj->vtotal; 2279 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 2280 } else { 2281 delta_adj = hblanking - HBLANKING_MIN; 2282 adj_clock = vref * delta_adj * adj->vtotal; 2283 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 2284 } 2285 2286 DRM_WARN("illegal hblanking timing, use default.\n"); 2287 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 2288 } else if (adj_hfp < HP_MIN) { 2289 /* Adjust hfp if hfp less than HP_MIN */ 2290 delta_adj = HP_MIN - adj_hfp; 2291 adj_hfp = HP_MIN; 2292 2293 /* 2294 * Balance total HBlanking pixel, if HBP does not have enough 2295 * space, adjust HSYNC length, otherwise adjust HBP 2296 */ 2297 if ((adj_hbp - delta_adj) < HP_MIN) 2298 /* HBP not enough space */ 2299 adj_hsync -= delta_adj; 2300 else 2301 adj_hbp -= delta_adj; 2302 } else if (adj_hbp < HP_MIN) { 2303 delta_adj = HP_MIN - adj_hbp; 2304 adj_hbp = HP_MIN; 2305 2306 /* 2307 * Balance total HBlanking pixel, if HBP hasn't enough space, 2308 * adjust HSYNC length, otherwize adjust HBP 2309 */ 2310 if ((adj_hfp - delta_adj) < HP_MIN) 2311 /* HFP not enough space */ 2312 adj_hsync -= delta_adj; 2313 else 2314 adj_hfp -= delta_adj; 2315 } 2316 2317 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 2318 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2319 adj_hsync, adj_hfp, adj_hbp, adj->clock); 2320 2321 /* Reconstruct timing */ 2322 adj->hsync_start = adj->hdisplay + adj_hfp; 2323 adj->hsync_end = adj->hsync_start + adj_hsync; 2324 adj->htotal = adj->hsync_end + adj_hbp; 2325 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2326 adj->hsync_start, adj->hsync_end, adj->htotal); 2327 2328 return true; 2329 } 2330 2331 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2332 struct drm_bridge_state *bridge_state, 2333 struct drm_crtc_state *crtc_state, 2334 struct drm_connector_state *conn_state) 2335 { 2336 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2337 struct device *dev = &ctx->client->dev; 2338 2339 dev_dbg(dev, "drm bridge atomic check\n"); 2340 2341 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2342 &crtc_state->adjusted_mode); 2343 2344 return anx7625_connector_atomic_check(ctx, conn_state); 2345 } 2346 2347 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2348 struct drm_bridge_state *state) 2349 { 2350 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2351 struct device *dev = &ctx->client->dev; 2352 struct drm_connector *connector; 2353 2354 dev_dbg(dev, "drm atomic enable\n"); 2355 2356 if (!bridge->encoder) { 2357 dev_err(dev, "Parent encoder object not found"); 2358 return; 2359 } 2360 2361 connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2362 bridge->encoder); 2363 if (!connector) 2364 return; 2365 2366 ctx->connector = connector; 2367 2368 pm_runtime_get_sync(dev); 2369 2370 anx7625_dp_start(ctx); 2371 } 2372 2373 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2374 struct drm_bridge_state *old) 2375 { 2376 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2377 struct device *dev = &ctx->client->dev; 2378 2379 dev_dbg(dev, "drm atomic disable\n"); 2380 2381 ctx->connector = NULL; 2382 anx7625_dp_stop(ctx); 2383 2384 pm_runtime_put_sync(dev); 2385 } 2386 2387 static enum drm_connector_status 2388 anx7625_bridge_detect(struct drm_bridge *bridge) 2389 { 2390 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2391 struct device *dev = &ctx->client->dev; 2392 2393 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 2394 2395 return anx7625_sink_detect(ctx); 2396 } 2397 2398 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 2399 struct drm_connector *connector) 2400 { 2401 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2402 struct device *dev = &ctx->client->dev; 2403 2404 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 2405 2406 return anx7625_get_edid(ctx); 2407 } 2408 2409 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 2410 .attach = anx7625_bridge_attach, 2411 .detach = anx7625_bridge_detach, 2412 .mode_valid = anx7625_bridge_mode_valid, 2413 .mode_set = anx7625_bridge_mode_set, 2414 .atomic_check = anx7625_bridge_atomic_check, 2415 .atomic_enable = anx7625_bridge_atomic_enable, 2416 .atomic_disable = anx7625_bridge_atomic_disable, 2417 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2418 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2419 .atomic_reset = drm_atomic_helper_bridge_reset, 2420 .detect = anx7625_bridge_detect, 2421 .get_edid = anx7625_bridge_get_edid, 2422 }; 2423 2424 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 2425 struct i2c_client *client) 2426 { 2427 int err = 0; 2428 2429 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 2430 TX_P0_ADDR >> 1); 2431 if (IS_ERR(ctx->i2c.tx_p0_client)) 2432 return PTR_ERR(ctx->i2c.tx_p0_client); 2433 2434 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 2435 TX_P1_ADDR >> 1); 2436 if (IS_ERR(ctx->i2c.tx_p1_client)) { 2437 err = PTR_ERR(ctx->i2c.tx_p1_client); 2438 goto free_tx_p0; 2439 } 2440 2441 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 2442 TX_P2_ADDR >> 1); 2443 if (IS_ERR(ctx->i2c.tx_p2_client)) { 2444 err = PTR_ERR(ctx->i2c.tx_p2_client); 2445 goto free_tx_p1; 2446 } 2447 2448 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 2449 RX_P0_ADDR >> 1); 2450 if (IS_ERR(ctx->i2c.rx_p0_client)) { 2451 err = PTR_ERR(ctx->i2c.rx_p0_client); 2452 goto free_tx_p2; 2453 } 2454 2455 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 2456 RX_P1_ADDR >> 1); 2457 if (IS_ERR(ctx->i2c.rx_p1_client)) { 2458 err = PTR_ERR(ctx->i2c.rx_p1_client); 2459 goto free_rx_p0; 2460 } 2461 2462 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 2463 RX_P2_ADDR >> 1); 2464 if (IS_ERR(ctx->i2c.rx_p2_client)) { 2465 err = PTR_ERR(ctx->i2c.rx_p2_client); 2466 goto free_rx_p1; 2467 } 2468 2469 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 2470 TCPC_INTERFACE_ADDR >> 1); 2471 if (IS_ERR(ctx->i2c.tcpc_client)) { 2472 err = PTR_ERR(ctx->i2c.tcpc_client); 2473 goto free_rx_p2; 2474 } 2475 2476 return 0; 2477 2478 free_rx_p2: 2479 i2c_unregister_device(ctx->i2c.rx_p2_client); 2480 free_rx_p1: 2481 i2c_unregister_device(ctx->i2c.rx_p1_client); 2482 free_rx_p0: 2483 i2c_unregister_device(ctx->i2c.rx_p0_client); 2484 free_tx_p2: 2485 i2c_unregister_device(ctx->i2c.tx_p2_client); 2486 free_tx_p1: 2487 i2c_unregister_device(ctx->i2c.tx_p1_client); 2488 free_tx_p0: 2489 i2c_unregister_device(ctx->i2c.tx_p0_client); 2490 2491 return err; 2492 } 2493 2494 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 2495 { 2496 i2c_unregister_device(ctx->i2c.tx_p0_client); 2497 i2c_unregister_device(ctx->i2c.tx_p1_client); 2498 i2c_unregister_device(ctx->i2c.tx_p2_client); 2499 i2c_unregister_device(ctx->i2c.rx_p0_client); 2500 i2c_unregister_device(ctx->i2c.rx_p1_client); 2501 i2c_unregister_device(ctx->i2c.rx_p2_client); 2502 i2c_unregister_device(ctx->i2c.tcpc_client); 2503 } 2504 2505 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2506 { 2507 struct anx7625_data *ctx = dev_get_drvdata(dev); 2508 2509 mutex_lock(&ctx->lock); 2510 2511 anx7625_stop_dp_work(ctx); 2512 anx7625_power_standby(ctx); 2513 2514 mutex_unlock(&ctx->lock); 2515 2516 return 0; 2517 } 2518 2519 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2520 { 2521 struct anx7625_data *ctx = dev_get_drvdata(dev); 2522 2523 mutex_lock(&ctx->lock); 2524 2525 anx7625_power_on_init(ctx); 2526 anx7625_hpd_polling(ctx); 2527 2528 mutex_unlock(&ctx->lock); 2529 2530 return 0; 2531 } 2532 2533 static int __maybe_unused anx7625_resume(struct device *dev) 2534 { 2535 struct anx7625_data *ctx = dev_get_drvdata(dev); 2536 2537 if (!ctx->pdata.intp_irq) 2538 return 0; 2539 2540 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2541 enable_irq(ctx->pdata.intp_irq); 2542 anx7625_runtime_pm_resume(dev); 2543 } 2544 2545 return 0; 2546 } 2547 2548 static int __maybe_unused anx7625_suspend(struct device *dev) 2549 { 2550 struct anx7625_data *ctx = dev_get_drvdata(dev); 2551 2552 if (!ctx->pdata.intp_irq) 2553 return 0; 2554 2555 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2556 anx7625_runtime_pm_suspend(dev); 2557 disable_irq(ctx->pdata.intp_irq); 2558 } 2559 2560 return 0; 2561 } 2562 2563 static const struct dev_pm_ops anx7625_pm_ops = { 2564 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 2565 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2566 anx7625_runtime_pm_resume, NULL) 2567 }; 2568 2569 static void anx7625_runtime_disable(void *data) 2570 { 2571 pm_runtime_dont_use_autosuspend(data); 2572 pm_runtime_disable(data); 2573 } 2574 2575 static int anx7625_i2c_probe(struct i2c_client *client, 2576 const struct i2c_device_id *id) 2577 { 2578 struct anx7625_data *platform; 2579 struct anx7625_platform_data *pdata; 2580 int ret = 0; 2581 struct device *dev = &client->dev; 2582 2583 if (!i2c_check_functionality(client->adapter, 2584 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2585 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2586 return -ENODEV; 2587 } 2588 2589 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL); 2590 if (!platform) { 2591 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2592 return -ENOMEM; 2593 } 2594 2595 pdata = &platform->pdata; 2596 2597 platform->client = client; 2598 i2c_set_clientdata(client, platform); 2599 2600 pdata->supplies[0].supply = "vdd10"; 2601 pdata->supplies[1].supply = "vdd18"; 2602 pdata->supplies[2].supply = "vdd33"; 2603 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2604 pdata->supplies); 2605 if (ret) { 2606 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2607 return ret; 2608 } 2609 anx7625_init_gpio(platform); 2610 2611 mutex_init(&platform->lock); 2612 mutex_init(&platform->hdcp_wq_lock); 2613 2614 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2615 platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2616 if (!platform->hdcp_workqueue) { 2617 dev_err(dev, "fail to create work queue\n"); 2618 ret = -ENOMEM; 2619 return ret; 2620 } 2621 2622 platform->pdata.intp_irq = client->irq; 2623 if (platform->pdata.intp_irq) { 2624 INIT_WORK(&platform->work, anx7625_work_func); 2625 platform->workqueue = alloc_workqueue("anx7625_work", 2626 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2627 if (!platform->workqueue) { 2628 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2629 ret = -ENOMEM; 2630 goto free_hdcp_wq; 2631 } 2632 2633 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2634 NULL, anx7625_intr_hpd_isr, 2635 IRQF_TRIGGER_FALLING | 2636 IRQF_ONESHOT, 2637 "anx7625-intp", platform); 2638 if (ret) { 2639 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2640 goto free_wq; 2641 } 2642 } 2643 2644 platform->aux.name = "anx7625-aux"; 2645 platform->aux.dev = dev; 2646 platform->aux.transfer = anx7625_aux_transfer; 2647 drm_dp_aux_init(&platform->aux); 2648 devm_of_dp_aux_populate_ep_devices(&platform->aux); 2649 2650 ret = anx7625_parse_dt(dev, pdata); 2651 if (ret) { 2652 if (ret != -EPROBE_DEFER) 2653 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2654 return ret; 2655 } 2656 2657 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2658 ret = -ENOMEM; 2659 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2660 goto free_wq; 2661 } 2662 2663 pm_runtime_enable(dev); 2664 pm_runtime_set_autosuspend_delay(dev, 1000); 2665 pm_runtime_use_autosuspend(dev); 2666 pm_suspend_ignore_children(dev, true); 2667 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev); 2668 if (ret) 2669 return ret; 2670 2671 if (!platform->pdata.low_power_mode) { 2672 anx7625_disable_pd_protocol(platform); 2673 pm_runtime_get_sync(dev); 2674 } 2675 2676 /* Add work function */ 2677 if (platform->pdata.intp_irq) 2678 queue_work(platform->workqueue, &platform->work); 2679 2680 platform->bridge.funcs = &anx7625_bridge_funcs; 2681 platform->bridge.of_node = client->dev.of_node; 2682 if (!anx7625_of_panel_on_aux_bus(&client->dev)) 2683 platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 2684 if (!platform->pdata.panel_bridge) 2685 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2686 DRM_BRIDGE_OP_DETECT; 2687 platform->bridge.type = platform->pdata.panel_bridge ? 2688 DRM_MODE_CONNECTOR_eDP : 2689 DRM_MODE_CONNECTOR_DisplayPort; 2690 2691 drm_bridge_add(&platform->bridge); 2692 2693 if (!platform->pdata.is_dpi) { 2694 ret = anx7625_attach_dsi(platform); 2695 if (ret) { 2696 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 2697 goto unregister_bridge; 2698 } 2699 } 2700 2701 if (platform->pdata.audio_en) 2702 anx7625_register_audio(dev, platform); 2703 2704 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2705 2706 return 0; 2707 2708 unregister_bridge: 2709 drm_bridge_remove(&platform->bridge); 2710 2711 if (!platform->pdata.low_power_mode) 2712 pm_runtime_put_sync_suspend(&client->dev); 2713 2714 anx7625_unregister_i2c_dummy_clients(platform); 2715 2716 free_wq: 2717 if (platform->workqueue) 2718 destroy_workqueue(platform->workqueue); 2719 2720 free_hdcp_wq: 2721 if (platform->hdcp_workqueue) 2722 destroy_workqueue(platform->hdcp_workqueue); 2723 2724 return ret; 2725 } 2726 2727 static int anx7625_i2c_remove(struct i2c_client *client) 2728 { 2729 struct anx7625_data *platform = i2c_get_clientdata(client); 2730 2731 drm_bridge_remove(&platform->bridge); 2732 2733 if (platform->pdata.intp_irq) 2734 destroy_workqueue(platform->workqueue); 2735 2736 if (platform->hdcp_workqueue) { 2737 cancel_delayed_work(&platform->hdcp_work); 2738 flush_workqueue(platform->workqueue); 2739 destroy_workqueue(platform->workqueue); 2740 } 2741 2742 if (!platform->pdata.low_power_mode) 2743 pm_runtime_put_sync_suspend(&client->dev); 2744 2745 anx7625_unregister_i2c_dummy_clients(platform); 2746 2747 if (platform->pdata.audio_en) 2748 anx7625_unregister_audio(platform); 2749 2750 return 0; 2751 } 2752 2753 static const struct i2c_device_id anx7625_id[] = { 2754 {"anx7625", 0}, 2755 {} 2756 }; 2757 2758 MODULE_DEVICE_TABLE(i2c, anx7625_id); 2759 2760 static const struct of_device_id anx_match_table[] = { 2761 {.compatible = "analogix,anx7625",}, 2762 {}, 2763 }; 2764 MODULE_DEVICE_TABLE(of, anx_match_table); 2765 2766 static struct i2c_driver anx7625_driver = { 2767 .driver = { 2768 .name = "anx7625", 2769 .of_match_table = anx_match_table, 2770 .pm = &anx7625_pm_ops, 2771 }, 2772 .probe = anx7625_i2c_probe, 2773 .remove = anx7625_i2c_remove, 2774 2775 .id_table = anx7625_id, 2776 }; 2777 2778 module_i2c_driver(anx7625_driver); 2779 2780 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 2781 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 2782 MODULE_LICENSE("GPL v2"); 2783 MODULE_VERSION(ANX7625_DRV_VERSION); 2784