1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_dp_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_mipi_dsi.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_panel.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 35 #include <video/display_timing.h> 36 37 #include "anx7625.h" 38 39 /* 40 * There is a sync issue while access I2C register between AP(CPU) and 41 * internal firmware(OCM), to avoid the race condition, AP should access 42 * the reserved slave address before slave address occurs changes. 43 */ 44 static int i2c_access_workaround(struct anx7625_data *ctx, 45 struct i2c_client *client) 46 { 47 u8 offset; 48 struct device *dev = &client->dev; 49 int ret; 50 51 if (client == ctx->last_client) 52 return 0; 53 54 ctx->last_client = client; 55 56 if (client == ctx->i2c.tcpc_client) 57 offset = RSVD_00_ADDR; 58 else if (client == ctx->i2c.tx_p0_client) 59 offset = RSVD_D1_ADDR; 60 else if (client == ctx->i2c.tx_p1_client) 61 offset = RSVD_60_ADDR; 62 else if (client == ctx->i2c.rx_p0_client) 63 offset = RSVD_39_ADDR; 64 else if (client == ctx->i2c.rx_p1_client) 65 offset = RSVD_7F_ADDR; 66 else 67 offset = RSVD_00_ADDR; 68 69 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 70 if (ret < 0) 71 DRM_DEV_ERROR(dev, 72 "fail to access i2c id=%x\n:%x", 73 client->addr, offset); 74 75 return ret; 76 } 77 78 static int anx7625_reg_read(struct anx7625_data *ctx, 79 struct i2c_client *client, u8 reg_addr) 80 { 81 int ret; 82 struct device *dev = &client->dev; 83 84 i2c_access_workaround(ctx, client); 85 86 ret = i2c_smbus_read_byte_data(client, reg_addr); 87 if (ret < 0) 88 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 89 client->addr, reg_addr); 90 91 return ret; 92 } 93 94 static int anx7625_reg_block_read(struct anx7625_data *ctx, 95 struct i2c_client *client, 96 u8 reg_addr, u8 len, u8 *buf) 97 { 98 int ret; 99 struct device *dev = &client->dev; 100 101 i2c_access_workaround(ctx, client); 102 103 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 104 if (ret < 0) 105 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 106 client->addr, reg_addr); 107 108 return ret; 109 } 110 111 static int anx7625_reg_write(struct anx7625_data *ctx, 112 struct i2c_client *client, 113 u8 reg_addr, u8 reg_val) 114 { 115 int ret; 116 struct device *dev = &client->dev; 117 118 i2c_access_workaround(ctx, client); 119 120 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 121 122 if (ret < 0) 123 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 124 client->addr, reg_addr); 125 126 return ret; 127 } 128 129 static int anx7625_write_or(struct anx7625_data *ctx, 130 struct i2c_client *client, 131 u8 offset, u8 mask) 132 { 133 int val; 134 135 val = anx7625_reg_read(ctx, client, offset); 136 if (val < 0) 137 return val; 138 139 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 140 } 141 142 static int anx7625_write_and(struct anx7625_data *ctx, 143 struct i2c_client *client, 144 u8 offset, u8 mask) 145 { 146 int val; 147 148 val = anx7625_reg_read(ctx, client, offset); 149 if (val < 0) 150 return val; 151 152 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 153 } 154 155 static int anx7625_write_and_or(struct anx7625_data *ctx, 156 struct i2c_client *client, 157 u8 offset, u8 and_mask, u8 or_mask) 158 { 159 int val; 160 161 val = anx7625_reg_read(ctx, client, offset); 162 if (val < 0) 163 return val; 164 165 return anx7625_reg_write(ctx, client, 166 offset, (val & and_mask) | (or_mask)); 167 } 168 169 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 170 { 171 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 172 } 173 174 static int wait_aux_op_finish(struct anx7625_data *ctx) 175 { 176 struct device *dev = &ctx->client->dev; 177 int val; 178 int ret; 179 180 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 181 ctx, val, 182 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 183 2000, 184 2000 * 150); 185 if (ret) { 186 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 187 return -EIO; 188 } 189 190 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 191 AP_AUX_CTRL_STATUS); 192 if (val < 0 || (val & 0x0F)) { 193 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 194 val = -EIO; 195 } 196 197 return val; 198 } 199 200 static int anx7625_video_mute_control(struct anx7625_data *ctx, 201 u8 status) 202 { 203 int ret; 204 205 if (status) { 206 /* Set mute on flag */ 207 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 208 AP_AV_STATUS, AP_MIPI_MUTE); 209 /* Clear mipi RX en */ 210 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 211 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 212 } else { 213 /* Mute off flag */ 214 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 215 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 216 /* Set MIPI RX EN */ 217 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 218 AP_AV_STATUS, AP_MIPI_RX_EN); 219 } 220 221 return ret; 222 } 223 224 static int anx7625_config_audio_input(struct anx7625_data *ctx) 225 { 226 struct device *dev = &ctx->client->dev; 227 int ret; 228 229 /* Channel num */ 230 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 231 AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5); 232 233 /* FS */ 234 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 235 AUDIO_CHANNEL_STATUS_4, 236 0xf0, AUDIO_FS_48K); 237 /* Word length */ 238 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 239 AUDIO_CHANNEL_STATUS_5, 240 0xf0, AUDIO_W_LEN_24_24MAX); 241 /* I2S */ 242 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 243 AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE); 244 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 245 AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE); 246 /* Audio change flag */ 247 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 248 AP_AV_STATUS, AP_AUDIO_CHG); 249 250 if (ret < 0) 251 DRM_DEV_ERROR(dev, "fail to config audio.\n"); 252 253 return ret; 254 } 255 256 /* Reduction of fraction a/b */ 257 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 258 { 259 unsigned long gcd_num; 260 unsigned long tmp_a, tmp_b; 261 u32 i = 1; 262 263 gcd_num = gcd(*a, *b); 264 *a /= gcd_num; 265 *b /= gcd_num; 266 267 tmp_a = *a; 268 tmp_b = *b; 269 270 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 271 i++; 272 *a = tmp_a / i; 273 *b = tmp_b / i; 274 } 275 276 /* 277 * In the end, make a, b larger to have higher ODFC PLL 278 * output frequency accuracy 279 */ 280 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 281 *a <<= 1; 282 *b <<= 1; 283 } 284 285 *a >>= 1; 286 *b >>= 1; 287 } 288 289 static int anx7625_calculate_m_n(u32 pixelclock, 290 unsigned long *m, 291 unsigned long *n, 292 u8 *post_divider) 293 { 294 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 295 /* Pixel clock frequency is too high */ 296 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 297 pixelclock, 298 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 299 return -EINVAL; 300 } 301 302 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 303 /* Pixel clock frequency is too low */ 304 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 305 pixelclock, 306 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 307 return -EINVAL; 308 } 309 310 for (*post_divider = 1; 311 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 312 *post_divider += 1; 313 314 if (*post_divider > POST_DIVIDER_MAX) { 315 for (*post_divider = 1; 316 (pixelclock < 317 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 318 *post_divider += 1; 319 320 if (*post_divider > POST_DIVIDER_MAX) { 321 DRM_ERROR("cannot find property post_divider(%d)\n", 322 *post_divider); 323 return -EDOM; 324 } 325 } 326 327 /* Patch to improve the accuracy */ 328 if (*post_divider == 7) { 329 /* 27,000,000 is not divisible by 7 */ 330 *post_divider = 8; 331 } else if (*post_divider == 11) { 332 /* 27,000,000 is not divisible by 11 */ 333 *post_divider = 12; 334 } else if ((*post_divider == 13) || (*post_divider == 14)) { 335 /* 27,000,000 is not divisible by 13 or 14 */ 336 *post_divider = 15; 337 } 338 339 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 340 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 341 pixelclock * (*post_divider), 342 PLL_OUT_FREQ_ABS_MAX); 343 return -EDOM; 344 } 345 346 *m = pixelclock; 347 *n = XTAL_FRQ / (*post_divider); 348 349 anx7625_reduction_of_a_fraction(m, n); 350 351 return 0; 352 } 353 354 static int anx7625_odfc_config(struct anx7625_data *ctx, 355 u8 post_divider) 356 { 357 int ret; 358 struct device *dev = &ctx->client->dev; 359 360 /* Config input reference clock frequency 27MHz/19.2MHz */ 361 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 362 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 363 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 364 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 365 /* Post divider */ 366 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 367 MIPI_DIGITAL_PLL_8, 0x0f); 368 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 369 post_divider << 4); 370 371 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 372 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 373 ~MIPI_PLL_VCO_TUNE_REG_VAL); 374 375 /* Reset ODFC PLL */ 376 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 377 ~MIPI_PLL_RESET_N); 378 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 379 MIPI_PLL_RESET_N); 380 381 if (ret < 0) 382 DRM_DEV_ERROR(dev, "IO error.\n"); 383 384 return ret; 385 } 386 387 /* 388 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 389 * anx7625 defined K ratio for matching MIPI input video clock and 390 * DP output video clock. Increase K value can match bigger video data 391 * variation. IVO panel has small variation than DP CTS spec, need 392 * decrease the K value. 393 */ 394 static int anx7625_set_k_value(struct anx7625_data *ctx) 395 { 396 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 397 398 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 399 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 400 MIPI_DIGITAL_ADJ_1, 0x3B); 401 402 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 403 MIPI_DIGITAL_ADJ_1, 0x3D); 404 } 405 406 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 407 { 408 struct device *dev = &ctx->client->dev; 409 unsigned long m, n; 410 u16 htotal; 411 int ret; 412 u8 post_divider = 0; 413 414 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 415 &m, &n, &post_divider); 416 417 if (ret) { 418 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 419 return ret; 420 } 421 422 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 423 m, n, post_divider); 424 425 /* Configure pixel clock */ 426 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 427 (ctx->dt.pixelclock.min / 1000) & 0xFF); 428 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 429 (ctx->dt.pixelclock.min / 1000) >> 8); 430 /* Lane count */ 431 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 432 MIPI_LANE_CTRL_0, 0xfc); 433 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 434 MIPI_LANE_CTRL_0, 3); 435 436 /* Htotal */ 437 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 438 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 439 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 440 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 441 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 442 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 443 /* Hactive */ 444 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 445 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 446 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 447 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 448 /* HFP */ 449 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 450 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 451 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 452 HORIZONTAL_FRONT_PORCH_H, 453 ctx->dt.hfront_porch.min >> 8); 454 /* HWS */ 455 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 456 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 457 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 458 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 459 /* HBP */ 460 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 461 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 462 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 463 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 464 /* Vactive */ 465 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 466 ctx->dt.vactive.min); 467 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 468 ctx->dt.vactive.min >> 8); 469 /* VFP */ 470 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 471 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 472 /* VWS */ 473 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 474 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 475 /* VBP */ 476 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 477 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 478 /* M value */ 479 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 480 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 481 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 482 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 483 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 484 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 485 /* N value */ 486 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 487 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 488 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 489 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 490 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 491 (n & 0xff)); 492 493 anx7625_set_k_value(ctx); 494 495 ret |= anx7625_odfc_config(ctx, post_divider - 1); 496 497 if (ret < 0) 498 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 499 500 return ret; 501 } 502 503 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 504 { 505 int val; 506 struct device *dev = &ctx->client->dev; 507 508 /* Swap MIPI-DSI data lane 3 P and N */ 509 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 510 if (val < 0) { 511 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 512 return -EIO; 513 } 514 515 val |= (1 << MIPI_SWAP_CH3); 516 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 517 } 518 519 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 520 521 { 522 int val, ret; 523 struct device *dev = &ctx->client->dev; 524 525 /* Swap MIPI-DSI data lane 3 P and N */ 526 ret = anx7625_swap_dsi_lane3(ctx); 527 if (ret < 0) { 528 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 529 return ret; 530 } 531 532 /* DSI clock settings */ 533 val = (0 << MIPI_HS_PWD_CLK) | 534 (0 << MIPI_HS_RT_CLK) | 535 (0 << MIPI_PD_CLK) | 536 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 537 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 538 (0 << MIPI_CLK_DET_DET_BYPASS) | 539 (0 << MIPI_CLK_MISS_CTRL) | 540 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 541 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 542 MIPI_PHY_CONTROL_3, val); 543 544 /* 545 * Decreased HS prepare timing delay from 160ns to 80ns work with 546 * a) Dragon board 810 series (Qualcomm AP) 547 * b) Moving Pixel DSI source (PG3A pattern generator + 548 * P332 D-PHY Probe) default D-PHY timing 549 * 5ns/step 550 */ 551 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 552 MIPI_TIME_HS_PRPR, 0x10); 553 554 /* Enable DSI mode*/ 555 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 556 SELECT_DSI << MIPI_DPI_SELECT); 557 558 ret |= anx7625_dsi_video_timing_config(ctx); 559 if (ret < 0) { 560 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 561 return ret; 562 } 563 564 /* Toggle m, n ready */ 565 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 566 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 567 usleep_range(1000, 1100); 568 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 569 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 570 571 /* Configure integer stable register */ 572 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 573 MIPI_VIDEO_STABLE_CNT, 0x02); 574 /* Power on MIPI RX */ 575 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 576 MIPI_LANE_CTRL_10, 0x00); 577 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 578 MIPI_LANE_CTRL_10, 0x80); 579 580 if (ret < 0) 581 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 582 583 return ret; 584 } 585 586 static int anx7625_dsi_config(struct anx7625_data *ctx) 587 { 588 struct device *dev = &ctx->client->dev; 589 int ret; 590 591 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 592 593 /* DSC disable */ 594 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 595 R_DSC_CTRL_0, ~DSC_EN); 596 597 ret |= anx7625_api_dsi_config(ctx); 598 599 if (ret < 0) { 600 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 601 return ret; 602 } 603 604 /* Set MIPI RX EN */ 605 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 606 AP_AV_STATUS, AP_MIPI_RX_EN); 607 /* Clear mute flag */ 608 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 609 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 610 if (ret < 0) 611 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 612 else 613 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 614 615 return ret; 616 } 617 618 static void anx7625_dp_start(struct anx7625_data *ctx) 619 { 620 int ret; 621 struct device *dev = &ctx->client->dev; 622 623 if (!ctx->display_timing_valid) { 624 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 625 return; 626 } 627 628 anx7625_config_audio_input(ctx); 629 630 ret = anx7625_dsi_config(ctx); 631 632 if (ret < 0) 633 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 634 } 635 636 static void anx7625_dp_stop(struct anx7625_data *ctx) 637 { 638 struct device *dev = &ctx->client->dev; 639 int ret; 640 641 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 642 643 /* 644 * Video disable: 0x72:08 bit 7 = 0; 645 * Audio disable: 0x70:87 bit 0 = 0; 646 */ 647 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 648 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 649 650 ret |= anx7625_video_mute_control(ctx, 1); 651 if (ret < 0) 652 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 653 } 654 655 static int sp_tx_rst_aux(struct anx7625_data *ctx) 656 { 657 int ret; 658 659 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 660 AUX_RST); 661 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 662 ~AUX_RST); 663 return ret; 664 } 665 666 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 667 { 668 int ret; 669 670 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 671 AP_AUX_BUFF_START, offset); 672 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 673 AP_AUX_COMMAND, 0x04); 674 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 675 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 676 return (ret | wait_aux_op_finish(ctx)); 677 } 678 679 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 680 { 681 int ret; 682 683 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 684 AP_AUX_COMMAND, len_cmd); 685 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 686 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 687 return (ret | wait_aux_op_finish(ctx)); 688 } 689 690 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 691 { 692 int c = 0; 693 struct device *dev = &ctx->client->dev; 694 695 sp_tx_aux_wr(ctx, 0x7e); 696 sp_tx_aux_rd(ctx, 0x01); 697 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 698 if (c < 0) { 699 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 700 return -EIO; 701 } 702 703 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 704 705 if (c > MAX_EDID_BLOCK) 706 c = 1; 707 708 return c; 709 } 710 711 static int edid_read(struct anx7625_data *ctx, 712 u8 offset, u8 *pblock_buf) 713 { 714 int ret, cnt; 715 struct device *dev = &ctx->client->dev; 716 717 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 718 sp_tx_aux_wr(ctx, offset); 719 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 720 ret = sp_tx_aux_rd(ctx, 0xf1); 721 722 if (ret) { 723 ret = sp_tx_rst_aux(ctx); 724 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 725 } else { 726 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 727 AP_AUX_BUFF_START, 728 MAX_DPCD_BUFFER_SIZE, 729 pblock_buf); 730 if (ret > 0) 731 break; 732 } 733 } 734 735 if (cnt > EDID_TRY_CNT) 736 return -EIO; 737 738 return ret; 739 } 740 741 static int segments_edid_read(struct anx7625_data *ctx, 742 u8 segment, u8 *buf, u8 offset) 743 { 744 u8 cnt; 745 int ret; 746 struct device *dev = &ctx->client->dev; 747 748 /* Write address only */ 749 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 750 AP_AUX_ADDR_7_0, 0x30); 751 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 752 AP_AUX_COMMAND, 0x04); 753 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 754 AP_AUX_CTRL_STATUS, 755 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 756 757 ret |= wait_aux_op_finish(ctx); 758 /* Write segment address */ 759 ret |= sp_tx_aux_wr(ctx, segment); 760 /* Data read */ 761 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 762 AP_AUX_ADDR_7_0, 0x50); 763 if (ret) { 764 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 765 return ret; 766 } 767 768 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 769 sp_tx_aux_wr(ctx, offset); 770 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 771 ret = sp_tx_aux_rd(ctx, 0xf1); 772 773 if (ret) { 774 ret = sp_tx_rst_aux(ctx); 775 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 776 } else { 777 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 778 AP_AUX_BUFF_START, 779 MAX_DPCD_BUFFER_SIZE, buf); 780 if (ret > 0) 781 break; 782 } 783 } 784 785 if (cnt > EDID_TRY_CNT) 786 return -EIO; 787 788 return ret; 789 } 790 791 static int sp_tx_edid_read(struct anx7625_data *ctx, 792 u8 *pedid_blocks_buf) 793 { 794 u8 offset; 795 int edid_pos; 796 int count, blocks_num; 797 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 798 u8 i, j; 799 u8 g_edid_break = 0; 800 int ret; 801 struct device *dev = &ctx->client->dev; 802 803 /* Address initial */ 804 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 805 AP_AUX_ADDR_7_0, 0x50); 806 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 807 AP_AUX_ADDR_15_8, 0); 808 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 809 AP_AUX_ADDR_19_16, 0xf0); 810 if (ret < 0) { 811 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 812 return -EIO; 813 } 814 815 blocks_num = sp_tx_get_edid_block(ctx); 816 if (blocks_num < 0) 817 return blocks_num; 818 819 count = 0; 820 821 do { 822 switch (count) { 823 case 0: 824 case 1: 825 for (i = 0; i < 8; i++) { 826 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 827 g_edid_break = edid_read(ctx, offset, 828 pblock_buf); 829 830 if (g_edid_break) 831 break; 832 833 memcpy(&pedid_blocks_buf[offset], 834 pblock_buf, 835 MAX_DPCD_BUFFER_SIZE); 836 } 837 838 break; 839 case 2: 840 offset = 0x00; 841 842 for (j = 0; j < 8; j++) { 843 edid_pos = (j + count * 8) * 844 MAX_DPCD_BUFFER_SIZE; 845 846 if (g_edid_break == 1) 847 break; 848 849 segments_edid_read(ctx, count / 2, 850 pblock_buf, offset); 851 memcpy(&pedid_blocks_buf[edid_pos], 852 pblock_buf, 853 MAX_DPCD_BUFFER_SIZE); 854 offset = offset + 0x10; 855 } 856 857 break; 858 case 3: 859 offset = 0x80; 860 861 for (j = 0; j < 8; j++) { 862 edid_pos = (j + count * 8) * 863 MAX_DPCD_BUFFER_SIZE; 864 if (g_edid_break == 1) 865 break; 866 867 segments_edid_read(ctx, count / 2, 868 pblock_buf, offset); 869 memcpy(&pedid_blocks_buf[edid_pos], 870 pblock_buf, 871 MAX_DPCD_BUFFER_SIZE); 872 offset = offset + 0x10; 873 } 874 875 break; 876 default: 877 break; 878 } 879 880 count++; 881 882 } while (blocks_num >= count); 883 884 /* Check edid data */ 885 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 886 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 887 return -EINVAL; 888 } 889 890 /* Reset aux channel */ 891 ret = sp_tx_rst_aux(ctx); 892 if (ret < 0) { 893 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 894 return ret; 895 } 896 897 return (blocks_num + 1); 898 } 899 900 static void anx7625_power_on(struct anx7625_data *ctx) 901 { 902 struct device *dev = &ctx->client->dev; 903 int ret, i; 904 905 if (!ctx->pdata.low_power_mode) { 906 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 907 return; 908 } 909 910 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 911 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 912 if (ret < 0) { 913 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 914 i, ret); 915 goto reg_err; 916 } 917 usleep_range(2000, 2100); 918 } 919 920 usleep_range(11000, 12000); 921 922 /* Power on pin enable */ 923 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 924 usleep_range(10000, 11000); 925 /* Power reset pin enable */ 926 gpiod_set_value(ctx->pdata.gpio_reset, 1); 927 usleep_range(10000, 11000); 928 929 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 930 return; 931 reg_err: 932 for (--i; i >= 0; i--) 933 regulator_disable(ctx->pdata.supplies[i].consumer); 934 } 935 936 static void anx7625_power_standby(struct anx7625_data *ctx) 937 { 938 struct device *dev = &ctx->client->dev; 939 int ret; 940 941 if (!ctx->pdata.low_power_mode) { 942 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 943 return; 944 } 945 946 gpiod_set_value(ctx->pdata.gpio_reset, 0); 947 usleep_range(1000, 1100); 948 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 949 usleep_range(1000, 1100); 950 951 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 952 ctx->pdata.supplies); 953 if (ret < 0) 954 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 955 956 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 957 } 958 959 /* Basic configurations of ANX7625 */ 960 static void anx7625_config(struct anx7625_data *ctx) 961 { 962 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 963 XTAL_FRQ_SEL, XTAL_FRQ_27M); 964 } 965 966 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 967 { 968 struct device *dev = &ctx->client->dev; 969 int ret; 970 971 /* Reset main ocm */ 972 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 973 /* Disable PD */ 974 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 975 AP_AV_STATUS, AP_DISABLE_PD); 976 /* Release main ocm */ 977 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 978 979 if (ret < 0) 980 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 981 else 982 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 983 } 984 985 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 986 { 987 int ret; 988 struct device *dev = &ctx->client->dev; 989 990 /* Check interface workable */ 991 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 992 FLASH_LOAD_STA); 993 if (ret < 0) { 994 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 995 return ret; 996 } 997 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 998 return -ENODEV; 999 1000 anx7625_disable_pd_protocol(ctx); 1001 1002 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1003 anx7625_reg_read(ctx, 1004 ctx->i2c.rx_p0_client, 1005 OCM_FW_VERSION), 1006 anx7625_reg_read(ctx, 1007 ctx->i2c.rx_p0_client, 1008 OCM_FW_REVERSION)); 1009 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1010 ANX7625_DRV_VERSION); 1011 1012 return 0; 1013 } 1014 1015 static void anx7625_power_on_init(struct anx7625_data *ctx) 1016 { 1017 int retry_count, i; 1018 1019 for (retry_count = 0; retry_count < 3; retry_count++) { 1020 anx7625_power_on(ctx); 1021 anx7625_config(ctx); 1022 1023 for (i = 0; i < OCM_LOADING_TIME; i++) { 1024 if (!anx7625_ocm_loading_check(ctx)) 1025 return; 1026 usleep_range(1000, 1100); 1027 } 1028 anx7625_power_standby(ctx); 1029 } 1030 } 1031 1032 static void anx7625_init_gpio(struct anx7625_data *platform) 1033 { 1034 struct device *dev = &platform->client->dev; 1035 1036 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1037 1038 /* Gpio for chip power enable */ 1039 platform->pdata.gpio_p_on = 1040 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1041 /* Gpio for chip reset */ 1042 platform->pdata.gpio_reset = 1043 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1044 1045 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1046 platform->pdata.low_power_mode = 1; 1047 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1048 desc_to_gpio(platform->pdata.gpio_p_on), 1049 desc_to_gpio(platform->pdata.gpio_reset)); 1050 } else { 1051 platform->pdata.low_power_mode = 0; 1052 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1053 } 1054 } 1055 1056 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1057 { 1058 ctx->hpd_status = 0; 1059 ctx->hpd_high_cnt = 0; 1060 ctx->display_timing_valid = 0; 1061 } 1062 1063 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1064 { 1065 int ret; 1066 struct device *dev = &ctx->client->dev; 1067 1068 if (ctx->hpd_high_cnt >= 2) { 1069 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1070 return; 1071 } 1072 1073 ctx->hpd_high_cnt++; 1074 1075 /* Not support HDCP */ 1076 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1077 1078 /* Try auth flag */ 1079 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1080 /* Interrupt for DRM */ 1081 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1082 if (ret < 0) 1083 return; 1084 1085 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1086 if (ret < 0) 1087 return; 1088 1089 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1090 } 1091 1092 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1093 { 1094 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1095 } 1096 1097 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1098 { 1099 int ret, val; 1100 struct device *dev = &ctx->client->dev; 1101 1102 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1103 ctx, val, 1104 ((val & HPD_STATUS) || (val < 0)), 1105 5000, 1106 5000 * 100); 1107 if (ret) { 1108 DRM_DEV_ERROR(dev, "no hpd.\n"); 1109 return; 1110 } 1111 1112 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1113 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1114 INTR_ALERT_1, 0xFF); 1115 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1116 INTERFACE_CHANGE_INT, 0); 1117 1118 anx7625_start_dp_work(ctx); 1119 1120 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1121 drm_helper_hpd_irq_event(ctx->bridge.dev); 1122 } 1123 1124 static void anx7625_remove_edid(struct anx7625_data *ctx) 1125 { 1126 ctx->slimport_edid_p.edid_block_num = -1; 1127 } 1128 1129 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1130 { 1131 struct device *dev = &ctx->client->dev; 1132 1133 /* HPD changed */ 1134 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1135 (u32)on); 1136 1137 if (on == 0) { 1138 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1139 anx7625_remove_edid(ctx); 1140 anx7625_stop_dp_work(ctx); 1141 } else { 1142 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1143 anx7625_start_dp_work(ctx); 1144 } 1145 1146 ctx->hpd_status = 1; 1147 } 1148 1149 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1150 { 1151 int intr_vector, status; 1152 struct device *dev = &ctx->client->dev; 1153 1154 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1155 INTR_ALERT_1, 0xFF); 1156 if (status < 0) { 1157 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1158 return status; 1159 } 1160 1161 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1162 INTERFACE_CHANGE_INT); 1163 if (intr_vector < 0) { 1164 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1165 return intr_vector; 1166 } 1167 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1168 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1169 INTERFACE_CHANGE_INT, 1170 intr_vector & (~intr_vector)); 1171 if (status < 0) { 1172 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1173 return status; 1174 } 1175 1176 if (!(intr_vector & HPD_STATUS_CHANGE)) 1177 return -ENOENT; 1178 1179 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1180 SYSTEM_STSTUS); 1181 if (status < 0) { 1182 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1183 return status; 1184 } 1185 1186 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1187 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1188 1189 return 0; 1190 } 1191 1192 static void anx7625_work_func(struct work_struct *work) 1193 { 1194 int event; 1195 struct anx7625_data *ctx = container_of(work, 1196 struct anx7625_data, work); 1197 1198 mutex_lock(&ctx->lock); 1199 1200 if (pm_runtime_suspended(&ctx->client->dev)) 1201 goto unlock; 1202 1203 event = anx7625_hpd_change_detect(ctx); 1204 if (event < 0) 1205 goto unlock; 1206 1207 if (ctx->bridge_attached) 1208 drm_helper_hpd_irq_event(ctx->bridge.dev); 1209 1210 unlock: 1211 mutex_unlock(&ctx->lock); 1212 } 1213 1214 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1215 { 1216 struct anx7625_data *ctx = (struct anx7625_data *)data; 1217 1218 queue_work(ctx->workqueue, &ctx->work); 1219 1220 return IRQ_HANDLED; 1221 } 1222 1223 static int anx7625_parse_dt(struct device *dev, 1224 struct anx7625_platform_data *pdata) 1225 { 1226 struct device_node *np = dev->of_node; 1227 struct drm_panel *panel; 1228 int ret; 1229 1230 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1231 if (!pdata->mipi_host_node) { 1232 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1233 return -ENODEV; 1234 } 1235 1236 DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n"); 1237 1238 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1239 if (ret < 0) { 1240 if (ret == -ENODEV) 1241 return 0; 1242 return ret; 1243 } 1244 if (!panel) 1245 return -ENODEV; 1246 1247 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1248 if (IS_ERR(pdata->panel_bridge)) 1249 return PTR_ERR(pdata->panel_bridge); 1250 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1251 1252 return 0; 1253 } 1254 1255 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1256 { 1257 return container_of(bridge, struct anx7625_data, bridge); 1258 } 1259 1260 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1261 { 1262 struct device *dev = &ctx->client->dev; 1263 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1264 int edid_num; 1265 u8 *edid; 1266 1267 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1268 if (!edid) { 1269 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1270 return NULL; 1271 } 1272 1273 if (ctx->slimport_edid_p.edid_block_num > 0) { 1274 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1275 FOUR_BLOCK_SIZE); 1276 return (struct edid *)edid; 1277 } 1278 1279 pm_runtime_get_sync(dev); 1280 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1281 pm_runtime_put_sync(dev); 1282 1283 if (edid_num < 1) { 1284 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1285 kfree(edid); 1286 return NULL; 1287 } 1288 1289 p_edid->edid_block_num = edid_num; 1290 1291 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1292 return (struct edid *)edid; 1293 } 1294 1295 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1296 { 1297 struct device *dev = &ctx->client->dev; 1298 1299 DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n"); 1300 1301 return connector_status_connected; 1302 } 1303 1304 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1305 { 1306 struct mipi_dsi_device *dsi; 1307 struct device *dev = &ctx->client->dev; 1308 struct mipi_dsi_host *host; 1309 const struct mipi_dsi_device_info info = { 1310 .type = "anx7625", 1311 .channel = 0, 1312 .node = NULL, 1313 }; 1314 1315 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1316 1317 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1318 if (!host) { 1319 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1320 return -EINVAL; 1321 } 1322 1323 dsi = mipi_dsi_device_register_full(host, &info); 1324 if (IS_ERR(dsi)) { 1325 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 1326 return -EINVAL; 1327 } 1328 1329 dsi->lanes = 4; 1330 dsi->format = MIPI_DSI_FMT_RGB888; 1331 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1332 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1333 MIPI_DSI_MODE_NO_EOT_PACKET | 1334 MIPI_DSI_MODE_VIDEO_HSE; 1335 1336 if (mipi_dsi_attach(dsi) < 0) { 1337 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 1338 mipi_dsi_device_unregister(dsi); 1339 return -EINVAL; 1340 } 1341 1342 ctx->dsi = dsi; 1343 1344 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 1345 1346 return 0; 1347 } 1348 1349 static void anx7625_bridge_detach(struct drm_bridge *bridge) 1350 { 1351 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1352 1353 if (ctx->dsi) { 1354 mipi_dsi_detach(ctx->dsi); 1355 mipi_dsi_device_unregister(ctx->dsi); 1356 } 1357 } 1358 1359 static int anx7625_bridge_attach(struct drm_bridge *bridge, 1360 enum drm_bridge_attach_flags flags) 1361 { 1362 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1363 int err; 1364 struct device *dev = &ctx->client->dev; 1365 1366 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 1367 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 1368 return -EINVAL; 1369 1370 if (!bridge->encoder) { 1371 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 1372 return -ENODEV; 1373 } 1374 1375 err = anx7625_attach_dsi(ctx); 1376 if (err) { 1377 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); 1378 return err; 1379 } 1380 1381 if (ctx->pdata.panel_bridge) { 1382 err = drm_bridge_attach(bridge->encoder, 1383 ctx->pdata.panel_bridge, 1384 &ctx->bridge, flags); 1385 if (err) 1386 return err; 1387 } 1388 1389 ctx->bridge_attached = 1; 1390 1391 return 0; 1392 } 1393 1394 static enum drm_mode_status 1395 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 1396 const struct drm_display_info *info, 1397 const struct drm_display_mode *mode) 1398 { 1399 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1400 struct device *dev = &ctx->client->dev; 1401 1402 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 1403 1404 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 1405 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 1406 DRM_DEV_DEBUG_DRIVER(dev, 1407 "drm mode invalid, pixelclock too high.\n"); 1408 return MODE_CLOCK_HIGH; 1409 } 1410 1411 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 1412 1413 return MODE_OK; 1414 } 1415 1416 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 1417 const struct drm_display_mode *old_mode, 1418 const struct drm_display_mode *mode) 1419 { 1420 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1421 struct device *dev = &ctx->client->dev; 1422 1423 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 1424 1425 ctx->dt.pixelclock.min = mode->clock; 1426 ctx->dt.hactive.min = mode->hdisplay; 1427 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 1428 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 1429 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 1430 ctx->dt.vactive.min = mode->vdisplay; 1431 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 1432 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 1433 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 1434 1435 ctx->display_timing_valid = 1; 1436 1437 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 1438 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 1439 ctx->dt.hactive.min, 1440 ctx->dt.hsync_len.min, 1441 ctx->dt.hfront_porch.min, 1442 ctx->dt.hback_porch.min); 1443 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 1444 ctx->dt.vactive.min, 1445 ctx->dt.vsync_len.min, 1446 ctx->dt.vfront_porch.min, 1447 ctx->dt.vback_porch.min); 1448 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 1449 mode->hdisplay, 1450 mode->hsync_start); 1451 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 1452 mode->hsync_end, 1453 mode->htotal); 1454 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 1455 mode->vdisplay, 1456 mode->vsync_start); 1457 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 1458 mode->vsync_end, 1459 mode->vtotal); 1460 } 1461 1462 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 1463 const struct drm_display_mode *mode, 1464 struct drm_display_mode *adj) 1465 { 1466 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1467 struct device *dev = &ctx->client->dev; 1468 u32 hsync, hfp, hbp, hblanking; 1469 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 1470 u32 vref, adj_clock; 1471 1472 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 1473 1474 hsync = mode->hsync_end - mode->hsync_start; 1475 hfp = mode->hsync_start - mode->hdisplay; 1476 hbp = mode->htotal - mode->hsync_end; 1477 hblanking = mode->htotal - mode->hdisplay; 1478 1479 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 1480 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1481 hsync, hfp, hbp, adj->clock); 1482 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1483 adj->hsync_start, adj->hsync_end, adj->htotal); 1484 1485 adj_hfp = hfp; 1486 adj_hsync = hsync; 1487 adj_hbp = hbp; 1488 adj_hblanking = hblanking; 1489 1490 /* HFP needs to be even */ 1491 if (hfp & 0x1) { 1492 adj_hfp += 1; 1493 adj_hblanking += 1; 1494 } 1495 1496 /* HBP needs to be even */ 1497 if (hbp & 0x1) { 1498 adj_hbp -= 1; 1499 adj_hblanking -= 1; 1500 } 1501 1502 /* HSYNC needs to be even */ 1503 if (hsync & 0x1) { 1504 if (adj_hblanking < hblanking) 1505 adj_hsync += 1; 1506 else 1507 adj_hsync -= 1; 1508 } 1509 1510 /* 1511 * Once illegal timing detected, use default HFP, HSYNC, HBP 1512 * This adjusting made for built-in eDP panel, for the externel 1513 * DP monitor, may need return false. 1514 */ 1515 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 1516 adj_hsync = SYNC_LEN_DEF; 1517 adj_hfp = HFP_HBP_DEF; 1518 adj_hbp = HFP_HBP_DEF; 1519 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 1520 if (hblanking < HBLANKING_MIN) { 1521 delta_adj = HBLANKING_MIN - hblanking; 1522 adj_clock = vref * delta_adj * adj->vtotal; 1523 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 1524 } else { 1525 delta_adj = hblanking - HBLANKING_MIN; 1526 adj_clock = vref * delta_adj * adj->vtotal; 1527 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 1528 } 1529 1530 DRM_WARN("illegal hblanking timing, use default.\n"); 1531 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 1532 } else if (adj_hfp < HP_MIN) { 1533 /* Adjust hfp if hfp less than HP_MIN */ 1534 delta_adj = HP_MIN - adj_hfp; 1535 adj_hfp = HP_MIN; 1536 1537 /* 1538 * Balance total HBlanking pixel, if HBP does not have enough 1539 * space, adjust HSYNC length, otherwise adjust HBP 1540 */ 1541 if ((adj_hbp - delta_adj) < HP_MIN) 1542 /* HBP not enough space */ 1543 adj_hsync -= delta_adj; 1544 else 1545 adj_hbp -= delta_adj; 1546 } else if (adj_hbp < HP_MIN) { 1547 delta_adj = HP_MIN - adj_hbp; 1548 adj_hbp = HP_MIN; 1549 1550 /* 1551 * Balance total HBlanking pixel, if HBP hasn't enough space, 1552 * adjust HSYNC length, otherwize adjust HBP 1553 */ 1554 if ((adj_hfp - delta_adj) < HP_MIN) 1555 /* HFP not enough space */ 1556 adj_hsync -= delta_adj; 1557 else 1558 adj_hfp -= delta_adj; 1559 } 1560 1561 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 1562 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1563 adj_hsync, adj_hfp, adj_hbp, adj->clock); 1564 1565 /* Reconstruct timing */ 1566 adj->hsync_start = adj->hdisplay + adj_hfp; 1567 adj->hsync_end = adj->hsync_start + adj_hsync; 1568 adj->htotal = adj->hsync_end + adj_hbp; 1569 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1570 adj->hsync_start, adj->hsync_end, adj->htotal); 1571 1572 return true; 1573 } 1574 1575 static void anx7625_bridge_enable(struct drm_bridge *bridge) 1576 { 1577 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1578 struct device *dev = &ctx->client->dev; 1579 1580 DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 1581 1582 pm_runtime_get_sync(dev); 1583 1584 anx7625_dp_start(ctx); 1585 } 1586 1587 static void anx7625_bridge_disable(struct drm_bridge *bridge) 1588 { 1589 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1590 struct device *dev = &ctx->client->dev; 1591 1592 DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 1593 1594 anx7625_dp_stop(ctx); 1595 1596 pm_runtime_put_sync(dev); 1597 } 1598 1599 static enum drm_connector_status 1600 anx7625_bridge_detect(struct drm_bridge *bridge) 1601 { 1602 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1603 struct device *dev = &ctx->client->dev; 1604 1605 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 1606 1607 return anx7625_sink_detect(ctx); 1608 } 1609 1610 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 1611 struct drm_connector *connector) 1612 { 1613 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1614 struct device *dev = &ctx->client->dev; 1615 1616 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 1617 1618 return anx7625_get_edid(ctx); 1619 } 1620 1621 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 1622 .attach = anx7625_bridge_attach, 1623 .detach = anx7625_bridge_detach, 1624 .disable = anx7625_bridge_disable, 1625 .mode_valid = anx7625_bridge_mode_valid, 1626 .mode_set = anx7625_bridge_mode_set, 1627 .mode_fixup = anx7625_bridge_mode_fixup, 1628 .enable = anx7625_bridge_enable, 1629 .detect = anx7625_bridge_detect, 1630 .get_edid = anx7625_bridge_get_edid, 1631 }; 1632 1633 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 1634 struct i2c_client *client) 1635 { 1636 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 1637 TX_P0_ADDR >> 1); 1638 if (!ctx->i2c.tx_p0_client) 1639 return -ENOMEM; 1640 1641 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 1642 TX_P1_ADDR >> 1); 1643 if (!ctx->i2c.tx_p1_client) 1644 goto free_tx_p0; 1645 1646 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 1647 TX_P2_ADDR >> 1); 1648 if (!ctx->i2c.tx_p2_client) 1649 goto free_tx_p1; 1650 1651 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 1652 RX_P0_ADDR >> 1); 1653 if (!ctx->i2c.rx_p0_client) 1654 goto free_tx_p2; 1655 1656 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 1657 RX_P1_ADDR >> 1); 1658 if (!ctx->i2c.rx_p1_client) 1659 goto free_rx_p0; 1660 1661 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 1662 RX_P2_ADDR >> 1); 1663 if (!ctx->i2c.rx_p2_client) 1664 goto free_rx_p1; 1665 1666 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 1667 TCPC_INTERFACE_ADDR >> 1); 1668 if (!ctx->i2c.tcpc_client) 1669 goto free_rx_p2; 1670 1671 return 0; 1672 1673 free_rx_p2: 1674 i2c_unregister_device(ctx->i2c.rx_p2_client); 1675 free_rx_p1: 1676 i2c_unregister_device(ctx->i2c.rx_p1_client); 1677 free_rx_p0: 1678 i2c_unregister_device(ctx->i2c.rx_p0_client); 1679 free_tx_p2: 1680 i2c_unregister_device(ctx->i2c.tx_p2_client); 1681 free_tx_p1: 1682 i2c_unregister_device(ctx->i2c.tx_p1_client); 1683 free_tx_p0: 1684 i2c_unregister_device(ctx->i2c.tx_p0_client); 1685 1686 return -ENOMEM; 1687 } 1688 1689 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 1690 { 1691 i2c_unregister_device(ctx->i2c.tx_p0_client); 1692 i2c_unregister_device(ctx->i2c.tx_p1_client); 1693 i2c_unregister_device(ctx->i2c.tx_p2_client); 1694 i2c_unregister_device(ctx->i2c.rx_p0_client); 1695 i2c_unregister_device(ctx->i2c.rx_p1_client); 1696 i2c_unregister_device(ctx->i2c.rx_p2_client); 1697 i2c_unregister_device(ctx->i2c.tcpc_client); 1698 } 1699 1700 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 1701 { 1702 struct anx7625_data *ctx = dev_get_drvdata(dev); 1703 1704 mutex_lock(&ctx->lock); 1705 1706 anx7625_stop_dp_work(ctx); 1707 anx7625_power_standby(ctx); 1708 1709 mutex_unlock(&ctx->lock); 1710 1711 return 0; 1712 } 1713 1714 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 1715 { 1716 struct anx7625_data *ctx = dev_get_drvdata(dev); 1717 1718 mutex_lock(&ctx->lock); 1719 1720 anx7625_power_on_init(ctx); 1721 anx7625_hpd_polling(ctx); 1722 1723 mutex_unlock(&ctx->lock); 1724 1725 return 0; 1726 } 1727 1728 static int __maybe_unused anx7625_resume(struct device *dev) 1729 { 1730 struct anx7625_data *ctx = dev_get_drvdata(dev); 1731 1732 if (!ctx->pdata.intp_irq) 1733 return 0; 1734 1735 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1736 enable_irq(ctx->pdata.intp_irq); 1737 anx7625_runtime_pm_resume(dev); 1738 } 1739 1740 return 0; 1741 } 1742 1743 static int __maybe_unused anx7625_suspend(struct device *dev) 1744 { 1745 struct anx7625_data *ctx = dev_get_drvdata(dev); 1746 1747 if (!ctx->pdata.intp_irq) 1748 return 0; 1749 1750 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1751 anx7625_runtime_pm_suspend(dev); 1752 disable_irq(ctx->pdata.intp_irq); 1753 } 1754 1755 return 0; 1756 } 1757 1758 static const struct dev_pm_ops anx7625_pm_ops = { 1759 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 1760 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 1761 anx7625_runtime_pm_resume, NULL) 1762 }; 1763 1764 static int anx7625_i2c_probe(struct i2c_client *client, 1765 const struct i2c_device_id *id) 1766 { 1767 struct anx7625_data *platform; 1768 struct anx7625_platform_data *pdata; 1769 int ret = 0; 1770 struct device *dev = &client->dev; 1771 1772 if (!i2c_check_functionality(client->adapter, 1773 I2C_FUNC_SMBUS_I2C_BLOCK)) { 1774 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 1775 return -ENODEV; 1776 } 1777 1778 platform = kzalloc(sizeof(*platform), GFP_KERNEL); 1779 if (!platform) { 1780 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 1781 return -ENOMEM; 1782 } 1783 1784 pdata = &platform->pdata; 1785 1786 ret = anx7625_parse_dt(dev, pdata); 1787 if (ret) { 1788 if (ret != -EPROBE_DEFER) 1789 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 1790 goto free_platform; 1791 } 1792 1793 platform->client = client; 1794 i2c_set_clientdata(client, platform); 1795 1796 pdata->supplies[0].supply = "vdd10"; 1797 pdata->supplies[1].supply = "vdd18"; 1798 pdata->supplies[2].supply = "vdd33"; 1799 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 1800 pdata->supplies); 1801 if (ret) { 1802 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 1803 return ret; 1804 } 1805 anx7625_init_gpio(platform); 1806 1807 mutex_init(&platform->lock); 1808 1809 platform->pdata.intp_irq = client->irq; 1810 if (platform->pdata.intp_irq) { 1811 INIT_WORK(&platform->work, anx7625_work_func); 1812 platform->workqueue = alloc_workqueue("anx7625_work", 1813 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 1814 if (!platform->workqueue) { 1815 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 1816 ret = -ENOMEM; 1817 goto free_platform; 1818 } 1819 1820 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 1821 NULL, anx7625_intr_hpd_isr, 1822 IRQF_TRIGGER_FALLING | 1823 IRQF_ONESHOT, 1824 "anx7625-intp", platform); 1825 if (ret) { 1826 DRM_DEV_ERROR(dev, "fail to request irq\n"); 1827 goto free_wq; 1828 } 1829 } 1830 1831 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 1832 ret = -ENOMEM; 1833 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 1834 goto free_wq; 1835 } 1836 1837 pm_runtime_enable(dev); 1838 1839 if (!platform->pdata.low_power_mode) { 1840 anx7625_disable_pd_protocol(platform); 1841 pm_runtime_get_sync(dev); 1842 } 1843 1844 /* Add work function */ 1845 if (platform->pdata.intp_irq) 1846 queue_work(platform->workqueue, &platform->work); 1847 1848 platform->bridge.funcs = &anx7625_bridge_funcs; 1849 platform->bridge.of_node = client->dev.of_node; 1850 platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 1851 platform->bridge.type = DRM_MODE_CONNECTOR_eDP; 1852 drm_bridge_add(&platform->bridge); 1853 1854 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 1855 1856 return 0; 1857 1858 free_wq: 1859 if (platform->workqueue) 1860 destroy_workqueue(platform->workqueue); 1861 1862 free_platform: 1863 kfree(platform); 1864 1865 return ret; 1866 } 1867 1868 static int anx7625_i2c_remove(struct i2c_client *client) 1869 { 1870 struct anx7625_data *platform = i2c_get_clientdata(client); 1871 1872 drm_bridge_remove(&platform->bridge); 1873 1874 if (platform->pdata.intp_irq) 1875 destroy_workqueue(platform->workqueue); 1876 1877 if (!platform->pdata.low_power_mode) 1878 pm_runtime_put_sync_suspend(&client->dev); 1879 1880 anx7625_unregister_i2c_dummy_clients(platform); 1881 1882 kfree(platform); 1883 return 0; 1884 } 1885 1886 static const struct i2c_device_id anx7625_id[] = { 1887 {"anx7625", 0}, 1888 {} 1889 }; 1890 1891 MODULE_DEVICE_TABLE(i2c, anx7625_id); 1892 1893 static const struct of_device_id anx_match_table[] = { 1894 {.compatible = "analogix,anx7625",}, 1895 {}, 1896 }; 1897 MODULE_DEVICE_TABLE(of, anx_match_table); 1898 1899 static struct i2c_driver anx7625_driver = { 1900 .driver = { 1901 .name = "anx7625", 1902 .of_match_table = anx_match_table, 1903 .pm = &anx7625_pm_ops, 1904 }, 1905 .probe = anx7625_i2c_probe, 1906 .remove = anx7625_i2c_remove, 1907 1908 .id_table = anx7625_id, 1909 }; 1910 1911 module_i2c_driver(anx7625_driver); 1912 1913 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 1914 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 1915 MODULE_LICENSE("GPL v2"); 1916 MODULE_VERSION(ANX7625_DRV_VERSION); 1917