1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_dp_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_mipi_dsi.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_panel.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 35 #include <media/v4l2-fwnode.h> 36 #include <sound/hdmi-codec.h> 37 #include <video/display_timing.h> 38 39 #include "anx7625.h" 40 41 /* 42 * There is a sync issue while access I2C register between AP(CPU) and 43 * internal firmware(OCM), to avoid the race condition, AP should access 44 * the reserved slave address before slave address occurs changes. 45 */ 46 static int i2c_access_workaround(struct anx7625_data *ctx, 47 struct i2c_client *client) 48 { 49 u8 offset; 50 struct device *dev = &client->dev; 51 int ret; 52 53 if (client == ctx->last_client) 54 return 0; 55 56 ctx->last_client = client; 57 58 if (client == ctx->i2c.tcpc_client) 59 offset = RSVD_00_ADDR; 60 else if (client == ctx->i2c.tx_p0_client) 61 offset = RSVD_D1_ADDR; 62 else if (client == ctx->i2c.tx_p1_client) 63 offset = RSVD_60_ADDR; 64 else if (client == ctx->i2c.rx_p0_client) 65 offset = RSVD_39_ADDR; 66 else if (client == ctx->i2c.rx_p1_client) 67 offset = RSVD_7F_ADDR; 68 else 69 offset = RSVD_00_ADDR; 70 71 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 72 if (ret < 0) 73 DRM_DEV_ERROR(dev, 74 "fail to access i2c id=%x\n:%x", 75 client->addr, offset); 76 77 return ret; 78 } 79 80 static int anx7625_reg_read(struct anx7625_data *ctx, 81 struct i2c_client *client, u8 reg_addr) 82 { 83 int ret; 84 struct device *dev = &client->dev; 85 86 i2c_access_workaround(ctx, client); 87 88 ret = i2c_smbus_read_byte_data(client, reg_addr); 89 if (ret < 0) 90 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 91 client->addr, reg_addr); 92 93 return ret; 94 } 95 96 static int anx7625_reg_block_read(struct anx7625_data *ctx, 97 struct i2c_client *client, 98 u8 reg_addr, u8 len, u8 *buf) 99 { 100 int ret; 101 struct device *dev = &client->dev; 102 103 i2c_access_workaround(ctx, client); 104 105 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 106 if (ret < 0) 107 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 108 client->addr, reg_addr); 109 110 return ret; 111 } 112 113 static int anx7625_reg_write(struct anx7625_data *ctx, 114 struct i2c_client *client, 115 u8 reg_addr, u8 reg_val) 116 { 117 int ret; 118 struct device *dev = &client->dev; 119 120 i2c_access_workaround(ctx, client); 121 122 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 123 124 if (ret < 0) 125 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 126 client->addr, reg_addr); 127 128 return ret; 129 } 130 131 static int anx7625_write_or(struct anx7625_data *ctx, 132 struct i2c_client *client, 133 u8 offset, u8 mask) 134 { 135 int val; 136 137 val = anx7625_reg_read(ctx, client, offset); 138 if (val < 0) 139 return val; 140 141 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 142 } 143 144 static int anx7625_write_and(struct anx7625_data *ctx, 145 struct i2c_client *client, 146 u8 offset, u8 mask) 147 { 148 int val; 149 150 val = anx7625_reg_read(ctx, client, offset); 151 if (val < 0) 152 return val; 153 154 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 155 } 156 157 static int anx7625_write_and_or(struct anx7625_data *ctx, 158 struct i2c_client *client, 159 u8 offset, u8 and_mask, u8 or_mask) 160 { 161 int val; 162 163 val = anx7625_reg_read(ctx, client, offset); 164 if (val < 0) 165 return val; 166 167 return anx7625_reg_write(ctx, client, 168 offset, (val & and_mask) | (or_mask)); 169 } 170 171 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 172 { 173 int i, ret; 174 175 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 176 AUDIO_CONTROL_REGISTER, 0x80); 177 for (i = 0; i < 13; i++) 178 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 179 VIDEO_BIT_MATRIX_12 + i, 180 0x18 + i); 181 182 return ret; 183 } 184 185 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 186 { 187 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 188 } 189 190 static int wait_aux_op_finish(struct anx7625_data *ctx) 191 { 192 struct device *dev = &ctx->client->dev; 193 int val; 194 int ret; 195 196 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 197 ctx, val, 198 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 199 2000, 200 2000 * 150); 201 if (ret) { 202 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 203 return -EIO; 204 } 205 206 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 207 AP_AUX_CTRL_STATUS); 208 if (val < 0 || (val & 0x0F)) { 209 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 210 return -EIO; 211 } 212 213 return 0; 214 } 215 216 static int anx7625_video_mute_control(struct anx7625_data *ctx, 217 u8 status) 218 { 219 int ret; 220 221 if (status) { 222 /* Set mute on flag */ 223 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 224 AP_AV_STATUS, AP_MIPI_MUTE); 225 /* Clear mipi RX en */ 226 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 227 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 228 } else { 229 /* Mute off flag */ 230 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 231 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 232 /* Set MIPI RX EN */ 233 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 234 AP_AV_STATUS, AP_MIPI_RX_EN); 235 } 236 237 return ret; 238 } 239 240 /* Reduction of fraction a/b */ 241 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 242 { 243 unsigned long gcd_num; 244 unsigned long tmp_a, tmp_b; 245 u32 i = 1; 246 247 gcd_num = gcd(*a, *b); 248 *a /= gcd_num; 249 *b /= gcd_num; 250 251 tmp_a = *a; 252 tmp_b = *b; 253 254 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 255 i++; 256 *a = tmp_a / i; 257 *b = tmp_b / i; 258 } 259 260 /* 261 * In the end, make a, b larger to have higher ODFC PLL 262 * output frequency accuracy 263 */ 264 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 265 *a <<= 1; 266 *b <<= 1; 267 } 268 269 *a >>= 1; 270 *b >>= 1; 271 } 272 273 static int anx7625_calculate_m_n(u32 pixelclock, 274 unsigned long *m, 275 unsigned long *n, 276 u8 *post_divider) 277 { 278 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 279 /* Pixel clock frequency is too high */ 280 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 281 pixelclock, 282 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 283 return -EINVAL; 284 } 285 286 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 287 /* Pixel clock frequency is too low */ 288 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 289 pixelclock, 290 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 291 return -EINVAL; 292 } 293 294 for (*post_divider = 1; 295 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 296 *post_divider += 1; 297 298 if (*post_divider > POST_DIVIDER_MAX) { 299 for (*post_divider = 1; 300 (pixelclock < 301 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 302 *post_divider += 1; 303 304 if (*post_divider > POST_DIVIDER_MAX) { 305 DRM_ERROR("cannot find property post_divider(%d)\n", 306 *post_divider); 307 return -EDOM; 308 } 309 } 310 311 /* Patch to improve the accuracy */ 312 if (*post_divider == 7) { 313 /* 27,000,000 is not divisible by 7 */ 314 *post_divider = 8; 315 } else if (*post_divider == 11) { 316 /* 27,000,000 is not divisible by 11 */ 317 *post_divider = 12; 318 } else if ((*post_divider == 13) || (*post_divider == 14)) { 319 /* 27,000,000 is not divisible by 13 or 14 */ 320 *post_divider = 15; 321 } 322 323 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 324 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 325 pixelclock * (*post_divider), 326 PLL_OUT_FREQ_ABS_MAX); 327 return -EDOM; 328 } 329 330 *m = pixelclock; 331 *n = XTAL_FRQ / (*post_divider); 332 333 anx7625_reduction_of_a_fraction(m, n); 334 335 return 0; 336 } 337 338 static int anx7625_odfc_config(struct anx7625_data *ctx, 339 u8 post_divider) 340 { 341 int ret; 342 struct device *dev = &ctx->client->dev; 343 344 /* Config input reference clock frequency 27MHz/19.2MHz */ 345 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 346 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 347 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 348 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 349 /* Post divider */ 350 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 351 MIPI_DIGITAL_PLL_8, 0x0f); 352 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 353 post_divider << 4); 354 355 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 356 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 357 ~MIPI_PLL_VCO_TUNE_REG_VAL); 358 359 /* Reset ODFC PLL */ 360 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 361 ~MIPI_PLL_RESET_N); 362 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 363 MIPI_PLL_RESET_N); 364 365 if (ret < 0) 366 DRM_DEV_ERROR(dev, "IO error.\n"); 367 368 return ret; 369 } 370 371 /* 372 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 373 * anx7625 defined K ratio for matching MIPI input video clock and 374 * DP output video clock. Increase K value can match bigger video data 375 * variation. IVO panel has small variation than DP CTS spec, need 376 * decrease the K value. 377 */ 378 static int anx7625_set_k_value(struct anx7625_data *ctx) 379 { 380 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 381 382 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 383 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 384 MIPI_DIGITAL_ADJ_1, 0x3B); 385 386 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 387 MIPI_DIGITAL_ADJ_1, 0x3D); 388 } 389 390 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 391 { 392 struct device *dev = &ctx->client->dev; 393 unsigned long m, n; 394 u16 htotal; 395 int ret; 396 u8 post_divider = 0; 397 398 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 399 &m, &n, &post_divider); 400 401 if (ret) { 402 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 403 return ret; 404 } 405 406 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 407 m, n, post_divider); 408 409 /* Configure pixel clock */ 410 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 411 (ctx->dt.pixelclock.min / 1000) & 0xFF); 412 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 413 (ctx->dt.pixelclock.min / 1000) >> 8); 414 /* Lane count */ 415 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 416 MIPI_LANE_CTRL_0, 0xfc); 417 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 418 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 419 420 /* Htotal */ 421 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 422 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 423 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 424 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 425 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 426 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 427 /* Hactive */ 428 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 429 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 430 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 431 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 432 /* HFP */ 433 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 434 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 435 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 436 HORIZONTAL_FRONT_PORCH_H, 437 ctx->dt.hfront_porch.min >> 8); 438 /* HWS */ 439 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 440 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 441 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 442 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 443 /* HBP */ 444 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 445 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 446 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 447 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 448 /* Vactive */ 449 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 450 ctx->dt.vactive.min); 451 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 452 ctx->dt.vactive.min >> 8); 453 /* VFP */ 454 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 455 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 456 /* VWS */ 457 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 458 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 459 /* VBP */ 460 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 461 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 462 /* M value */ 463 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 464 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 465 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 466 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 467 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 468 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 469 /* N value */ 470 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 471 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 472 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 473 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 474 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 475 (n & 0xff)); 476 477 anx7625_set_k_value(ctx); 478 479 ret |= anx7625_odfc_config(ctx, post_divider - 1); 480 481 if (ret < 0) 482 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 483 484 return ret; 485 } 486 487 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 488 { 489 int val; 490 struct device *dev = &ctx->client->dev; 491 492 /* Swap MIPI-DSI data lane 3 P and N */ 493 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 494 if (val < 0) { 495 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 496 return -EIO; 497 } 498 499 val |= (1 << MIPI_SWAP_CH3); 500 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 501 } 502 503 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 504 505 { 506 int val, ret; 507 struct device *dev = &ctx->client->dev; 508 509 /* Swap MIPI-DSI data lane 3 P and N */ 510 ret = anx7625_swap_dsi_lane3(ctx); 511 if (ret < 0) { 512 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 513 return ret; 514 } 515 516 /* DSI clock settings */ 517 val = (0 << MIPI_HS_PWD_CLK) | 518 (0 << MIPI_HS_RT_CLK) | 519 (0 << MIPI_PD_CLK) | 520 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 521 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 522 (0 << MIPI_CLK_DET_DET_BYPASS) | 523 (0 << MIPI_CLK_MISS_CTRL) | 524 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 525 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 526 MIPI_PHY_CONTROL_3, val); 527 528 /* 529 * Decreased HS prepare timing delay from 160ns to 80ns work with 530 * a) Dragon board 810 series (Qualcomm AP) 531 * b) Moving Pixel DSI source (PG3A pattern generator + 532 * P332 D-PHY Probe) default D-PHY timing 533 * 5ns/step 534 */ 535 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 536 MIPI_TIME_HS_PRPR, 0x10); 537 538 /* Enable DSI mode*/ 539 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 540 SELECT_DSI << MIPI_DPI_SELECT); 541 542 ret |= anx7625_dsi_video_timing_config(ctx); 543 if (ret < 0) { 544 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 545 return ret; 546 } 547 548 /* Toggle m, n ready */ 549 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 550 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 551 usleep_range(1000, 1100); 552 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 553 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 554 555 /* Configure integer stable register */ 556 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 557 MIPI_VIDEO_STABLE_CNT, 0x02); 558 /* Power on MIPI RX */ 559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 560 MIPI_LANE_CTRL_10, 0x00); 561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 562 MIPI_LANE_CTRL_10, 0x80); 563 564 if (ret < 0) 565 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 566 567 return ret; 568 } 569 570 static int anx7625_dsi_config(struct anx7625_data *ctx) 571 { 572 struct device *dev = &ctx->client->dev; 573 int ret; 574 575 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 576 577 /* DSC disable */ 578 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 579 R_DSC_CTRL_0, ~DSC_EN); 580 581 ret |= anx7625_api_dsi_config(ctx); 582 583 if (ret < 0) { 584 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 585 return ret; 586 } 587 588 /* Set MIPI RX EN */ 589 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 590 AP_AV_STATUS, AP_MIPI_RX_EN); 591 /* Clear mute flag */ 592 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 593 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 594 if (ret < 0) 595 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 596 else 597 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 598 599 return ret; 600 } 601 602 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 603 { 604 struct device *dev = &ctx->client->dev; 605 u16 freq = ctx->dt.pixelclock.min / 1000; 606 int ret; 607 608 /* configure pixel clock */ 609 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 610 PIXEL_CLOCK_L, freq & 0xFF); 611 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 612 PIXEL_CLOCK_H, (freq >> 8)); 613 614 /* set DPI mode */ 615 /* set to DPI PLL module sel */ 616 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 617 MIPI_DIGITAL_PLL_9, 0x20); 618 /* power down MIPI */ 619 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 620 MIPI_LANE_CTRL_10, 0x08); 621 /* enable DPI mode */ 622 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 623 MIPI_DIGITAL_PLL_18, 0x1C); 624 /* set first edge */ 625 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 626 VIDEO_CONTROL_0, 0x06); 627 if (ret < 0) 628 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 629 630 return ret; 631 } 632 633 static int anx7625_dpi_config(struct anx7625_data *ctx) 634 { 635 struct device *dev = &ctx->client->dev; 636 int ret; 637 638 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 639 640 /* DSC disable */ 641 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 642 R_DSC_CTRL_0, ~DSC_EN); 643 if (ret < 0) { 644 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 645 return ret; 646 } 647 648 ret = anx7625_config_bit_matrix(ctx); 649 if (ret < 0) { 650 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 651 return ret; 652 } 653 654 ret = anx7625_api_dpi_config(ctx); 655 if (ret < 0) { 656 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 657 return ret; 658 } 659 660 /* set MIPI RX EN */ 661 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 662 AP_AV_STATUS, AP_MIPI_RX_EN); 663 /* clear mute flag */ 664 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 665 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 666 if (ret < 0) 667 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 668 669 return ret; 670 } 671 672 static void anx7625_dp_start(struct anx7625_data *ctx) 673 { 674 int ret; 675 struct device *dev = &ctx->client->dev; 676 677 if (!ctx->display_timing_valid) { 678 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 679 return; 680 } 681 682 if (ctx->pdata.is_dpi) 683 ret = anx7625_dpi_config(ctx); 684 else 685 ret = anx7625_dsi_config(ctx); 686 687 if (ret < 0) 688 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 689 } 690 691 static void anx7625_dp_stop(struct anx7625_data *ctx) 692 { 693 struct device *dev = &ctx->client->dev; 694 int ret; 695 696 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 697 698 /* 699 * Video disable: 0x72:08 bit 7 = 0; 700 * Audio disable: 0x70:87 bit 0 = 0; 701 */ 702 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 703 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 704 705 ret |= anx7625_video_mute_control(ctx, 1); 706 if (ret < 0) 707 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 708 } 709 710 static int sp_tx_rst_aux(struct anx7625_data *ctx) 711 { 712 int ret; 713 714 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 715 AUX_RST); 716 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 717 ~AUX_RST); 718 return ret; 719 } 720 721 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 722 { 723 int ret; 724 725 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 726 AP_AUX_BUFF_START, offset); 727 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 728 AP_AUX_COMMAND, 0x04); 729 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 730 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 731 return (ret | wait_aux_op_finish(ctx)); 732 } 733 734 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 735 { 736 int ret; 737 738 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 739 AP_AUX_COMMAND, len_cmd); 740 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 741 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 742 return (ret | wait_aux_op_finish(ctx)); 743 } 744 745 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 746 { 747 int c = 0; 748 struct device *dev = &ctx->client->dev; 749 750 sp_tx_aux_wr(ctx, 0x7e); 751 sp_tx_aux_rd(ctx, 0x01); 752 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 753 if (c < 0) { 754 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 755 return -EIO; 756 } 757 758 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 759 760 if (c > MAX_EDID_BLOCK) 761 c = 1; 762 763 return c; 764 } 765 766 static int edid_read(struct anx7625_data *ctx, 767 u8 offset, u8 *pblock_buf) 768 { 769 int ret, cnt; 770 struct device *dev = &ctx->client->dev; 771 772 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 773 sp_tx_aux_wr(ctx, offset); 774 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 775 ret = sp_tx_aux_rd(ctx, 0xf1); 776 777 if (ret) { 778 ret = sp_tx_rst_aux(ctx); 779 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 780 } else { 781 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 782 AP_AUX_BUFF_START, 783 MAX_DPCD_BUFFER_SIZE, 784 pblock_buf); 785 if (ret > 0) 786 break; 787 } 788 } 789 790 if (cnt > EDID_TRY_CNT) 791 return -EIO; 792 793 return ret; 794 } 795 796 static int segments_edid_read(struct anx7625_data *ctx, 797 u8 segment, u8 *buf, u8 offset) 798 { 799 u8 cnt; 800 int ret; 801 struct device *dev = &ctx->client->dev; 802 803 /* Write address only */ 804 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 805 AP_AUX_ADDR_7_0, 0x30); 806 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 807 AP_AUX_COMMAND, 0x04); 808 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 809 AP_AUX_CTRL_STATUS, 810 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 811 812 ret |= wait_aux_op_finish(ctx); 813 /* Write segment address */ 814 ret |= sp_tx_aux_wr(ctx, segment); 815 /* Data read */ 816 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 817 AP_AUX_ADDR_7_0, 0x50); 818 if (ret) { 819 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 820 return ret; 821 } 822 823 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 824 sp_tx_aux_wr(ctx, offset); 825 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 826 ret = sp_tx_aux_rd(ctx, 0xf1); 827 828 if (ret) { 829 ret = sp_tx_rst_aux(ctx); 830 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 831 } else { 832 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 833 AP_AUX_BUFF_START, 834 MAX_DPCD_BUFFER_SIZE, buf); 835 if (ret > 0) 836 break; 837 } 838 } 839 840 if (cnt > EDID_TRY_CNT) 841 return -EIO; 842 843 return ret; 844 } 845 846 static int sp_tx_edid_read(struct anx7625_data *ctx, 847 u8 *pedid_blocks_buf) 848 { 849 u8 offset, edid_pos; 850 int count, blocks_num; 851 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 852 u8 i, j; 853 u8 g_edid_break = 0; 854 int ret; 855 struct device *dev = &ctx->client->dev; 856 857 /* Address initial */ 858 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 859 AP_AUX_ADDR_7_0, 0x50); 860 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 861 AP_AUX_ADDR_15_8, 0); 862 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 863 AP_AUX_ADDR_19_16, 0xf0); 864 if (ret < 0) { 865 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 866 return -EIO; 867 } 868 869 blocks_num = sp_tx_get_edid_block(ctx); 870 if (blocks_num < 0) 871 return blocks_num; 872 873 count = 0; 874 875 do { 876 switch (count) { 877 case 0: 878 case 1: 879 for (i = 0; i < 8; i++) { 880 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 881 g_edid_break = edid_read(ctx, offset, 882 pblock_buf); 883 884 if (g_edid_break) 885 break; 886 887 memcpy(&pedid_blocks_buf[offset], 888 pblock_buf, 889 MAX_DPCD_BUFFER_SIZE); 890 } 891 892 break; 893 case 2: 894 offset = 0x00; 895 896 for (j = 0; j < 8; j++) { 897 edid_pos = (j + count * 8) * 898 MAX_DPCD_BUFFER_SIZE; 899 900 if (g_edid_break == 1) 901 break; 902 903 ret = segments_edid_read(ctx, count / 2, 904 pblock_buf, offset); 905 if (ret < 0) 906 return ret; 907 908 memcpy(&pedid_blocks_buf[edid_pos], 909 pblock_buf, 910 MAX_DPCD_BUFFER_SIZE); 911 offset = offset + 0x10; 912 } 913 914 break; 915 case 3: 916 offset = 0x80; 917 918 for (j = 0; j < 8; j++) { 919 edid_pos = (j + count * 8) * 920 MAX_DPCD_BUFFER_SIZE; 921 if (g_edid_break == 1) 922 break; 923 924 ret = segments_edid_read(ctx, count / 2, 925 pblock_buf, offset); 926 if (ret < 0) 927 return ret; 928 929 memcpy(&pedid_blocks_buf[edid_pos], 930 pblock_buf, 931 MAX_DPCD_BUFFER_SIZE); 932 offset = offset + 0x10; 933 } 934 935 break; 936 default: 937 break; 938 } 939 940 count++; 941 942 } while (blocks_num >= count); 943 944 /* Check edid data */ 945 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 946 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 947 return -EINVAL; 948 } 949 950 /* Reset aux channel */ 951 ret = sp_tx_rst_aux(ctx); 952 if (ret < 0) { 953 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 954 return ret; 955 } 956 957 return (blocks_num + 1); 958 } 959 960 static void anx7625_power_on(struct anx7625_data *ctx) 961 { 962 struct device *dev = &ctx->client->dev; 963 int ret, i; 964 965 if (!ctx->pdata.low_power_mode) { 966 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 967 return; 968 } 969 970 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 971 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 972 if (ret < 0) { 973 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 974 i, ret); 975 goto reg_err; 976 } 977 usleep_range(2000, 2100); 978 } 979 980 usleep_range(11000, 12000); 981 982 /* Power on pin enable */ 983 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 984 usleep_range(10000, 11000); 985 /* Power reset pin enable */ 986 gpiod_set_value(ctx->pdata.gpio_reset, 1); 987 usleep_range(10000, 11000); 988 989 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 990 return; 991 reg_err: 992 for (--i; i >= 0; i--) 993 regulator_disable(ctx->pdata.supplies[i].consumer); 994 } 995 996 static void anx7625_power_standby(struct anx7625_data *ctx) 997 { 998 struct device *dev = &ctx->client->dev; 999 int ret; 1000 1001 if (!ctx->pdata.low_power_mode) { 1002 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1003 return; 1004 } 1005 1006 gpiod_set_value(ctx->pdata.gpio_reset, 0); 1007 usleep_range(1000, 1100); 1008 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 1009 usleep_range(1000, 1100); 1010 1011 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1012 ctx->pdata.supplies); 1013 if (ret < 0) 1014 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1015 1016 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1017 } 1018 1019 /* Basic configurations of ANX7625 */ 1020 static void anx7625_config(struct anx7625_data *ctx) 1021 { 1022 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1023 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1024 } 1025 1026 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1027 { 1028 struct device *dev = &ctx->client->dev; 1029 int ret; 1030 1031 /* Reset main ocm */ 1032 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1033 /* Disable PD */ 1034 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1035 AP_AV_STATUS, AP_DISABLE_PD); 1036 /* Release main ocm */ 1037 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1038 1039 if (ret < 0) 1040 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1041 else 1042 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1043 } 1044 1045 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1046 { 1047 int ret; 1048 struct device *dev = &ctx->client->dev; 1049 1050 /* Check interface workable */ 1051 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1052 FLASH_LOAD_STA); 1053 if (ret < 0) { 1054 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1055 return ret; 1056 } 1057 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1058 return -ENODEV; 1059 1060 anx7625_disable_pd_protocol(ctx); 1061 1062 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1063 anx7625_reg_read(ctx, 1064 ctx->i2c.rx_p0_client, 1065 OCM_FW_VERSION), 1066 anx7625_reg_read(ctx, 1067 ctx->i2c.rx_p0_client, 1068 OCM_FW_REVERSION)); 1069 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1070 ANX7625_DRV_VERSION); 1071 1072 return 0; 1073 } 1074 1075 static void anx7625_power_on_init(struct anx7625_data *ctx) 1076 { 1077 int retry_count, i; 1078 1079 for (retry_count = 0; retry_count < 3; retry_count++) { 1080 anx7625_power_on(ctx); 1081 anx7625_config(ctx); 1082 1083 for (i = 0; i < OCM_LOADING_TIME; i++) { 1084 if (!anx7625_ocm_loading_check(ctx)) 1085 return; 1086 usleep_range(1000, 1100); 1087 } 1088 anx7625_power_standby(ctx); 1089 } 1090 } 1091 1092 static void anx7625_init_gpio(struct anx7625_data *platform) 1093 { 1094 struct device *dev = &platform->client->dev; 1095 1096 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1097 1098 /* Gpio for chip power enable */ 1099 platform->pdata.gpio_p_on = 1100 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1101 /* Gpio for chip reset */ 1102 platform->pdata.gpio_reset = 1103 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1104 1105 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1106 platform->pdata.low_power_mode = 1; 1107 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1108 desc_to_gpio(platform->pdata.gpio_p_on), 1109 desc_to_gpio(platform->pdata.gpio_reset)); 1110 } else { 1111 platform->pdata.low_power_mode = 0; 1112 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1113 } 1114 } 1115 1116 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1117 { 1118 ctx->hpd_status = 0; 1119 ctx->hpd_high_cnt = 0; 1120 ctx->display_timing_valid = 0; 1121 } 1122 1123 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1124 { 1125 int ret; 1126 struct device *dev = &ctx->client->dev; 1127 1128 if (ctx->hpd_high_cnt >= 2) { 1129 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1130 return; 1131 } 1132 1133 ctx->hpd_status = 1; 1134 ctx->hpd_high_cnt++; 1135 1136 /* Not support HDCP */ 1137 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1138 1139 /* Try auth flag */ 1140 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1141 /* Interrupt for DRM */ 1142 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1143 if (ret < 0) { 1144 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1145 return; 1146 } 1147 1148 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1149 if (ret < 0) 1150 return; 1151 1152 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1153 } 1154 1155 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1156 { 1157 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1158 } 1159 1160 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1161 { 1162 int ret, val; 1163 struct device *dev = &ctx->client->dev; 1164 1165 /* Interrupt mode, no need poll HPD status, just return */ 1166 if (ctx->pdata.intp_irq) 1167 return; 1168 1169 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1170 ctx, val, 1171 ((val & HPD_STATUS) || (val < 0)), 1172 5000, 1173 5000 * 100); 1174 if (ret) { 1175 DRM_DEV_ERROR(dev, "no hpd.\n"); 1176 return; 1177 } 1178 1179 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1180 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1181 INTR_ALERT_1, 0xFF); 1182 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1183 INTERFACE_CHANGE_INT, 0); 1184 1185 anx7625_start_dp_work(ctx); 1186 1187 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1188 drm_helper_hpd_irq_event(ctx->bridge.dev); 1189 } 1190 1191 static void anx7625_remove_edid(struct anx7625_data *ctx) 1192 { 1193 ctx->slimport_edid_p.edid_block_num = -1; 1194 } 1195 1196 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1197 { 1198 int i; 1199 1200 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1201 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1202 DP_TX_LANE0_SWING_REG0 + i, 1203 ctx->pdata.lane0_reg_data[i] & 0xFF); 1204 1205 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1206 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1207 DP_TX_LANE1_SWING_REG0 + i, 1208 ctx->pdata.lane1_reg_data[i] & 0xFF); 1209 } 1210 1211 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1212 { 1213 struct device *dev = &ctx->client->dev; 1214 1215 /* HPD changed */ 1216 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1217 (u32)on); 1218 1219 if (on == 0) { 1220 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1221 anx7625_remove_edid(ctx); 1222 anx7625_stop_dp_work(ctx); 1223 } else { 1224 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1225 anx7625_start_dp_work(ctx); 1226 anx7625_dp_adjust_swing(ctx); 1227 } 1228 } 1229 1230 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1231 { 1232 int intr_vector, status; 1233 struct device *dev = &ctx->client->dev; 1234 1235 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1236 INTR_ALERT_1, 0xFF); 1237 if (status < 0) { 1238 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1239 return status; 1240 } 1241 1242 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1243 INTERFACE_CHANGE_INT); 1244 if (intr_vector < 0) { 1245 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1246 return intr_vector; 1247 } 1248 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1249 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1250 INTERFACE_CHANGE_INT, 1251 intr_vector & (~intr_vector)); 1252 if (status < 0) { 1253 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1254 return status; 1255 } 1256 1257 if (!(intr_vector & HPD_STATUS_CHANGE)) 1258 return -ENOENT; 1259 1260 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1261 SYSTEM_STSTUS); 1262 if (status < 0) { 1263 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1264 return status; 1265 } 1266 1267 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1268 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1269 1270 return 0; 1271 } 1272 1273 static void anx7625_work_func(struct work_struct *work) 1274 { 1275 int event; 1276 struct anx7625_data *ctx = container_of(work, 1277 struct anx7625_data, work); 1278 1279 mutex_lock(&ctx->lock); 1280 1281 if (pm_runtime_suspended(&ctx->client->dev)) 1282 goto unlock; 1283 1284 event = anx7625_hpd_change_detect(ctx); 1285 if (event < 0) 1286 goto unlock; 1287 1288 if (ctx->bridge_attached) 1289 drm_helper_hpd_irq_event(ctx->bridge.dev); 1290 1291 unlock: 1292 mutex_unlock(&ctx->lock); 1293 } 1294 1295 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1296 { 1297 struct anx7625_data *ctx = (struct anx7625_data *)data; 1298 1299 queue_work(ctx->workqueue, &ctx->work); 1300 1301 return IRQ_HANDLED; 1302 } 1303 1304 static int anx7625_get_swing_setting(struct device *dev, 1305 struct anx7625_platform_data *pdata) 1306 { 1307 int num_regs; 1308 1309 if (of_get_property(dev->of_node, 1310 "analogix,lane0-swing", &num_regs)) { 1311 if (num_regs > DP_TX_SWING_REG_CNT) 1312 num_regs = DP_TX_SWING_REG_CNT; 1313 1314 pdata->dp_lane0_swing_reg_cnt = num_regs; 1315 of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1316 pdata->lane0_reg_data, num_regs); 1317 } 1318 1319 if (of_get_property(dev->of_node, 1320 "analogix,lane1-swing", &num_regs)) { 1321 if (num_regs > DP_TX_SWING_REG_CNT) 1322 num_regs = DP_TX_SWING_REG_CNT; 1323 1324 pdata->dp_lane1_swing_reg_cnt = num_regs; 1325 of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1326 pdata->lane1_reg_data, num_regs); 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int anx7625_parse_dt(struct device *dev, 1333 struct anx7625_platform_data *pdata) 1334 { 1335 struct device_node *np = dev->of_node, *ep0; 1336 struct drm_panel *panel; 1337 int ret; 1338 int bus_type, mipi_lanes; 1339 1340 anx7625_get_swing_setting(dev, pdata); 1341 1342 pdata->is_dpi = 1; /* default dpi mode */ 1343 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1344 if (!pdata->mipi_host_node) { 1345 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1346 return -ENODEV; 1347 } 1348 1349 bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1350 mipi_lanes = MAX_LANES_SUPPORT; 1351 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1352 if (ep0) { 1353 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1354 bus_type = 0; 1355 1356 mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1357 } 1358 1359 if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1360 pdata->is_dpi = 0; 1361 1362 pdata->mipi_lanes = mipi_lanes; 1363 if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1364 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1365 1366 if (pdata->is_dpi) 1367 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1368 else 1369 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1370 1371 if (of_property_read_bool(np, "analogix,audio-enable")) 1372 pdata->audio_en = 1; 1373 1374 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1375 if (ret < 0) { 1376 if (ret == -ENODEV) 1377 return 0; 1378 return ret; 1379 } 1380 if (!panel) 1381 return -ENODEV; 1382 1383 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1384 if (IS_ERR(pdata->panel_bridge)) 1385 return PTR_ERR(pdata->panel_bridge); 1386 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1387 1388 return 0; 1389 } 1390 1391 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1392 { 1393 return container_of(bridge, struct anx7625_data, bridge); 1394 } 1395 1396 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1397 { 1398 struct device *dev = &ctx->client->dev; 1399 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1400 int edid_num; 1401 u8 *edid; 1402 1403 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1404 if (!edid) { 1405 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1406 return NULL; 1407 } 1408 1409 if (ctx->slimport_edid_p.edid_block_num > 0) { 1410 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1411 FOUR_BLOCK_SIZE); 1412 return (struct edid *)edid; 1413 } 1414 1415 pm_runtime_get_sync(dev); 1416 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1417 pm_runtime_put_sync(dev); 1418 1419 if (edid_num < 1) { 1420 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1421 kfree(edid); 1422 return NULL; 1423 } 1424 1425 p_edid->edid_block_num = edid_num; 1426 1427 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1428 return (struct edid *)edid; 1429 } 1430 1431 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1432 { 1433 struct device *dev = &ctx->client->dev; 1434 1435 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1436 1437 if (ctx->pdata.panel_bridge) 1438 return connector_status_connected; 1439 1440 return ctx->hpd_status ? connector_status_connected : 1441 connector_status_disconnected; 1442 } 1443 1444 static int anx7625_audio_hw_params(struct device *dev, void *data, 1445 struct hdmi_codec_daifmt *fmt, 1446 struct hdmi_codec_params *params) 1447 { 1448 struct anx7625_data *ctx = dev_get_drvdata(dev); 1449 int wl, ch, rate; 1450 int ret = 0; 1451 1452 if (fmt->fmt != HDMI_DSP_A) { 1453 DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1454 return -EINVAL; 1455 } 1456 1457 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1458 params->sample_rate, params->sample_width, 1459 params->cea.channels); 1460 1461 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1462 AUDIO_CHANNEL_STATUS_6, 1463 ~I2S_SLAVE_MODE, 1464 TDM_SLAVE_MODE); 1465 1466 /* Word length */ 1467 switch (params->sample_width) { 1468 case 16: 1469 wl = AUDIO_W_LEN_16_20MAX; 1470 break; 1471 case 18: 1472 wl = AUDIO_W_LEN_18_20MAX; 1473 break; 1474 case 20: 1475 wl = AUDIO_W_LEN_20_20MAX; 1476 break; 1477 case 24: 1478 wl = AUDIO_W_LEN_24_24MAX; 1479 break; 1480 default: 1481 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1482 params->sample_width); 1483 return -EINVAL; 1484 } 1485 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1486 AUDIO_CHANNEL_STATUS_5, 1487 0xf0, wl); 1488 1489 /* Channel num */ 1490 switch (params->cea.channels) { 1491 case 2: 1492 ch = I2S_CH_2; 1493 break; 1494 case 4: 1495 ch = TDM_CH_4; 1496 break; 1497 case 6: 1498 ch = TDM_CH_6; 1499 break; 1500 case 8: 1501 ch = TDM_CH_8; 1502 break; 1503 default: 1504 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1505 params->cea.channels); 1506 return -EINVAL; 1507 } 1508 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1509 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1510 if (ch > I2S_CH_2) 1511 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1512 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1513 else 1514 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1515 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1516 1517 /* FS */ 1518 switch (params->sample_rate) { 1519 case 32000: 1520 rate = AUDIO_FS_32K; 1521 break; 1522 case 44100: 1523 rate = AUDIO_FS_441K; 1524 break; 1525 case 48000: 1526 rate = AUDIO_FS_48K; 1527 break; 1528 case 88200: 1529 rate = AUDIO_FS_882K; 1530 break; 1531 case 96000: 1532 rate = AUDIO_FS_96K; 1533 break; 1534 case 176400: 1535 rate = AUDIO_FS_1764K; 1536 break; 1537 case 192000: 1538 rate = AUDIO_FS_192K; 1539 break; 1540 default: 1541 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1542 params->sample_rate); 1543 return -EINVAL; 1544 } 1545 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1546 AUDIO_CHANNEL_STATUS_4, 1547 0xf0, rate); 1548 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1549 AP_AV_STATUS, AP_AUDIO_CHG); 1550 if (ret < 0) { 1551 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1552 return -EIO; 1553 } 1554 1555 return 0; 1556 } 1557 1558 static void anx7625_audio_shutdown(struct device *dev, void *data) 1559 { 1560 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1561 } 1562 1563 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1564 struct device_node *endpoint) 1565 { 1566 struct of_endpoint of_ep; 1567 int ret; 1568 1569 ret = of_graph_parse_endpoint(endpoint, &of_ep); 1570 if (ret < 0) 1571 return ret; 1572 1573 /* 1574 * HDMI sound should be located at external DPI port 1575 * Didn't have good way to check where is internal(DSI) 1576 * or external(DPI) bridge 1577 */ 1578 return 0; 1579 } 1580 1581 static void 1582 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1583 enum drm_connector_status status) 1584 { 1585 if (ctx->plugged_cb && ctx->codec_dev) { 1586 ctx->plugged_cb(ctx->codec_dev, 1587 status == connector_status_connected); 1588 } 1589 } 1590 1591 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1592 hdmi_codec_plugged_cb fn, 1593 struct device *codec_dev) 1594 { 1595 struct anx7625_data *ctx = data; 1596 1597 ctx->plugged_cb = fn; 1598 ctx->codec_dev = codec_dev; 1599 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1600 1601 return 0; 1602 } 1603 1604 static const struct hdmi_codec_ops anx7625_codec_ops = { 1605 .hw_params = anx7625_audio_hw_params, 1606 .audio_shutdown = anx7625_audio_shutdown, 1607 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1608 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1609 }; 1610 1611 static void anx7625_unregister_audio(struct anx7625_data *ctx) 1612 { 1613 struct device *dev = &ctx->client->dev; 1614 1615 if (ctx->audio_pdev) { 1616 platform_device_unregister(ctx->audio_pdev); 1617 ctx->audio_pdev = NULL; 1618 } 1619 1620 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1621 } 1622 1623 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1624 { 1625 struct hdmi_codec_pdata codec_data = { 1626 .ops = &anx7625_codec_ops, 1627 .max_i2s_channels = 8, 1628 .i2s = 1, 1629 .data = ctx, 1630 }; 1631 1632 ctx->audio_pdev = platform_device_register_data(dev, 1633 HDMI_CODEC_DRV_NAME, 1634 PLATFORM_DEVID_AUTO, 1635 &codec_data, 1636 sizeof(codec_data)); 1637 1638 if (IS_ERR(ctx->audio_pdev)) 1639 return IS_ERR(ctx->audio_pdev); 1640 1641 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1642 1643 return 0; 1644 } 1645 1646 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1647 { 1648 struct mipi_dsi_device *dsi; 1649 struct device *dev = &ctx->client->dev; 1650 struct mipi_dsi_host *host; 1651 const struct mipi_dsi_device_info info = { 1652 .type = "anx7625", 1653 .channel = 0, 1654 .node = NULL, 1655 }; 1656 int ret; 1657 1658 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1659 1660 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1661 if (!host) { 1662 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1663 return -EINVAL; 1664 } 1665 1666 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 1667 if (IS_ERR(dsi)) { 1668 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 1669 return -EINVAL; 1670 } 1671 1672 dsi->lanes = ctx->pdata.mipi_lanes; 1673 dsi->format = MIPI_DSI_FMT_RGB888; 1674 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1675 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1676 MIPI_DSI_MODE_VIDEO_HSE; 1677 1678 ret = devm_mipi_dsi_attach(dev, dsi); 1679 if (ret) { 1680 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 1681 return ret; 1682 } 1683 1684 ctx->dsi = dsi; 1685 1686 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 1687 1688 return 0; 1689 } 1690 1691 static int anx7625_bridge_attach(struct drm_bridge *bridge, 1692 enum drm_bridge_attach_flags flags) 1693 { 1694 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1695 int err; 1696 struct device *dev = &ctx->client->dev; 1697 1698 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 1699 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 1700 return -EINVAL; 1701 1702 if (!bridge->encoder) { 1703 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 1704 return -ENODEV; 1705 } 1706 1707 if (ctx->pdata.panel_bridge) { 1708 err = drm_bridge_attach(bridge->encoder, 1709 ctx->pdata.panel_bridge, 1710 &ctx->bridge, flags); 1711 if (err) 1712 return err; 1713 } 1714 1715 ctx->bridge_attached = 1; 1716 1717 return 0; 1718 } 1719 1720 static enum drm_mode_status 1721 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 1722 const struct drm_display_info *info, 1723 const struct drm_display_mode *mode) 1724 { 1725 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1726 struct device *dev = &ctx->client->dev; 1727 1728 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 1729 1730 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 1731 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 1732 DRM_DEV_DEBUG_DRIVER(dev, 1733 "drm mode invalid, pixelclock too high.\n"); 1734 return MODE_CLOCK_HIGH; 1735 } 1736 1737 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 1738 1739 return MODE_OK; 1740 } 1741 1742 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 1743 const struct drm_display_mode *old_mode, 1744 const struct drm_display_mode *mode) 1745 { 1746 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1747 struct device *dev = &ctx->client->dev; 1748 1749 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 1750 1751 ctx->dt.pixelclock.min = mode->clock; 1752 ctx->dt.hactive.min = mode->hdisplay; 1753 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 1754 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 1755 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 1756 ctx->dt.vactive.min = mode->vdisplay; 1757 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 1758 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 1759 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 1760 1761 ctx->display_timing_valid = 1; 1762 1763 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 1764 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 1765 ctx->dt.hactive.min, 1766 ctx->dt.hsync_len.min, 1767 ctx->dt.hfront_porch.min, 1768 ctx->dt.hback_porch.min); 1769 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 1770 ctx->dt.vactive.min, 1771 ctx->dt.vsync_len.min, 1772 ctx->dt.vfront_porch.min, 1773 ctx->dt.vback_porch.min); 1774 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 1775 mode->hdisplay, 1776 mode->hsync_start); 1777 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 1778 mode->hsync_end, 1779 mode->htotal); 1780 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 1781 mode->vdisplay, 1782 mode->vsync_start); 1783 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 1784 mode->vsync_end, 1785 mode->vtotal); 1786 } 1787 1788 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 1789 const struct drm_display_mode *mode, 1790 struct drm_display_mode *adj) 1791 { 1792 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1793 struct device *dev = &ctx->client->dev; 1794 u32 hsync, hfp, hbp, hblanking; 1795 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 1796 u32 vref, adj_clock; 1797 1798 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 1799 1800 /* No need fixup for external monitor */ 1801 if (!ctx->pdata.panel_bridge) 1802 return true; 1803 1804 hsync = mode->hsync_end - mode->hsync_start; 1805 hfp = mode->hsync_start - mode->hdisplay; 1806 hbp = mode->htotal - mode->hsync_end; 1807 hblanking = mode->htotal - mode->hdisplay; 1808 1809 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 1810 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1811 hsync, hfp, hbp, adj->clock); 1812 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1813 adj->hsync_start, adj->hsync_end, adj->htotal); 1814 1815 adj_hfp = hfp; 1816 adj_hsync = hsync; 1817 adj_hbp = hbp; 1818 adj_hblanking = hblanking; 1819 1820 /* HFP needs to be even */ 1821 if (hfp & 0x1) { 1822 adj_hfp += 1; 1823 adj_hblanking += 1; 1824 } 1825 1826 /* HBP needs to be even */ 1827 if (hbp & 0x1) { 1828 adj_hbp -= 1; 1829 adj_hblanking -= 1; 1830 } 1831 1832 /* HSYNC needs to be even */ 1833 if (hsync & 0x1) { 1834 if (adj_hblanking < hblanking) 1835 adj_hsync += 1; 1836 else 1837 adj_hsync -= 1; 1838 } 1839 1840 /* 1841 * Once illegal timing detected, use default HFP, HSYNC, HBP 1842 * This adjusting made for built-in eDP panel, for the externel 1843 * DP monitor, may need return false. 1844 */ 1845 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 1846 adj_hsync = SYNC_LEN_DEF; 1847 adj_hfp = HFP_HBP_DEF; 1848 adj_hbp = HFP_HBP_DEF; 1849 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 1850 if (hblanking < HBLANKING_MIN) { 1851 delta_adj = HBLANKING_MIN - hblanking; 1852 adj_clock = vref * delta_adj * adj->vtotal; 1853 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 1854 } else { 1855 delta_adj = hblanking - HBLANKING_MIN; 1856 adj_clock = vref * delta_adj * adj->vtotal; 1857 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 1858 } 1859 1860 DRM_WARN("illegal hblanking timing, use default.\n"); 1861 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 1862 } else if (adj_hfp < HP_MIN) { 1863 /* Adjust hfp if hfp less than HP_MIN */ 1864 delta_adj = HP_MIN - adj_hfp; 1865 adj_hfp = HP_MIN; 1866 1867 /* 1868 * Balance total HBlanking pixel, if HBP does not have enough 1869 * space, adjust HSYNC length, otherwise adjust HBP 1870 */ 1871 if ((adj_hbp - delta_adj) < HP_MIN) 1872 /* HBP not enough space */ 1873 adj_hsync -= delta_adj; 1874 else 1875 adj_hbp -= delta_adj; 1876 } else if (adj_hbp < HP_MIN) { 1877 delta_adj = HP_MIN - adj_hbp; 1878 adj_hbp = HP_MIN; 1879 1880 /* 1881 * Balance total HBlanking pixel, if HBP hasn't enough space, 1882 * adjust HSYNC length, otherwize adjust HBP 1883 */ 1884 if ((adj_hfp - delta_adj) < HP_MIN) 1885 /* HFP not enough space */ 1886 adj_hsync -= delta_adj; 1887 else 1888 adj_hfp -= delta_adj; 1889 } 1890 1891 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 1892 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1893 adj_hsync, adj_hfp, adj_hbp, adj->clock); 1894 1895 /* Reconstruct timing */ 1896 adj->hsync_start = adj->hdisplay + adj_hfp; 1897 adj->hsync_end = adj->hsync_start + adj_hsync; 1898 adj->htotal = adj->hsync_end + adj_hbp; 1899 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1900 adj->hsync_start, adj->hsync_end, adj->htotal); 1901 1902 return true; 1903 } 1904 1905 static void anx7625_bridge_enable(struct drm_bridge *bridge) 1906 { 1907 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1908 struct device *dev = &ctx->client->dev; 1909 1910 DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 1911 1912 pm_runtime_get_sync(dev); 1913 1914 anx7625_dp_start(ctx); 1915 } 1916 1917 static void anx7625_bridge_disable(struct drm_bridge *bridge) 1918 { 1919 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1920 struct device *dev = &ctx->client->dev; 1921 1922 DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 1923 1924 anx7625_dp_stop(ctx); 1925 1926 pm_runtime_put_sync(dev); 1927 } 1928 1929 static enum drm_connector_status 1930 anx7625_bridge_detect(struct drm_bridge *bridge) 1931 { 1932 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1933 struct device *dev = &ctx->client->dev; 1934 1935 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 1936 1937 return anx7625_sink_detect(ctx); 1938 } 1939 1940 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 1941 struct drm_connector *connector) 1942 { 1943 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1944 struct device *dev = &ctx->client->dev; 1945 1946 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 1947 1948 return anx7625_get_edid(ctx); 1949 } 1950 1951 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 1952 .attach = anx7625_bridge_attach, 1953 .disable = anx7625_bridge_disable, 1954 .mode_valid = anx7625_bridge_mode_valid, 1955 .mode_set = anx7625_bridge_mode_set, 1956 .mode_fixup = anx7625_bridge_mode_fixup, 1957 .enable = anx7625_bridge_enable, 1958 .detect = anx7625_bridge_detect, 1959 .get_edid = anx7625_bridge_get_edid, 1960 }; 1961 1962 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 1963 struct i2c_client *client) 1964 { 1965 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 1966 TX_P0_ADDR >> 1); 1967 if (!ctx->i2c.tx_p0_client) 1968 return -ENOMEM; 1969 1970 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 1971 TX_P1_ADDR >> 1); 1972 if (!ctx->i2c.tx_p1_client) 1973 goto free_tx_p0; 1974 1975 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 1976 TX_P2_ADDR >> 1); 1977 if (!ctx->i2c.tx_p2_client) 1978 goto free_tx_p1; 1979 1980 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 1981 RX_P0_ADDR >> 1); 1982 if (!ctx->i2c.rx_p0_client) 1983 goto free_tx_p2; 1984 1985 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 1986 RX_P1_ADDR >> 1); 1987 if (!ctx->i2c.rx_p1_client) 1988 goto free_rx_p0; 1989 1990 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 1991 RX_P2_ADDR >> 1); 1992 if (!ctx->i2c.rx_p2_client) 1993 goto free_rx_p1; 1994 1995 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 1996 TCPC_INTERFACE_ADDR >> 1); 1997 if (!ctx->i2c.tcpc_client) 1998 goto free_rx_p2; 1999 2000 return 0; 2001 2002 free_rx_p2: 2003 i2c_unregister_device(ctx->i2c.rx_p2_client); 2004 free_rx_p1: 2005 i2c_unregister_device(ctx->i2c.rx_p1_client); 2006 free_rx_p0: 2007 i2c_unregister_device(ctx->i2c.rx_p0_client); 2008 free_tx_p2: 2009 i2c_unregister_device(ctx->i2c.tx_p2_client); 2010 free_tx_p1: 2011 i2c_unregister_device(ctx->i2c.tx_p1_client); 2012 free_tx_p0: 2013 i2c_unregister_device(ctx->i2c.tx_p0_client); 2014 2015 return -ENOMEM; 2016 } 2017 2018 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 2019 { 2020 i2c_unregister_device(ctx->i2c.tx_p0_client); 2021 i2c_unregister_device(ctx->i2c.tx_p1_client); 2022 i2c_unregister_device(ctx->i2c.tx_p2_client); 2023 i2c_unregister_device(ctx->i2c.rx_p0_client); 2024 i2c_unregister_device(ctx->i2c.rx_p1_client); 2025 i2c_unregister_device(ctx->i2c.rx_p2_client); 2026 i2c_unregister_device(ctx->i2c.tcpc_client); 2027 } 2028 2029 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2030 { 2031 struct anx7625_data *ctx = dev_get_drvdata(dev); 2032 2033 mutex_lock(&ctx->lock); 2034 2035 anx7625_stop_dp_work(ctx); 2036 anx7625_power_standby(ctx); 2037 2038 mutex_unlock(&ctx->lock); 2039 2040 return 0; 2041 } 2042 2043 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2044 { 2045 struct anx7625_data *ctx = dev_get_drvdata(dev); 2046 2047 mutex_lock(&ctx->lock); 2048 2049 anx7625_power_on_init(ctx); 2050 anx7625_hpd_polling(ctx); 2051 2052 mutex_unlock(&ctx->lock); 2053 2054 return 0; 2055 } 2056 2057 static int __maybe_unused anx7625_resume(struct device *dev) 2058 { 2059 struct anx7625_data *ctx = dev_get_drvdata(dev); 2060 2061 if (!ctx->pdata.intp_irq) 2062 return 0; 2063 2064 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2065 enable_irq(ctx->pdata.intp_irq); 2066 anx7625_runtime_pm_resume(dev); 2067 } 2068 2069 return 0; 2070 } 2071 2072 static int __maybe_unused anx7625_suspend(struct device *dev) 2073 { 2074 struct anx7625_data *ctx = dev_get_drvdata(dev); 2075 2076 if (!ctx->pdata.intp_irq) 2077 return 0; 2078 2079 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2080 anx7625_runtime_pm_suspend(dev); 2081 disable_irq(ctx->pdata.intp_irq); 2082 } 2083 2084 return 0; 2085 } 2086 2087 static const struct dev_pm_ops anx7625_pm_ops = { 2088 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 2089 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2090 anx7625_runtime_pm_resume, NULL) 2091 }; 2092 2093 static int anx7625_i2c_probe(struct i2c_client *client, 2094 const struct i2c_device_id *id) 2095 { 2096 struct anx7625_data *platform; 2097 struct anx7625_platform_data *pdata; 2098 int ret = 0; 2099 struct device *dev = &client->dev; 2100 2101 if (!i2c_check_functionality(client->adapter, 2102 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2103 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2104 return -ENODEV; 2105 } 2106 2107 platform = kzalloc(sizeof(*platform), GFP_KERNEL); 2108 if (!platform) { 2109 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2110 return -ENOMEM; 2111 } 2112 2113 pdata = &platform->pdata; 2114 2115 ret = anx7625_parse_dt(dev, pdata); 2116 if (ret) { 2117 if (ret != -EPROBE_DEFER) 2118 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2119 goto free_platform; 2120 } 2121 2122 platform->client = client; 2123 i2c_set_clientdata(client, platform); 2124 2125 pdata->supplies[0].supply = "vdd10"; 2126 pdata->supplies[1].supply = "vdd18"; 2127 pdata->supplies[2].supply = "vdd33"; 2128 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2129 pdata->supplies); 2130 if (ret) { 2131 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2132 return ret; 2133 } 2134 anx7625_init_gpio(platform); 2135 2136 mutex_init(&platform->lock); 2137 2138 platform->pdata.intp_irq = client->irq; 2139 if (platform->pdata.intp_irq) { 2140 INIT_WORK(&platform->work, anx7625_work_func); 2141 platform->workqueue = alloc_workqueue("anx7625_work", 2142 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2143 if (!platform->workqueue) { 2144 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2145 ret = -ENOMEM; 2146 goto free_platform; 2147 } 2148 2149 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2150 NULL, anx7625_intr_hpd_isr, 2151 IRQF_TRIGGER_FALLING | 2152 IRQF_ONESHOT, 2153 "anx7625-intp", platform); 2154 if (ret) { 2155 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2156 goto free_wq; 2157 } 2158 } 2159 2160 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2161 ret = -ENOMEM; 2162 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2163 goto free_wq; 2164 } 2165 2166 pm_runtime_enable(dev); 2167 2168 if (!platform->pdata.low_power_mode) { 2169 anx7625_disable_pd_protocol(platform); 2170 pm_runtime_get_sync(dev); 2171 } 2172 2173 /* Add work function */ 2174 if (platform->pdata.intp_irq) 2175 queue_work(platform->workqueue, &platform->work); 2176 2177 platform->bridge.funcs = &anx7625_bridge_funcs; 2178 platform->bridge.of_node = client->dev.of_node; 2179 platform->bridge.ops = DRM_BRIDGE_OP_EDID; 2180 if (!platform->pdata.panel_bridge) 2181 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2182 DRM_BRIDGE_OP_DETECT; 2183 platform->bridge.type = platform->pdata.panel_bridge ? 2184 DRM_MODE_CONNECTOR_eDP : 2185 DRM_MODE_CONNECTOR_DisplayPort; 2186 2187 drm_bridge_add(&platform->bridge); 2188 2189 if (!platform->pdata.is_dpi) { 2190 ret = anx7625_attach_dsi(platform); 2191 if (ret) { 2192 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 2193 goto unregister_bridge; 2194 } 2195 } 2196 2197 if (platform->pdata.audio_en) 2198 anx7625_register_audio(dev, platform); 2199 2200 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2201 2202 return 0; 2203 2204 unregister_bridge: 2205 drm_bridge_remove(&platform->bridge); 2206 2207 if (!platform->pdata.low_power_mode) 2208 pm_runtime_put_sync_suspend(&client->dev); 2209 2210 anx7625_unregister_i2c_dummy_clients(platform); 2211 2212 free_wq: 2213 if (platform->workqueue) 2214 destroy_workqueue(platform->workqueue); 2215 2216 free_platform: 2217 kfree(platform); 2218 2219 return ret; 2220 } 2221 2222 static int anx7625_i2c_remove(struct i2c_client *client) 2223 { 2224 struct anx7625_data *platform = i2c_get_clientdata(client); 2225 2226 drm_bridge_remove(&platform->bridge); 2227 2228 if (platform->pdata.intp_irq) 2229 destroy_workqueue(platform->workqueue); 2230 2231 if (!platform->pdata.low_power_mode) 2232 pm_runtime_put_sync_suspend(&client->dev); 2233 2234 anx7625_unregister_i2c_dummy_clients(platform); 2235 2236 if (platform->pdata.audio_en) 2237 anx7625_unregister_audio(platform); 2238 2239 kfree(platform); 2240 return 0; 2241 } 2242 2243 static const struct i2c_device_id anx7625_id[] = { 2244 {"anx7625", 0}, 2245 {} 2246 }; 2247 2248 MODULE_DEVICE_TABLE(i2c, anx7625_id); 2249 2250 static const struct of_device_id anx_match_table[] = { 2251 {.compatible = "analogix,anx7625",}, 2252 {}, 2253 }; 2254 MODULE_DEVICE_TABLE(of, anx_match_table); 2255 2256 static struct i2c_driver anx7625_driver = { 2257 .driver = { 2258 .name = "anx7625", 2259 .of_match_table = anx_match_table, 2260 .pm = &anx7625_pm_ops, 2261 }, 2262 .probe = anx7625_i2c_probe, 2263 .remove = anx7625_i2c_remove, 2264 2265 .id_table = anx7625_id, 2266 }; 2267 2268 module_i2c_driver(anx7625_driver); 2269 2270 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 2271 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 2272 MODULE_LICENSE("GPL v2"); 2273 MODULE_VERSION(ANX7625_DRV_VERSION); 2274