1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/display/drm_dp_aux_bus.h> 25 #include <drm/display/drm_dp_helper.h> 26 #include <drm/display/drm_hdcp_helper.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_bridge.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_mipi_dsi.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_panel.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_probe_helper.h> 35 36 #include <media/v4l2-fwnode.h> 37 #include <sound/hdmi-codec.h> 38 #include <video/display_timing.h> 39 40 #include "anx7625.h" 41 42 /* 43 * There is a sync issue while access I2C register between AP(CPU) and 44 * internal firmware(OCM), to avoid the race condition, AP should access 45 * the reserved slave address before slave address occurs changes. 46 */ 47 static int i2c_access_workaround(struct anx7625_data *ctx, 48 struct i2c_client *client) 49 { 50 u8 offset; 51 struct device *dev = &client->dev; 52 int ret; 53 54 if (client == ctx->last_client) 55 return 0; 56 57 ctx->last_client = client; 58 59 if (client == ctx->i2c.tcpc_client) 60 offset = RSVD_00_ADDR; 61 else if (client == ctx->i2c.tx_p0_client) 62 offset = RSVD_D1_ADDR; 63 else if (client == ctx->i2c.tx_p1_client) 64 offset = RSVD_60_ADDR; 65 else if (client == ctx->i2c.rx_p0_client) 66 offset = RSVD_39_ADDR; 67 else if (client == ctx->i2c.rx_p1_client) 68 offset = RSVD_7F_ADDR; 69 else 70 offset = RSVD_00_ADDR; 71 72 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 73 if (ret < 0) 74 DRM_DEV_ERROR(dev, 75 "fail to access i2c id=%x\n:%x", 76 client->addr, offset); 77 78 return ret; 79 } 80 81 static int anx7625_reg_read(struct anx7625_data *ctx, 82 struct i2c_client *client, u8 reg_addr) 83 { 84 int ret; 85 struct device *dev = &client->dev; 86 87 i2c_access_workaround(ctx, client); 88 89 ret = i2c_smbus_read_byte_data(client, reg_addr); 90 if (ret < 0) 91 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 92 client->addr, reg_addr); 93 94 return ret; 95 } 96 97 static int anx7625_reg_block_read(struct anx7625_data *ctx, 98 struct i2c_client *client, 99 u8 reg_addr, u8 len, u8 *buf) 100 { 101 int ret; 102 struct device *dev = &client->dev; 103 104 i2c_access_workaround(ctx, client); 105 106 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 107 if (ret < 0) 108 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 109 client->addr, reg_addr); 110 111 return ret; 112 } 113 114 static int anx7625_reg_write(struct anx7625_data *ctx, 115 struct i2c_client *client, 116 u8 reg_addr, u8 reg_val) 117 { 118 int ret; 119 struct device *dev = &client->dev; 120 121 i2c_access_workaround(ctx, client); 122 123 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 124 125 if (ret < 0) 126 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 127 client->addr, reg_addr); 128 129 return ret; 130 } 131 132 static int anx7625_reg_block_write(struct anx7625_data *ctx, 133 struct i2c_client *client, 134 u8 reg_addr, u8 len, u8 *buf) 135 { 136 int ret; 137 struct device *dev = &client->dev; 138 139 i2c_access_workaround(ctx, client); 140 141 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 142 if (ret < 0) 143 dev_err(dev, "write i2c block failed id=%x\n:%x", 144 client->addr, reg_addr); 145 146 return ret; 147 } 148 149 static int anx7625_write_or(struct anx7625_data *ctx, 150 struct i2c_client *client, 151 u8 offset, u8 mask) 152 { 153 int val; 154 155 val = anx7625_reg_read(ctx, client, offset); 156 if (val < 0) 157 return val; 158 159 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 160 } 161 162 static int anx7625_write_and(struct anx7625_data *ctx, 163 struct i2c_client *client, 164 u8 offset, u8 mask) 165 { 166 int val; 167 168 val = anx7625_reg_read(ctx, client, offset); 169 if (val < 0) 170 return val; 171 172 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 173 } 174 175 static int anx7625_write_and_or(struct anx7625_data *ctx, 176 struct i2c_client *client, 177 u8 offset, u8 and_mask, u8 or_mask) 178 { 179 int val; 180 181 val = anx7625_reg_read(ctx, client, offset); 182 if (val < 0) 183 return val; 184 185 return anx7625_reg_write(ctx, client, 186 offset, (val & and_mask) | (or_mask)); 187 } 188 189 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 190 { 191 int i, ret; 192 193 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 194 AUDIO_CONTROL_REGISTER, 0x80); 195 for (i = 0; i < 13; i++) 196 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 197 VIDEO_BIT_MATRIX_12 + i, 198 0x18 + i); 199 200 return ret; 201 } 202 203 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 204 { 205 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 206 } 207 208 static int wait_aux_op_finish(struct anx7625_data *ctx) 209 { 210 struct device *dev = &ctx->client->dev; 211 int val; 212 int ret; 213 214 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 215 ctx, val, 216 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 217 2000, 218 2000 * 150); 219 if (ret) { 220 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 221 return -EIO; 222 } 223 224 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 225 AP_AUX_CTRL_STATUS); 226 if (val < 0 || (val & 0x0F)) { 227 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 228 return -EIO; 229 } 230 231 return 0; 232 } 233 234 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 235 u8 len, u8 *buf) 236 { 237 struct device *dev = &ctx->client->dev; 238 int ret; 239 u8 addrh, addrm, addrl; 240 u8 cmd; 241 bool is_write = !(op & DP_AUX_I2C_READ); 242 243 if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 244 dev_err(dev, "exceed aux buffer len.\n"); 245 return -EINVAL; 246 } 247 248 if (!len) 249 return len; 250 251 addrl = address & 0xFF; 252 addrm = (address >> 8) & 0xFF; 253 addrh = (address >> 16) & 0xFF; 254 255 if (!is_write) 256 op &= ~DP_AUX_I2C_MOT; 257 cmd = DPCD_CMD(len, op); 258 259 /* Set command and length */ 260 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 261 AP_AUX_COMMAND, cmd); 262 263 /* Set aux access address */ 264 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 265 AP_AUX_ADDR_7_0, addrl); 266 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 267 AP_AUX_ADDR_15_8, addrm); 268 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 269 AP_AUX_ADDR_19_16, addrh); 270 271 if (is_write) 272 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 273 AP_AUX_BUFF_START, len, buf); 274 /* Enable aux access */ 275 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 276 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 277 278 if (ret < 0) { 279 dev_err(dev, "cannot access aux related register.\n"); 280 return -EIO; 281 } 282 283 ret = wait_aux_op_finish(ctx); 284 if (ret < 0) { 285 dev_err(dev, "aux IO error: wait aux op finish.\n"); 286 return ret; 287 } 288 289 /* Write done */ 290 if (is_write) 291 return len; 292 293 /* Read done, read out dpcd data */ 294 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 295 AP_AUX_BUFF_START, len, buf); 296 if (ret < 0) { 297 dev_err(dev, "read dpcd register failed\n"); 298 return -EIO; 299 } 300 301 return len; 302 } 303 304 static int anx7625_video_mute_control(struct anx7625_data *ctx, 305 u8 status) 306 { 307 int ret; 308 309 if (status) { 310 /* Set mute on flag */ 311 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 312 AP_AV_STATUS, AP_MIPI_MUTE); 313 /* Clear mipi RX en */ 314 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 315 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 316 } else { 317 /* Mute off flag */ 318 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 319 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 320 /* Set MIPI RX EN */ 321 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 322 AP_AV_STATUS, AP_MIPI_RX_EN); 323 } 324 325 return ret; 326 } 327 328 /* Reduction of fraction a/b */ 329 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 330 { 331 unsigned long gcd_num; 332 unsigned long tmp_a, tmp_b; 333 u32 i = 1; 334 335 gcd_num = gcd(*a, *b); 336 *a /= gcd_num; 337 *b /= gcd_num; 338 339 tmp_a = *a; 340 tmp_b = *b; 341 342 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 343 i++; 344 *a = tmp_a / i; 345 *b = tmp_b / i; 346 } 347 348 /* 349 * In the end, make a, b larger to have higher ODFC PLL 350 * output frequency accuracy 351 */ 352 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 353 *a <<= 1; 354 *b <<= 1; 355 } 356 357 *a >>= 1; 358 *b >>= 1; 359 } 360 361 static int anx7625_calculate_m_n(u32 pixelclock, 362 unsigned long *m, 363 unsigned long *n, 364 u8 *post_divider) 365 { 366 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 367 /* Pixel clock frequency is too high */ 368 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 369 pixelclock, 370 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 371 return -EINVAL; 372 } 373 374 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 375 /* Pixel clock frequency is too low */ 376 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 377 pixelclock, 378 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 379 return -EINVAL; 380 } 381 382 for (*post_divider = 1; 383 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 384 *post_divider += 1; 385 386 if (*post_divider > POST_DIVIDER_MAX) { 387 for (*post_divider = 1; 388 (pixelclock < 389 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 390 *post_divider += 1; 391 392 if (*post_divider > POST_DIVIDER_MAX) { 393 DRM_ERROR("cannot find property post_divider(%d)\n", 394 *post_divider); 395 return -EDOM; 396 } 397 } 398 399 /* Patch to improve the accuracy */ 400 if (*post_divider == 7) { 401 /* 27,000,000 is not divisible by 7 */ 402 *post_divider = 8; 403 } else if (*post_divider == 11) { 404 /* 27,000,000 is not divisible by 11 */ 405 *post_divider = 12; 406 } else if ((*post_divider == 13) || (*post_divider == 14)) { 407 /* 27,000,000 is not divisible by 13 or 14 */ 408 *post_divider = 15; 409 } 410 411 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 412 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 413 pixelclock * (*post_divider), 414 PLL_OUT_FREQ_ABS_MAX); 415 return -EDOM; 416 } 417 418 *m = pixelclock; 419 *n = XTAL_FRQ / (*post_divider); 420 421 anx7625_reduction_of_a_fraction(m, n); 422 423 return 0; 424 } 425 426 static int anx7625_odfc_config(struct anx7625_data *ctx, 427 u8 post_divider) 428 { 429 int ret; 430 struct device *dev = &ctx->client->dev; 431 432 /* Config input reference clock frequency 27MHz/19.2MHz */ 433 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 434 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 435 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 436 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 437 /* Post divider */ 438 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 439 MIPI_DIGITAL_PLL_8, 0x0f); 440 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 441 post_divider << 4); 442 443 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 444 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 445 ~MIPI_PLL_VCO_TUNE_REG_VAL); 446 447 /* Reset ODFC PLL */ 448 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 449 ~MIPI_PLL_RESET_N); 450 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 451 MIPI_PLL_RESET_N); 452 453 if (ret < 0) 454 DRM_DEV_ERROR(dev, "IO error.\n"); 455 456 return ret; 457 } 458 459 /* 460 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 461 * anx7625 defined K ratio for matching MIPI input video clock and 462 * DP output video clock. Increase K value can match bigger video data 463 * variation. IVO panel has small variation than DP CTS spec, need 464 * decrease the K value. 465 */ 466 static int anx7625_set_k_value(struct anx7625_data *ctx) 467 { 468 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 469 470 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 471 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 472 MIPI_DIGITAL_ADJ_1, 0x3B); 473 474 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 475 MIPI_DIGITAL_ADJ_1, 0x3D); 476 } 477 478 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 479 { 480 struct device *dev = &ctx->client->dev; 481 unsigned long m, n; 482 u16 htotal; 483 int ret; 484 u8 post_divider = 0; 485 486 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 487 &m, &n, &post_divider); 488 489 if (ret) { 490 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 491 return ret; 492 } 493 494 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 495 m, n, post_divider); 496 497 /* Configure pixel clock */ 498 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 499 (ctx->dt.pixelclock.min / 1000) & 0xFF); 500 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 501 (ctx->dt.pixelclock.min / 1000) >> 8); 502 /* Lane count */ 503 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 504 MIPI_LANE_CTRL_0, 0xfc); 505 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 506 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 507 508 /* Htotal */ 509 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 510 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 511 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 512 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 513 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 514 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 515 /* Hactive */ 516 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 517 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 518 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 519 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 520 /* HFP */ 521 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 522 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 523 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 524 HORIZONTAL_FRONT_PORCH_H, 525 ctx->dt.hfront_porch.min >> 8); 526 /* HWS */ 527 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 528 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 529 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 530 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 531 /* HBP */ 532 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 533 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 534 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 535 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 536 /* Vactive */ 537 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 538 ctx->dt.vactive.min); 539 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 540 ctx->dt.vactive.min >> 8); 541 /* VFP */ 542 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 543 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 544 /* VWS */ 545 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 546 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 547 /* VBP */ 548 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 549 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 550 /* M value */ 551 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 552 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 553 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 554 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 555 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 556 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 557 /* N value */ 558 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 559 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 560 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 561 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 562 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 563 (n & 0xff)); 564 565 anx7625_set_k_value(ctx); 566 567 ret |= anx7625_odfc_config(ctx, post_divider - 1); 568 569 if (ret < 0) 570 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 571 572 return ret; 573 } 574 575 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 576 { 577 int val; 578 struct device *dev = &ctx->client->dev; 579 580 /* Swap MIPI-DSI data lane 3 P and N */ 581 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 582 if (val < 0) { 583 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 584 return -EIO; 585 } 586 587 val |= (1 << MIPI_SWAP_CH3); 588 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 589 } 590 591 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 592 593 { 594 int val, ret; 595 struct device *dev = &ctx->client->dev; 596 597 /* Swap MIPI-DSI data lane 3 P and N */ 598 ret = anx7625_swap_dsi_lane3(ctx); 599 if (ret < 0) { 600 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 601 return ret; 602 } 603 604 /* DSI clock settings */ 605 val = (0 << MIPI_HS_PWD_CLK) | 606 (0 << MIPI_HS_RT_CLK) | 607 (0 << MIPI_PD_CLK) | 608 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 609 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 610 (0 << MIPI_CLK_DET_DET_BYPASS) | 611 (0 << MIPI_CLK_MISS_CTRL) | 612 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 613 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 614 MIPI_PHY_CONTROL_3, val); 615 616 /* 617 * Decreased HS prepare timing delay from 160ns to 80ns work with 618 * a) Dragon board 810 series (Qualcomm AP) 619 * b) Moving Pixel DSI source (PG3A pattern generator + 620 * P332 D-PHY Probe) default D-PHY timing 621 * 5ns/step 622 */ 623 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 624 MIPI_TIME_HS_PRPR, 0x10); 625 626 /* Enable DSI mode*/ 627 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 628 SELECT_DSI << MIPI_DPI_SELECT); 629 630 ret |= anx7625_dsi_video_timing_config(ctx); 631 if (ret < 0) { 632 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 633 return ret; 634 } 635 636 /* Toggle m, n ready */ 637 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 638 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 639 usleep_range(1000, 1100); 640 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 641 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 642 643 /* Configure integer stable register */ 644 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 645 MIPI_VIDEO_STABLE_CNT, 0x02); 646 /* Power on MIPI RX */ 647 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 648 MIPI_LANE_CTRL_10, 0x00); 649 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 650 MIPI_LANE_CTRL_10, 0x80); 651 652 if (ret < 0) 653 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 654 655 return ret; 656 } 657 658 static int anx7625_dsi_config(struct anx7625_data *ctx) 659 { 660 struct device *dev = &ctx->client->dev; 661 int ret; 662 663 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 664 665 /* DSC disable */ 666 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 667 R_DSC_CTRL_0, ~DSC_EN); 668 669 ret |= anx7625_api_dsi_config(ctx); 670 671 if (ret < 0) { 672 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 673 return ret; 674 } 675 676 /* Set MIPI RX EN */ 677 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 678 AP_AV_STATUS, AP_MIPI_RX_EN); 679 /* Clear mute flag */ 680 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 681 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 682 if (ret < 0) 683 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 684 else 685 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 686 687 return ret; 688 } 689 690 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 691 { 692 struct device *dev = &ctx->client->dev; 693 u16 freq = ctx->dt.pixelclock.min / 1000; 694 int ret; 695 696 /* configure pixel clock */ 697 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 698 PIXEL_CLOCK_L, freq & 0xFF); 699 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 700 PIXEL_CLOCK_H, (freq >> 8)); 701 702 /* set DPI mode */ 703 /* set to DPI PLL module sel */ 704 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 705 MIPI_DIGITAL_PLL_9, 0x20); 706 /* power down MIPI */ 707 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 708 MIPI_LANE_CTRL_10, 0x08); 709 /* enable DPI mode */ 710 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 711 MIPI_DIGITAL_PLL_18, 0x1C); 712 /* set first edge */ 713 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 714 VIDEO_CONTROL_0, 0x06); 715 if (ret < 0) 716 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 717 718 return ret; 719 } 720 721 static int anx7625_dpi_config(struct anx7625_data *ctx) 722 { 723 struct device *dev = &ctx->client->dev; 724 int ret; 725 726 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 727 728 /* DSC disable */ 729 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 730 R_DSC_CTRL_0, ~DSC_EN); 731 if (ret < 0) { 732 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 733 return ret; 734 } 735 736 ret = anx7625_config_bit_matrix(ctx); 737 if (ret < 0) { 738 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 739 return ret; 740 } 741 742 ret = anx7625_api_dpi_config(ctx); 743 if (ret < 0) { 744 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 745 return ret; 746 } 747 748 /* set MIPI RX EN */ 749 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 750 AP_AV_STATUS, AP_MIPI_RX_EN); 751 /* clear mute flag */ 752 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 753 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 754 if (ret < 0) 755 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 756 757 return ret; 758 } 759 760 static int anx7625_read_flash_status(struct anx7625_data *ctx) 761 { 762 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 763 } 764 765 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 766 { 767 int ret, val; 768 struct device *dev = &ctx->client->dev; 769 u8 ident[FLASH_BUF_LEN]; 770 771 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 772 FLASH_ADDR_HIGH, 0x91); 773 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 774 FLASH_ADDR_LOW, 0xA0); 775 if (ret < 0) { 776 dev_err(dev, "IO error : set key flash address.\n"); 777 return ret; 778 } 779 780 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 781 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 782 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 783 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 784 if (ret < 0) { 785 dev_err(dev, "IO error : set key flash len.\n"); 786 return ret; 787 } 788 789 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 790 R_FLASH_RW_CTRL, FLASH_READ); 791 ret |= readx_poll_timeout(anx7625_read_flash_status, 792 ctx, val, 793 ((val & FLASH_DONE) || (val < 0)), 794 2000, 795 2000 * 150); 796 if (ret) { 797 dev_err(dev, "flash read access fail!\n"); 798 return -EIO; 799 } 800 801 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 802 FLASH_BUF_BASE_ADDR, 803 FLASH_BUF_LEN, ident); 804 if (ret < 0) { 805 dev_err(dev, "read flash data fail!\n"); 806 return -EIO; 807 } 808 809 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 810 return -EINVAL; 811 812 return 0; 813 } 814 815 static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 816 { 817 int ret; 818 struct device *dev = &ctx->client->dev; 819 820 /* Select HDCP 1.4 KEY */ 821 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 822 R_BOOT_RETRY, 0x12); 823 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 824 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 825 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 826 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 827 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 828 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 829 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 830 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 831 832 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 833 R_RAM_ADDR_H, 0); 834 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 835 R_RAM_ADDR_L, 0); 836 /* Enable HDCP 1.4 KEY load */ 837 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 838 R_RAM_CTRL, DECRYPT_EN | LOAD_START); 839 dev_dbg(dev, "load HDCP 1.4 key done\n"); 840 return ret; 841 } 842 843 static int anx7625_hdcp_disable(struct anx7625_data *ctx) 844 { 845 int ret; 846 struct device *dev = &ctx->client->dev; 847 848 dev_dbg(dev, "disable HDCP 1.4\n"); 849 850 /* Disable HDCP */ 851 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 852 /* Try auth flag */ 853 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 854 /* Interrupt for DRM */ 855 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 856 if (ret < 0) 857 dev_err(dev, "fail to disable HDCP\n"); 858 859 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 860 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 861 } 862 863 static int anx7625_hdcp_enable(struct anx7625_data *ctx) 864 { 865 u8 bcap; 866 int ret; 867 struct device *dev = &ctx->client->dev; 868 869 ret = anx7625_hdcp_key_probe(ctx); 870 if (ret) { 871 dev_dbg(dev, "no key found, not to do hdcp\n"); 872 return ret; 873 } 874 875 /* Read downstream capability */ 876 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap); 877 if (ret < 0) 878 return ret; 879 880 if (!(bcap & 0x01)) { 881 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 882 return 0; 883 } 884 885 dev_dbg(dev, "enable HDCP 1.4\n"); 886 887 /* First clear HDCP state */ 888 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 889 TX_HDCP_CTRL0, 890 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 891 usleep_range(1000, 1100); 892 /* Second clear HDCP state */ 893 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 894 TX_HDCP_CTRL0, 895 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 896 897 /* Set time for waiting KSVR */ 898 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 899 SP_TX_WAIT_KSVR_TIME, 0xc8); 900 /* Set time for waiting R0 */ 901 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 902 SP_TX_WAIT_R0_TIME, 0xb0); 903 ret |= anx7625_hdcp_key_load(ctx); 904 if (ret) { 905 pr_warn("prepare HDCP key failed.\n"); 906 return ret; 907 } 908 909 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 910 911 /* Try auth flag */ 912 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 913 /* Interrupt for DRM */ 914 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 915 if (ret < 0) 916 dev_err(dev, "fail to enable HDCP\n"); 917 918 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 919 TX_HDCP_CTRL0, HARD_AUTH_EN); 920 } 921 922 static void anx7625_dp_start(struct anx7625_data *ctx) 923 { 924 int ret; 925 struct device *dev = &ctx->client->dev; 926 u8 data; 927 928 if (!ctx->display_timing_valid) { 929 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 930 return; 931 } 932 933 dev_dbg(dev, "set downstream sink into normal\n"); 934 /* Downstream sink enter into normal mode */ 935 data = 1; 936 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data); 937 if (ret < 0) 938 dev_err(dev, "IO error : set sink into normal mode fail\n"); 939 940 /* Disable HDCP */ 941 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 942 943 if (ctx->pdata.is_dpi) 944 ret = anx7625_dpi_config(ctx); 945 else 946 ret = anx7625_dsi_config(ctx); 947 948 if (ret < 0) 949 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 950 951 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 952 953 ctx->dp_en = 1; 954 } 955 956 static void anx7625_dp_stop(struct anx7625_data *ctx) 957 { 958 struct device *dev = &ctx->client->dev; 959 int ret; 960 u8 data; 961 962 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 963 964 /* 965 * Video disable: 0x72:08 bit 7 = 0; 966 * Audio disable: 0x70:87 bit 0 = 0; 967 */ 968 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 969 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 970 971 ret |= anx7625_video_mute_control(ctx, 1); 972 973 dev_dbg(dev, "notify downstream enter into standby\n"); 974 /* Downstream monitor enter into standby mode */ 975 data = 2; 976 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data); 977 if (ret < 0) 978 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 979 980 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 981 982 ctx->dp_en = 0; 983 } 984 985 static int sp_tx_rst_aux(struct anx7625_data *ctx) 986 { 987 int ret; 988 989 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 990 AUX_RST); 991 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 992 ~AUX_RST); 993 return ret; 994 } 995 996 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 997 { 998 int ret; 999 1000 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1001 AP_AUX_BUFF_START, offset); 1002 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1003 AP_AUX_COMMAND, 0x04); 1004 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1005 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1006 return (ret | wait_aux_op_finish(ctx)); 1007 } 1008 1009 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 1010 { 1011 int ret; 1012 1013 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1014 AP_AUX_COMMAND, len_cmd); 1015 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1016 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1017 return (ret | wait_aux_op_finish(ctx)); 1018 } 1019 1020 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 1021 { 1022 int c = 0; 1023 struct device *dev = &ctx->client->dev; 1024 1025 sp_tx_aux_wr(ctx, 0x7e); 1026 sp_tx_aux_rd(ctx, 0x01); 1027 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 1028 if (c < 0) { 1029 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 1030 return -EIO; 1031 } 1032 1033 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 1034 1035 if (c > MAX_EDID_BLOCK) 1036 c = 1; 1037 1038 return c; 1039 } 1040 1041 static int edid_read(struct anx7625_data *ctx, 1042 u8 offset, u8 *pblock_buf) 1043 { 1044 int ret, cnt; 1045 struct device *dev = &ctx->client->dev; 1046 1047 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1048 sp_tx_aux_wr(ctx, offset); 1049 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1050 ret = sp_tx_aux_rd(ctx, 0xf1); 1051 1052 if (ret) { 1053 ret = sp_tx_rst_aux(ctx); 1054 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 1055 } else { 1056 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1057 AP_AUX_BUFF_START, 1058 MAX_DPCD_BUFFER_SIZE, 1059 pblock_buf); 1060 if (ret > 0) 1061 break; 1062 } 1063 } 1064 1065 if (cnt > EDID_TRY_CNT) 1066 return -EIO; 1067 1068 return ret; 1069 } 1070 1071 static int segments_edid_read(struct anx7625_data *ctx, 1072 u8 segment, u8 *buf, u8 offset) 1073 { 1074 u8 cnt; 1075 int ret; 1076 struct device *dev = &ctx->client->dev; 1077 1078 /* Write address only */ 1079 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1080 AP_AUX_ADDR_7_0, 0x30); 1081 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1082 AP_AUX_COMMAND, 0x04); 1083 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1084 AP_AUX_CTRL_STATUS, 1085 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 1086 1087 ret |= wait_aux_op_finish(ctx); 1088 /* Write segment address */ 1089 ret |= sp_tx_aux_wr(ctx, segment); 1090 /* Data read */ 1091 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1092 AP_AUX_ADDR_7_0, 0x50); 1093 if (ret) { 1094 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 1095 return ret; 1096 } 1097 1098 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1099 sp_tx_aux_wr(ctx, offset); 1100 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1101 ret = sp_tx_aux_rd(ctx, 0xf1); 1102 1103 if (ret) { 1104 ret = sp_tx_rst_aux(ctx); 1105 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 1106 } else { 1107 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1108 AP_AUX_BUFF_START, 1109 MAX_DPCD_BUFFER_SIZE, buf); 1110 if (ret > 0) 1111 break; 1112 } 1113 } 1114 1115 if (cnt > EDID_TRY_CNT) 1116 return -EIO; 1117 1118 return ret; 1119 } 1120 1121 static int sp_tx_edid_read(struct anx7625_data *ctx, 1122 u8 *pedid_blocks_buf) 1123 { 1124 u8 offset; 1125 int edid_pos; 1126 int count, blocks_num; 1127 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 1128 u8 i, j; 1129 int g_edid_break = 0; 1130 int ret; 1131 struct device *dev = &ctx->client->dev; 1132 1133 /* Address initial */ 1134 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1135 AP_AUX_ADDR_7_0, 0x50); 1136 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1137 AP_AUX_ADDR_15_8, 0); 1138 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 1139 AP_AUX_ADDR_19_16, 0xf0); 1140 if (ret < 0) { 1141 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 1142 return -EIO; 1143 } 1144 1145 blocks_num = sp_tx_get_edid_block(ctx); 1146 if (blocks_num < 0) 1147 return blocks_num; 1148 1149 count = 0; 1150 1151 do { 1152 switch (count) { 1153 case 0: 1154 case 1: 1155 for (i = 0; i < 8; i++) { 1156 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 1157 g_edid_break = edid_read(ctx, offset, 1158 pblock_buf); 1159 1160 if (g_edid_break < 0) 1161 break; 1162 1163 memcpy(&pedid_blocks_buf[offset], 1164 pblock_buf, 1165 MAX_DPCD_BUFFER_SIZE); 1166 } 1167 1168 break; 1169 case 2: 1170 offset = 0x00; 1171 1172 for (j = 0; j < 8; j++) { 1173 edid_pos = (j + count * 8) * 1174 MAX_DPCD_BUFFER_SIZE; 1175 1176 if (g_edid_break == 1) 1177 break; 1178 1179 ret = segments_edid_read(ctx, count / 2, 1180 pblock_buf, offset); 1181 if (ret < 0) 1182 return ret; 1183 1184 memcpy(&pedid_blocks_buf[edid_pos], 1185 pblock_buf, 1186 MAX_DPCD_BUFFER_SIZE); 1187 offset = offset + 0x10; 1188 } 1189 1190 break; 1191 case 3: 1192 offset = 0x80; 1193 1194 for (j = 0; j < 8; j++) { 1195 edid_pos = (j + count * 8) * 1196 MAX_DPCD_BUFFER_SIZE; 1197 if (g_edid_break == 1) 1198 break; 1199 1200 ret = segments_edid_read(ctx, count / 2, 1201 pblock_buf, offset); 1202 if (ret < 0) 1203 return ret; 1204 1205 memcpy(&pedid_blocks_buf[edid_pos], 1206 pblock_buf, 1207 MAX_DPCD_BUFFER_SIZE); 1208 offset = offset + 0x10; 1209 } 1210 1211 break; 1212 default: 1213 break; 1214 } 1215 1216 count++; 1217 1218 } while (blocks_num >= count); 1219 1220 /* Check edid data */ 1221 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 1222 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 1223 return -EINVAL; 1224 } 1225 1226 /* Reset aux channel */ 1227 ret = sp_tx_rst_aux(ctx); 1228 if (ret < 0) { 1229 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 1230 return ret; 1231 } 1232 1233 return (blocks_num + 1); 1234 } 1235 1236 static void anx7625_power_on(struct anx7625_data *ctx) 1237 { 1238 struct device *dev = &ctx->client->dev; 1239 int ret, i; 1240 1241 if (!ctx->pdata.low_power_mode) { 1242 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1243 return; 1244 } 1245 1246 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 1247 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 1248 if (ret < 0) { 1249 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 1250 i, ret); 1251 goto reg_err; 1252 } 1253 usleep_range(2000, 2100); 1254 } 1255 1256 usleep_range(11000, 12000); 1257 1258 /* Power on pin enable */ 1259 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 1260 usleep_range(10000, 11000); 1261 /* Power reset pin enable */ 1262 gpiod_set_value(ctx->pdata.gpio_reset, 1); 1263 usleep_range(10000, 11000); 1264 1265 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 1266 return; 1267 reg_err: 1268 for (--i; i >= 0; i--) 1269 regulator_disable(ctx->pdata.supplies[i].consumer); 1270 } 1271 1272 static void anx7625_power_standby(struct anx7625_data *ctx) 1273 { 1274 struct device *dev = &ctx->client->dev; 1275 int ret; 1276 1277 if (!ctx->pdata.low_power_mode) { 1278 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1279 return; 1280 } 1281 1282 gpiod_set_value(ctx->pdata.gpio_reset, 0); 1283 usleep_range(1000, 1100); 1284 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 1285 usleep_range(1000, 1100); 1286 1287 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1288 ctx->pdata.supplies); 1289 if (ret < 0) 1290 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1291 1292 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1293 } 1294 1295 /* Basic configurations of ANX7625 */ 1296 static void anx7625_config(struct anx7625_data *ctx) 1297 { 1298 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1299 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1300 } 1301 1302 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1303 { 1304 struct device *dev = &ctx->client->dev; 1305 int ret; 1306 1307 /* Reset main ocm */ 1308 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1309 /* Disable PD */ 1310 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1311 AP_AV_STATUS, AP_DISABLE_PD); 1312 /* Release main ocm */ 1313 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1314 1315 if (ret < 0) 1316 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1317 else 1318 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1319 } 1320 1321 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1322 { 1323 int ret; 1324 struct device *dev = &ctx->client->dev; 1325 1326 /* Check interface workable */ 1327 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1328 FLASH_LOAD_STA); 1329 if (ret < 0) { 1330 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1331 return ret; 1332 } 1333 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1334 return -ENODEV; 1335 1336 anx7625_disable_pd_protocol(ctx); 1337 1338 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1339 anx7625_reg_read(ctx, 1340 ctx->i2c.rx_p0_client, 1341 OCM_FW_VERSION), 1342 anx7625_reg_read(ctx, 1343 ctx->i2c.rx_p0_client, 1344 OCM_FW_REVERSION)); 1345 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1346 ANX7625_DRV_VERSION); 1347 1348 return 0; 1349 } 1350 1351 static void anx7625_power_on_init(struct anx7625_data *ctx) 1352 { 1353 int retry_count, i; 1354 1355 for (retry_count = 0; retry_count < 3; retry_count++) { 1356 anx7625_power_on(ctx); 1357 anx7625_config(ctx); 1358 1359 for (i = 0; i < OCM_LOADING_TIME; i++) { 1360 if (!anx7625_ocm_loading_check(ctx)) 1361 return; 1362 usleep_range(1000, 1100); 1363 } 1364 anx7625_power_standby(ctx); 1365 } 1366 } 1367 1368 static void anx7625_init_gpio(struct anx7625_data *platform) 1369 { 1370 struct device *dev = &platform->client->dev; 1371 1372 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1373 1374 /* Gpio for chip power enable */ 1375 platform->pdata.gpio_p_on = 1376 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1377 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 1378 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 1379 platform->pdata.gpio_p_on = NULL; 1380 } 1381 1382 /* Gpio for chip reset */ 1383 platform->pdata.gpio_reset = 1384 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1385 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 1386 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 1387 platform->pdata.gpio_reset = NULL; 1388 } 1389 1390 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1391 platform->pdata.low_power_mode = 1; 1392 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1393 desc_to_gpio(platform->pdata.gpio_p_on), 1394 desc_to_gpio(platform->pdata.gpio_reset)); 1395 } else { 1396 platform->pdata.low_power_mode = 0; 1397 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1398 } 1399 } 1400 1401 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1402 { 1403 ctx->hpd_status = 0; 1404 ctx->hpd_high_cnt = 0; 1405 } 1406 1407 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1408 { 1409 int ret; 1410 struct device *dev = &ctx->client->dev; 1411 1412 if (ctx->hpd_high_cnt >= 2) { 1413 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1414 return; 1415 } 1416 1417 ctx->hpd_status = 1; 1418 ctx->hpd_high_cnt++; 1419 1420 /* Not support HDCP */ 1421 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1422 1423 /* Try auth flag */ 1424 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1425 /* Interrupt for DRM */ 1426 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1427 if (ret < 0) { 1428 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1429 return; 1430 } 1431 1432 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1433 if (ret < 0) 1434 return; 1435 1436 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1437 } 1438 1439 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1440 { 1441 int ret; 1442 1443 /* Set irq detect window to 2ms */ 1444 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1445 HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF); 1446 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1447 HPD_DET_TIMER_BIT8_15, 1448 (HPD_TIME >> 8) & 0xFF); 1449 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1450 HPD_DET_TIMER_BIT16_23, 1451 (HPD_TIME >> 16) & 0xFF); 1452 if (ret < 0) 1453 return ret; 1454 1455 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1456 } 1457 1458 static int _anx7625_hpd_polling(struct anx7625_data *ctx, 1459 unsigned long wait_us) 1460 { 1461 int ret, val; 1462 struct device *dev = &ctx->client->dev; 1463 1464 /* Interrupt mode, no need poll HPD status, just return */ 1465 if (ctx->pdata.intp_irq) 1466 return 0; 1467 1468 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1469 ctx, val, 1470 ((val & HPD_STATUS) || (val < 0)), 1471 wait_us / 100, 1472 wait_us); 1473 if (ret) { 1474 DRM_DEV_ERROR(dev, "no hpd.\n"); 1475 return ret; 1476 } 1477 1478 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1479 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1480 INTR_ALERT_1, 0xFF); 1481 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1482 INTERFACE_CHANGE_INT, 0); 1483 1484 anx7625_start_dp_work(ctx); 1485 1486 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1487 drm_helper_hpd_irq_event(ctx->bridge.dev); 1488 1489 return 0; 1490 } 1491 1492 static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux, 1493 unsigned long wait_us) 1494 { 1495 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1496 struct device *dev = &ctx->client->dev; 1497 int ret; 1498 1499 pm_runtime_get_sync(dev); 1500 ret = _anx7625_hpd_polling(ctx, wait_us); 1501 pm_runtime_mark_last_busy(dev); 1502 pm_runtime_put_autosuspend(dev); 1503 1504 return ret; 1505 } 1506 1507 static void anx7625_remove_edid(struct anx7625_data *ctx) 1508 { 1509 ctx->slimport_edid_p.edid_block_num = -1; 1510 } 1511 1512 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1513 { 1514 int i; 1515 1516 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1517 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1518 DP_TX_LANE0_SWING_REG0 + i, 1519 ctx->pdata.lane0_reg_data[i]); 1520 1521 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1522 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1523 DP_TX_LANE1_SWING_REG0 + i, 1524 ctx->pdata.lane1_reg_data[i]); 1525 } 1526 1527 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1528 { 1529 struct device *dev = &ctx->client->dev; 1530 1531 /* HPD changed */ 1532 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1533 (u32)on); 1534 1535 if (on == 0) { 1536 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1537 anx7625_remove_edid(ctx); 1538 anx7625_stop_dp_work(ctx); 1539 } else { 1540 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1541 anx7625_start_dp_work(ctx); 1542 anx7625_dp_adjust_swing(ctx); 1543 } 1544 } 1545 1546 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1547 { 1548 int intr_vector, status; 1549 struct device *dev = &ctx->client->dev; 1550 1551 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1552 INTR_ALERT_1, 0xFF); 1553 if (status < 0) { 1554 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1555 return status; 1556 } 1557 1558 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1559 INTERFACE_CHANGE_INT); 1560 if (intr_vector < 0) { 1561 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1562 return intr_vector; 1563 } 1564 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1565 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1566 INTERFACE_CHANGE_INT, 1567 intr_vector & (~intr_vector)); 1568 if (status < 0) { 1569 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1570 return status; 1571 } 1572 1573 if (!(intr_vector & HPD_STATUS_CHANGE)) 1574 return -ENOENT; 1575 1576 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1577 SYSTEM_STSTUS); 1578 if (status < 0) { 1579 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1580 return status; 1581 } 1582 1583 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1584 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1585 1586 return 0; 1587 } 1588 1589 static void anx7625_work_func(struct work_struct *work) 1590 { 1591 int event; 1592 struct anx7625_data *ctx = container_of(work, 1593 struct anx7625_data, work); 1594 1595 mutex_lock(&ctx->lock); 1596 1597 if (pm_runtime_suspended(&ctx->client->dev)) 1598 goto unlock; 1599 1600 event = anx7625_hpd_change_detect(ctx); 1601 if (event < 0) 1602 goto unlock; 1603 1604 if (ctx->bridge_attached) 1605 drm_helper_hpd_irq_event(ctx->bridge.dev); 1606 1607 unlock: 1608 mutex_unlock(&ctx->lock); 1609 } 1610 1611 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1612 { 1613 struct anx7625_data *ctx = (struct anx7625_data *)data; 1614 1615 queue_work(ctx->workqueue, &ctx->work); 1616 1617 return IRQ_HANDLED; 1618 } 1619 1620 static int anx7625_get_swing_setting(struct device *dev, 1621 struct anx7625_platform_data *pdata) 1622 { 1623 int num_regs; 1624 1625 if (of_get_property(dev->of_node, 1626 "analogix,lane0-swing", &num_regs)) { 1627 if (num_regs > DP_TX_SWING_REG_CNT) 1628 num_regs = DP_TX_SWING_REG_CNT; 1629 1630 pdata->dp_lane0_swing_reg_cnt = num_regs; 1631 of_property_read_u8_array(dev->of_node, "analogix,lane0-swing", 1632 pdata->lane0_reg_data, num_regs); 1633 } 1634 1635 if (of_get_property(dev->of_node, 1636 "analogix,lane1-swing", &num_regs)) { 1637 if (num_regs > DP_TX_SWING_REG_CNT) 1638 num_regs = DP_TX_SWING_REG_CNT; 1639 1640 pdata->dp_lane1_swing_reg_cnt = num_regs; 1641 of_property_read_u8_array(dev->of_node, "analogix,lane1-swing", 1642 pdata->lane1_reg_data, num_regs); 1643 } 1644 1645 return 0; 1646 } 1647 1648 static int anx7625_parse_dt(struct device *dev, 1649 struct anx7625_platform_data *pdata) 1650 { 1651 struct device_node *np = dev->of_node, *ep0; 1652 int bus_type, mipi_lanes; 1653 1654 anx7625_get_swing_setting(dev, pdata); 1655 1656 pdata->is_dpi = 0; /* default dsi mode */ 1657 of_node_put(pdata->mipi_host_node); 1658 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1659 if (!pdata->mipi_host_node) { 1660 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1661 return -ENODEV; 1662 } 1663 1664 bus_type = 0; 1665 mipi_lanes = MAX_LANES_SUPPORT; 1666 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1667 if (ep0) { 1668 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1669 bus_type = 0; 1670 1671 mipi_lanes = drm_of_get_data_lanes_count(ep0, 1, MAX_LANES_SUPPORT); 1672 of_node_put(ep0); 1673 } 1674 1675 if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */ 1676 pdata->is_dpi = 1; 1677 1678 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1679 if (mipi_lanes > 0) 1680 pdata->mipi_lanes = mipi_lanes; 1681 1682 if (pdata->is_dpi) 1683 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1684 else 1685 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1686 1687 if (of_property_read_bool(np, "analogix,audio-enable")) 1688 pdata->audio_en = 1; 1689 1690 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); 1691 if (IS_ERR(pdata->panel_bridge)) { 1692 if (PTR_ERR(pdata->panel_bridge) == -ENODEV) { 1693 pdata->panel_bridge = NULL; 1694 return 0; 1695 } 1696 1697 return PTR_ERR(pdata->panel_bridge); 1698 } 1699 1700 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1701 1702 return 0; 1703 } 1704 1705 static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1706 { 1707 struct device_node *bus, *panel; 1708 1709 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1710 if (!bus) 1711 return false; 1712 1713 panel = of_get_child_by_name(bus, "panel"); 1714 of_node_put(bus); 1715 if (!panel) 1716 return false; 1717 of_node_put(panel); 1718 1719 return true; 1720 } 1721 1722 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1723 { 1724 return container_of(bridge, struct anx7625_data, bridge); 1725 } 1726 1727 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1728 struct drm_dp_aux_msg *msg) 1729 { 1730 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1731 struct device *dev = &ctx->client->dev; 1732 u8 request = msg->request & ~DP_AUX_I2C_MOT; 1733 int ret = 0; 1734 1735 pm_runtime_get_sync(dev); 1736 msg->reply = 0; 1737 switch (request) { 1738 case DP_AUX_NATIVE_WRITE: 1739 case DP_AUX_I2C_WRITE: 1740 case DP_AUX_NATIVE_READ: 1741 case DP_AUX_I2C_READ: 1742 break; 1743 default: 1744 ret = -EINVAL; 1745 } 1746 if (!ret) 1747 ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1748 msg->size, msg->buffer); 1749 pm_runtime_mark_last_busy(dev); 1750 pm_runtime_put_autosuspend(dev); 1751 1752 return ret; 1753 } 1754 1755 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1756 { 1757 struct device *dev = &ctx->client->dev; 1758 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1759 int edid_num; 1760 u8 *edid; 1761 1762 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1763 if (!edid) { 1764 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1765 return NULL; 1766 } 1767 1768 if (ctx->slimport_edid_p.edid_block_num > 0) { 1769 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1770 FOUR_BLOCK_SIZE); 1771 return (struct edid *)edid; 1772 } 1773 1774 pm_runtime_get_sync(dev); 1775 _anx7625_hpd_polling(ctx, 5000 * 100); 1776 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1777 pm_runtime_put_sync(dev); 1778 1779 if (edid_num < 1) { 1780 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1781 kfree(edid); 1782 return NULL; 1783 } 1784 1785 p_edid->edid_block_num = edid_num; 1786 1787 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1788 return (struct edid *)edid; 1789 } 1790 1791 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1792 { 1793 struct device *dev = &ctx->client->dev; 1794 1795 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1796 1797 if (ctx->pdata.panel_bridge) 1798 return connector_status_connected; 1799 1800 return ctx->hpd_status ? connector_status_connected : 1801 connector_status_disconnected; 1802 } 1803 1804 static int anx7625_audio_hw_params(struct device *dev, void *data, 1805 struct hdmi_codec_daifmt *fmt, 1806 struct hdmi_codec_params *params) 1807 { 1808 struct anx7625_data *ctx = dev_get_drvdata(dev); 1809 int wl, ch, rate; 1810 int ret = 0; 1811 1812 if (anx7625_sink_detect(ctx) == connector_status_disconnected) { 1813 DRM_DEV_DEBUG_DRIVER(dev, "DP not connected\n"); 1814 return 0; 1815 } 1816 1817 if (fmt->fmt != HDMI_DSP_A && fmt->fmt != HDMI_I2S) { 1818 DRM_DEV_ERROR(dev, "only supports DSP_A & I2S\n"); 1819 return -EINVAL; 1820 } 1821 1822 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1823 params->sample_rate, params->sample_width, 1824 params->cea.channels); 1825 1826 if (fmt->fmt == HDMI_DSP_A) 1827 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1828 AUDIO_CHANNEL_STATUS_6, 1829 ~I2S_SLAVE_MODE, 1830 TDM_SLAVE_MODE); 1831 else 1832 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1833 AUDIO_CHANNEL_STATUS_6, 1834 ~TDM_SLAVE_MODE, 1835 I2S_SLAVE_MODE); 1836 1837 /* Word length */ 1838 switch (params->sample_width) { 1839 case 16: 1840 wl = AUDIO_W_LEN_16_20MAX; 1841 break; 1842 case 18: 1843 wl = AUDIO_W_LEN_18_20MAX; 1844 break; 1845 case 20: 1846 wl = AUDIO_W_LEN_20_20MAX; 1847 break; 1848 case 24: 1849 wl = AUDIO_W_LEN_24_24MAX; 1850 break; 1851 default: 1852 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1853 params->sample_width); 1854 return -EINVAL; 1855 } 1856 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1857 AUDIO_CHANNEL_STATUS_5, 1858 0xf0, wl); 1859 1860 /* Channel num */ 1861 switch (params->cea.channels) { 1862 case 2: 1863 ch = I2S_CH_2; 1864 break; 1865 case 4: 1866 ch = TDM_CH_4; 1867 break; 1868 case 6: 1869 ch = TDM_CH_6; 1870 break; 1871 case 8: 1872 ch = TDM_CH_8; 1873 break; 1874 default: 1875 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1876 params->cea.channels); 1877 return -EINVAL; 1878 } 1879 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1880 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1881 if (ch > I2S_CH_2) 1882 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1883 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1884 else 1885 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1886 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1887 1888 /* FS */ 1889 switch (params->sample_rate) { 1890 case 32000: 1891 rate = AUDIO_FS_32K; 1892 break; 1893 case 44100: 1894 rate = AUDIO_FS_441K; 1895 break; 1896 case 48000: 1897 rate = AUDIO_FS_48K; 1898 break; 1899 case 88200: 1900 rate = AUDIO_FS_882K; 1901 break; 1902 case 96000: 1903 rate = AUDIO_FS_96K; 1904 break; 1905 case 176400: 1906 rate = AUDIO_FS_1764K; 1907 break; 1908 case 192000: 1909 rate = AUDIO_FS_192K; 1910 break; 1911 default: 1912 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1913 params->sample_rate); 1914 return -EINVAL; 1915 } 1916 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1917 AUDIO_CHANNEL_STATUS_4, 1918 0xf0, rate); 1919 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1920 AP_AV_STATUS, AP_AUDIO_CHG); 1921 if (ret < 0) { 1922 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1923 return -EIO; 1924 } 1925 1926 return 0; 1927 } 1928 1929 static void anx7625_audio_shutdown(struct device *dev, void *data) 1930 { 1931 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1932 } 1933 1934 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1935 struct device_node *endpoint) 1936 { 1937 struct of_endpoint of_ep; 1938 int ret; 1939 1940 ret = of_graph_parse_endpoint(endpoint, &of_ep); 1941 if (ret < 0) 1942 return ret; 1943 1944 /* 1945 * HDMI sound should be located at external DPI port 1946 * Didn't have good way to check where is internal(DSI) 1947 * or external(DPI) bridge 1948 */ 1949 return 0; 1950 } 1951 1952 static void 1953 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1954 enum drm_connector_status status) 1955 { 1956 if (ctx->plugged_cb && ctx->codec_dev) { 1957 ctx->plugged_cb(ctx->codec_dev, 1958 status == connector_status_connected); 1959 } 1960 } 1961 1962 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1963 hdmi_codec_plugged_cb fn, 1964 struct device *codec_dev) 1965 { 1966 struct anx7625_data *ctx = data; 1967 1968 ctx->plugged_cb = fn; 1969 ctx->codec_dev = codec_dev; 1970 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1971 1972 return 0; 1973 } 1974 1975 static int anx7625_audio_get_eld(struct device *dev, void *data, 1976 u8 *buf, size_t len) 1977 { 1978 struct anx7625_data *ctx = dev_get_drvdata(dev); 1979 1980 if (!ctx->connector) { 1981 /* Pass en empty ELD if connector not available */ 1982 memset(buf, 0, len); 1983 } else { 1984 dev_dbg(dev, "audio copy eld\n"); 1985 memcpy(buf, ctx->connector->eld, 1986 min(sizeof(ctx->connector->eld), len)); 1987 } 1988 1989 return 0; 1990 } 1991 1992 static const struct hdmi_codec_ops anx7625_codec_ops = { 1993 .hw_params = anx7625_audio_hw_params, 1994 .audio_shutdown = anx7625_audio_shutdown, 1995 .get_eld = anx7625_audio_get_eld, 1996 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1997 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1998 }; 1999 2000 static void anx7625_unregister_audio(struct anx7625_data *ctx) 2001 { 2002 struct device *dev = &ctx->client->dev; 2003 2004 if (ctx->audio_pdev) { 2005 platform_device_unregister(ctx->audio_pdev); 2006 ctx->audio_pdev = NULL; 2007 } 2008 2009 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 2010 } 2011 2012 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 2013 { 2014 struct hdmi_codec_pdata codec_data = { 2015 .ops = &anx7625_codec_ops, 2016 .max_i2s_channels = 8, 2017 .i2s = 1, 2018 .data = ctx, 2019 }; 2020 2021 ctx->audio_pdev = platform_device_register_data(dev, 2022 HDMI_CODEC_DRV_NAME, 2023 PLATFORM_DEVID_AUTO, 2024 &codec_data, 2025 sizeof(codec_data)); 2026 2027 if (IS_ERR(ctx->audio_pdev)) 2028 return PTR_ERR(ctx->audio_pdev); 2029 2030 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 2031 2032 return 0; 2033 } 2034 2035 static int anx7625_attach_dsi(struct anx7625_data *ctx) 2036 { 2037 struct mipi_dsi_device *dsi; 2038 struct device *dev = &ctx->client->dev; 2039 struct mipi_dsi_host *host; 2040 const struct mipi_dsi_device_info info = { 2041 .type = "anx7625", 2042 .channel = 0, 2043 .node = NULL, 2044 }; 2045 int ret; 2046 2047 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 2048 2049 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 2050 if (!host) { 2051 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 2052 return -EPROBE_DEFER; 2053 } 2054 2055 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2056 if (IS_ERR(dsi)) { 2057 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 2058 return -EINVAL; 2059 } 2060 2061 dsi->lanes = ctx->pdata.mipi_lanes; 2062 dsi->format = MIPI_DSI_FMT_RGB888; 2063 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 2064 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2065 MIPI_DSI_MODE_VIDEO_HSE | 2066 MIPI_DSI_HS_PKT_END_ALIGNED; 2067 2068 ret = devm_mipi_dsi_attach(dev, dsi); 2069 if (ret) { 2070 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 2071 return ret; 2072 } 2073 2074 ctx->dsi = dsi; 2075 2076 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 2077 2078 return 0; 2079 } 2080 2081 static void hdcp_check_work_func(struct work_struct *work) 2082 { 2083 u8 status; 2084 struct delayed_work *dwork; 2085 struct anx7625_data *ctx; 2086 struct device *dev; 2087 struct drm_device *drm_dev; 2088 2089 dwork = to_delayed_work(work); 2090 ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2091 dev = &ctx->client->dev; 2092 2093 if (!ctx->connector) { 2094 dev_err(dev, "HDCP connector is null!"); 2095 return; 2096 } 2097 2098 drm_dev = ctx->connector->dev; 2099 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2100 mutex_lock(&ctx->hdcp_wq_lock); 2101 2102 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2103 dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2104 if (status & BIT(1)) { 2105 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2106 drm_hdcp_update_content_protection(ctx->connector, 2107 ctx->hdcp_cp); 2108 dev_dbg(dev, "update CP to ENABLE\n"); 2109 } 2110 2111 mutex_unlock(&ctx->hdcp_wq_lock); 2112 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2113 } 2114 2115 static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2116 struct drm_connector_state *state) 2117 { 2118 struct device *dev = &ctx->client->dev; 2119 int cp; 2120 2121 dev_dbg(dev, "hdcp state check\n"); 2122 cp = state->content_protection; 2123 2124 if (cp == ctx->hdcp_cp) 2125 return 0; 2126 2127 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2128 if (ctx->dp_en) { 2129 dev_dbg(dev, "enable HDCP\n"); 2130 anx7625_hdcp_enable(ctx); 2131 2132 queue_delayed_work(ctx->hdcp_workqueue, 2133 &ctx->hdcp_work, 2134 msecs_to_jiffies(2000)); 2135 } 2136 } 2137 2138 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2139 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2140 dev_err(dev, "current CP is not ENABLED\n"); 2141 return -EINVAL; 2142 } 2143 anx7625_hdcp_disable(ctx); 2144 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2145 drm_hdcp_update_content_protection(ctx->connector, 2146 ctx->hdcp_cp); 2147 dev_dbg(dev, "update CP to UNDESIRE\n"); 2148 } 2149 2150 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2151 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2152 return -EINVAL; 2153 } 2154 2155 return 0; 2156 } 2157 2158 static int anx7625_bridge_attach(struct drm_bridge *bridge, 2159 enum drm_bridge_attach_flags flags) 2160 { 2161 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2162 int err; 2163 struct device *dev = &ctx->client->dev; 2164 2165 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 2166 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 2167 return -EINVAL; 2168 2169 if (!bridge->encoder) { 2170 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 2171 return -ENODEV; 2172 } 2173 2174 ctx->aux.drm_dev = bridge->dev; 2175 err = drm_dp_aux_register(&ctx->aux); 2176 if (err) { 2177 dev_err(dev, "failed to register aux channel: %d\n", err); 2178 return err; 2179 } 2180 2181 if (ctx->pdata.panel_bridge) { 2182 err = drm_bridge_attach(bridge->encoder, 2183 ctx->pdata.panel_bridge, 2184 &ctx->bridge, flags); 2185 if (err) 2186 return err; 2187 } 2188 2189 ctx->bridge_attached = 1; 2190 2191 return 0; 2192 } 2193 2194 static void anx7625_bridge_detach(struct drm_bridge *bridge) 2195 { 2196 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2197 2198 drm_dp_aux_unregister(&ctx->aux); 2199 } 2200 2201 static enum drm_mode_status 2202 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 2203 const struct drm_display_info *info, 2204 const struct drm_display_mode *mode) 2205 { 2206 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2207 struct device *dev = &ctx->client->dev; 2208 2209 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 2210 2211 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 2212 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 2213 DRM_DEV_DEBUG_DRIVER(dev, 2214 "drm mode invalid, pixelclock too high.\n"); 2215 return MODE_CLOCK_HIGH; 2216 } 2217 2218 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 2219 2220 return MODE_OK; 2221 } 2222 2223 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 2224 const struct drm_display_mode *old_mode, 2225 const struct drm_display_mode *mode) 2226 { 2227 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2228 struct device *dev = &ctx->client->dev; 2229 2230 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 2231 2232 ctx->dt.pixelclock.min = mode->clock; 2233 ctx->dt.hactive.min = mode->hdisplay; 2234 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 2235 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 2236 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 2237 ctx->dt.vactive.min = mode->vdisplay; 2238 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 2239 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 2240 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 2241 2242 ctx->display_timing_valid = 1; 2243 2244 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 2245 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 2246 ctx->dt.hactive.min, 2247 ctx->dt.hsync_len.min, 2248 ctx->dt.hfront_porch.min, 2249 ctx->dt.hback_porch.min); 2250 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 2251 ctx->dt.vactive.min, 2252 ctx->dt.vsync_len.min, 2253 ctx->dt.vfront_porch.min, 2254 ctx->dt.vback_porch.min); 2255 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 2256 mode->hdisplay, 2257 mode->hsync_start); 2258 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 2259 mode->hsync_end, 2260 mode->htotal); 2261 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 2262 mode->vdisplay, 2263 mode->vsync_start); 2264 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 2265 mode->vsync_end, 2266 mode->vtotal); 2267 } 2268 2269 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 2270 const struct drm_display_mode *mode, 2271 struct drm_display_mode *adj) 2272 { 2273 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2274 struct device *dev = &ctx->client->dev; 2275 u32 hsync, hfp, hbp, hblanking; 2276 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 2277 u32 vref, adj_clock; 2278 2279 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 2280 2281 /* No need fixup for external monitor */ 2282 if (!ctx->pdata.panel_bridge) 2283 return true; 2284 2285 hsync = mode->hsync_end - mode->hsync_start; 2286 hfp = mode->hsync_start - mode->hdisplay; 2287 hbp = mode->htotal - mode->hsync_end; 2288 hblanking = mode->htotal - mode->hdisplay; 2289 2290 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 2291 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2292 hsync, hfp, hbp, adj->clock); 2293 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2294 adj->hsync_start, adj->hsync_end, adj->htotal); 2295 2296 adj_hfp = hfp; 2297 adj_hsync = hsync; 2298 adj_hbp = hbp; 2299 adj_hblanking = hblanking; 2300 2301 /* HFP needs to be even */ 2302 if (hfp & 0x1) { 2303 adj_hfp += 1; 2304 adj_hblanking += 1; 2305 } 2306 2307 /* HBP needs to be even */ 2308 if (hbp & 0x1) { 2309 adj_hbp -= 1; 2310 adj_hblanking -= 1; 2311 } 2312 2313 /* HSYNC needs to be even */ 2314 if (hsync & 0x1) { 2315 if (adj_hblanking < hblanking) 2316 adj_hsync += 1; 2317 else 2318 adj_hsync -= 1; 2319 } 2320 2321 /* 2322 * Once illegal timing detected, use default HFP, HSYNC, HBP 2323 * This adjusting made for built-in eDP panel, for the externel 2324 * DP monitor, may need return false. 2325 */ 2326 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 2327 adj_hsync = SYNC_LEN_DEF; 2328 adj_hfp = HFP_HBP_DEF; 2329 adj_hbp = HFP_HBP_DEF; 2330 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 2331 if (hblanking < HBLANKING_MIN) { 2332 delta_adj = HBLANKING_MIN - hblanking; 2333 adj_clock = vref * delta_adj * adj->vtotal; 2334 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 2335 } else { 2336 delta_adj = hblanking - HBLANKING_MIN; 2337 adj_clock = vref * delta_adj * adj->vtotal; 2338 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 2339 } 2340 2341 DRM_WARN("illegal hblanking timing, use default.\n"); 2342 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 2343 } else if (adj_hfp < HP_MIN) { 2344 /* Adjust hfp if hfp less than HP_MIN */ 2345 delta_adj = HP_MIN - adj_hfp; 2346 adj_hfp = HP_MIN; 2347 2348 /* 2349 * Balance total HBlanking pixel, if HBP does not have enough 2350 * space, adjust HSYNC length, otherwise adjust HBP 2351 */ 2352 if ((adj_hbp - delta_adj) < HP_MIN) 2353 /* HBP not enough space */ 2354 adj_hsync -= delta_adj; 2355 else 2356 adj_hbp -= delta_adj; 2357 } else if (adj_hbp < HP_MIN) { 2358 delta_adj = HP_MIN - adj_hbp; 2359 adj_hbp = HP_MIN; 2360 2361 /* 2362 * Balance total HBlanking pixel, if HBP hasn't enough space, 2363 * adjust HSYNC length, otherwize adjust HBP 2364 */ 2365 if ((adj_hfp - delta_adj) < HP_MIN) 2366 /* HFP not enough space */ 2367 adj_hsync -= delta_adj; 2368 else 2369 adj_hfp -= delta_adj; 2370 } 2371 2372 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 2373 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2374 adj_hsync, adj_hfp, adj_hbp, adj->clock); 2375 2376 /* Reconstruct timing */ 2377 adj->hsync_start = adj->hdisplay + adj_hfp; 2378 adj->hsync_end = adj->hsync_start + adj_hsync; 2379 adj->htotal = adj->hsync_end + adj_hbp; 2380 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2381 adj->hsync_start, adj->hsync_end, adj->htotal); 2382 2383 return true; 2384 } 2385 2386 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2387 struct drm_bridge_state *bridge_state, 2388 struct drm_crtc_state *crtc_state, 2389 struct drm_connector_state *conn_state) 2390 { 2391 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2392 struct device *dev = &ctx->client->dev; 2393 2394 dev_dbg(dev, "drm bridge atomic check\n"); 2395 2396 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2397 &crtc_state->adjusted_mode); 2398 2399 return anx7625_connector_atomic_check(ctx, conn_state); 2400 } 2401 2402 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2403 struct drm_bridge_state *state) 2404 { 2405 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2406 struct device *dev = &ctx->client->dev; 2407 struct drm_connector *connector; 2408 2409 dev_dbg(dev, "drm atomic enable\n"); 2410 2411 if (!bridge->encoder) { 2412 dev_err(dev, "Parent encoder object not found"); 2413 return; 2414 } 2415 2416 connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2417 bridge->encoder); 2418 if (!connector) 2419 return; 2420 2421 ctx->connector = connector; 2422 2423 pm_runtime_get_sync(dev); 2424 _anx7625_hpd_polling(ctx, 5000 * 100); 2425 2426 anx7625_dp_start(ctx); 2427 } 2428 2429 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2430 struct drm_bridge_state *old) 2431 { 2432 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2433 struct device *dev = &ctx->client->dev; 2434 2435 dev_dbg(dev, "drm atomic disable\n"); 2436 2437 ctx->connector = NULL; 2438 anx7625_dp_stop(ctx); 2439 2440 pm_runtime_put_sync(dev); 2441 } 2442 2443 static enum drm_connector_status 2444 anx7625_bridge_detect(struct drm_bridge *bridge) 2445 { 2446 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2447 struct device *dev = &ctx->client->dev; 2448 2449 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 2450 2451 return anx7625_sink_detect(ctx); 2452 } 2453 2454 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 2455 struct drm_connector *connector) 2456 { 2457 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2458 struct device *dev = &ctx->client->dev; 2459 2460 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 2461 2462 return anx7625_get_edid(ctx); 2463 } 2464 2465 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 2466 .attach = anx7625_bridge_attach, 2467 .detach = anx7625_bridge_detach, 2468 .mode_valid = anx7625_bridge_mode_valid, 2469 .mode_set = anx7625_bridge_mode_set, 2470 .atomic_check = anx7625_bridge_atomic_check, 2471 .atomic_enable = anx7625_bridge_atomic_enable, 2472 .atomic_disable = anx7625_bridge_atomic_disable, 2473 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2474 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2475 .atomic_reset = drm_atomic_helper_bridge_reset, 2476 .detect = anx7625_bridge_detect, 2477 .get_edid = anx7625_bridge_get_edid, 2478 }; 2479 2480 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 2481 struct i2c_client *client) 2482 { 2483 struct device *dev = &ctx->client->dev; 2484 2485 ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter, 2486 TX_P0_ADDR >> 1); 2487 if (IS_ERR(ctx->i2c.tx_p0_client)) 2488 return PTR_ERR(ctx->i2c.tx_p0_client); 2489 2490 ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter, 2491 TX_P1_ADDR >> 1); 2492 if (IS_ERR(ctx->i2c.tx_p1_client)) 2493 return PTR_ERR(ctx->i2c.tx_p1_client); 2494 2495 ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter, 2496 TX_P2_ADDR >> 1); 2497 if (IS_ERR(ctx->i2c.tx_p2_client)) 2498 return PTR_ERR(ctx->i2c.tx_p2_client); 2499 2500 ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter, 2501 RX_P0_ADDR >> 1); 2502 if (IS_ERR(ctx->i2c.rx_p0_client)) 2503 return PTR_ERR(ctx->i2c.rx_p0_client); 2504 2505 ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter, 2506 RX_P1_ADDR >> 1); 2507 if (IS_ERR(ctx->i2c.rx_p1_client)) 2508 return PTR_ERR(ctx->i2c.rx_p1_client); 2509 2510 ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter, 2511 RX_P2_ADDR >> 1); 2512 if (IS_ERR(ctx->i2c.rx_p2_client)) 2513 return PTR_ERR(ctx->i2c.rx_p2_client); 2514 2515 ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter, 2516 TCPC_INTERFACE_ADDR >> 1); 2517 if (IS_ERR(ctx->i2c.tcpc_client)) 2518 return PTR_ERR(ctx->i2c.tcpc_client); 2519 2520 return 0; 2521 } 2522 2523 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2524 { 2525 struct anx7625_data *ctx = dev_get_drvdata(dev); 2526 2527 mutex_lock(&ctx->lock); 2528 2529 anx7625_stop_dp_work(ctx); 2530 anx7625_power_standby(ctx); 2531 2532 mutex_unlock(&ctx->lock); 2533 2534 return 0; 2535 } 2536 2537 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2538 { 2539 struct anx7625_data *ctx = dev_get_drvdata(dev); 2540 2541 mutex_lock(&ctx->lock); 2542 2543 anx7625_power_on_init(ctx); 2544 2545 mutex_unlock(&ctx->lock); 2546 2547 return 0; 2548 } 2549 2550 static const struct dev_pm_ops anx7625_pm_ops = { 2551 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2552 pm_runtime_force_resume) 2553 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2554 anx7625_runtime_pm_resume, NULL) 2555 }; 2556 2557 static void anx7625_runtime_disable(void *data) 2558 { 2559 pm_runtime_dont_use_autosuspend(data); 2560 pm_runtime_disable(data); 2561 } 2562 2563 static int anx7625_i2c_probe(struct i2c_client *client) 2564 { 2565 struct anx7625_data *platform; 2566 struct anx7625_platform_data *pdata; 2567 int ret = 0; 2568 struct device *dev = &client->dev; 2569 2570 if (!i2c_check_functionality(client->adapter, 2571 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2572 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2573 return -ENODEV; 2574 } 2575 2576 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL); 2577 if (!platform) { 2578 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2579 return -ENOMEM; 2580 } 2581 2582 pdata = &platform->pdata; 2583 2584 platform->client = client; 2585 i2c_set_clientdata(client, platform); 2586 2587 pdata->supplies[0].supply = "vdd10"; 2588 pdata->supplies[1].supply = "vdd18"; 2589 pdata->supplies[2].supply = "vdd33"; 2590 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2591 pdata->supplies); 2592 if (ret) { 2593 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2594 return ret; 2595 } 2596 anx7625_init_gpio(platform); 2597 2598 mutex_init(&platform->lock); 2599 mutex_init(&platform->hdcp_wq_lock); 2600 2601 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2602 platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2603 if (!platform->hdcp_workqueue) { 2604 dev_err(dev, "fail to create work queue\n"); 2605 ret = -ENOMEM; 2606 return ret; 2607 } 2608 2609 platform->pdata.intp_irq = client->irq; 2610 if (platform->pdata.intp_irq) { 2611 INIT_WORK(&platform->work, anx7625_work_func); 2612 platform->workqueue = alloc_workqueue("anx7625_work", 2613 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2614 if (!platform->workqueue) { 2615 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2616 ret = -ENOMEM; 2617 goto free_hdcp_wq; 2618 } 2619 2620 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2621 NULL, anx7625_intr_hpd_isr, 2622 IRQF_TRIGGER_FALLING | 2623 IRQF_ONESHOT, 2624 "anx7625-intp", platform); 2625 if (ret) { 2626 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2627 goto free_wq; 2628 } 2629 } 2630 2631 platform->aux.name = "anx7625-aux"; 2632 platform->aux.dev = dev; 2633 platform->aux.transfer = anx7625_aux_transfer; 2634 platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted; 2635 drm_dp_aux_init(&platform->aux); 2636 2637 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2638 ret = -ENOMEM; 2639 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2640 goto free_wq; 2641 } 2642 2643 pm_runtime_enable(dev); 2644 pm_runtime_set_autosuspend_delay(dev, 1000); 2645 pm_runtime_use_autosuspend(dev); 2646 pm_suspend_ignore_children(dev, true); 2647 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev); 2648 if (ret) 2649 goto free_wq; 2650 2651 devm_of_dp_aux_populate_ep_devices(&platform->aux); 2652 2653 ret = anx7625_parse_dt(dev, pdata); 2654 if (ret) { 2655 if (ret != -EPROBE_DEFER) 2656 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2657 goto free_wq; 2658 } 2659 2660 if (!platform->pdata.low_power_mode) { 2661 anx7625_disable_pd_protocol(platform); 2662 pm_runtime_get_sync(dev); 2663 _anx7625_hpd_polling(platform, 5000 * 100); 2664 } 2665 2666 /* Add work function */ 2667 if (platform->pdata.intp_irq) 2668 queue_work(platform->workqueue, &platform->work); 2669 2670 platform->bridge.funcs = &anx7625_bridge_funcs; 2671 platform->bridge.of_node = client->dev.of_node; 2672 if (!anx7625_of_panel_on_aux_bus(&client->dev)) 2673 platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 2674 if (!platform->pdata.panel_bridge) 2675 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2676 DRM_BRIDGE_OP_DETECT; 2677 platform->bridge.type = platform->pdata.panel_bridge ? 2678 DRM_MODE_CONNECTOR_eDP : 2679 DRM_MODE_CONNECTOR_DisplayPort; 2680 2681 drm_bridge_add(&platform->bridge); 2682 2683 if (!platform->pdata.is_dpi) { 2684 ret = anx7625_attach_dsi(platform); 2685 if (ret) { 2686 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 2687 goto unregister_bridge; 2688 } 2689 } 2690 2691 if (platform->pdata.audio_en) 2692 anx7625_register_audio(dev, platform); 2693 2694 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2695 2696 return 0; 2697 2698 unregister_bridge: 2699 drm_bridge_remove(&platform->bridge); 2700 2701 if (!platform->pdata.low_power_mode) 2702 pm_runtime_put_sync_suspend(&client->dev); 2703 2704 free_wq: 2705 if (platform->workqueue) 2706 destroy_workqueue(platform->workqueue); 2707 2708 free_hdcp_wq: 2709 if (platform->hdcp_workqueue) 2710 destroy_workqueue(platform->hdcp_workqueue); 2711 2712 return ret; 2713 } 2714 2715 static void anx7625_i2c_remove(struct i2c_client *client) 2716 { 2717 struct anx7625_data *platform = i2c_get_clientdata(client); 2718 2719 drm_bridge_remove(&platform->bridge); 2720 2721 if (platform->pdata.intp_irq) 2722 destroy_workqueue(platform->workqueue); 2723 2724 if (platform->hdcp_workqueue) { 2725 cancel_delayed_work(&platform->hdcp_work); 2726 flush_workqueue(platform->hdcp_workqueue); 2727 destroy_workqueue(platform->hdcp_workqueue); 2728 } 2729 2730 if (!platform->pdata.low_power_mode) 2731 pm_runtime_put_sync_suspend(&client->dev); 2732 2733 if (platform->pdata.audio_en) 2734 anx7625_unregister_audio(platform); 2735 } 2736 2737 static const struct i2c_device_id anx7625_id[] = { 2738 {"anx7625", 0}, 2739 {} 2740 }; 2741 2742 MODULE_DEVICE_TABLE(i2c, anx7625_id); 2743 2744 static const struct of_device_id anx_match_table[] = { 2745 {.compatible = "analogix,anx7625",}, 2746 {}, 2747 }; 2748 MODULE_DEVICE_TABLE(of, anx_match_table); 2749 2750 static struct i2c_driver anx7625_driver = { 2751 .driver = { 2752 .name = "anx7625", 2753 .of_match_table = anx_match_table, 2754 .pm = &anx7625_pm_ops, 2755 }, 2756 .probe_new = anx7625_i2c_probe, 2757 .remove = anx7625_i2c_remove, 2758 2759 .id_table = anx7625_id, 2760 }; 2761 2762 module_i2c_driver(anx7625_driver); 2763 2764 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 2765 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 2766 MODULE_LICENSE("GPL v2"); 2767 MODULE_VERSION(ANX7625_DRV_VERSION); 2768