1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_dp_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_mipi_dsi.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_panel.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 35 #include <video/display_timing.h> 36 37 #include "anx7625.h" 38 39 /* 40 * There is a sync issue while access I2C register between AP(CPU) and 41 * internal firmware(OCM), to avoid the race condition, AP should access 42 * the reserved slave address before slave address occurs changes. 43 */ 44 static int i2c_access_workaround(struct anx7625_data *ctx, 45 struct i2c_client *client) 46 { 47 u8 offset; 48 struct device *dev = &client->dev; 49 int ret; 50 51 if (client == ctx->last_client) 52 return 0; 53 54 ctx->last_client = client; 55 56 if (client == ctx->i2c.tcpc_client) 57 offset = RSVD_00_ADDR; 58 else if (client == ctx->i2c.tx_p0_client) 59 offset = RSVD_D1_ADDR; 60 else if (client == ctx->i2c.tx_p1_client) 61 offset = RSVD_60_ADDR; 62 else if (client == ctx->i2c.rx_p0_client) 63 offset = RSVD_39_ADDR; 64 else if (client == ctx->i2c.rx_p1_client) 65 offset = RSVD_7F_ADDR; 66 else 67 offset = RSVD_00_ADDR; 68 69 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 70 if (ret < 0) 71 DRM_DEV_ERROR(dev, 72 "fail to access i2c id=%x\n:%x", 73 client->addr, offset); 74 75 return ret; 76 } 77 78 static int anx7625_reg_read(struct anx7625_data *ctx, 79 struct i2c_client *client, u8 reg_addr) 80 { 81 int ret; 82 struct device *dev = &client->dev; 83 84 i2c_access_workaround(ctx, client); 85 86 ret = i2c_smbus_read_byte_data(client, reg_addr); 87 if (ret < 0) 88 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 89 client->addr, reg_addr); 90 91 return ret; 92 } 93 94 static int anx7625_reg_block_read(struct anx7625_data *ctx, 95 struct i2c_client *client, 96 u8 reg_addr, u8 len, u8 *buf) 97 { 98 int ret; 99 struct device *dev = &client->dev; 100 101 i2c_access_workaround(ctx, client); 102 103 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 104 if (ret < 0) 105 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 106 client->addr, reg_addr); 107 108 return ret; 109 } 110 111 static int anx7625_reg_write(struct anx7625_data *ctx, 112 struct i2c_client *client, 113 u8 reg_addr, u8 reg_val) 114 { 115 int ret; 116 struct device *dev = &client->dev; 117 118 i2c_access_workaround(ctx, client); 119 120 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 121 122 if (ret < 0) 123 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 124 client->addr, reg_addr); 125 126 return ret; 127 } 128 129 static int anx7625_write_or(struct anx7625_data *ctx, 130 struct i2c_client *client, 131 u8 offset, u8 mask) 132 { 133 int val; 134 135 val = anx7625_reg_read(ctx, client, offset); 136 if (val < 0) 137 return val; 138 139 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 140 } 141 142 static int anx7625_write_and(struct anx7625_data *ctx, 143 struct i2c_client *client, 144 u8 offset, u8 mask) 145 { 146 int val; 147 148 val = anx7625_reg_read(ctx, client, offset); 149 if (val < 0) 150 return val; 151 152 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 153 } 154 155 static int anx7625_write_and_or(struct anx7625_data *ctx, 156 struct i2c_client *client, 157 u8 offset, u8 and_mask, u8 or_mask) 158 { 159 int val; 160 161 val = anx7625_reg_read(ctx, client, offset); 162 if (val < 0) 163 return val; 164 165 return anx7625_reg_write(ctx, client, 166 offset, (val & and_mask) | (or_mask)); 167 } 168 169 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 170 { 171 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 172 } 173 174 static int wait_aux_op_finish(struct anx7625_data *ctx) 175 { 176 struct device *dev = &ctx->client->dev; 177 int val; 178 int ret; 179 180 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 181 ctx, val, 182 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 183 2000, 184 2000 * 150); 185 if (ret) { 186 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 187 return -EIO; 188 } 189 190 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 191 AP_AUX_CTRL_STATUS); 192 if (val < 0 || (val & 0x0F)) { 193 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 194 val = -EIO; 195 } 196 197 return val; 198 } 199 200 static int anx7625_video_mute_control(struct anx7625_data *ctx, 201 u8 status) 202 { 203 int ret; 204 205 if (status) { 206 /* Set mute on flag */ 207 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 208 AP_AV_STATUS, AP_MIPI_MUTE); 209 /* Clear mipi RX en */ 210 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 211 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 212 } else { 213 /* Mute off flag */ 214 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 215 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 216 /* Set MIPI RX EN */ 217 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 218 AP_AV_STATUS, AP_MIPI_RX_EN); 219 } 220 221 return ret; 222 } 223 224 static int anx7625_config_audio_input(struct anx7625_data *ctx) 225 { 226 struct device *dev = &ctx->client->dev; 227 int ret; 228 229 /* Channel num */ 230 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 231 AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5); 232 233 /* FS */ 234 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 235 AUDIO_CHANNEL_STATUS_4, 236 0xf0, AUDIO_FS_48K); 237 /* Word length */ 238 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 239 AUDIO_CHANNEL_STATUS_5, 240 0xf0, AUDIO_W_LEN_24_24MAX); 241 /* I2S */ 242 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 243 AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE); 244 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 245 AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE); 246 /* Audio change flag */ 247 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 248 AP_AV_STATUS, AP_AUDIO_CHG); 249 250 if (ret < 0) 251 DRM_DEV_ERROR(dev, "fail to config audio.\n"); 252 253 return ret; 254 } 255 256 /* Reduction of fraction a/b */ 257 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 258 { 259 unsigned long gcd_num; 260 unsigned long tmp_a, tmp_b; 261 u32 i = 1; 262 263 gcd_num = gcd(*a, *b); 264 *a /= gcd_num; 265 *b /= gcd_num; 266 267 tmp_a = *a; 268 tmp_b = *b; 269 270 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 271 i++; 272 *a = tmp_a / i; 273 *b = tmp_b / i; 274 } 275 276 /* 277 * In the end, make a, b larger to have higher ODFC PLL 278 * output frequency accuracy 279 */ 280 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 281 *a <<= 1; 282 *b <<= 1; 283 } 284 285 *a >>= 1; 286 *b >>= 1; 287 } 288 289 static int anx7625_calculate_m_n(u32 pixelclock, 290 unsigned long *m, 291 unsigned long *n, 292 u8 *post_divider) 293 { 294 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 295 /* Pixel clock frequency is too high */ 296 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 297 pixelclock, 298 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 299 return -EINVAL; 300 } 301 302 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 303 /* Pixel clock frequency is too low */ 304 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 305 pixelclock, 306 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 307 return -EINVAL; 308 } 309 310 for (*post_divider = 1; 311 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 312 *post_divider += 1; 313 314 if (*post_divider > POST_DIVIDER_MAX) { 315 for (*post_divider = 1; 316 (pixelclock < 317 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 318 *post_divider += 1; 319 320 if (*post_divider > POST_DIVIDER_MAX) { 321 DRM_ERROR("cannot find property post_divider(%d)\n", 322 *post_divider); 323 return -EDOM; 324 } 325 } 326 327 /* Patch to improve the accuracy */ 328 if (*post_divider == 7) { 329 /* 27,000,000 is not divisible by 7 */ 330 *post_divider = 8; 331 } else if (*post_divider == 11) { 332 /* 27,000,000 is not divisible by 11 */ 333 *post_divider = 12; 334 } else if ((*post_divider == 13) || (*post_divider == 14)) { 335 /* 27,000,000 is not divisible by 13 or 14 */ 336 *post_divider = 15; 337 } 338 339 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 340 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 341 pixelclock * (*post_divider), 342 PLL_OUT_FREQ_ABS_MAX); 343 return -EDOM; 344 } 345 346 *m = pixelclock; 347 *n = XTAL_FRQ / (*post_divider); 348 349 anx7625_reduction_of_a_fraction(m, n); 350 351 return 0; 352 } 353 354 static int anx7625_odfc_config(struct anx7625_data *ctx, 355 u8 post_divider) 356 { 357 int ret; 358 struct device *dev = &ctx->client->dev; 359 360 /* Config input reference clock frequency 27MHz/19.2MHz */ 361 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 362 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 363 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 364 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 365 /* Post divider */ 366 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 367 MIPI_DIGITAL_PLL_8, 0x0f); 368 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 369 post_divider << 4); 370 371 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 372 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 373 ~MIPI_PLL_VCO_TUNE_REG_VAL); 374 375 /* Reset ODFC PLL */ 376 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 377 ~MIPI_PLL_RESET_N); 378 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 379 MIPI_PLL_RESET_N); 380 381 if (ret < 0) 382 DRM_DEV_ERROR(dev, "IO error.\n"); 383 384 return ret; 385 } 386 387 /* 388 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 389 * anx7625 defined K ratio for matching MIPI input video clock and 390 * DP output video clock. Increase K value can match bigger video data 391 * variation. IVO panel has small variation than DP CTS spec, need 392 * decrease the K value. 393 */ 394 static int anx7625_set_k_value(struct anx7625_data *ctx) 395 { 396 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 397 398 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 399 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 400 MIPI_DIGITAL_ADJ_1, 0x3B); 401 402 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 403 MIPI_DIGITAL_ADJ_1, 0x3D); 404 } 405 406 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 407 { 408 struct device *dev = &ctx->client->dev; 409 unsigned long m, n; 410 u16 htotal; 411 int ret; 412 u8 post_divider = 0; 413 414 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 415 &m, &n, &post_divider); 416 417 if (ret) { 418 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 419 return ret; 420 } 421 422 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 423 m, n, post_divider); 424 425 /* Configure pixel clock */ 426 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 427 (ctx->dt.pixelclock.min / 1000) & 0xFF); 428 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 429 (ctx->dt.pixelclock.min / 1000) >> 8); 430 /* Lane count */ 431 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 432 MIPI_LANE_CTRL_0, 0xfc); 433 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 434 MIPI_LANE_CTRL_0, 3); 435 436 /* Htotal */ 437 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 438 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 439 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 440 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 441 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 442 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 443 /* Hactive */ 444 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 445 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 446 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 447 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 448 /* HFP */ 449 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 450 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 451 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 452 HORIZONTAL_FRONT_PORCH_H, 453 ctx->dt.hfront_porch.min >> 8); 454 /* HWS */ 455 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 456 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 457 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 458 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 459 /* HBP */ 460 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 461 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 462 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 463 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 464 /* Vactive */ 465 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 466 ctx->dt.vactive.min); 467 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 468 ctx->dt.vactive.min >> 8); 469 /* VFP */ 470 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 471 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 472 /* VWS */ 473 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 474 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 475 /* VBP */ 476 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 477 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 478 /* M value */ 479 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 480 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 481 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 482 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 483 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 484 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 485 /* N value */ 486 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 487 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 488 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 489 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 490 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 491 (n & 0xff)); 492 493 anx7625_set_k_value(ctx); 494 495 ret |= anx7625_odfc_config(ctx, post_divider - 1); 496 497 if (ret < 0) 498 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 499 500 return ret; 501 } 502 503 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 504 { 505 int val; 506 struct device *dev = &ctx->client->dev; 507 508 /* Swap MIPI-DSI data lane 3 P and N */ 509 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 510 if (val < 0) { 511 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 512 return -EIO; 513 } 514 515 val |= (1 << MIPI_SWAP_CH3); 516 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 517 } 518 519 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 520 521 { 522 int val, ret; 523 struct device *dev = &ctx->client->dev; 524 525 /* Swap MIPI-DSI data lane 3 P and N */ 526 ret = anx7625_swap_dsi_lane3(ctx); 527 if (ret < 0) { 528 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 529 return ret; 530 } 531 532 /* DSI clock settings */ 533 val = (0 << MIPI_HS_PWD_CLK) | 534 (0 << MIPI_HS_RT_CLK) | 535 (0 << MIPI_PD_CLK) | 536 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 537 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 538 (0 << MIPI_CLK_DET_DET_BYPASS) | 539 (0 << MIPI_CLK_MISS_CTRL) | 540 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 541 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 542 MIPI_PHY_CONTROL_3, val); 543 544 /* 545 * Decreased HS prepare timing delay from 160ns to 80ns work with 546 * a) Dragon board 810 series (Qualcomm AP) 547 * b) Moving Pixel DSI source (PG3A pattern generator + 548 * P332 D-PHY Probe) default D-PHY timing 549 * 5ns/step 550 */ 551 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 552 MIPI_TIME_HS_PRPR, 0x10); 553 554 /* Enable DSI mode*/ 555 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 556 SELECT_DSI << MIPI_DPI_SELECT); 557 558 ret |= anx7625_dsi_video_timing_config(ctx); 559 if (ret < 0) { 560 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 561 return ret; 562 } 563 564 /* Toggle m, n ready */ 565 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 566 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 567 usleep_range(1000, 1100); 568 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 569 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 570 571 /* Configure integer stable register */ 572 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 573 MIPI_VIDEO_STABLE_CNT, 0x02); 574 /* Power on MIPI RX */ 575 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 576 MIPI_LANE_CTRL_10, 0x00); 577 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 578 MIPI_LANE_CTRL_10, 0x80); 579 580 if (ret < 0) 581 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 582 583 return ret; 584 } 585 586 static int anx7625_dsi_config(struct anx7625_data *ctx) 587 { 588 struct device *dev = &ctx->client->dev; 589 int ret; 590 591 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 592 593 /* DSC disable */ 594 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 595 R_DSC_CTRL_0, ~DSC_EN); 596 597 ret |= anx7625_api_dsi_config(ctx); 598 599 if (ret < 0) { 600 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 601 return ret; 602 } 603 604 /* Set MIPI RX EN */ 605 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 606 AP_AV_STATUS, AP_MIPI_RX_EN); 607 /* Clear mute flag */ 608 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 609 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 610 if (ret < 0) 611 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 612 else 613 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 614 615 return ret; 616 } 617 618 static void anx7625_dp_start(struct anx7625_data *ctx) 619 { 620 int ret; 621 struct device *dev = &ctx->client->dev; 622 623 if (!ctx->display_timing_valid) { 624 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 625 return; 626 } 627 628 anx7625_config_audio_input(ctx); 629 630 ret = anx7625_dsi_config(ctx); 631 632 if (ret < 0) 633 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 634 } 635 636 static void anx7625_dp_stop(struct anx7625_data *ctx) 637 { 638 struct device *dev = &ctx->client->dev; 639 int ret; 640 641 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 642 643 /* 644 * Video disable: 0x72:08 bit 7 = 0; 645 * Audio disable: 0x70:87 bit 0 = 0; 646 */ 647 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 648 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 649 650 ret |= anx7625_video_mute_control(ctx, 1); 651 if (ret < 0) 652 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 653 } 654 655 static int sp_tx_rst_aux(struct anx7625_data *ctx) 656 { 657 int ret; 658 659 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 660 AUX_RST); 661 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 662 ~AUX_RST); 663 return ret; 664 } 665 666 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 667 { 668 int ret; 669 670 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 671 AP_AUX_BUFF_START, offset); 672 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 673 AP_AUX_COMMAND, 0x04); 674 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 675 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 676 return (ret | wait_aux_op_finish(ctx)); 677 } 678 679 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 680 { 681 int ret; 682 683 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 684 AP_AUX_COMMAND, len_cmd); 685 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 686 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 687 return (ret | wait_aux_op_finish(ctx)); 688 } 689 690 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 691 { 692 int c = 0; 693 struct device *dev = &ctx->client->dev; 694 695 sp_tx_aux_wr(ctx, 0x7e); 696 sp_tx_aux_rd(ctx, 0x01); 697 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 698 if (c < 0) { 699 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 700 return -EIO; 701 } 702 703 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 704 705 if (c > MAX_EDID_BLOCK) 706 c = 1; 707 708 return c; 709 } 710 711 static int edid_read(struct anx7625_data *ctx, 712 u8 offset, u8 *pblock_buf) 713 { 714 int ret, cnt; 715 struct device *dev = &ctx->client->dev; 716 717 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 718 sp_tx_aux_wr(ctx, offset); 719 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 720 ret = sp_tx_aux_rd(ctx, 0xf1); 721 722 if (ret) { 723 ret = sp_tx_rst_aux(ctx); 724 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 725 } else { 726 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 727 AP_AUX_BUFF_START, 728 MAX_DPCD_BUFFER_SIZE, 729 pblock_buf); 730 if (ret > 0) 731 break; 732 } 733 } 734 735 if (cnt > EDID_TRY_CNT) 736 return -EIO; 737 738 return ret; 739 } 740 741 static int segments_edid_read(struct anx7625_data *ctx, 742 u8 segment, u8 *buf, u8 offset) 743 { 744 u8 cnt; 745 int ret; 746 struct device *dev = &ctx->client->dev; 747 748 /* Write address only */ 749 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 750 AP_AUX_ADDR_7_0, 0x30); 751 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 752 AP_AUX_COMMAND, 0x04); 753 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 754 AP_AUX_CTRL_STATUS, 755 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 756 757 ret |= wait_aux_op_finish(ctx); 758 /* Write segment address */ 759 ret |= sp_tx_aux_wr(ctx, segment); 760 /* Data read */ 761 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 762 AP_AUX_ADDR_7_0, 0x50); 763 if (ret) { 764 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 765 return ret; 766 } 767 768 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 769 sp_tx_aux_wr(ctx, offset); 770 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 771 ret = sp_tx_aux_rd(ctx, 0xf1); 772 773 if (ret) { 774 ret = sp_tx_rst_aux(ctx); 775 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 776 } else { 777 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 778 AP_AUX_BUFF_START, 779 MAX_DPCD_BUFFER_SIZE, buf); 780 if (ret > 0) 781 break; 782 } 783 } 784 785 if (cnt > EDID_TRY_CNT) 786 return -EIO; 787 788 return ret; 789 } 790 791 static int sp_tx_edid_read(struct anx7625_data *ctx, 792 u8 *pedid_blocks_buf) 793 { 794 u8 offset, edid_pos; 795 int count, blocks_num; 796 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 797 u8 i, j; 798 u8 g_edid_break = 0; 799 int ret; 800 struct device *dev = &ctx->client->dev; 801 802 /* Address initial */ 803 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 804 AP_AUX_ADDR_7_0, 0x50); 805 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 806 AP_AUX_ADDR_15_8, 0); 807 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 808 AP_AUX_ADDR_19_16, 0xf0); 809 if (ret < 0) { 810 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 811 return -EIO; 812 } 813 814 blocks_num = sp_tx_get_edid_block(ctx); 815 if (blocks_num < 0) 816 return blocks_num; 817 818 count = 0; 819 820 do { 821 switch (count) { 822 case 0: 823 case 1: 824 for (i = 0; i < 8; i++) { 825 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 826 g_edid_break = edid_read(ctx, offset, 827 pblock_buf); 828 829 if (g_edid_break) 830 break; 831 832 memcpy(&pedid_blocks_buf[offset], 833 pblock_buf, 834 MAX_DPCD_BUFFER_SIZE); 835 } 836 837 break; 838 case 2: 839 offset = 0x00; 840 841 for (j = 0; j < 8; j++) { 842 edid_pos = (j + count * 8) * 843 MAX_DPCD_BUFFER_SIZE; 844 845 if (g_edid_break == 1) 846 break; 847 848 ret = segments_edid_read(ctx, count / 2, 849 pblock_buf, offset); 850 if (ret < 0) 851 return ret; 852 853 memcpy(&pedid_blocks_buf[edid_pos], 854 pblock_buf, 855 MAX_DPCD_BUFFER_SIZE); 856 offset = offset + 0x10; 857 } 858 859 break; 860 case 3: 861 offset = 0x80; 862 863 for (j = 0; j < 8; j++) { 864 edid_pos = (j + count * 8) * 865 MAX_DPCD_BUFFER_SIZE; 866 if (g_edid_break == 1) 867 break; 868 869 ret = segments_edid_read(ctx, count / 2, 870 pblock_buf, offset); 871 if (ret < 0) 872 return ret; 873 874 memcpy(&pedid_blocks_buf[edid_pos], 875 pblock_buf, 876 MAX_DPCD_BUFFER_SIZE); 877 offset = offset + 0x10; 878 } 879 880 break; 881 default: 882 break; 883 } 884 885 count++; 886 887 } while (blocks_num >= count); 888 889 /* Check edid data */ 890 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 891 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 892 return -EINVAL; 893 } 894 895 /* Reset aux channel */ 896 ret = sp_tx_rst_aux(ctx); 897 if (ret < 0) { 898 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 899 return ret; 900 } 901 902 return (blocks_num + 1); 903 } 904 905 static void anx7625_power_on(struct anx7625_data *ctx) 906 { 907 struct device *dev = &ctx->client->dev; 908 int ret, i; 909 910 if (!ctx->pdata.low_power_mode) { 911 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 912 return; 913 } 914 915 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 916 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 917 if (ret < 0) { 918 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 919 i, ret); 920 goto reg_err; 921 } 922 usleep_range(2000, 2100); 923 } 924 925 usleep_range(11000, 12000); 926 927 /* Power on pin enable */ 928 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 929 usleep_range(10000, 11000); 930 /* Power reset pin enable */ 931 gpiod_set_value(ctx->pdata.gpio_reset, 1); 932 usleep_range(10000, 11000); 933 934 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 935 return; 936 reg_err: 937 for (--i; i >= 0; i--) 938 regulator_disable(ctx->pdata.supplies[i].consumer); 939 } 940 941 static void anx7625_power_standby(struct anx7625_data *ctx) 942 { 943 struct device *dev = &ctx->client->dev; 944 int ret; 945 946 if (!ctx->pdata.low_power_mode) { 947 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 948 return; 949 } 950 951 gpiod_set_value(ctx->pdata.gpio_reset, 0); 952 usleep_range(1000, 1100); 953 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 954 usleep_range(1000, 1100); 955 956 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 957 ctx->pdata.supplies); 958 if (ret < 0) 959 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 960 961 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 962 } 963 964 /* Basic configurations of ANX7625 */ 965 static void anx7625_config(struct anx7625_data *ctx) 966 { 967 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 968 XTAL_FRQ_SEL, XTAL_FRQ_27M); 969 } 970 971 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 972 { 973 struct device *dev = &ctx->client->dev; 974 int ret; 975 976 /* Reset main ocm */ 977 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 978 /* Disable PD */ 979 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 980 AP_AV_STATUS, AP_DISABLE_PD); 981 /* Release main ocm */ 982 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 983 984 if (ret < 0) 985 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 986 else 987 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 988 } 989 990 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 991 { 992 int ret; 993 struct device *dev = &ctx->client->dev; 994 995 /* Check interface workable */ 996 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 997 FLASH_LOAD_STA); 998 if (ret < 0) { 999 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1000 return ret; 1001 } 1002 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1003 return -ENODEV; 1004 1005 anx7625_disable_pd_protocol(ctx); 1006 1007 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1008 anx7625_reg_read(ctx, 1009 ctx->i2c.rx_p0_client, 1010 OCM_FW_VERSION), 1011 anx7625_reg_read(ctx, 1012 ctx->i2c.rx_p0_client, 1013 OCM_FW_REVERSION)); 1014 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1015 ANX7625_DRV_VERSION); 1016 1017 return 0; 1018 } 1019 1020 static void anx7625_power_on_init(struct anx7625_data *ctx) 1021 { 1022 int retry_count, i; 1023 1024 for (retry_count = 0; retry_count < 3; retry_count++) { 1025 anx7625_power_on(ctx); 1026 anx7625_config(ctx); 1027 1028 for (i = 0; i < OCM_LOADING_TIME; i++) { 1029 if (!anx7625_ocm_loading_check(ctx)) 1030 return; 1031 usleep_range(1000, 1100); 1032 } 1033 anx7625_power_standby(ctx); 1034 } 1035 } 1036 1037 static void anx7625_init_gpio(struct anx7625_data *platform) 1038 { 1039 struct device *dev = &platform->client->dev; 1040 1041 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1042 1043 /* Gpio for chip power enable */ 1044 platform->pdata.gpio_p_on = 1045 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1046 /* Gpio for chip reset */ 1047 platform->pdata.gpio_reset = 1048 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1049 1050 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1051 platform->pdata.low_power_mode = 1; 1052 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1053 desc_to_gpio(platform->pdata.gpio_p_on), 1054 desc_to_gpio(platform->pdata.gpio_reset)); 1055 } else { 1056 platform->pdata.low_power_mode = 0; 1057 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1058 } 1059 } 1060 1061 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1062 { 1063 ctx->hpd_status = 0; 1064 ctx->hpd_high_cnt = 0; 1065 ctx->display_timing_valid = 0; 1066 } 1067 1068 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1069 { 1070 int ret; 1071 struct device *dev = &ctx->client->dev; 1072 1073 if (ctx->hpd_high_cnt >= 2) { 1074 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1075 return; 1076 } 1077 1078 ctx->hpd_high_cnt++; 1079 1080 /* Not support HDCP */ 1081 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1082 1083 /* Try auth flag */ 1084 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1085 /* Interrupt for DRM */ 1086 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1087 if (ret < 0) 1088 return; 1089 1090 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1091 if (ret < 0) 1092 return; 1093 1094 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1095 } 1096 1097 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1098 { 1099 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1100 } 1101 1102 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1103 { 1104 int ret, val; 1105 struct device *dev = &ctx->client->dev; 1106 1107 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1108 ctx, val, 1109 ((val & HPD_STATUS) || (val < 0)), 1110 5000, 1111 5000 * 100); 1112 if (ret) { 1113 DRM_DEV_ERROR(dev, "no hpd.\n"); 1114 return; 1115 } 1116 1117 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1118 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1119 INTR_ALERT_1, 0xFF); 1120 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1121 INTERFACE_CHANGE_INT, 0); 1122 1123 anx7625_start_dp_work(ctx); 1124 1125 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1126 drm_helper_hpd_irq_event(ctx->bridge.dev); 1127 } 1128 1129 static void anx7625_remove_edid(struct anx7625_data *ctx) 1130 { 1131 ctx->slimport_edid_p.edid_block_num = -1; 1132 } 1133 1134 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1135 { 1136 struct device *dev = &ctx->client->dev; 1137 1138 /* HPD changed */ 1139 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1140 (u32)on); 1141 1142 if (on == 0) { 1143 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1144 anx7625_remove_edid(ctx); 1145 anx7625_stop_dp_work(ctx); 1146 } else { 1147 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1148 anx7625_start_dp_work(ctx); 1149 } 1150 1151 ctx->hpd_status = 1; 1152 } 1153 1154 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1155 { 1156 int intr_vector, status; 1157 struct device *dev = &ctx->client->dev; 1158 1159 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1160 INTR_ALERT_1, 0xFF); 1161 if (status < 0) { 1162 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1163 return status; 1164 } 1165 1166 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1167 INTERFACE_CHANGE_INT); 1168 if (intr_vector < 0) { 1169 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1170 return intr_vector; 1171 } 1172 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1173 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1174 INTERFACE_CHANGE_INT, 1175 intr_vector & (~intr_vector)); 1176 if (status < 0) { 1177 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1178 return status; 1179 } 1180 1181 if (!(intr_vector & HPD_STATUS_CHANGE)) 1182 return -ENOENT; 1183 1184 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1185 SYSTEM_STSTUS); 1186 if (status < 0) { 1187 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1188 return status; 1189 } 1190 1191 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1192 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1193 1194 return 0; 1195 } 1196 1197 static void anx7625_work_func(struct work_struct *work) 1198 { 1199 int event; 1200 struct anx7625_data *ctx = container_of(work, 1201 struct anx7625_data, work); 1202 1203 mutex_lock(&ctx->lock); 1204 1205 if (pm_runtime_suspended(&ctx->client->dev)) 1206 goto unlock; 1207 1208 event = anx7625_hpd_change_detect(ctx); 1209 if (event < 0) 1210 goto unlock; 1211 1212 if (ctx->bridge_attached) 1213 drm_helper_hpd_irq_event(ctx->bridge.dev); 1214 1215 unlock: 1216 mutex_unlock(&ctx->lock); 1217 } 1218 1219 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1220 { 1221 struct anx7625_data *ctx = (struct anx7625_data *)data; 1222 1223 queue_work(ctx->workqueue, &ctx->work); 1224 1225 return IRQ_HANDLED; 1226 } 1227 1228 static int anx7625_parse_dt(struct device *dev, 1229 struct anx7625_platform_data *pdata) 1230 { 1231 struct device_node *np = dev->of_node; 1232 struct drm_panel *panel; 1233 int ret; 1234 1235 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1236 if (!pdata->mipi_host_node) { 1237 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1238 return -ENODEV; 1239 } 1240 1241 DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n"); 1242 1243 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1244 if (ret < 0) { 1245 if (ret == -ENODEV) 1246 return 0; 1247 return ret; 1248 } 1249 if (!panel) 1250 return -ENODEV; 1251 1252 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1253 if (IS_ERR(pdata->panel_bridge)) 1254 return PTR_ERR(pdata->panel_bridge); 1255 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1256 1257 return 0; 1258 } 1259 1260 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1261 { 1262 return container_of(bridge, struct anx7625_data, bridge); 1263 } 1264 1265 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1266 { 1267 struct device *dev = &ctx->client->dev; 1268 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1269 int edid_num; 1270 u8 *edid; 1271 1272 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1273 if (!edid) { 1274 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1275 return NULL; 1276 } 1277 1278 if (ctx->slimport_edid_p.edid_block_num > 0) { 1279 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1280 FOUR_BLOCK_SIZE); 1281 return (struct edid *)edid; 1282 } 1283 1284 pm_runtime_get_sync(dev); 1285 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1286 pm_runtime_put_sync(dev); 1287 1288 if (edid_num < 1) { 1289 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1290 kfree(edid); 1291 return NULL; 1292 } 1293 1294 p_edid->edid_block_num = edid_num; 1295 1296 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1297 return (struct edid *)edid; 1298 } 1299 1300 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1301 { 1302 struct device *dev = &ctx->client->dev; 1303 1304 DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n"); 1305 1306 return connector_status_connected; 1307 } 1308 1309 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1310 { 1311 struct mipi_dsi_device *dsi; 1312 struct device *dev = &ctx->client->dev; 1313 struct mipi_dsi_host *host; 1314 const struct mipi_dsi_device_info info = { 1315 .type = "anx7625", 1316 .channel = 0, 1317 .node = NULL, 1318 }; 1319 1320 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1321 1322 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1323 if (!host) { 1324 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1325 return -EINVAL; 1326 } 1327 1328 dsi = mipi_dsi_device_register_full(host, &info); 1329 if (IS_ERR(dsi)) { 1330 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 1331 return -EINVAL; 1332 } 1333 1334 dsi->lanes = 4; 1335 dsi->format = MIPI_DSI_FMT_RGB888; 1336 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1337 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1338 MIPI_DSI_MODE_VIDEO_HSE; 1339 1340 if (mipi_dsi_attach(dsi) < 0) { 1341 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 1342 mipi_dsi_device_unregister(dsi); 1343 return -EINVAL; 1344 } 1345 1346 ctx->dsi = dsi; 1347 1348 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 1349 1350 return 0; 1351 } 1352 1353 static void anx7625_bridge_detach(struct drm_bridge *bridge) 1354 { 1355 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1356 1357 if (ctx->dsi) { 1358 mipi_dsi_detach(ctx->dsi); 1359 mipi_dsi_device_unregister(ctx->dsi); 1360 } 1361 } 1362 1363 static int anx7625_bridge_attach(struct drm_bridge *bridge, 1364 enum drm_bridge_attach_flags flags) 1365 { 1366 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1367 int err; 1368 struct device *dev = &ctx->client->dev; 1369 1370 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 1371 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 1372 return -EINVAL; 1373 1374 if (!bridge->encoder) { 1375 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 1376 return -ENODEV; 1377 } 1378 1379 err = anx7625_attach_dsi(ctx); 1380 if (err) { 1381 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); 1382 return err; 1383 } 1384 1385 if (ctx->pdata.panel_bridge) { 1386 err = drm_bridge_attach(bridge->encoder, 1387 ctx->pdata.panel_bridge, 1388 &ctx->bridge, flags); 1389 if (err) 1390 return err; 1391 } 1392 1393 ctx->bridge_attached = 1; 1394 1395 return 0; 1396 } 1397 1398 static enum drm_mode_status 1399 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 1400 const struct drm_display_info *info, 1401 const struct drm_display_mode *mode) 1402 { 1403 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1404 struct device *dev = &ctx->client->dev; 1405 1406 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 1407 1408 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 1409 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 1410 DRM_DEV_DEBUG_DRIVER(dev, 1411 "drm mode invalid, pixelclock too high.\n"); 1412 return MODE_CLOCK_HIGH; 1413 } 1414 1415 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 1416 1417 return MODE_OK; 1418 } 1419 1420 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 1421 const struct drm_display_mode *old_mode, 1422 const struct drm_display_mode *mode) 1423 { 1424 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1425 struct device *dev = &ctx->client->dev; 1426 1427 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 1428 1429 ctx->dt.pixelclock.min = mode->clock; 1430 ctx->dt.hactive.min = mode->hdisplay; 1431 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 1432 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 1433 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 1434 ctx->dt.vactive.min = mode->vdisplay; 1435 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 1436 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 1437 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 1438 1439 ctx->display_timing_valid = 1; 1440 1441 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 1442 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 1443 ctx->dt.hactive.min, 1444 ctx->dt.hsync_len.min, 1445 ctx->dt.hfront_porch.min, 1446 ctx->dt.hback_porch.min); 1447 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 1448 ctx->dt.vactive.min, 1449 ctx->dt.vsync_len.min, 1450 ctx->dt.vfront_porch.min, 1451 ctx->dt.vback_porch.min); 1452 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 1453 mode->hdisplay, 1454 mode->hsync_start); 1455 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 1456 mode->hsync_end, 1457 mode->htotal); 1458 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 1459 mode->vdisplay, 1460 mode->vsync_start); 1461 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 1462 mode->vsync_end, 1463 mode->vtotal); 1464 } 1465 1466 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 1467 const struct drm_display_mode *mode, 1468 struct drm_display_mode *adj) 1469 { 1470 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1471 struct device *dev = &ctx->client->dev; 1472 u32 hsync, hfp, hbp, hblanking; 1473 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 1474 u32 vref, adj_clock; 1475 1476 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 1477 1478 hsync = mode->hsync_end - mode->hsync_start; 1479 hfp = mode->hsync_start - mode->hdisplay; 1480 hbp = mode->htotal - mode->hsync_end; 1481 hblanking = mode->htotal - mode->hdisplay; 1482 1483 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 1484 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1485 hsync, hfp, hbp, adj->clock); 1486 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1487 adj->hsync_start, adj->hsync_end, adj->htotal); 1488 1489 adj_hfp = hfp; 1490 adj_hsync = hsync; 1491 adj_hbp = hbp; 1492 adj_hblanking = hblanking; 1493 1494 /* HFP needs to be even */ 1495 if (hfp & 0x1) { 1496 adj_hfp += 1; 1497 adj_hblanking += 1; 1498 } 1499 1500 /* HBP needs to be even */ 1501 if (hbp & 0x1) { 1502 adj_hbp -= 1; 1503 adj_hblanking -= 1; 1504 } 1505 1506 /* HSYNC needs to be even */ 1507 if (hsync & 0x1) { 1508 if (adj_hblanking < hblanking) 1509 adj_hsync += 1; 1510 else 1511 adj_hsync -= 1; 1512 } 1513 1514 /* 1515 * Once illegal timing detected, use default HFP, HSYNC, HBP 1516 * This adjusting made for built-in eDP panel, for the externel 1517 * DP monitor, may need return false. 1518 */ 1519 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 1520 adj_hsync = SYNC_LEN_DEF; 1521 adj_hfp = HFP_HBP_DEF; 1522 adj_hbp = HFP_HBP_DEF; 1523 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 1524 if (hblanking < HBLANKING_MIN) { 1525 delta_adj = HBLANKING_MIN - hblanking; 1526 adj_clock = vref * delta_adj * adj->vtotal; 1527 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 1528 } else { 1529 delta_adj = hblanking - HBLANKING_MIN; 1530 adj_clock = vref * delta_adj * adj->vtotal; 1531 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 1532 } 1533 1534 DRM_WARN("illegal hblanking timing, use default.\n"); 1535 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 1536 } else if (adj_hfp < HP_MIN) { 1537 /* Adjust hfp if hfp less than HP_MIN */ 1538 delta_adj = HP_MIN - adj_hfp; 1539 adj_hfp = HP_MIN; 1540 1541 /* 1542 * Balance total HBlanking pixel, if HBP does not have enough 1543 * space, adjust HSYNC length, otherwise adjust HBP 1544 */ 1545 if ((adj_hbp - delta_adj) < HP_MIN) 1546 /* HBP not enough space */ 1547 adj_hsync -= delta_adj; 1548 else 1549 adj_hbp -= delta_adj; 1550 } else if (adj_hbp < HP_MIN) { 1551 delta_adj = HP_MIN - adj_hbp; 1552 adj_hbp = HP_MIN; 1553 1554 /* 1555 * Balance total HBlanking pixel, if HBP hasn't enough space, 1556 * adjust HSYNC length, otherwize adjust HBP 1557 */ 1558 if ((adj_hfp - delta_adj) < HP_MIN) 1559 /* HFP not enough space */ 1560 adj_hsync -= delta_adj; 1561 else 1562 adj_hfp -= delta_adj; 1563 } 1564 1565 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 1566 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1567 adj_hsync, adj_hfp, adj_hbp, adj->clock); 1568 1569 /* Reconstruct timing */ 1570 adj->hsync_start = adj->hdisplay + adj_hfp; 1571 adj->hsync_end = adj->hsync_start + adj_hsync; 1572 adj->htotal = adj->hsync_end + adj_hbp; 1573 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1574 adj->hsync_start, adj->hsync_end, adj->htotal); 1575 1576 return true; 1577 } 1578 1579 static void anx7625_bridge_enable(struct drm_bridge *bridge) 1580 { 1581 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1582 struct device *dev = &ctx->client->dev; 1583 1584 DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 1585 1586 pm_runtime_get_sync(dev); 1587 1588 anx7625_dp_start(ctx); 1589 } 1590 1591 static void anx7625_bridge_disable(struct drm_bridge *bridge) 1592 { 1593 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1594 struct device *dev = &ctx->client->dev; 1595 1596 DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 1597 1598 anx7625_dp_stop(ctx); 1599 1600 pm_runtime_put_sync(dev); 1601 } 1602 1603 static enum drm_connector_status 1604 anx7625_bridge_detect(struct drm_bridge *bridge) 1605 { 1606 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1607 struct device *dev = &ctx->client->dev; 1608 1609 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 1610 1611 return anx7625_sink_detect(ctx); 1612 } 1613 1614 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 1615 struct drm_connector *connector) 1616 { 1617 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1618 struct device *dev = &ctx->client->dev; 1619 1620 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 1621 1622 return anx7625_get_edid(ctx); 1623 } 1624 1625 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 1626 .attach = anx7625_bridge_attach, 1627 .detach = anx7625_bridge_detach, 1628 .disable = anx7625_bridge_disable, 1629 .mode_valid = anx7625_bridge_mode_valid, 1630 .mode_set = anx7625_bridge_mode_set, 1631 .mode_fixup = anx7625_bridge_mode_fixup, 1632 .enable = anx7625_bridge_enable, 1633 .detect = anx7625_bridge_detect, 1634 .get_edid = anx7625_bridge_get_edid, 1635 }; 1636 1637 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 1638 struct i2c_client *client) 1639 { 1640 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 1641 TX_P0_ADDR >> 1); 1642 if (!ctx->i2c.tx_p0_client) 1643 return -ENOMEM; 1644 1645 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 1646 TX_P1_ADDR >> 1); 1647 if (!ctx->i2c.tx_p1_client) 1648 goto free_tx_p0; 1649 1650 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 1651 TX_P2_ADDR >> 1); 1652 if (!ctx->i2c.tx_p2_client) 1653 goto free_tx_p1; 1654 1655 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 1656 RX_P0_ADDR >> 1); 1657 if (!ctx->i2c.rx_p0_client) 1658 goto free_tx_p2; 1659 1660 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 1661 RX_P1_ADDR >> 1); 1662 if (!ctx->i2c.rx_p1_client) 1663 goto free_rx_p0; 1664 1665 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 1666 RX_P2_ADDR >> 1); 1667 if (!ctx->i2c.rx_p2_client) 1668 goto free_rx_p1; 1669 1670 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 1671 TCPC_INTERFACE_ADDR >> 1); 1672 if (!ctx->i2c.tcpc_client) 1673 goto free_rx_p2; 1674 1675 return 0; 1676 1677 free_rx_p2: 1678 i2c_unregister_device(ctx->i2c.rx_p2_client); 1679 free_rx_p1: 1680 i2c_unregister_device(ctx->i2c.rx_p1_client); 1681 free_rx_p0: 1682 i2c_unregister_device(ctx->i2c.rx_p0_client); 1683 free_tx_p2: 1684 i2c_unregister_device(ctx->i2c.tx_p2_client); 1685 free_tx_p1: 1686 i2c_unregister_device(ctx->i2c.tx_p1_client); 1687 free_tx_p0: 1688 i2c_unregister_device(ctx->i2c.tx_p0_client); 1689 1690 return -ENOMEM; 1691 } 1692 1693 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 1694 { 1695 i2c_unregister_device(ctx->i2c.tx_p0_client); 1696 i2c_unregister_device(ctx->i2c.tx_p1_client); 1697 i2c_unregister_device(ctx->i2c.tx_p2_client); 1698 i2c_unregister_device(ctx->i2c.rx_p0_client); 1699 i2c_unregister_device(ctx->i2c.rx_p1_client); 1700 i2c_unregister_device(ctx->i2c.rx_p2_client); 1701 i2c_unregister_device(ctx->i2c.tcpc_client); 1702 } 1703 1704 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 1705 { 1706 struct anx7625_data *ctx = dev_get_drvdata(dev); 1707 1708 mutex_lock(&ctx->lock); 1709 1710 anx7625_stop_dp_work(ctx); 1711 anx7625_power_standby(ctx); 1712 1713 mutex_unlock(&ctx->lock); 1714 1715 return 0; 1716 } 1717 1718 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 1719 { 1720 struct anx7625_data *ctx = dev_get_drvdata(dev); 1721 1722 mutex_lock(&ctx->lock); 1723 1724 anx7625_power_on_init(ctx); 1725 anx7625_hpd_polling(ctx); 1726 1727 mutex_unlock(&ctx->lock); 1728 1729 return 0; 1730 } 1731 1732 static int __maybe_unused anx7625_resume(struct device *dev) 1733 { 1734 struct anx7625_data *ctx = dev_get_drvdata(dev); 1735 1736 if (!ctx->pdata.intp_irq) 1737 return 0; 1738 1739 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1740 enable_irq(ctx->pdata.intp_irq); 1741 anx7625_runtime_pm_resume(dev); 1742 } 1743 1744 return 0; 1745 } 1746 1747 static int __maybe_unused anx7625_suspend(struct device *dev) 1748 { 1749 struct anx7625_data *ctx = dev_get_drvdata(dev); 1750 1751 if (!ctx->pdata.intp_irq) 1752 return 0; 1753 1754 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1755 anx7625_runtime_pm_suspend(dev); 1756 disable_irq(ctx->pdata.intp_irq); 1757 } 1758 1759 return 0; 1760 } 1761 1762 static const struct dev_pm_ops anx7625_pm_ops = { 1763 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 1764 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 1765 anx7625_runtime_pm_resume, NULL) 1766 }; 1767 1768 static int anx7625_i2c_probe(struct i2c_client *client, 1769 const struct i2c_device_id *id) 1770 { 1771 struct anx7625_data *platform; 1772 struct anx7625_platform_data *pdata; 1773 int ret = 0; 1774 struct device *dev = &client->dev; 1775 1776 if (!i2c_check_functionality(client->adapter, 1777 I2C_FUNC_SMBUS_I2C_BLOCK)) { 1778 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 1779 return -ENODEV; 1780 } 1781 1782 platform = kzalloc(sizeof(*platform), GFP_KERNEL); 1783 if (!platform) { 1784 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 1785 return -ENOMEM; 1786 } 1787 1788 pdata = &platform->pdata; 1789 1790 ret = anx7625_parse_dt(dev, pdata); 1791 if (ret) { 1792 if (ret != -EPROBE_DEFER) 1793 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 1794 goto free_platform; 1795 } 1796 1797 platform->client = client; 1798 i2c_set_clientdata(client, platform); 1799 1800 pdata->supplies[0].supply = "vdd10"; 1801 pdata->supplies[1].supply = "vdd18"; 1802 pdata->supplies[2].supply = "vdd33"; 1803 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 1804 pdata->supplies); 1805 if (ret) { 1806 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 1807 return ret; 1808 } 1809 anx7625_init_gpio(platform); 1810 1811 mutex_init(&platform->lock); 1812 1813 platform->pdata.intp_irq = client->irq; 1814 if (platform->pdata.intp_irq) { 1815 INIT_WORK(&platform->work, anx7625_work_func); 1816 platform->workqueue = alloc_workqueue("anx7625_work", 1817 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 1818 if (!platform->workqueue) { 1819 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 1820 ret = -ENOMEM; 1821 goto free_platform; 1822 } 1823 1824 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 1825 NULL, anx7625_intr_hpd_isr, 1826 IRQF_TRIGGER_FALLING | 1827 IRQF_ONESHOT, 1828 "anx7625-intp", platform); 1829 if (ret) { 1830 DRM_DEV_ERROR(dev, "fail to request irq\n"); 1831 goto free_wq; 1832 } 1833 } 1834 1835 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 1836 ret = -ENOMEM; 1837 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 1838 goto free_wq; 1839 } 1840 1841 pm_runtime_enable(dev); 1842 1843 if (!platform->pdata.low_power_mode) { 1844 anx7625_disable_pd_protocol(platform); 1845 pm_runtime_get_sync(dev); 1846 } 1847 1848 /* Add work function */ 1849 if (platform->pdata.intp_irq) 1850 queue_work(platform->workqueue, &platform->work); 1851 1852 platform->bridge.funcs = &anx7625_bridge_funcs; 1853 platform->bridge.of_node = client->dev.of_node; 1854 platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 1855 platform->bridge.type = DRM_MODE_CONNECTOR_eDP; 1856 drm_bridge_add(&platform->bridge); 1857 1858 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 1859 1860 return 0; 1861 1862 free_wq: 1863 if (platform->workqueue) 1864 destroy_workqueue(platform->workqueue); 1865 1866 free_platform: 1867 kfree(platform); 1868 1869 return ret; 1870 } 1871 1872 static int anx7625_i2c_remove(struct i2c_client *client) 1873 { 1874 struct anx7625_data *platform = i2c_get_clientdata(client); 1875 1876 drm_bridge_remove(&platform->bridge); 1877 1878 if (platform->pdata.intp_irq) 1879 destroy_workqueue(platform->workqueue); 1880 1881 if (!platform->pdata.low_power_mode) 1882 pm_runtime_put_sync_suspend(&client->dev); 1883 1884 anx7625_unregister_i2c_dummy_clients(platform); 1885 1886 kfree(platform); 1887 return 0; 1888 } 1889 1890 static const struct i2c_device_id anx7625_id[] = { 1891 {"anx7625", 0}, 1892 {} 1893 }; 1894 1895 MODULE_DEVICE_TABLE(i2c, anx7625_id); 1896 1897 static const struct of_device_id anx_match_table[] = { 1898 {.compatible = "analogix,anx7625",}, 1899 {}, 1900 }; 1901 MODULE_DEVICE_TABLE(of, anx_match_table); 1902 1903 static struct i2c_driver anx7625_driver = { 1904 .driver = { 1905 .name = "anx7625", 1906 .of_match_table = anx_match_table, 1907 .pm = &anx7625_pm_ops, 1908 }, 1909 .probe = anx7625_i2c_probe, 1910 .remove = anx7625_i2c_remove, 1911 1912 .id_table = anx7625_id, 1913 }; 1914 1915 module_i2c_driver(anx7625_driver); 1916 1917 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 1918 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 1919 MODULE_LICENSE("GPL v2"); 1920 MODULE_VERSION(ANX7625_DRV_VERSION); 1921