1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/dp/drm_dp_aux_bus.h> 28 #include <drm/dp/drm_dp_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_hdcp.h> 31 #include <drm/drm_mipi_dsi.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_panel.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include <media/v4l2-fwnode.h> 38 #include <sound/hdmi-codec.h> 39 #include <video/display_timing.h> 40 41 #include "anx7625.h" 42 43 /* 44 * There is a sync issue while access I2C register between AP(CPU) and 45 * internal firmware(OCM), to avoid the race condition, AP should access 46 * the reserved slave address before slave address occurs changes. 47 */ 48 static int i2c_access_workaround(struct anx7625_data *ctx, 49 struct i2c_client *client) 50 { 51 u8 offset; 52 struct device *dev = &client->dev; 53 int ret; 54 55 if (client == ctx->last_client) 56 return 0; 57 58 ctx->last_client = client; 59 60 if (client == ctx->i2c.tcpc_client) 61 offset = RSVD_00_ADDR; 62 else if (client == ctx->i2c.tx_p0_client) 63 offset = RSVD_D1_ADDR; 64 else if (client == ctx->i2c.tx_p1_client) 65 offset = RSVD_60_ADDR; 66 else if (client == ctx->i2c.rx_p0_client) 67 offset = RSVD_39_ADDR; 68 else if (client == ctx->i2c.rx_p1_client) 69 offset = RSVD_7F_ADDR; 70 else 71 offset = RSVD_00_ADDR; 72 73 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 74 if (ret < 0) 75 DRM_DEV_ERROR(dev, 76 "fail to access i2c id=%x\n:%x", 77 client->addr, offset); 78 79 return ret; 80 } 81 82 static int anx7625_reg_read(struct anx7625_data *ctx, 83 struct i2c_client *client, u8 reg_addr) 84 { 85 int ret; 86 struct device *dev = &client->dev; 87 88 i2c_access_workaround(ctx, client); 89 90 ret = i2c_smbus_read_byte_data(client, reg_addr); 91 if (ret < 0) 92 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 93 client->addr, reg_addr); 94 95 return ret; 96 } 97 98 static int anx7625_reg_block_read(struct anx7625_data *ctx, 99 struct i2c_client *client, 100 u8 reg_addr, u8 len, u8 *buf) 101 { 102 int ret; 103 struct device *dev = &client->dev; 104 105 i2c_access_workaround(ctx, client); 106 107 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 108 if (ret < 0) 109 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 110 client->addr, reg_addr); 111 112 return ret; 113 } 114 115 static int anx7625_reg_write(struct anx7625_data *ctx, 116 struct i2c_client *client, 117 u8 reg_addr, u8 reg_val) 118 { 119 int ret; 120 struct device *dev = &client->dev; 121 122 i2c_access_workaround(ctx, client); 123 124 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 125 126 if (ret < 0) 127 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 128 client->addr, reg_addr); 129 130 return ret; 131 } 132 133 static int anx7625_reg_block_write(struct anx7625_data *ctx, 134 struct i2c_client *client, 135 u8 reg_addr, u8 len, u8 *buf) 136 { 137 int ret; 138 struct device *dev = &client->dev; 139 140 i2c_access_workaround(ctx, client); 141 142 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 143 if (ret < 0) 144 dev_err(dev, "write i2c block failed id=%x\n:%x", 145 client->addr, reg_addr); 146 147 return ret; 148 } 149 150 static int anx7625_write_or(struct anx7625_data *ctx, 151 struct i2c_client *client, 152 u8 offset, u8 mask) 153 { 154 int val; 155 156 val = anx7625_reg_read(ctx, client, offset); 157 if (val < 0) 158 return val; 159 160 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 161 } 162 163 static int anx7625_write_and(struct anx7625_data *ctx, 164 struct i2c_client *client, 165 u8 offset, u8 mask) 166 { 167 int val; 168 169 val = anx7625_reg_read(ctx, client, offset); 170 if (val < 0) 171 return val; 172 173 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 174 } 175 176 static int anx7625_write_and_or(struct anx7625_data *ctx, 177 struct i2c_client *client, 178 u8 offset, u8 and_mask, u8 or_mask) 179 { 180 int val; 181 182 val = anx7625_reg_read(ctx, client, offset); 183 if (val < 0) 184 return val; 185 186 return anx7625_reg_write(ctx, client, 187 offset, (val & and_mask) | (or_mask)); 188 } 189 190 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 191 { 192 int i, ret; 193 194 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 195 AUDIO_CONTROL_REGISTER, 0x80); 196 for (i = 0; i < 13; i++) 197 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 198 VIDEO_BIT_MATRIX_12 + i, 199 0x18 + i); 200 201 return ret; 202 } 203 204 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 205 { 206 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 207 } 208 209 static int wait_aux_op_finish(struct anx7625_data *ctx) 210 { 211 struct device *dev = &ctx->client->dev; 212 int val; 213 int ret; 214 215 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 216 ctx, val, 217 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 218 2000, 219 2000 * 150); 220 if (ret) { 221 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 222 return -EIO; 223 } 224 225 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 226 AP_AUX_CTRL_STATUS); 227 if (val < 0 || (val & 0x0F)) { 228 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 229 return -EIO; 230 } 231 232 return 0; 233 } 234 235 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 236 u8 len, u8 *buf) 237 { 238 struct device *dev = &ctx->client->dev; 239 int ret; 240 u8 addrh, addrm, addrl; 241 u8 cmd; 242 bool is_write = !(op & DP_AUX_I2C_READ); 243 244 if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 245 dev_err(dev, "exceed aux buffer len.\n"); 246 return -EINVAL; 247 } 248 249 if (!len) 250 return len; 251 252 addrl = address & 0xFF; 253 addrm = (address >> 8) & 0xFF; 254 addrh = (address >> 16) & 0xFF; 255 256 cmd = DPCD_CMD(len, op); 257 258 /* Set command and length */ 259 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 260 AP_AUX_COMMAND, cmd); 261 262 /* Set aux access address */ 263 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 264 AP_AUX_ADDR_7_0, addrl); 265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 266 AP_AUX_ADDR_15_8, addrm); 267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 268 AP_AUX_ADDR_19_16, addrh); 269 270 if (is_write) 271 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 272 AP_AUX_BUFF_START, len, buf); 273 /* Enable aux access */ 274 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 275 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 276 277 if (ret < 0) { 278 dev_err(dev, "cannot access aux related register.\n"); 279 return -EIO; 280 } 281 282 ret = wait_aux_op_finish(ctx); 283 if (ret < 0) { 284 dev_err(dev, "aux IO error: wait aux op finish.\n"); 285 return ret; 286 } 287 288 /* Write done */ 289 if (is_write) 290 return len; 291 292 /* Read done, read out dpcd data */ 293 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 294 AP_AUX_BUFF_START, len, buf); 295 if (ret < 0) { 296 dev_err(dev, "read dpcd register failed\n"); 297 return -EIO; 298 } 299 300 return len; 301 } 302 303 static int anx7625_video_mute_control(struct anx7625_data *ctx, 304 u8 status) 305 { 306 int ret; 307 308 if (status) { 309 /* Set mute on flag */ 310 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 311 AP_AV_STATUS, AP_MIPI_MUTE); 312 /* Clear mipi RX en */ 313 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 314 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 315 } else { 316 /* Mute off flag */ 317 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 318 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 319 /* Set MIPI RX EN */ 320 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 321 AP_AV_STATUS, AP_MIPI_RX_EN); 322 } 323 324 return ret; 325 } 326 327 /* Reduction of fraction a/b */ 328 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 329 { 330 unsigned long gcd_num; 331 unsigned long tmp_a, tmp_b; 332 u32 i = 1; 333 334 gcd_num = gcd(*a, *b); 335 *a /= gcd_num; 336 *b /= gcd_num; 337 338 tmp_a = *a; 339 tmp_b = *b; 340 341 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 342 i++; 343 *a = tmp_a / i; 344 *b = tmp_b / i; 345 } 346 347 /* 348 * In the end, make a, b larger to have higher ODFC PLL 349 * output frequency accuracy 350 */ 351 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 352 *a <<= 1; 353 *b <<= 1; 354 } 355 356 *a >>= 1; 357 *b >>= 1; 358 } 359 360 static int anx7625_calculate_m_n(u32 pixelclock, 361 unsigned long *m, 362 unsigned long *n, 363 u8 *post_divider) 364 { 365 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 366 /* Pixel clock frequency is too high */ 367 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 368 pixelclock, 369 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 370 return -EINVAL; 371 } 372 373 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 374 /* Pixel clock frequency is too low */ 375 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 376 pixelclock, 377 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 378 return -EINVAL; 379 } 380 381 for (*post_divider = 1; 382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 383 *post_divider += 1; 384 385 if (*post_divider > POST_DIVIDER_MAX) { 386 for (*post_divider = 1; 387 (pixelclock < 388 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 389 *post_divider += 1; 390 391 if (*post_divider > POST_DIVIDER_MAX) { 392 DRM_ERROR("cannot find property post_divider(%d)\n", 393 *post_divider); 394 return -EDOM; 395 } 396 } 397 398 /* Patch to improve the accuracy */ 399 if (*post_divider == 7) { 400 /* 27,000,000 is not divisible by 7 */ 401 *post_divider = 8; 402 } else if (*post_divider == 11) { 403 /* 27,000,000 is not divisible by 11 */ 404 *post_divider = 12; 405 } else if ((*post_divider == 13) || (*post_divider == 14)) { 406 /* 27,000,000 is not divisible by 13 or 14 */ 407 *post_divider = 15; 408 } 409 410 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 411 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 412 pixelclock * (*post_divider), 413 PLL_OUT_FREQ_ABS_MAX); 414 return -EDOM; 415 } 416 417 *m = pixelclock; 418 *n = XTAL_FRQ / (*post_divider); 419 420 anx7625_reduction_of_a_fraction(m, n); 421 422 return 0; 423 } 424 425 static int anx7625_odfc_config(struct anx7625_data *ctx, 426 u8 post_divider) 427 { 428 int ret; 429 struct device *dev = &ctx->client->dev; 430 431 /* Config input reference clock frequency 27MHz/19.2MHz */ 432 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 433 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 434 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 435 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 436 /* Post divider */ 437 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 438 MIPI_DIGITAL_PLL_8, 0x0f); 439 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 440 post_divider << 4); 441 442 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 443 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 444 ~MIPI_PLL_VCO_TUNE_REG_VAL); 445 446 /* Reset ODFC PLL */ 447 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 448 ~MIPI_PLL_RESET_N); 449 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 450 MIPI_PLL_RESET_N); 451 452 if (ret < 0) 453 DRM_DEV_ERROR(dev, "IO error.\n"); 454 455 return ret; 456 } 457 458 /* 459 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 460 * anx7625 defined K ratio for matching MIPI input video clock and 461 * DP output video clock. Increase K value can match bigger video data 462 * variation. IVO panel has small variation than DP CTS spec, need 463 * decrease the K value. 464 */ 465 static int anx7625_set_k_value(struct anx7625_data *ctx) 466 { 467 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 468 469 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 470 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 471 MIPI_DIGITAL_ADJ_1, 0x3B); 472 473 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 474 MIPI_DIGITAL_ADJ_1, 0x3D); 475 } 476 477 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 478 { 479 struct device *dev = &ctx->client->dev; 480 unsigned long m, n; 481 u16 htotal; 482 int ret; 483 u8 post_divider = 0; 484 485 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 486 &m, &n, &post_divider); 487 488 if (ret) { 489 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 490 return ret; 491 } 492 493 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 494 m, n, post_divider); 495 496 /* Configure pixel clock */ 497 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 498 (ctx->dt.pixelclock.min / 1000) & 0xFF); 499 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 500 (ctx->dt.pixelclock.min / 1000) >> 8); 501 /* Lane count */ 502 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 503 MIPI_LANE_CTRL_0, 0xfc); 504 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 505 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 506 507 /* Htotal */ 508 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 509 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 510 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 511 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 513 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 514 /* Hactive */ 515 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 516 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 518 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 519 /* HFP */ 520 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 521 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 523 HORIZONTAL_FRONT_PORCH_H, 524 ctx->dt.hfront_porch.min >> 8); 525 /* HWS */ 526 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 527 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 529 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 530 /* HBP */ 531 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 532 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 534 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 535 /* Vactive */ 536 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 537 ctx->dt.vactive.min); 538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 539 ctx->dt.vactive.min >> 8); 540 /* VFP */ 541 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 542 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 543 /* VWS */ 544 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 545 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 546 /* VBP */ 547 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 548 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 549 /* M value */ 550 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 551 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 553 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 555 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 556 /* N value */ 557 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 558 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 560 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 562 (n & 0xff)); 563 564 anx7625_set_k_value(ctx); 565 566 ret |= anx7625_odfc_config(ctx, post_divider - 1); 567 568 if (ret < 0) 569 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 570 571 return ret; 572 } 573 574 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 575 { 576 int val; 577 struct device *dev = &ctx->client->dev; 578 579 /* Swap MIPI-DSI data lane 3 P and N */ 580 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 581 if (val < 0) { 582 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 583 return -EIO; 584 } 585 586 val |= (1 << MIPI_SWAP_CH3); 587 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 588 } 589 590 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 591 592 { 593 int val, ret; 594 struct device *dev = &ctx->client->dev; 595 596 /* Swap MIPI-DSI data lane 3 P and N */ 597 ret = anx7625_swap_dsi_lane3(ctx); 598 if (ret < 0) { 599 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 600 return ret; 601 } 602 603 /* DSI clock settings */ 604 val = (0 << MIPI_HS_PWD_CLK) | 605 (0 << MIPI_HS_RT_CLK) | 606 (0 << MIPI_PD_CLK) | 607 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 608 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 609 (0 << MIPI_CLK_DET_DET_BYPASS) | 610 (0 << MIPI_CLK_MISS_CTRL) | 611 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 612 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 613 MIPI_PHY_CONTROL_3, val); 614 615 /* 616 * Decreased HS prepare timing delay from 160ns to 80ns work with 617 * a) Dragon board 810 series (Qualcomm AP) 618 * b) Moving Pixel DSI source (PG3A pattern generator + 619 * P332 D-PHY Probe) default D-PHY timing 620 * 5ns/step 621 */ 622 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 623 MIPI_TIME_HS_PRPR, 0x10); 624 625 /* Enable DSI mode*/ 626 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 627 SELECT_DSI << MIPI_DPI_SELECT); 628 629 ret |= anx7625_dsi_video_timing_config(ctx); 630 if (ret < 0) { 631 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 632 return ret; 633 } 634 635 /* Toggle m, n ready */ 636 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 637 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 638 usleep_range(1000, 1100); 639 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 640 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 641 642 /* Configure integer stable register */ 643 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 644 MIPI_VIDEO_STABLE_CNT, 0x02); 645 /* Power on MIPI RX */ 646 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 647 MIPI_LANE_CTRL_10, 0x00); 648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 649 MIPI_LANE_CTRL_10, 0x80); 650 651 if (ret < 0) 652 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 653 654 return ret; 655 } 656 657 static int anx7625_dsi_config(struct anx7625_data *ctx) 658 { 659 struct device *dev = &ctx->client->dev; 660 int ret; 661 662 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 663 664 /* DSC disable */ 665 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 666 R_DSC_CTRL_0, ~DSC_EN); 667 668 ret |= anx7625_api_dsi_config(ctx); 669 670 if (ret < 0) { 671 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 672 return ret; 673 } 674 675 /* Set MIPI RX EN */ 676 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 677 AP_AV_STATUS, AP_MIPI_RX_EN); 678 /* Clear mute flag */ 679 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 680 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 681 if (ret < 0) 682 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 683 else 684 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 685 686 return ret; 687 } 688 689 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 690 { 691 struct device *dev = &ctx->client->dev; 692 u16 freq = ctx->dt.pixelclock.min / 1000; 693 int ret; 694 695 /* configure pixel clock */ 696 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 697 PIXEL_CLOCK_L, freq & 0xFF); 698 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 699 PIXEL_CLOCK_H, (freq >> 8)); 700 701 /* set DPI mode */ 702 /* set to DPI PLL module sel */ 703 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 704 MIPI_DIGITAL_PLL_9, 0x20); 705 /* power down MIPI */ 706 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 707 MIPI_LANE_CTRL_10, 0x08); 708 /* enable DPI mode */ 709 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 710 MIPI_DIGITAL_PLL_18, 0x1C); 711 /* set first edge */ 712 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 713 VIDEO_CONTROL_0, 0x06); 714 if (ret < 0) 715 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 716 717 return ret; 718 } 719 720 static int anx7625_dpi_config(struct anx7625_data *ctx) 721 { 722 struct device *dev = &ctx->client->dev; 723 int ret; 724 725 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 726 727 /* DSC disable */ 728 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 729 R_DSC_CTRL_0, ~DSC_EN); 730 if (ret < 0) { 731 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 732 return ret; 733 } 734 735 ret = anx7625_config_bit_matrix(ctx); 736 if (ret < 0) { 737 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 738 return ret; 739 } 740 741 ret = anx7625_api_dpi_config(ctx); 742 if (ret < 0) { 743 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 744 return ret; 745 } 746 747 /* set MIPI RX EN */ 748 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 749 AP_AV_STATUS, AP_MIPI_RX_EN); 750 /* clear mute flag */ 751 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 752 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 753 if (ret < 0) 754 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 755 756 return ret; 757 } 758 759 static int anx7625_read_flash_status(struct anx7625_data *ctx) 760 { 761 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 762 } 763 764 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 765 { 766 int ret, val; 767 struct device *dev = &ctx->client->dev; 768 u8 ident[FLASH_BUF_LEN]; 769 770 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 771 FLASH_ADDR_HIGH, 0x91); 772 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 773 FLASH_ADDR_LOW, 0xA0); 774 if (ret < 0) { 775 dev_err(dev, "IO error : set key flash address.\n"); 776 return ret; 777 } 778 779 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 780 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 781 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 782 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 783 if (ret < 0) { 784 dev_err(dev, "IO error : set key flash len.\n"); 785 return ret; 786 } 787 788 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 789 R_FLASH_RW_CTRL, FLASH_READ); 790 ret |= readx_poll_timeout(anx7625_read_flash_status, 791 ctx, val, 792 ((val & FLASH_DONE) || (val < 0)), 793 2000, 794 2000 * 150); 795 if (ret) { 796 dev_err(dev, "flash read access fail!\n"); 797 return -EIO; 798 } 799 800 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 801 FLASH_BUF_BASE_ADDR, 802 FLASH_BUF_LEN, ident); 803 if (ret < 0) { 804 dev_err(dev, "read flash data fail!\n"); 805 return -EIO; 806 } 807 808 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 809 return -EINVAL; 810 811 return 0; 812 } 813 814 static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 815 { 816 int ret; 817 struct device *dev = &ctx->client->dev; 818 819 /* Select HDCP 1.4 KEY */ 820 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 821 R_BOOT_RETRY, 0x12); 822 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 823 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 825 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 830 831 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 832 R_RAM_ADDR_H, 0); 833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 834 R_RAM_ADDR_L, 0); 835 /* Enable HDCP 1.4 KEY load */ 836 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 837 R_RAM_CTRL, DECRYPT_EN | LOAD_START); 838 dev_dbg(dev, "load HDCP 1.4 key done\n"); 839 return ret; 840 } 841 842 static int anx7625_hdcp_disable(struct anx7625_data *ctx) 843 { 844 int ret; 845 struct device *dev = &ctx->client->dev; 846 847 dev_dbg(dev, "disable HDCP 1.4\n"); 848 849 /* Disable HDCP */ 850 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 851 /* Try auth flag */ 852 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 853 /* Interrupt for DRM */ 854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 855 if (ret < 0) 856 dev_err(dev, "fail to disable HDCP\n"); 857 858 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 859 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 860 } 861 862 static int anx7625_hdcp_enable(struct anx7625_data *ctx) 863 { 864 u8 bcap; 865 int ret; 866 struct device *dev = &ctx->client->dev; 867 868 ret = anx7625_hdcp_key_probe(ctx); 869 if (ret) { 870 dev_dbg(dev, "no key found, not to do hdcp\n"); 871 return ret; 872 } 873 874 /* Read downstream capability */ 875 anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap); 876 if (!(bcap & 0x01)) { 877 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 878 return 0; 879 } 880 881 dev_dbg(dev, "enable HDCP 1.4\n"); 882 883 /* First clear HDCP state */ 884 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 885 TX_HDCP_CTRL0, 886 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 887 usleep_range(1000, 1100); 888 /* Second clear HDCP state */ 889 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 890 TX_HDCP_CTRL0, 891 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 892 893 /* Set time for waiting KSVR */ 894 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 895 SP_TX_WAIT_KSVR_TIME, 0xc8); 896 /* Set time for waiting R0 */ 897 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 898 SP_TX_WAIT_R0_TIME, 0xb0); 899 ret |= anx7625_hdcp_key_load(ctx); 900 if (ret) { 901 pr_warn("prepare HDCP key failed.\n"); 902 return ret; 903 } 904 905 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 906 907 /* Try auth flag */ 908 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 909 /* Interrupt for DRM */ 910 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 911 if (ret < 0) 912 dev_err(dev, "fail to enable HDCP\n"); 913 914 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 915 TX_HDCP_CTRL0, HARD_AUTH_EN); 916 } 917 918 static void anx7625_dp_start(struct anx7625_data *ctx) 919 { 920 int ret; 921 struct device *dev = &ctx->client->dev; 922 923 if (!ctx->display_timing_valid) { 924 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 925 return; 926 } 927 928 /* Disable HDCP */ 929 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 930 931 if (ctx->pdata.is_dpi) 932 ret = anx7625_dpi_config(ctx); 933 else 934 ret = anx7625_dsi_config(ctx); 935 936 if (ret < 0) 937 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 938 939 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 940 941 ctx->dp_en = 1; 942 } 943 944 static void anx7625_dp_stop(struct anx7625_data *ctx) 945 { 946 struct device *dev = &ctx->client->dev; 947 int ret; 948 u8 data; 949 950 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 951 952 /* 953 * Video disable: 0x72:08 bit 7 = 0; 954 * Audio disable: 0x70:87 bit 0 = 0; 955 */ 956 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 957 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 958 959 ret |= anx7625_video_mute_control(ctx, 1); 960 961 dev_dbg(dev, "notify downstream enter into standby\n"); 962 /* Downstream monitor enter into standby mode */ 963 data = 2; 964 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data); 965 if (ret < 0) 966 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 967 968 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 969 970 ctx->dp_en = 0; 971 } 972 973 static int sp_tx_rst_aux(struct anx7625_data *ctx) 974 { 975 int ret; 976 977 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 978 AUX_RST); 979 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 980 ~AUX_RST); 981 return ret; 982 } 983 984 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 985 { 986 int ret; 987 988 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 989 AP_AUX_BUFF_START, offset); 990 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 991 AP_AUX_COMMAND, 0x04); 992 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 993 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 994 return (ret | wait_aux_op_finish(ctx)); 995 } 996 997 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 998 { 999 int ret; 1000 1001 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1002 AP_AUX_COMMAND, len_cmd); 1003 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1004 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1005 return (ret | wait_aux_op_finish(ctx)); 1006 } 1007 1008 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 1009 { 1010 int c = 0; 1011 struct device *dev = &ctx->client->dev; 1012 1013 sp_tx_aux_wr(ctx, 0x7e); 1014 sp_tx_aux_rd(ctx, 0x01); 1015 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 1016 if (c < 0) { 1017 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 1018 return -EIO; 1019 } 1020 1021 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 1022 1023 if (c > MAX_EDID_BLOCK) 1024 c = 1; 1025 1026 return c; 1027 } 1028 1029 static int edid_read(struct anx7625_data *ctx, 1030 u8 offset, u8 *pblock_buf) 1031 { 1032 int ret, cnt; 1033 struct device *dev = &ctx->client->dev; 1034 1035 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1036 sp_tx_aux_wr(ctx, offset); 1037 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1038 ret = sp_tx_aux_rd(ctx, 0xf1); 1039 1040 if (ret) { 1041 ret = sp_tx_rst_aux(ctx); 1042 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 1043 } else { 1044 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1045 AP_AUX_BUFF_START, 1046 MAX_DPCD_BUFFER_SIZE, 1047 pblock_buf); 1048 if (ret > 0) 1049 break; 1050 } 1051 } 1052 1053 if (cnt > EDID_TRY_CNT) 1054 return -EIO; 1055 1056 return ret; 1057 } 1058 1059 static int segments_edid_read(struct anx7625_data *ctx, 1060 u8 segment, u8 *buf, u8 offset) 1061 { 1062 u8 cnt; 1063 int ret; 1064 struct device *dev = &ctx->client->dev; 1065 1066 /* Write address only */ 1067 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1068 AP_AUX_ADDR_7_0, 0x30); 1069 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1070 AP_AUX_COMMAND, 0x04); 1071 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1072 AP_AUX_CTRL_STATUS, 1073 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 1074 1075 ret |= wait_aux_op_finish(ctx); 1076 /* Write segment address */ 1077 ret |= sp_tx_aux_wr(ctx, segment); 1078 /* Data read */ 1079 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1080 AP_AUX_ADDR_7_0, 0x50); 1081 if (ret) { 1082 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 1083 return ret; 1084 } 1085 1086 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1087 sp_tx_aux_wr(ctx, offset); 1088 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1089 ret = sp_tx_aux_rd(ctx, 0xf1); 1090 1091 if (ret) { 1092 ret = sp_tx_rst_aux(ctx); 1093 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 1094 } else { 1095 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1096 AP_AUX_BUFF_START, 1097 MAX_DPCD_BUFFER_SIZE, buf); 1098 if (ret > 0) 1099 break; 1100 } 1101 } 1102 1103 if (cnt > EDID_TRY_CNT) 1104 return -EIO; 1105 1106 return ret; 1107 } 1108 1109 static int sp_tx_edid_read(struct anx7625_data *ctx, 1110 u8 *pedid_blocks_buf) 1111 { 1112 u8 offset; 1113 int edid_pos; 1114 int count, blocks_num; 1115 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 1116 u8 i, j; 1117 int g_edid_break = 0; 1118 int ret; 1119 struct device *dev = &ctx->client->dev; 1120 1121 /* Address initial */ 1122 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1123 AP_AUX_ADDR_7_0, 0x50); 1124 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1125 AP_AUX_ADDR_15_8, 0); 1126 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 1127 AP_AUX_ADDR_19_16, 0xf0); 1128 if (ret < 0) { 1129 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 1130 return -EIO; 1131 } 1132 1133 blocks_num = sp_tx_get_edid_block(ctx); 1134 if (blocks_num < 0) 1135 return blocks_num; 1136 1137 count = 0; 1138 1139 do { 1140 switch (count) { 1141 case 0: 1142 case 1: 1143 for (i = 0; i < 8; i++) { 1144 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 1145 g_edid_break = edid_read(ctx, offset, 1146 pblock_buf); 1147 1148 if (g_edid_break < 0) 1149 break; 1150 1151 memcpy(&pedid_blocks_buf[offset], 1152 pblock_buf, 1153 MAX_DPCD_BUFFER_SIZE); 1154 } 1155 1156 break; 1157 case 2: 1158 offset = 0x00; 1159 1160 for (j = 0; j < 8; j++) { 1161 edid_pos = (j + count * 8) * 1162 MAX_DPCD_BUFFER_SIZE; 1163 1164 if (g_edid_break == 1) 1165 break; 1166 1167 ret = segments_edid_read(ctx, count / 2, 1168 pblock_buf, offset); 1169 if (ret < 0) 1170 return ret; 1171 1172 memcpy(&pedid_blocks_buf[edid_pos], 1173 pblock_buf, 1174 MAX_DPCD_BUFFER_SIZE); 1175 offset = offset + 0x10; 1176 } 1177 1178 break; 1179 case 3: 1180 offset = 0x80; 1181 1182 for (j = 0; j < 8; j++) { 1183 edid_pos = (j + count * 8) * 1184 MAX_DPCD_BUFFER_SIZE; 1185 if (g_edid_break == 1) 1186 break; 1187 1188 ret = segments_edid_read(ctx, count / 2, 1189 pblock_buf, offset); 1190 if (ret < 0) 1191 return ret; 1192 1193 memcpy(&pedid_blocks_buf[edid_pos], 1194 pblock_buf, 1195 MAX_DPCD_BUFFER_SIZE); 1196 offset = offset + 0x10; 1197 } 1198 1199 break; 1200 default: 1201 break; 1202 } 1203 1204 count++; 1205 1206 } while (blocks_num >= count); 1207 1208 /* Check edid data */ 1209 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 1210 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 1211 return -EINVAL; 1212 } 1213 1214 /* Reset aux channel */ 1215 ret = sp_tx_rst_aux(ctx); 1216 if (ret < 0) { 1217 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 1218 return ret; 1219 } 1220 1221 return (blocks_num + 1); 1222 } 1223 1224 static void anx7625_power_on(struct anx7625_data *ctx) 1225 { 1226 struct device *dev = &ctx->client->dev; 1227 int ret, i; 1228 1229 if (!ctx->pdata.low_power_mode) { 1230 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1231 return; 1232 } 1233 1234 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 1235 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 1236 if (ret < 0) { 1237 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 1238 i, ret); 1239 goto reg_err; 1240 } 1241 usleep_range(2000, 2100); 1242 } 1243 1244 usleep_range(11000, 12000); 1245 1246 /* Power on pin enable */ 1247 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 1248 usleep_range(10000, 11000); 1249 /* Power reset pin enable */ 1250 gpiod_set_value(ctx->pdata.gpio_reset, 1); 1251 usleep_range(10000, 11000); 1252 1253 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 1254 return; 1255 reg_err: 1256 for (--i; i >= 0; i--) 1257 regulator_disable(ctx->pdata.supplies[i].consumer); 1258 } 1259 1260 static void anx7625_power_standby(struct anx7625_data *ctx) 1261 { 1262 struct device *dev = &ctx->client->dev; 1263 int ret; 1264 1265 if (!ctx->pdata.low_power_mode) { 1266 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1267 return; 1268 } 1269 1270 gpiod_set_value(ctx->pdata.gpio_reset, 0); 1271 usleep_range(1000, 1100); 1272 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 1273 usleep_range(1000, 1100); 1274 1275 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1276 ctx->pdata.supplies); 1277 if (ret < 0) 1278 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1279 1280 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1281 } 1282 1283 /* Basic configurations of ANX7625 */ 1284 static void anx7625_config(struct anx7625_data *ctx) 1285 { 1286 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1287 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1288 } 1289 1290 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1291 { 1292 struct device *dev = &ctx->client->dev; 1293 int ret; 1294 1295 /* Reset main ocm */ 1296 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1297 /* Disable PD */ 1298 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1299 AP_AV_STATUS, AP_DISABLE_PD); 1300 /* Release main ocm */ 1301 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1302 1303 if (ret < 0) 1304 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1305 else 1306 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1307 } 1308 1309 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1310 { 1311 int ret; 1312 struct device *dev = &ctx->client->dev; 1313 1314 /* Check interface workable */ 1315 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1316 FLASH_LOAD_STA); 1317 if (ret < 0) { 1318 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1319 return ret; 1320 } 1321 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1322 return -ENODEV; 1323 1324 anx7625_disable_pd_protocol(ctx); 1325 1326 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1327 anx7625_reg_read(ctx, 1328 ctx->i2c.rx_p0_client, 1329 OCM_FW_VERSION), 1330 anx7625_reg_read(ctx, 1331 ctx->i2c.rx_p0_client, 1332 OCM_FW_REVERSION)); 1333 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1334 ANX7625_DRV_VERSION); 1335 1336 return 0; 1337 } 1338 1339 static void anx7625_power_on_init(struct anx7625_data *ctx) 1340 { 1341 int retry_count, i; 1342 1343 for (retry_count = 0; retry_count < 3; retry_count++) { 1344 anx7625_power_on(ctx); 1345 anx7625_config(ctx); 1346 1347 for (i = 0; i < OCM_LOADING_TIME; i++) { 1348 if (!anx7625_ocm_loading_check(ctx)) 1349 return; 1350 usleep_range(1000, 1100); 1351 } 1352 anx7625_power_standby(ctx); 1353 } 1354 } 1355 1356 static void anx7625_init_gpio(struct anx7625_data *platform) 1357 { 1358 struct device *dev = &platform->client->dev; 1359 1360 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1361 1362 /* Gpio for chip power enable */ 1363 platform->pdata.gpio_p_on = 1364 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1365 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 1366 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 1367 platform->pdata.gpio_p_on = NULL; 1368 } 1369 1370 /* Gpio for chip reset */ 1371 platform->pdata.gpio_reset = 1372 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1373 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 1374 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 1375 platform->pdata.gpio_reset = NULL; 1376 } 1377 1378 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1379 platform->pdata.low_power_mode = 1; 1380 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1381 desc_to_gpio(platform->pdata.gpio_p_on), 1382 desc_to_gpio(platform->pdata.gpio_reset)); 1383 } else { 1384 platform->pdata.low_power_mode = 0; 1385 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1386 } 1387 } 1388 1389 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1390 { 1391 ctx->hpd_status = 0; 1392 ctx->hpd_high_cnt = 0; 1393 ctx->display_timing_valid = 0; 1394 } 1395 1396 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1397 { 1398 int ret; 1399 struct device *dev = &ctx->client->dev; 1400 1401 if (ctx->hpd_high_cnt >= 2) { 1402 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1403 return; 1404 } 1405 1406 ctx->hpd_status = 1; 1407 ctx->hpd_high_cnt++; 1408 1409 /* Not support HDCP */ 1410 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1411 1412 /* Try auth flag */ 1413 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1414 /* Interrupt for DRM */ 1415 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1416 if (ret < 0) { 1417 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1418 return; 1419 } 1420 1421 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1422 if (ret < 0) 1423 return; 1424 1425 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1426 } 1427 1428 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1429 { 1430 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1431 } 1432 1433 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1434 { 1435 int ret, val; 1436 struct device *dev = &ctx->client->dev; 1437 1438 /* Interrupt mode, no need poll HPD status, just return */ 1439 if (ctx->pdata.intp_irq) 1440 return; 1441 1442 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1443 ctx, val, 1444 ((val & HPD_STATUS) || (val < 0)), 1445 5000, 1446 5000 * 100); 1447 if (ret) { 1448 DRM_DEV_ERROR(dev, "no hpd.\n"); 1449 return; 1450 } 1451 1452 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1453 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1454 INTR_ALERT_1, 0xFF); 1455 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1456 INTERFACE_CHANGE_INT, 0); 1457 1458 anx7625_start_dp_work(ctx); 1459 1460 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1461 drm_helper_hpd_irq_event(ctx->bridge.dev); 1462 } 1463 1464 static void anx7625_remove_edid(struct anx7625_data *ctx) 1465 { 1466 ctx->slimport_edid_p.edid_block_num = -1; 1467 } 1468 1469 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1470 { 1471 int i; 1472 1473 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1474 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1475 DP_TX_LANE0_SWING_REG0 + i, 1476 ctx->pdata.lane0_reg_data[i] & 0xFF); 1477 1478 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1479 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1480 DP_TX_LANE1_SWING_REG0 + i, 1481 ctx->pdata.lane1_reg_data[i] & 0xFF); 1482 } 1483 1484 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1485 { 1486 struct device *dev = &ctx->client->dev; 1487 1488 /* HPD changed */ 1489 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1490 (u32)on); 1491 1492 if (on == 0) { 1493 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1494 anx7625_remove_edid(ctx); 1495 anx7625_stop_dp_work(ctx); 1496 } else { 1497 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1498 anx7625_start_dp_work(ctx); 1499 anx7625_dp_adjust_swing(ctx); 1500 } 1501 } 1502 1503 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1504 { 1505 int intr_vector, status; 1506 struct device *dev = &ctx->client->dev; 1507 1508 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1509 INTR_ALERT_1, 0xFF); 1510 if (status < 0) { 1511 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1512 return status; 1513 } 1514 1515 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1516 INTERFACE_CHANGE_INT); 1517 if (intr_vector < 0) { 1518 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1519 return intr_vector; 1520 } 1521 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1522 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1523 INTERFACE_CHANGE_INT, 1524 intr_vector & (~intr_vector)); 1525 if (status < 0) { 1526 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1527 return status; 1528 } 1529 1530 if (!(intr_vector & HPD_STATUS_CHANGE)) 1531 return -ENOENT; 1532 1533 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1534 SYSTEM_STSTUS); 1535 if (status < 0) { 1536 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1537 return status; 1538 } 1539 1540 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1541 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1542 1543 return 0; 1544 } 1545 1546 static void anx7625_work_func(struct work_struct *work) 1547 { 1548 int event; 1549 struct anx7625_data *ctx = container_of(work, 1550 struct anx7625_data, work); 1551 1552 mutex_lock(&ctx->lock); 1553 1554 if (pm_runtime_suspended(&ctx->client->dev)) 1555 goto unlock; 1556 1557 event = anx7625_hpd_change_detect(ctx); 1558 if (event < 0) 1559 goto unlock; 1560 1561 if (ctx->bridge_attached) 1562 drm_helper_hpd_irq_event(ctx->bridge.dev); 1563 1564 unlock: 1565 mutex_unlock(&ctx->lock); 1566 } 1567 1568 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1569 { 1570 struct anx7625_data *ctx = (struct anx7625_data *)data; 1571 1572 queue_work(ctx->workqueue, &ctx->work); 1573 1574 return IRQ_HANDLED; 1575 } 1576 1577 static int anx7625_get_swing_setting(struct device *dev, 1578 struct anx7625_platform_data *pdata) 1579 { 1580 int num_regs; 1581 1582 if (of_get_property(dev->of_node, 1583 "analogix,lane0-swing", &num_regs)) { 1584 if (num_regs > DP_TX_SWING_REG_CNT) 1585 num_regs = DP_TX_SWING_REG_CNT; 1586 1587 pdata->dp_lane0_swing_reg_cnt = num_regs; 1588 of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1589 pdata->lane0_reg_data, num_regs); 1590 } 1591 1592 if (of_get_property(dev->of_node, 1593 "analogix,lane1-swing", &num_regs)) { 1594 if (num_regs > DP_TX_SWING_REG_CNT) 1595 num_regs = DP_TX_SWING_REG_CNT; 1596 1597 pdata->dp_lane1_swing_reg_cnt = num_regs; 1598 of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1599 pdata->lane1_reg_data, num_regs); 1600 } 1601 1602 return 0; 1603 } 1604 1605 static int anx7625_parse_dt(struct device *dev, 1606 struct anx7625_platform_data *pdata) 1607 { 1608 struct device_node *np = dev->of_node, *ep0; 1609 struct drm_panel *panel; 1610 int ret; 1611 int bus_type, mipi_lanes; 1612 1613 anx7625_get_swing_setting(dev, pdata); 1614 1615 pdata->is_dpi = 1; /* default dpi mode */ 1616 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1617 if (!pdata->mipi_host_node) { 1618 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1619 return -ENODEV; 1620 } 1621 1622 bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1623 mipi_lanes = MAX_LANES_SUPPORT; 1624 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1625 if (ep0) { 1626 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1627 bus_type = 0; 1628 1629 mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1630 } 1631 1632 if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1633 pdata->is_dpi = 0; 1634 1635 pdata->mipi_lanes = mipi_lanes; 1636 if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1637 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1638 1639 if (pdata->is_dpi) 1640 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1641 else 1642 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1643 1644 if (of_property_read_bool(np, "analogix,audio-enable")) 1645 pdata->audio_en = 1; 1646 1647 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1648 if (ret < 0) { 1649 if (ret == -ENODEV) 1650 return 0; 1651 return ret; 1652 } 1653 if (!panel) 1654 return -ENODEV; 1655 1656 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1657 if (IS_ERR(pdata->panel_bridge)) 1658 return PTR_ERR(pdata->panel_bridge); 1659 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1660 1661 return 0; 1662 } 1663 1664 static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1665 { 1666 struct device_node *bus, *panel; 1667 1668 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1669 if (!bus) 1670 return false; 1671 1672 panel = of_get_child_by_name(bus, "panel"); 1673 of_node_put(bus); 1674 if (!panel) 1675 return false; 1676 of_node_put(panel); 1677 1678 return true; 1679 } 1680 1681 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1682 { 1683 return container_of(bridge, struct anx7625_data, bridge); 1684 } 1685 1686 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1687 struct drm_dp_aux_msg *msg) 1688 { 1689 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1690 struct device *dev = &ctx->client->dev; 1691 u8 request = msg->request & ~DP_AUX_I2C_MOT; 1692 int ret = 0; 1693 1694 pm_runtime_get_sync(dev); 1695 msg->reply = 0; 1696 switch (request) { 1697 case DP_AUX_NATIVE_WRITE: 1698 case DP_AUX_I2C_WRITE: 1699 case DP_AUX_NATIVE_READ: 1700 case DP_AUX_I2C_READ: 1701 break; 1702 default: 1703 ret = -EINVAL; 1704 } 1705 if (!ret) 1706 ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1707 msg->size, msg->buffer); 1708 pm_runtime_mark_last_busy(dev); 1709 pm_runtime_put_autosuspend(dev); 1710 1711 return ret; 1712 } 1713 1714 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1715 { 1716 struct device *dev = &ctx->client->dev; 1717 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1718 int edid_num; 1719 u8 *edid; 1720 1721 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1722 if (!edid) { 1723 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1724 return NULL; 1725 } 1726 1727 if (ctx->slimport_edid_p.edid_block_num > 0) { 1728 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1729 FOUR_BLOCK_SIZE); 1730 return (struct edid *)edid; 1731 } 1732 1733 pm_runtime_get_sync(dev); 1734 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1735 pm_runtime_put_sync(dev); 1736 1737 if (edid_num < 1) { 1738 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1739 kfree(edid); 1740 return NULL; 1741 } 1742 1743 p_edid->edid_block_num = edid_num; 1744 1745 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1746 return (struct edid *)edid; 1747 } 1748 1749 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1750 { 1751 struct device *dev = &ctx->client->dev; 1752 1753 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1754 1755 if (ctx->pdata.panel_bridge) 1756 return connector_status_connected; 1757 1758 return ctx->hpd_status ? connector_status_connected : 1759 connector_status_disconnected; 1760 } 1761 1762 static int anx7625_audio_hw_params(struct device *dev, void *data, 1763 struct hdmi_codec_daifmt *fmt, 1764 struct hdmi_codec_params *params) 1765 { 1766 struct anx7625_data *ctx = dev_get_drvdata(dev); 1767 int wl, ch, rate; 1768 int ret = 0; 1769 1770 if (fmt->fmt != HDMI_DSP_A) { 1771 DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1772 return -EINVAL; 1773 } 1774 1775 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1776 params->sample_rate, params->sample_width, 1777 params->cea.channels); 1778 1779 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1780 AUDIO_CHANNEL_STATUS_6, 1781 ~I2S_SLAVE_MODE, 1782 TDM_SLAVE_MODE); 1783 1784 /* Word length */ 1785 switch (params->sample_width) { 1786 case 16: 1787 wl = AUDIO_W_LEN_16_20MAX; 1788 break; 1789 case 18: 1790 wl = AUDIO_W_LEN_18_20MAX; 1791 break; 1792 case 20: 1793 wl = AUDIO_W_LEN_20_20MAX; 1794 break; 1795 case 24: 1796 wl = AUDIO_W_LEN_24_24MAX; 1797 break; 1798 default: 1799 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1800 params->sample_width); 1801 return -EINVAL; 1802 } 1803 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1804 AUDIO_CHANNEL_STATUS_5, 1805 0xf0, wl); 1806 1807 /* Channel num */ 1808 switch (params->cea.channels) { 1809 case 2: 1810 ch = I2S_CH_2; 1811 break; 1812 case 4: 1813 ch = TDM_CH_4; 1814 break; 1815 case 6: 1816 ch = TDM_CH_6; 1817 break; 1818 case 8: 1819 ch = TDM_CH_8; 1820 break; 1821 default: 1822 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1823 params->cea.channels); 1824 return -EINVAL; 1825 } 1826 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1827 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1828 if (ch > I2S_CH_2) 1829 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1830 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1831 else 1832 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1833 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1834 1835 /* FS */ 1836 switch (params->sample_rate) { 1837 case 32000: 1838 rate = AUDIO_FS_32K; 1839 break; 1840 case 44100: 1841 rate = AUDIO_FS_441K; 1842 break; 1843 case 48000: 1844 rate = AUDIO_FS_48K; 1845 break; 1846 case 88200: 1847 rate = AUDIO_FS_882K; 1848 break; 1849 case 96000: 1850 rate = AUDIO_FS_96K; 1851 break; 1852 case 176400: 1853 rate = AUDIO_FS_1764K; 1854 break; 1855 case 192000: 1856 rate = AUDIO_FS_192K; 1857 break; 1858 default: 1859 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1860 params->sample_rate); 1861 return -EINVAL; 1862 } 1863 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1864 AUDIO_CHANNEL_STATUS_4, 1865 0xf0, rate); 1866 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1867 AP_AV_STATUS, AP_AUDIO_CHG); 1868 if (ret < 0) { 1869 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1870 return -EIO; 1871 } 1872 1873 return 0; 1874 } 1875 1876 static void anx7625_audio_shutdown(struct device *dev, void *data) 1877 { 1878 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1879 } 1880 1881 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1882 struct device_node *endpoint) 1883 { 1884 struct of_endpoint of_ep; 1885 int ret; 1886 1887 ret = of_graph_parse_endpoint(endpoint, &of_ep); 1888 if (ret < 0) 1889 return ret; 1890 1891 /* 1892 * HDMI sound should be located at external DPI port 1893 * Didn't have good way to check where is internal(DSI) 1894 * or external(DPI) bridge 1895 */ 1896 return 0; 1897 } 1898 1899 static void 1900 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1901 enum drm_connector_status status) 1902 { 1903 if (ctx->plugged_cb && ctx->codec_dev) { 1904 ctx->plugged_cb(ctx->codec_dev, 1905 status == connector_status_connected); 1906 } 1907 } 1908 1909 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1910 hdmi_codec_plugged_cb fn, 1911 struct device *codec_dev) 1912 { 1913 struct anx7625_data *ctx = data; 1914 1915 ctx->plugged_cb = fn; 1916 ctx->codec_dev = codec_dev; 1917 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1918 1919 return 0; 1920 } 1921 1922 static int anx7625_audio_get_eld(struct device *dev, void *data, 1923 u8 *buf, size_t len) 1924 { 1925 struct anx7625_data *ctx = dev_get_drvdata(dev); 1926 1927 if (!ctx->connector) { 1928 dev_err(dev, "connector not initial\n"); 1929 return -EINVAL; 1930 } 1931 1932 dev_dbg(dev, "audio copy eld\n"); 1933 memcpy(buf, ctx->connector->eld, 1934 min(sizeof(ctx->connector->eld), len)); 1935 1936 return 0; 1937 } 1938 1939 static const struct hdmi_codec_ops anx7625_codec_ops = { 1940 .hw_params = anx7625_audio_hw_params, 1941 .audio_shutdown = anx7625_audio_shutdown, 1942 .get_eld = anx7625_audio_get_eld, 1943 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1944 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1945 }; 1946 1947 static void anx7625_unregister_audio(struct anx7625_data *ctx) 1948 { 1949 struct device *dev = &ctx->client->dev; 1950 1951 if (ctx->audio_pdev) { 1952 platform_device_unregister(ctx->audio_pdev); 1953 ctx->audio_pdev = NULL; 1954 } 1955 1956 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1957 } 1958 1959 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1960 { 1961 struct hdmi_codec_pdata codec_data = { 1962 .ops = &anx7625_codec_ops, 1963 .max_i2s_channels = 8, 1964 .i2s = 1, 1965 .data = ctx, 1966 }; 1967 1968 ctx->audio_pdev = platform_device_register_data(dev, 1969 HDMI_CODEC_DRV_NAME, 1970 PLATFORM_DEVID_AUTO, 1971 &codec_data, 1972 sizeof(codec_data)); 1973 1974 if (IS_ERR(ctx->audio_pdev)) 1975 return PTR_ERR(ctx->audio_pdev); 1976 1977 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1978 1979 return 0; 1980 } 1981 1982 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1983 { 1984 struct mipi_dsi_device *dsi; 1985 struct device *dev = &ctx->client->dev; 1986 struct mipi_dsi_host *host; 1987 const struct mipi_dsi_device_info info = { 1988 .type = "anx7625", 1989 .channel = 0, 1990 .node = NULL, 1991 }; 1992 int ret; 1993 1994 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1995 1996 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1997 if (!host) { 1998 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1999 return -EPROBE_DEFER; 2000 } 2001 2002 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2003 if (IS_ERR(dsi)) { 2004 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 2005 return -EINVAL; 2006 } 2007 2008 dsi->lanes = ctx->pdata.mipi_lanes; 2009 dsi->format = MIPI_DSI_FMT_RGB888; 2010 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 2011 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2012 MIPI_DSI_MODE_VIDEO_HSE; 2013 2014 ret = devm_mipi_dsi_attach(dev, dsi); 2015 if (ret) { 2016 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 2017 return ret; 2018 } 2019 2020 ctx->dsi = dsi; 2021 2022 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 2023 2024 return 0; 2025 } 2026 2027 static void hdcp_check_work_func(struct work_struct *work) 2028 { 2029 u8 status; 2030 struct delayed_work *dwork; 2031 struct anx7625_data *ctx; 2032 struct device *dev; 2033 struct drm_device *drm_dev; 2034 2035 dwork = to_delayed_work(work); 2036 ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2037 dev = &ctx->client->dev; 2038 2039 if (!ctx->connector) { 2040 dev_err(dev, "HDCP connector is null!"); 2041 return; 2042 } 2043 2044 drm_dev = ctx->connector->dev; 2045 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2046 mutex_lock(&ctx->hdcp_wq_lock); 2047 2048 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2049 dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2050 if (status & BIT(1)) { 2051 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2052 drm_hdcp_update_content_protection(ctx->connector, 2053 ctx->hdcp_cp); 2054 dev_dbg(dev, "update CP to ENABLE\n"); 2055 } 2056 2057 mutex_unlock(&ctx->hdcp_wq_lock); 2058 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2059 } 2060 2061 static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2062 struct drm_connector_state *state) 2063 { 2064 struct device *dev = &ctx->client->dev; 2065 int cp; 2066 2067 dev_dbg(dev, "hdcp state check\n"); 2068 cp = state->content_protection; 2069 2070 if (cp == ctx->hdcp_cp) 2071 return 0; 2072 2073 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2074 if (ctx->dp_en) { 2075 dev_dbg(dev, "enable HDCP\n"); 2076 anx7625_hdcp_enable(ctx); 2077 2078 queue_delayed_work(ctx->hdcp_workqueue, 2079 &ctx->hdcp_work, 2080 msecs_to_jiffies(2000)); 2081 } 2082 } 2083 2084 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2085 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2086 dev_err(dev, "current CP is not ENABLED\n"); 2087 return -EINVAL; 2088 } 2089 anx7625_hdcp_disable(ctx); 2090 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2091 drm_hdcp_update_content_protection(ctx->connector, 2092 ctx->hdcp_cp); 2093 dev_dbg(dev, "update CP to UNDESIRE\n"); 2094 } 2095 2096 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2097 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2098 return -EINVAL; 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int anx7625_bridge_attach(struct drm_bridge *bridge, 2105 enum drm_bridge_attach_flags flags) 2106 { 2107 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2108 int err; 2109 struct device *dev = &ctx->client->dev; 2110 2111 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 2112 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 2113 return -EINVAL; 2114 2115 if (!bridge->encoder) { 2116 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 2117 return -ENODEV; 2118 } 2119 2120 ctx->aux.drm_dev = bridge->dev; 2121 err = drm_dp_aux_register(&ctx->aux); 2122 if (err) { 2123 dev_err(dev, "failed to register aux channel: %d\n", err); 2124 return err; 2125 } 2126 2127 if (ctx->pdata.panel_bridge) { 2128 err = drm_bridge_attach(bridge->encoder, 2129 ctx->pdata.panel_bridge, 2130 &ctx->bridge, flags); 2131 if (err) 2132 return err; 2133 } 2134 2135 ctx->bridge_attached = 1; 2136 2137 return 0; 2138 } 2139 2140 static void anx7625_bridge_detach(struct drm_bridge *bridge) 2141 { 2142 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2143 2144 drm_dp_aux_unregister(&ctx->aux); 2145 } 2146 2147 static enum drm_mode_status 2148 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 2149 const struct drm_display_info *info, 2150 const struct drm_display_mode *mode) 2151 { 2152 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2153 struct device *dev = &ctx->client->dev; 2154 2155 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 2156 2157 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 2158 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 2159 DRM_DEV_DEBUG_DRIVER(dev, 2160 "drm mode invalid, pixelclock too high.\n"); 2161 return MODE_CLOCK_HIGH; 2162 } 2163 2164 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 2165 2166 return MODE_OK; 2167 } 2168 2169 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 2170 const struct drm_display_mode *old_mode, 2171 const struct drm_display_mode *mode) 2172 { 2173 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2174 struct device *dev = &ctx->client->dev; 2175 2176 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 2177 2178 ctx->dt.pixelclock.min = mode->clock; 2179 ctx->dt.hactive.min = mode->hdisplay; 2180 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 2181 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 2182 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 2183 ctx->dt.vactive.min = mode->vdisplay; 2184 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 2185 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 2186 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 2187 2188 ctx->display_timing_valid = 1; 2189 2190 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 2191 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 2192 ctx->dt.hactive.min, 2193 ctx->dt.hsync_len.min, 2194 ctx->dt.hfront_porch.min, 2195 ctx->dt.hback_porch.min); 2196 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 2197 ctx->dt.vactive.min, 2198 ctx->dt.vsync_len.min, 2199 ctx->dt.vfront_porch.min, 2200 ctx->dt.vback_porch.min); 2201 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 2202 mode->hdisplay, 2203 mode->hsync_start); 2204 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 2205 mode->hsync_end, 2206 mode->htotal); 2207 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 2208 mode->vdisplay, 2209 mode->vsync_start); 2210 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 2211 mode->vsync_end, 2212 mode->vtotal); 2213 } 2214 2215 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 2216 const struct drm_display_mode *mode, 2217 struct drm_display_mode *adj) 2218 { 2219 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2220 struct device *dev = &ctx->client->dev; 2221 u32 hsync, hfp, hbp, hblanking; 2222 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 2223 u32 vref, adj_clock; 2224 2225 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 2226 2227 /* No need fixup for external monitor */ 2228 if (!ctx->pdata.panel_bridge) 2229 return true; 2230 2231 hsync = mode->hsync_end - mode->hsync_start; 2232 hfp = mode->hsync_start - mode->hdisplay; 2233 hbp = mode->htotal - mode->hsync_end; 2234 hblanking = mode->htotal - mode->hdisplay; 2235 2236 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 2237 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2238 hsync, hfp, hbp, adj->clock); 2239 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2240 adj->hsync_start, adj->hsync_end, adj->htotal); 2241 2242 adj_hfp = hfp; 2243 adj_hsync = hsync; 2244 adj_hbp = hbp; 2245 adj_hblanking = hblanking; 2246 2247 /* HFP needs to be even */ 2248 if (hfp & 0x1) { 2249 adj_hfp += 1; 2250 adj_hblanking += 1; 2251 } 2252 2253 /* HBP needs to be even */ 2254 if (hbp & 0x1) { 2255 adj_hbp -= 1; 2256 adj_hblanking -= 1; 2257 } 2258 2259 /* HSYNC needs to be even */ 2260 if (hsync & 0x1) { 2261 if (adj_hblanking < hblanking) 2262 adj_hsync += 1; 2263 else 2264 adj_hsync -= 1; 2265 } 2266 2267 /* 2268 * Once illegal timing detected, use default HFP, HSYNC, HBP 2269 * This adjusting made for built-in eDP panel, for the externel 2270 * DP monitor, may need return false. 2271 */ 2272 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 2273 adj_hsync = SYNC_LEN_DEF; 2274 adj_hfp = HFP_HBP_DEF; 2275 adj_hbp = HFP_HBP_DEF; 2276 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 2277 if (hblanking < HBLANKING_MIN) { 2278 delta_adj = HBLANKING_MIN - hblanking; 2279 adj_clock = vref * delta_adj * adj->vtotal; 2280 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 2281 } else { 2282 delta_adj = hblanking - HBLANKING_MIN; 2283 adj_clock = vref * delta_adj * adj->vtotal; 2284 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 2285 } 2286 2287 DRM_WARN("illegal hblanking timing, use default.\n"); 2288 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 2289 } else if (adj_hfp < HP_MIN) { 2290 /* Adjust hfp if hfp less than HP_MIN */ 2291 delta_adj = HP_MIN - adj_hfp; 2292 adj_hfp = HP_MIN; 2293 2294 /* 2295 * Balance total HBlanking pixel, if HBP does not have enough 2296 * space, adjust HSYNC length, otherwise adjust HBP 2297 */ 2298 if ((adj_hbp - delta_adj) < HP_MIN) 2299 /* HBP not enough space */ 2300 adj_hsync -= delta_adj; 2301 else 2302 adj_hbp -= delta_adj; 2303 } else if (adj_hbp < HP_MIN) { 2304 delta_adj = HP_MIN - adj_hbp; 2305 adj_hbp = HP_MIN; 2306 2307 /* 2308 * Balance total HBlanking pixel, if HBP hasn't enough space, 2309 * adjust HSYNC length, otherwize adjust HBP 2310 */ 2311 if ((adj_hfp - delta_adj) < HP_MIN) 2312 /* HFP not enough space */ 2313 adj_hsync -= delta_adj; 2314 else 2315 adj_hfp -= delta_adj; 2316 } 2317 2318 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 2319 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2320 adj_hsync, adj_hfp, adj_hbp, adj->clock); 2321 2322 /* Reconstruct timing */ 2323 adj->hsync_start = adj->hdisplay + adj_hfp; 2324 adj->hsync_end = adj->hsync_start + adj_hsync; 2325 adj->htotal = adj->hsync_end + adj_hbp; 2326 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2327 adj->hsync_start, adj->hsync_end, adj->htotal); 2328 2329 return true; 2330 } 2331 2332 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2333 struct drm_bridge_state *bridge_state, 2334 struct drm_crtc_state *crtc_state, 2335 struct drm_connector_state *conn_state) 2336 { 2337 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2338 struct device *dev = &ctx->client->dev; 2339 2340 dev_dbg(dev, "drm bridge atomic check\n"); 2341 2342 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2343 &crtc_state->adjusted_mode); 2344 2345 return anx7625_connector_atomic_check(ctx, conn_state); 2346 } 2347 2348 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2349 struct drm_bridge_state *state) 2350 { 2351 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2352 struct device *dev = &ctx->client->dev; 2353 struct drm_connector *connector; 2354 2355 dev_dbg(dev, "drm atomic enable\n"); 2356 2357 if (!bridge->encoder) { 2358 dev_err(dev, "Parent encoder object not found"); 2359 return; 2360 } 2361 2362 connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2363 bridge->encoder); 2364 if (!connector) 2365 return; 2366 2367 ctx->connector = connector; 2368 2369 pm_runtime_get_sync(dev); 2370 2371 anx7625_dp_start(ctx); 2372 } 2373 2374 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2375 struct drm_bridge_state *old) 2376 { 2377 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2378 struct device *dev = &ctx->client->dev; 2379 2380 dev_dbg(dev, "drm atomic disable\n"); 2381 2382 ctx->connector = NULL; 2383 anx7625_dp_stop(ctx); 2384 2385 pm_runtime_put_sync(dev); 2386 } 2387 2388 static enum drm_connector_status 2389 anx7625_bridge_detect(struct drm_bridge *bridge) 2390 { 2391 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2392 struct device *dev = &ctx->client->dev; 2393 2394 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 2395 2396 return anx7625_sink_detect(ctx); 2397 } 2398 2399 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 2400 struct drm_connector *connector) 2401 { 2402 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2403 struct device *dev = &ctx->client->dev; 2404 2405 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 2406 2407 return anx7625_get_edid(ctx); 2408 } 2409 2410 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 2411 .attach = anx7625_bridge_attach, 2412 .detach = anx7625_bridge_detach, 2413 .mode_valid = anx7625_bridge_mode_valid, 2414 .mode_set = anx7625_bridge_mode_set, 2415 .atomic_check = anx7625_bridge_atomic_check, 2416 .atomic_enable = anx7625_bridge_atomic_enable, 2417 .atomic_disable = anx7625_bridge_atomic_disable, 2418 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2419 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2420 .atomic_reset = drm_atomic_helper_bridge_reset, 2421 .detect = anx7625_bridge_detect, 2422 .get_edid = anx7625_bridge_get_edid, 2423 }; 2424 2425 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 2426 struct i2c_client *client) 2427 { 2428 int err = 0; 2429 2430 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 2431 TX_P0_ADDR >> 1); 2432 if (IS_ERR(ctx->i2c.tx_p0_client)) 2433 return PTR_ERR(ctx->i2c.tx_p0_client); 2434 2435 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 2436 TX_P1_ADDR >> 1); 2437 if (IS_ERR(ctx->i2c.tx_p1_client)) { 2438 err = PTR_ERR(ctx->i2c.tx_p1_client); 2439 goto free_tx_p0; 2440 } 2441 2442 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 2443 TX_P2_ADDR >> 1); 2444 if (IS_ERR(ctx->i2c.tx_p2_client)) { 2445 err = PTR_ERR(ctx->i2c.tx_p2_client); 2446 goto free_tx_p1; 2447 } 2448 2449 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 2450 RX_P0_ADDR >> 1); 2451 if (IS_ERR(ctx->i2c.rx_p0_client)) { 2452 err = PTR_ERR(ctx->i2c.rx_p0_client); 2453 goto free_tx_p2; 2454 } 2455 2456 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 2457 RX_P1_ADDR >> 1); 2458 if (IS_ERR(ctx->i2c.rx_p1_client)) { 2459 err = PTR_ERR(ctx->i2c.rx_p1_client); 2460 goto free_rx_p0; 2461 } 2462 2463 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 2464 RX_P2_ADDR >> 1); 2465 if (IS_ERR(ctx->i2c.rx_p2_client)) { 2466 err = PTR_ERR(ctx->i2c.rx_p2_client); 2467 goto free_rx_p1; 2468 } 2469 2470 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 2471 TCPC_INTERFACE_ADDR >> 1); 2472 if (IS_ERR(ctx->i2c.tcpc_client)) { 2473 err = PTR_ERR(ctx->i2c.tcpc_client); 2474 goto free_rx_p2; 2475 } 2476 2477 return 0; 2478 2479 free_rx_p2: 2480 i2c_unregister_device(ctx->i2c.rx_p2_client); 2481 free_rx_p1: 2482 i2c_unregister_device(ctx->i2c.rx_p1_client); 2483 free_rx_p0: 2484 i2c_unregister_device(ctx->i2c.rx_p0_client); 2485 free_tx_p2: 2486 i2c_unregister_device(ctx->i2c.tx_p2_client); 2487 free_tx_p1: 2488 i2c_unregister_device(ctx->i2c.tx_p1_client); 2489 free_tx_p0: 2490 i2c_unregister_device(ctx->i2c.tx_p0_client); 2491 2492 return err; 2493 } 2494 2495 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 2496 { 2497 i2c_unregister_device(ctx->i2c.tx_p0_client); 2498 i2c_unregister_device(ctx->i2c.tx_p1_client); 2499 i2c_unregister_device(ctx->i2c.tx_p2_client); 2500 i2c_unregister_device(ctx->i2c.rx_p0_client); 2501 i2c_unregister_device(ctx->i2c.rx_p1_client); 2502 i2c_unregister_device(ctx->i2c.rx_p2_client); 2503 i2c_unregister_device(ctx->i2c.tcpc_client); 2504 } 2505 2506 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2507 { 2508 struct anx7625_data *ctx = dev_get_drvdata(dev); 2509 2510 mutex_lock(&ctx->lock); 2511 2512 anx7625_stop_dp_work(ctx); 2513 anx7625_power_standby(ctx); 2514 2515 mutex_unlock(&ctx->lock); 2516 2517 return 0; 2518 } 2519 2520 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2521 { 2522 struct anx7625_data *ctx = dev_get_drvdata(dev); 2523 2524 mutex_lock(&ctx->lock); 2525 2526 anx7625_power_on_init(ctx); 2527 anx7625_hpd_polling(ctx); 2528 2529 mutex_unlock(&ctx->lock); 2530 2531 return 0; 2532 } 2533 2534 static int __maybe_unused anx7625_resume(struct device *dev) 2535 { 2536 struct anx7625_data *ctx = dev_get_drvdata(dev); 2537 2538 if (!ctx->pdata.intp_irq) 2539 return 0; 2540 2541 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2542 enable_irq(ctx->pdata.intp_irq); 2543 anx7625_runtime_pm_resume(dev); 2544 } 2545 2546 return 0; 2547 } 2548 2549 static int __maybe_unused anx7625_suspend(struct device *dev) 2550 { 2551 struct anx7625_data *ctx = dev_get_drvdata(dev); 2552 2553 if (!ctx->pdata.intp_irq) 2554 return 0; 2555 2556 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2557 anx7625_runtime_pm_suspend(dev); 2558 disable_irq(ctx->pdata.intp_irq); 2559 } 2560 2561 return 0; 2562 } 2563 2564 static const struct dev_pm_ops anx7625_pm_ops = { 2565 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 2566 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2567 anx7625_runtime_pm_resume, NULL) 2568 }; 2569 2570 static void anx7625_runtime_disable(void *data) 2571 { 2572 pm_runtime_dont_use_autosuspend(data); 2573 pm_runtime_disable(data); 2574 } 2575 2576 static int anx7625_i2c_probe(struct i2c_client *client, 2577 const struct i2c_device_id *id) 2578 { 2579 struct anx7625_data *platform; 2580 struct anx7625_platform_data *pdata; 2581 int ret = 0; 2582 struct device *dev = &client->dev; 2583 2584 if (!i2c_check_functionality(client->adapter, 2585 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2586 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2587 return -ENODEV; 2588 } 2589 2590 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL); 2591 if (!platform) { 2592 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2593 return -ENOMEM; 2594 } 2595 2596 pdata = &platform->pdata; 2597 2598 platform->client = client; 2599 i2c_set_clientdata(client, platform); 2600 2601 pdata->supplies[0].supply = "vdd10"; 2602 pdata->supplies[1].supply = "vdd18"; 2603 pdata->supplies[2].supply = "vdd33"; 2604 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2605 pdata->supplies); 2606 if (ret) { 2607 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2608 return ret; 2609 } 2610 anx7625_init_gpio(platform); 2611 2612 mutex_init(&platform->lock); 2613 mutex_init(&platform->hdcp_wq_lock); 2614 2615 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2616 platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2617 if (!platform->hdcp_workqueue) { 2618 dev_err(dev, "fail to create work queue\n"); 2619 ret = -ENOMEM; 2620 return ret; 2621 } 2622 2623 platform->pdata.intp_irq = client->irq; 2624 if (platform->pdata.intp_irq) { 2625 INIT_WORK(&platform->work, anx7625_work_func); 2626 platform->workqueue = alloc_workqueue("anx7625_work", 2627 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2628 if (!platform->workqueue) { 2629 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2630 ret = -ENOMEM; 2631 goto free_hdcp_wq; 2632 } 2633 2634 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2635 NULL, anx7625_intr_hpd_isr, 2636 IRQF_TRIGGER_FALLING | 2637 IRQF_ONESHOT, 2638 "anx7625-intp", platform); 2639 if (ret) { 2640 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2641 goto free_wq; 2642 } 2643 } 2644 2645 platform->aux.name = "anx7625-aux"; 2646 platform->aux.dev = dev; 2647 platform->aux.transfer = anx7625_aux_transfer; 2648 drm_dp_aux_init(&platform->aux); 2649 devm_of_dp_aux_populate_ep_devices(&platform->aux); 2650 2651 ret = anx7625_parse_dt(dev, pdata); 2652 if (ret) { 2653 if (ret != -EPROBE_DEFER) 2654 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2655 return ret; 2656 } 2657 2658 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2659 ret = -ENOMEM; 2660 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2661 goto free_wq; 2662 } 2663 2664 pm_runtime_enable(dev); 2665 pm_runtime_set_autosuspend_delay(dev, 1000); 2666 pm_runtime_use_autosuspend(dev); 2667 pm_suspend_ignore_children(dev, true); 2668 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev); 2669 if (ret) 2670 return ret; 2671 2672 if (!platform->pdata.low_power_mode) { 2673 anx7625_disable_pd_protocol(platform); 2674 pm_runtime_get_sync(dev); 2675 } 2676 2677 /* Add work function */ 2678 if (platform->pdata.intp_irq) 2679 queue_work(platform->workqueue, &platform->work); 2680 2681 platform->bridge.funcs = &anx7625_bridge_funcs; 2682 platform->bridge.of_node = client->dev.of_node; 2683 if (!anx7625_of_panel_on_aux_bus(&client->dev)) 2684 platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 2685 if (!platform->pdata.panel_bridge) 2686 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2687 DRM_BRIDGE_OP_DETECT; 2688 platform->bridge.type = platform->pdata.panel_bridge ? 2689 DRM_MODE_CONNECTOR_eDP : 2690 DRM_MODE_CONNECTOR_DisplayPort; 2691 2692 drm_bridge_add(&platform->bridge); 2693 2694 if (!platform->pdata.is_dpi) { 2695 ret = anx7625_attach_dsi(platform); 2696 if (ret) { 2697 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 2698 goto unregister_bridge; 2699 } 2700 } 2701 2702 if (platform->pdata.audio_en) 2703 anx7625_register_audio(dev, platform); 2704 2705 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2706 2707 return 0; 2708 2709 unregister_bridge: 2710 drm_bridge_remove(&platform->bridge); 2711 2712 if (!platform->pdata.low_power_mode) 2713 pm_runtime_put_sync_suspend(&client->dev); 2714 2715 anx7625_unregister_i2c_dummy_clients(platform); 2716 2717 free_wq: 2718 if (platform->workqueue) 2719 destroy_workqueue(platform->workqueue); 2720 2721 free_hdcp_wq: 2722 if (platform->hdcp_workqueue) 2723 destroy_workqueue(platform->hdcp_workqueue); 2724 2725 return ret; 2726 } 2727 2728 static int anx7625_i2c_remove(struct i2c_client *client) 2729 { 2730 struct anx7625_data *platform = i2c_get_clientdata(client); 2731 2732 drm_bridge_remove(&platform->bridge); 2733 2734 if (platform->pdata.intp_irq) 2735 destroy_workqueue(platform->workqueue); 2736 2737 if (platform->hdcp_workqueue) { 2738 cancel_delayed_work(&platform->hdcp_work); 2739 flush_workqueue(platform->workqueue); 2740 destroy_workqueue(platform->workqueue); 2741 } 2742 2743 if (!platform->pdata.low_power_mode) 2744 pm_runtime_put_sync_suspend(&client->dev); 2745 2746 anx7625_unregister_i2c_dummy_clients(platform); 2747 2748 if (platform->pdata.audio_en) 2749 anx7625_unregister_audio(platform); 2750 2751 return 0; 2752 } 2753 2754 static const struct i2c_device_id anx7625_id[] = { 2755 {"anx7625", 0}, 2756 {} 2757 }; 2758 2759 MODULE_DEVICE_TABLE(i2c, anx7625_id); 2760 2761 static const struct of_device_id anx_match_table[] = { 2762 {.compatible = "analogix,anx7625",}, 2763 {}, 2764 }; 2765 MODULE_DEVICE_TABLE(of, anx_match_table); 2766 2767 static struct i2c_driver anx7625_driver = { 2768 .driver = { 2769 .name = "anx7625", 2770 .of_match_table = anx_match_table, 2771 .pm = &anx7625_pm_ops, 2772 }, 2773 .probe = anx7625_i2c_probe, 2774 .remove = anx7625_i2c_remove, 2775 2776 .id_table = anx7625_id, 2777 }; 2778 2779 module_i2c_driver(anx7625_driver); 2780 2781 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 2782 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 2783 MODULE_LICENSE("GPL v2"); 2784 MODULE_VERSION(ANX7625_DRV_VERSION); 2785