1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/slab.h> 15 #include <linux/types.h> 16 #include <linux/workqueue.h> 17 18 #include <linux/of_gpio.h> 19 #include <linux/of_graph.h> 20 #include <linux/of_platform.h> 21 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_dp_helper.h> 26 #include <drm/drm_edid.h> 27 #include <drm/drm_mipi_dsi.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_panel.h> 30 #include <drm/drm_print.h> 31 #include <drm/drm_probe_helper.h> 32 33 #include <video/display_timing.h> 34 35 #include "anx7625.h" 36 37 /* 38 * There is a sync issue while access I2C register between AP(CPU) and 39 * internal firmware(OCM), to avoid the race condition, AP should access 40 * the reserved slave address before slave address occurs changes. 41 */ 42 static int i2c_access_workaround(struct anx7625_data *ctx, 43 struct i2c_client *client) 44 { 45 u8 offset; 46 struct device *dev = &client->dev; 47 int ret; 48 49 if (client == ctx->last_client) 50 return 0; 51 52 ctx->last_client = client; 53 54 if (client == ctx->i2c.tcpc_client) 55 offset = RSVD_00_ADDR; 56 else if (client == ctx->i2c.tx_p0_client) 57 offset = RSVD_D1_ADDR; 58 else if (client == ctx->i2c.tx_p1_client) 59 offset = RSVD_60_ADDR; 60 else if (client == ctx->i2c.rx_p0_client) 61 offset = RSVD_39_ADDR; 62 else if (client == ctx->i2c.rx_p1_client) 63 offset = RSVD_7F_ADDR; 64 else 65 offset = RSVD_00_ADDR; 66 67 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 68 if (ret < 0) 69 DRM_DEV_ERROR(dev, 70 "fail to access i2c id=%x\n:%x", 71 client->addr, offset); 72 73 return ret; 74 } 75 76 static int anx7625_reg_read(struct anx7625_data *ctx, 77 struct i2c_client *client, u8 reg_addr) 78 { 79 int ret; 80 struct device *dev = &client->dev; 81 82 i2c_access_workaround(ctx, client); 83 84 ret = i2c_smbus_read_byte_data(client, reg_addr); 85 if (ret < 0) 86 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 87 client->addr, reg_addr); 88 89 return ret; 90 } 91 92 static int anx7625_reg_block_read(struct anx7625_data *ctx, 93 struct i2c_client *client, 94 u8 reg_addr, u8 len, u8 *buf) 95 { 96 int ret; 97 struct device *dev = &client->dev; 98 99 i2c_access_workaround(ctx, client); 100 101 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 102 if (ret < 0) 103 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 104 client->addr, reg_addr); 105 106 return ret; 107 } 108 109 static int anx7625_reg_write(struct anx7625_data *ctx, 110 struct i2c_client *client, 111 u8 reg_addr, u8 reg_val) 112 { 113 int ret; 114 struct device *dev = &client->dev; 115 116 i2c_access_workaround(ctx, client); 117 118 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 119 120 if (ret < 0) 121 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 122 client->addr, reg_addr); 123 124 return ret; 125 } 126 127 static int anx7625_write_or(struct anx7625_data *ctx, 128 struct i2c_client *client, 129 u8 offset, u8 mask) 130 { 131 int val; 132 133 val = anx7625_reg_read(ctx, client, offset); 134 if (val < 0) 135 return val; 136 137 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 138 } 139 140 static int anx7625_write_and(struct anx7625_data *ctx, 141 struct i2c_client *client, 142 u8 offset, u8 mask) 143 { 144 int val; 145 146 val = anx7625_reg_read(ctx, client, offset); 147 if (val < 0) 148 return val; 149 150 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 151 } 152 153 static int anx7625_write_and_or(struct anx7625_data *ctx, 154 struct i2c_client *client, 155 u8 offset, u8 and_mask, u8 or_mask) 156 { 157 int val; 158 159 val = anx7625_reg_read(ctx, client, offset); 160 if (val < 0) 161 return val; 162 163 return anx7625_reg_write(ctx, client, 164 offset, (val & and_mask) | (or_mask)); 165 } 166 167 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 168 { 169 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 170 } 171 172 static int wait_aux_op_finish(struct anx7625_data *ctx) 173 { 174 struct device *dev = &ctx->client->dev; 175 int val; 176 int ret; 177 178 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 179 ctx, val, 180 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 181 2000, 182 2000 * 150); 183 if (ret) { 184 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 185 return -EIO; 186 } 187 188 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 189 AP_AUX_CTRL_STATUS); 190 if (val < 0 || (val & 0x0F)) { 191 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 192 val = -EIO; 193 } 194 195 return val; 196 } 197 198 static int anx7625_video_mute_control(struct anx7625_data *ctx, 199 u8 status) 200 { 201 int ret; 202 203 if (status) { 204 /* Set mute on flag */ 205 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 206 AP_AV_STATUS, AP_MIPI_MUTE); 207 /* Clear mipi RX en */ 208 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 209 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 210 } else { 211 /* Mute off flag */ 212 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 213 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 214 /* Set MIPI RX EN */ 215 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 216 AP_AV_STATUS, AP_MIPI_RX_EN); 217 } 218 219 return ret; 220 } 221 222 static int anx7625_config_audio_input(struct anx7625_data *ctx) 223 { 224 struct device *dev = &ctx->client->dev; 225 int ret; 226 227 /* Channel num */ 228 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 229 AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5); 230 231 /* FS */ 232 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 233 AUDIO_CHANNEL_STATUS_4, 234 0xf0, AUDIO_FS_48K); 235 /* Word length */ 236 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 237 AUDIO_CHANNEL_STATUS_5, 238 0xf0, AUDIO_W_LEN_24_24MAX); 239 /* I2S */ 240 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 241 AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE); 242 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 243 AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE); 244 /* Audio change flag */ 245 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 246 AP_AV_STATUS, AP_AUDIO_CHG); 247 248 if (ret < 0) 249 DRM_DEV_ERROR(dev, "fail to config audio.\n"); 250 251 return ret; 252 } 253 254 /* Reduction of fraction a/b */ 255 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 256 { 257 unsigned long gcd_num; 258 unsigned long tmp_a, tmp_b; 259 u32 i = 1; 260 261 gcd_num = gcd(*a, *b); 262 *a /= gcd_num; 263 *b /= gcd_num; 264 265 tmp_a = *a; 266 tmp_b = *b; 267 268 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 269 i++; 270 *a = tmp_a / i; 271 *b = tmp_b / i; 272 } 273 274 /* 275 * In the end, make a, b larger to have higher ODFC PLL 276 * output frequency accuracy 277 */ 278 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 279 *a <<= 1; 280 *b <<= 1; 281 } 282 283 *a >>= 1; 284 *b >>= 1; 285 } 286 287 static int anx7625_calculate_m_n(u32 pixelclock, 288 unsigned long *m, 289 unsigned long *n, 290 u8 *post_divider) 291 { 292 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 293 /* Pixel clock frequency is too high */ 294 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 295 pixelclock, 296 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 297 return -EINVAL; 298 } 299 300 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 301 /* Pixel clock frequency is too low */ 302 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 303 pixelclock, 304 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 305 return -EINVAL; 306 } 307 308 for (*post_divider = 1; 309 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 310 *post_divider += 1; 311 312 if (*post_divider > POST_DIVIDER_MAX) { 313 for (*post_divider = 1; 314 (pixelclock < 315 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 316 *post_divider += 1; 317 318 if (*post_divider > POST_DIVIDER_MAX) { 319 DRM_ERROR("cannot find property post_divider(%d)\n", 320 *post_divider); 321 return -EDOM; 322 } 323 } 324 325 /* Patch to improve the accuracy */ 326 if (*post_divider == 7) { 327 /* 27,000,000 is not divisible by 7 */ 328 *post_divider = 8; 329 } else if (*post_divider == 11) { 330 /* 27,000,000 is not divisible by 11 */ 331 *post_divider = 12; 332 } else if ((*post_divider == 13) || (*post_divider == 14)) { 333 /* 27,000,000 is not divisible by 13 or 14 */ 334 *post_divider = 15; 335 } 336 337 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 338 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 339 pixelclock * (*post_divider), 340 PLL_OUT_FREQ_ABS_MAX); 341 return -EDOM; 342 } 343 344 *m = pixelclock; 345 *n = XTAL_FRQ / (*post_divider); 346 347 anx7625_reduction_of_a_fraction(m, n); 348 349 return 0; 350 } 351 352 static int anx7625_odfc_config(struct anx7625_data *ctx, 353 u8 post_divider) 354 { 355 int ret; 356 struct device *dev = &ctx->client->dev; 357 358 /* Config input reference clock frequency 27MHz/19.2MHz */ 359 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 360 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 361 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 362 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 363 /* Post divider */ 364 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 365 MIPI_DIGITAL_PLL_8, 0x0f); 366 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 367 post_divider << 4); 368 369 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 370 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 371 ~MIPI_PLL_VCO_TUNE_REG_VAL); 372 373 /* Reset ODFC PLL */ 374 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 375 ~MIPI_PLL_RESET_N); 376 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 377 MIPI_PLL_RESET_N); 378 379 if (ret < 0) 380 DRM_DEV_ERROR(dev, "IO error.\n"); 381 382 return ret; 383 } 384 385 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 386 { 387 struct device *dev = &ctx->client->dev; 388 unsigned long m, n; 389 u16 htotal; 390 int ret; 391 u8 post_divider = 0; 392 393 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 394 &m, &n, &post_divider); 395 396 if (ret) { 397 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 398 return ret; 399 } 400 401 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 402 m, n, post_divider); 403 404 /* Configure pixel clock */ 405 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 406 (ctx->dt.pixelclock.min / 1000) & 0xFF); 407 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 408 (ctx->dt.pixelclock.min / 1000) >> 8); 409 /* Lane count */ 410 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 411 MIPI_LANE_CTRL_0, 0xfc); 412 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 413 MIPI_LANE_CTRL_0, 3); 414 415 /* Htotal */ 416 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 417 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 418 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 419 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 420 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 421 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 422 /* Hactive */ 423 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 424 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 425 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 426 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 427 /* HFP */ 428 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 429 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 430 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 431 HORIZONTAL_FRONT_PORCH_H, 432 ctx->dt.hfront_porch.min >> 8); 433 /* HWS */ 434 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 435 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 436 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 437 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 438 /* HBP */ 439 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 440 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 441 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 442 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 443 /* Vactive */ 444 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 445 ctx->dt.vactive.min); 446 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 447 ctx->dt.vactive.min >> 8); 448 /* VFP */ 449 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 450 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 451 /* VWS */ 452 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 453 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 454 /* VBP */ 455 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 456 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 457 /* M value */ 458 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 459 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 460 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 461 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 462 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 463 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 464 /* N value */ 465 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 466 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 467 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 468 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 469 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 470 (n & 0xff)); 471 /* Diff */ 472 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 473 MIPI_DIGITAL_ADJ_1, 0x3D); 474 475 ret |= anx7625_odfc_config(ctx, post_divider - 1); 476 477 if (ret < 0) 478 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 479 480 return ret; 481 } 482 483 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 484 { 485 int val; 486 struct device *dev = &ctx->client->dev; 487 488 /* Swap MIPI-DSI data lane 3 P and N */ 489 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 490 if (val < 0) { 491 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 492 return -EIO; 493 } 494 495 val |= (1 << MIPI_SWAP_CH3); 496 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 497 } 498 499 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 500 501 { 502 int val, ret; 503 struct device *dev = &ctx->client->dev; 504 505 /* Swap MIPI-DSI data lane 3 P and N */ 506 ret = anx7625_swap_dsi_lane3(ctx); 507 if (ret < 0) { 508 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 509 return ret; 510 } 511 512 /* DSI clock settings */ 513 val = (0 << MIPI_HS_PWD_CLK) | 514 (0 << MIPI_HS_RT_CLK) | 515 (0 << MIPI_PD_CLK) | 516 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 517 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 518 (0 << MIPI_CLK_DET_DET_BYPASS) | 519 (0 << MIPI_CLK_MISS_CTRL) | 520 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 521 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 522 MIPI_PHY_CONTROL_3, val); 523 524 /* 525 * Decreased HS prepare timing delay from 160ns to 80ns work with 526 * a) Dragon board 810 series (Qualcomm AP) 527 * b) Moving Pixel DSI source (PG3A pattern generator + 528 * P332 D-PHY Probe) default D-PHY timing 529 * 5ns/step 530 */ 531 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 532 MIPI_TIME_HS_PRPR, 0x10); 533 534 /* Enable DSI mode*/ 535 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 536 SELECT_DSI << MIPI_DPI_SELECT); 537 538 ret |= anx7625_dsi_video_timing_config(ctx); 539 if (ret < 0) { 540 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 541 return ret; 542 } 543 544 /* Toggle m, n ready */ 545 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 546 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 547 usleep_range(1000, 1100); 548 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 549 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 550 551 /* Configure integer stable register */ 552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 553 MIPI_VIDEO_STABLE_CNT, 0x02); 554 /* Power on MIPI RX */ 555 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 556 MIPI_LANE_CTRL_10, 0x00); 557 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 558 MIPI_LANE_CTRL_10, 0x80); 559 560 if (ret < 0) 561 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 562 563 return ret; 564 } 565 566 static int anx7625_dsi_config(struct anx7625_data *ctx) 567 { 568 struct device *dev = &ctx->client->dev; 569 int ret; 570 571 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 572 573 /* DSC disable */ 574 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 575 R_DSC_CTRL_0, ~DSC_EN); 576 577 ret |= anx7625_api_dsi_config(ctx); 578 579 if (ret < 0) { 580 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 581 return ret; 582 } 583 584 /* Set MIPI RX EN */ 585 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 586 AP_AV_STATUS, AP_MIPI_RX_EN); 587 /* Clear mute flag */ 588 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 589 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 590 if (ret < 0) 591 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 592 else 593 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 594 595 return ret; 596 } 597 598 static void anx7625_dp_start(struct anx7625_data *ctx) 599 { 600 int ret; 601 struct device *dev = &ctx->client->dev; 602 603 if (!ctx->display_timing_valid) { 604 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 605 return; 606 } 607 608 anx7625_config_audio_input(ctx); 609 610 ret = anx7625_dsi_config(ctx); 611 612 if (ret < 0) 613 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 614 } 615 616 static void anx7625_dp_stop(struct anx7625_data *ctx) 617 { 618 struct device *dev = &ctx->client->dev; 619 int ret; 620 621 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 622 623 /* 624 * Video disable: 0x72:08 bit 7 = 0; 625 * Audio disable: 0x70:87 bit 0 = 0; 626 */ 627 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 628 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 629 630 ret |= anx7625_video_mute_control(ctx, 1); 631 if (ret < 0) 632 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 633 } 634 635 static int sp_tx_rst_aux(struct anx7625_data *ctx) 636 { 637 int ret; 638 639 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 640 AUX_RST); 641 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 642 ~AUX_RST); 643 return ret; 644 } 645 646 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 647 { 648 int ret; 649 650 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 651 AP_AUX_BUFF_START, offset); 652 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 653 AP_AUX_COMMAND, 0x04); 654 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 655 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 656 return (ret | wait_aux_op_finish(ctx)); 657 } 658 659 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 660 { 661 int ret; 662 663 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 664 AP_AUX_COMMAND, len_cmd); 665 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 666 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 667 return (ret | wait_aux_op_finish(ctx)); 668 } 669 670 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 671 { 672 int c = 0; 673 struct device *dev = &ctx->client->dev; 674 675 sp_tx_aux_wr(ctx, 0x7e); 676 sp_tx_aux_rd(ctx, 0x01); 677 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 678 if (c < 0) { 679 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 680 return -EIO; 681 } 682 683 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 684 685 if (c > MAX_EDID_BLOCK) 686 c = 1; 687 688 return c; 689 } 690 691 static int edid_read(struct anx7625_data *ctx, 692 u8 offset, u8 *pblock_buf) 693 { 694 int ret, cnt; 695 struct device *dev = &ctx->client->dev; 696 697 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 698 sp_tx_aux_wr(ctx, offset); 699 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 700 ret = sp_tx_aux_rd(ctx, 0xf1); 701 702 if (ret) { 703 sp_tx_rst_aux(ctx); 704 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 705 } else { 706 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 707 AP_AUX_BUFF_START, 708 MAX_DPCD_BUFFER_SIZE, 709 pblock_buf); 710 if (ret > 0) 711 break; 712 } 713 } 714 715 if (cnt > EDID_TRY_CNT) 716 return -EIO; 717 718 return 0; 719 } 720 721 static int segments_edid_read(struct anx7625_data *ctx, 722 u8 segment, u8 *buf, u8 offset) 723 { 724 u8 cnt; 725 int ret; 726 struct device *dev = &ctx->client->dev; 727 728 /* Write address only */ 729 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 730 AP_AUX_ADDR_7_0, 0x30); 731 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 732 AP_AUX_COMMAND, 0x04); 733 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 734 AP_AUX_CTRL_STATUS, 735 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 736 737 ret |= wait_aux_op_finish(ctx); 738 /* Write segment address */ 739 ret |= sp_tx_aux_wr(ctx, segment); 740 /* Data read */ 741 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 742 AP_AUX_ADDR_7_0, 0x50); 743 if (ret) { 744 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 745 return ret; 746 } 747 748 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 749 sp_tx_aux_wr(ctx, offset); 750 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 751 ret = sp_tx_aux_rd(ctx, 0xf1); 752 753 if (ret) { 754 ret = sp_tx_rst_aux(ctx); 755 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 756 } else { 757 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 758 AP_AUX_BUFF_START, 759 MAX_DPCD_BUFFER_SIZE, buf); 760 if (ret > 0) 761 break; 762 } 763 } 764 765 if (cnt > EDID_TRY_CNT) 766 return -EIO; 767 768 return 0; 769 } 770 771 static int sp_tx_edid_read(struct anx7625_data *ctx, 772 u8 *pedid_blocks_buf) 773 { 774 u8 offset, edid_pos; 775 int count, blocks_num; 776 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 777 u8 i, j; 778 u8 g_edid_break = 0; 779 int ret; 780 struct device *dev = &ctx->client->dev; 781 782 /* Address initial */ 783 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 784 AP_AUX_ADDR_7_0, 0x50); 785 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 786 AP_AUX_ADDR_15_8, 0); 787 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 788 AP_AUX_ADDR_19_16, 0xf0); 789 if (ret < 0) { 790 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 791 return -EIO; 792 } 793 794 blocks_num = sp_tx_get_edid_block(ctx); 795 if (blocks_num < 0) 796 return blocks_num; 797 798 count = 0; 799 800 do { 801 switch (count) { 802 case 0: 803 case 1: 804 for (i = 0; i < 8; i++) { 805 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 806 g_edid_break = edid_read(ctx, offset, 807 pblock_buf); 808 809 if (g_edid_break) 810 break; 811 812 memcpy(&pedid_blocks_buf[offset], 813 pblock_buf, 814 MAX_DPCD_BUFFER_SIZE); 815 } 816 817 break; 818 case 2: 819 offset = 0x00; 820 821 for (j = 0; j < 8; j++) { 822 edid_pos = (j + count * 8) * 823 MAX_DPCD_BUFFER_SIZE; 824 825 if (g_edid_break == 1) 826 break; 827 828 segments_edid_read(ctx, count / 2, 829 pblock_buf, offset); 830 memcpy(&pedid_blocks_buf[edid_pos], 831 pblock_buf, 832 MAX_DPCD_BUFFER_SIZE); 833 offset = offset + 0x10; 834 } 835 836 break; 837 case 3: 838 offset = 0x80; 839 840 for (j = 0; j < 8; j++) { 841 edid_pos = (j + count * 8) * 842 MAX_DPCD_BUFFER_SIZE; 843 if (g_edid_break == 1) 844 break; 845 846 segments_edid_read(ctx, count / 2, 847 pblock_buf, offset); 848 memcpy(&pedid_blocks_buf[edid_pos], 849 pblock_buf, 850 MAX_DPCD_BUFFER_SIZE); 851 offset = offset + 0x10; 852 } 853 854 break; 855 default: 856 break; 857 } 858 859 count++; 860 861 } while (blocks_num >= count); 862 863 /* Check edid data */ 864 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 865 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 866 return -EINVAL; 867 } 868 869 /* Reset aux channel */ 870 sp_tx_rst_aux(ctx); 871 872 return (blocks_num + 1); 873 } 874 875 static void anx7625_power_on(struct anx7625_data *ctx) 876 { 877 struct device *dev = &ctx->client->dev; 878 879 if (!ctx->pdata.low_power_mode) { 880 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 881 return; 882 } 883 884 /* Power on pin enable */ 885 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 886 usleep_range(10000, 11000); 887 /* Power reset pin enable */ 888 gpiod_set_value(ctx->pdata.gpio_reset, 1); 889 usleep_range(10000, 11000); 890 891 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 892 } 893 894 static void anx7625_power_standby(struct anx7625_data *ctx) 895 { 896 struct device *dev = &ctx->client->dev; 897 898 if (!ctx->pdata.low_power_mode) { 899 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 900 return; 901 } 902 903 gpiod_set_value(ctx->pdata.gpio_reset, 0); 904 usleep_range(1000, 1100); 905 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 906 usleep_range(1000, 1100); 907 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 908 } 909 910 /* Basic configurations of ANX7625 */ 911 static void anx7625_config(struct anx7625_data *ctx) 912 { 913 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 914 XTAL_FRQ_SEL, XTAL_FRQ_27M); 915 } 916 917 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 918 { 919 struct device *dev = &ctx->client->dev; 920 int ret; 921 922 /* Reset main ocm */ 923 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 924 /* Disable PD */ 925 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 926 AP_AV_STATUS, AP_DISABLE_PD); 927 /* Release main ocm */ 928 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 929 930 if (ret < 0) 931 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 932 else 933 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 934 } 935 936 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 937 { 938 int ret; 939 struct device *dev = &ctx->client->dev; 940 941 /* Check interface workable */ 942 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 943 FLASH_LOAD_STA); 944 if (ret < 0) { 945 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 946 return ret; 947 } 948 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 949 return -ENODEV; 950 951 anx7625_disable_pd_protocol(ctx); 952 953 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 954 anx7625_reg_read(ctx, 955 ctx->i2c.rx_p0_client, 956 OCM_FW_VERSION), 957 anx7625_reg_read(ctx, 958 ctx->i2c.rx_p0_client, 959 OCM_FW_REVERSION)); 960 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 961 ANX7625_DRV_VERSION); 962 963 return 0; 964 } 965 966 static void anx7625_power_on_init(struct anx7625_data *ctx) 967 { 968 int retry_count, i; 969 970 for (retry_count = 0; retry_count < 3; retry_count++) { 971 anx7625_power_on(ctx); 972 anx7625_config(ctx); 973 974 for (i = 0; i < OCM_LOADING_TIME; i++) { 975 if (!anx7625_ocm_loading_check(ctx)) 976 return; 977 usleep_range(1000, 1100); 978 } 979 anx7625_power_standby(ctx); 980 } 981 } 982 983 static void anx7625_chip_control(struct anx7625_data *ctx, int state) 984 { 985 struct device *dev = &ctx->client->dev; 986 987 DRM_DEV_DEBUG_DRIVER(dev, "before set, power_state(%d).\n", 988 atomic_read(&ctx->power_status)); 989 990 if (!ctx->pdata.low_power_mode) 991 return; 992 993 if (state) { 994 atomic_inc(&ctx->power_status); 995 if (atomic_read(&ctx->power_status) == 1) 996 anx7625_power_on_init(ctx); 997 } else { 998 if (atomic_read(&ctx->power_status)) { 999 atomic_dec(&ctx->power_status); 1000 1001 if (atomic_read(&ctx->power_status) == 0) 1002 anx7625_power_standby(ctx); 1003 } 1004 } 1005 1006 DRM_DEV_DEBUG_DRIVER(dev, "after set, power_state(%d).\n", 1007 atomic_read(&ctx->power_status)); 1008 } 1009 1010 static void anx7625_init_gpio(struct anx7625_data *platform) 1011 { 1012 struct device *dev = &platform->client->dev; 1013 1014 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1015 1016 /* Gpio for chip power enable */ 1017 platform->pdata.gpio_p_on = 1018 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1019 /* Gpio for chip reset */ 1020 platform->pdata.gpio_reset = 1021 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1022 1023 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1024 platform->pdata.low_power_mode = 1; 1025 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1026 desc_to_gpio(platform->pdata.gpio_p_on), 1027 desc_to_gpio(platform->pdata.gpio_reset)); 1028 } else { 1029 platform->pdata.low_power_mode = 0; 1030 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1031 } 1032 } 1033 1034 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1035 { 1036 ctx->hpd_status = 0; 1037 ctx->hpd_high_cnt = 0; 1038 ctx->display_timing_valid = 0; 1039 1040 if (ctx->pdata.low_power_mode == 0) 1041 anx7625_disable_pd_protocol(ctx); 1042 } 1043 1044 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1045 { 1046 int ret; 1047 struct device *dev = &ctx->client->dev; 1048 1049 if (ctx->hpd_high_cnt >= 2) { 1050 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1051 return; 1052 } 1053 1054 ctx->hpd_high_cnt++; 1055 1056 /* Not support HDCP */ 1057 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1058 1059 /* Try auth flag */ 1060 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1061 /* Interrupt for DRM */ 1062 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1063 if (ret < 0) 1064 return; 1065 1066 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1067 if (ret < 0) 1068 return; 1069 1070 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1071 } 1072 1073 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1074 { 1075 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1076 } 1077 1078 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1079 { 1080 int ret, val; 1081 struct device *dev = &ctx->client->dev; 1082 1083 if (atomic_read(&ctx->power_status) != 1) { 1084 DRM_DEV_DEBUG_DRIVER(dev, "No need to poling HPD status.\n"); 1085 return; 1086 } 1087 1088 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1089 ctx, val, 1090 ((val & HPD_STATUS) || (val < 0)), 1091 5000, 1092 5000 * 100); 1093 if (ret) { 1094 DRM_DEV_ERROR(dev, "HPD polling timeout!\n"); 1095 } else { 1096 DRM_DEV_DEBUG_DRIVER(dev, "HPD raise up.\n"); 1097 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1098 INTR_ALERT_1, 0xFF); 1099 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1100 INTERFACE_CHANGE_INT, 0); 1101 } 1102 1103 anx7625_start_dp_work(ctx); 1104 } 1105 1106 static void anx7625_disconnect_check(struct anx7625_data *ctx) 1107 { 1108 if (atomic_read(&ctx->power_status) == 0) 1109 anx7625_stop_dp_work(ctx); 1110 } 1111 1112 static void anx7625_low_power_mode_check(struct anx7625_data *ctx, 1113 int state) 1114 { 1115 struct device *dev = &ctx->client->dev; 1116 1117 DRM_DEV_DEBUG_DRIVER(dev, "low power mode check, state(%d).\n", state); 1118 1119 if (ctx->pdata.low_power_mode) { 1120 anx7625_chip_control(ctx, state); 1121 if (state) 1122 anx7625_hpd_polling(ctx); 1123 else 1124 anx7625_disconnect_check(ctx); 1125 } 1126 } 1127 1128 static void anx7625_remove_edid(struct anx7625_data *ctx) 1129 { 1130 ctx->slimport_edid_p.edid_block_num = -1; 1131 } 1132 1133 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1134 { 1135 struct device *dev = &ctx->client->dev; 1136 1137 /* HPD changed */ 1138 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1139 (u32)on); 1140 1141 if (on == 0) { 1142 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1143 anx7625_remove_edid(ctx); 1144 anx7625_stop_dp_work(ctx); 1145 } else { 1146 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1147 anx7625_start_dp_work(ctx); 1148 } 1149 1150 ctx->hpd_status = 1; 1151 } 1152 1153 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1154 { 1155 int intr_vector, status; 1156 struct device *dev = &ctx->client->dev; 1157 1158 DRM_DEV_DEBUG_DRIVER(dev, "power_status=%d\n", 1159 (u32)atomic_read(&ctx->power_status)); 1160 1161 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1162 INTR_ALERT_1, 0xFF); 1163 if (status < 0) { 1164 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1165 return status; 1166 } 1167 1168 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1169 INTERFACE_CHANGE_INT); 1170 if (intr_vector < 0) { 1171 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1172 return intr_vector; 1173 } 1174 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1175 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1176 INTERFACE_CHANGE_INT, 1177 intr_vector & (~intr_vector)); 1178 if (status < 0) { 1179 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1180 return status; 1181 } 1182 1183 if (!(intr_vector & HPD_STATUS_CHANGE)) 1184 return -ENOENT; 1185 1186 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1187 SYSTEM_STSTUS); 1188 if (status < 0) { 1189 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1190 return status; 1191 } 1192 1193 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1194 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1195 1196 return 0; 1197 } 1198 1199 static void anx7625_work_func(struct work_struct *work) 1200 { 1201 int event; 1202 struct anx7625_data *ctx = container_of(work, 1203 struct anx7625_data, work); 1204 1205 mutex_lock(&ctx->lock); 1206 event = anx7625_hpd_change_detect(ctx); 1207 mutex_unlock(&ctx->lock); 1208 if (event < 0) 1209 return; 1210 1211 if (ctx->bridge_attached) 1212 drm_helper_hpd_irq_event(ctx->bridge.dev); 1213 } 1214 1215 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1216 { 1217 struct anx7625_data *ctx = (struct anx7625_data *)data; 1218 1219 if (atomic_read(&ctx->power_status) != 1) 1220 return IRQ_NONE; 1221 1222 queue_work(ctx->workqueue, &ctx->work); 1223 1224 return IRQ_HANDLED; 1225 } 1226 1227 static int anx7625_parse_dt(struct device *dev, 1228 struct anx7625_platform_data *pdata) 1229 { 1230 struct device_node *np = dev->of_node; 1231 struct drm_panel *panel; 1232 int ret; 1233 1234 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1235 if (!pdata->mipi_host_node) { 1236 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1237 return -ENODEV; 1238 } 1239 1240 DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n"); 1241 1242 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1243 if (ret < 0) { 1244 if (ret == -ENODEV) 1245 return 0; 1246 return ret; 1247 } 1248 if (!panel) 1249 return -ENODEV; 1250 1251 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1252 if (IS_ERR(pdata->panel_bridge)) 1253 return PTR_ERR(pdata->panel_bridge); 1254 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1255 1256 return 0; 1257 } 1258 1259 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1260 { 1261 return container_of(bridge, struct anx7625_data, bridge); 1262 } 1263 1264 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1265 { 1266 struct device *dev = &ctx->client->dev; 1267 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1268 int edid_num; 1269 u8 *edid; 1270 1271 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1272 if (!edid) { 1273 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1274 return NULL; 1275 } 1276 1277 if (ctx->slimport_edid_p.edid_block_num > 0) { 1278 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1279 FOUR_BLOCK_SIZE); 1280 return (struct edid *)edid; 1281 } 1282 1283 anx7625_low_power_mode_check(ctx, 1); 1284 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1285 anx7625_low_power_mode_check(ctx, 0); 1286 1287 if (edid_num < 1) { 1288 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1289 kfree(edid); 1290 return NULL; 1291 } 1292 1293 p_edid->edid_block_num = edid_num; 1294 1295 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1296 return (struct edid *)edid; 1297 } 1298 1299 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1300 { 1301 struct device *dev = &ctx->client->dev; 1302 1303 DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n"); 1304 1305 return connector_status_connected; 1306 } 1307 1308 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1309 { 1310 struct mipi_dsi_device *dsi; 1311 struct device *dev = &ctx->client->dev; 1312 struct mipi_dsi_host *host; 1313 const struct mipi_dsi_device_info info = { 1314 .type = "anx7625", 1315 .channel = 0, 1316 .node = NULL, 1317 }; 1318 1319 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1320 1321 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1322 if (!host) { 1323 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1324 return -EINVAL; 1325 } 1326 1327 dsi = mipi_dsi_device_register_full(host, &info); 1328 if (IS_ERR(dsi)) { 1329 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 1330 return -EINVAL; 1331 } 1332 1333 dsi->lanes = 4; 1334 dsi->format = MIPI_DSI_FMT_RGB888; 1335 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1336 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1337 MIPI_DSI_MODE_EOT_PACKET | 1338 MIPI_DSI_MODE_VIDEO_HSE; 1339 1340 if (mipi_dsi_attach(dsi) < 0) { 1341 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 1342 mipi_dsi_device_unregister(dsi); 1343 return -EINVAL; 1344 } 1345 1346 ctx->dsi = dsi; 1347 1348 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 1349 1350 return 0; 1351 } 1352 1353 static void anx7625_bridge_detach(struct drm_bridge *bridge) 1354 { 1355 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1356 1357 if (ctx->dsi) { 1358 mipi_dsi_detach(ctx->dsi); 1359 mipi_dsi_device_unregister(ctx->dsi); 1360 } 1361 } 1362 1363 static int anx7625_bridge_attach(struct drm_bridge *bridge, 1364 enum drm_bridge_attach_flags flags) 1365 { 1366 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1367 int err; 1368 struct device *dev = &ctx->client->dev; 1369 1370 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 1371 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 1372 return -EINVAL; 1373 1374 if (!bridge->encoder) { 1375 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 1376 return -ENODEV; 1377 } 1378 1379 err = anx7625_attach_dsi(ctx); 1380 if (err) { 1381 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); 1382 return err; 1383 } 1384 1385 if (ctx->pdata.panel_bridge) { 1386 err = drm_bridge_attach(bridge->encoder, 1387 ctx->pdata.panel_bridge, 1388 &ctx->bridge, flags); 1389 if (err) { 1390 DRM_DEV_ERROR(dev, 1391 "Fail to attach panel bridge: %d\n", err); 1392 return err; 1393 } 1394 } 1395 1396 ctx->bridge_attached = 1; 1397 1398 return 0; 1399 } 1400 1401 static enum drm_mode_status 1402 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 1403 const struct drm_display_info *info, 1404 const struct drm_display_mode *mode) 1405 { 1406 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1407 struct device *dev = &ctx->client->dev; 1408 1409 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 1410 1411 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 1412 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 1413 DRM_DEV_DEBUG_DRIVER(dev, 1414 "drm mode invalid, pixelclock too high.\n"); 1415 return MODE_CLOCK_HIGH; 1416 } 1417 1418 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 1419 1420 return MODE_OK; 1421 } 1422 1423 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 1424 const struct drm_display_mode *old_mode, 1425 const struct drm_display_mode *mode) 1426 { 1427 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1428 struct device *dev = &ctx->client->dev; 1429 1430 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 1431 1432 ctx->dt.pixelclock.min = mode->clock; 1433 ctx->dt.hactive.min = mode->hdisplay; 1434 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 1435 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 1436 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 1437 ctx->dt.vactive.min = mode->vdisplay; 1438 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 1439 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 1440 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 1441 1442 ctx->display_timing_valid = 1; 1443 1444 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 1445 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 1446 ctx->dt.hactive.min, 1447 ctx->dt.hsync_len.min, 1448 ctx->dt.hfront_porch.min, 1449 ctx->dt.hback_porch.min); 1450 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 1451 ctx->dt.vactive.min, 1452 ctx->dt.vsync_len.min, 1453 ctx->dt.vfront_porch.min, 1454 ctx->dt.vback_porch.min); 1455 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 1456 mode->hdisplay, 1457 mode->hsync_start); 1458 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 1459 mode->hsync_end, 1460 mode->htotal); 1461 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 1462 mode->vdisplay, 1463 mode->vsync_start); 1464 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 1465 mode->vsync_end, 1466 mode->vtotal); 1467 } 1468 1469 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 1470 const struct drm_display_mode *mode, 1471 struct drm_display_mode *adj) 1472 { 1473 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1474 struct device *dev = &ctx->client->dev; 1475 u32 hsync, hfp, hbp, hblanking; 1476 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 1477 u32 vref, adj_clock; 1478 1479 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 1480 1481 hsync = mode->hsync_end - mode->hsync_start; 1482 hfp = mode->hsync_start - mode->hdisplay; 1483 hbp = mode->htotal - mode->hsync_end; 1484 hblanking = mode->htotal - mode->hdisplay; 1485 1486 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 1487 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1488 hsync, hfp, hbp, adj->clock); 1489 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1490 adj->hsync_start, adj->hsync_end, adj->htotal); 1491 1492 adj_hfp = hfp; 1493 adj_hsync = hsync; 1494 adj_hbp = hbp; 1495 adj_hblanking = hblanking; 1496 1497 /* HFP needs to be even */ 1498 if (hfp & 0x1) { 1499 adj_hfp += 1; 1500 adj_hblanking += 1; 1501 } 1502 1503 /* HBP needs to be even */ 1504 if (hbp & 0x1) { 1505 adj_hbp -= 1; 1506 adj_hblanking -= 1; 1507 } 1508 1509 /* HSYNC needs to be even */ 1510 if (hsync & 0x1) { 1511 if (adj_hblanking < hblanking) 1512 adj_hsync += 1; 1513 else 1514 adj_hsync -= 1; 1515 } 1516 1517 /* 1518 * Once illegal timing detected, use default HFP, HSYNC, HBP 1519 * This adjusting made for built-in eDP panel, for the externel 1520 * DP monitor, may need return false. 1521 */ 1522 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 1523 adj_hsync = SYNC_LEN_DEF; 1524 adj_hfp = HFP_HBP_DEF; 1525 adj_hbp = HFP_HBP_DEF; 1526 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 1527 if (hblanking < HBLANKING_MIN) { 1528 delta_adj = HBLANKING_MIN - hblanking; 1529 adj_clock = vref * delta_adj * adj->vtotal; 1530 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 1531 } else { 1532 delta_adj = hblanking - HBLANKING_MIN; 1533 adj_clock = vref * delta_adj * adj->vtotal; 1534 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 1535 } 1536 1537 DRM_WARN("illegal hblanking timing, use default.\n"); 1538 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 1539 } else if (adj_hfp < HP_MIN) { 1540 /* Adjust hfp if hfp less than HP_MIN */ 1541 delta_adj = HP_MIN - adj_hfp; 1542 adj_hfp = HP_MIN; 1543 1544 /* 1545 * Balance total HBlanking pixel, if HBP does not have enough 1546 * space, adjust HSYNC length, otherwise adjust HBP 1547 */ 1548 if ((adj_hbp - delta_adj) < HP_MIN) 1549 /* HBP not enough space */ 1550 adj_hsync -= delta_adj; 1551 else 1552 adj_hbp -= delta_adj; 1553 } else if (adj_hbp < HP_MIN) { 1554 delta_adj = HP_MIN - adj_hbp; 1555 adj_hbp = HP_MIN; 1556 1557 /* 1558 * Balance total HBlanking pixel, if HBP hasn't enough space, 1559 * adjust HSYNC length, otherwize adjust HBP 1560 */ 1561 if ((adj_hfp - delta_adj) < HP_MIN) 1562 /* HFP not enough space */ 1563 adj_hsync -= delta_adj; 1564 else 1565 adj_hfp -= delta_adj; 1566 } 1567 1568 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 1569 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1570 adj_hsync, adj_hfp, adj_hbp, adj->clock); 1571 1572 /* Reconstruct timing */ 1573 adj->hsync_start = adj->hdisplay + adj_hfp; 1574 adj->hsync_end = adj->hsync_start + adj_hsync; 1575 adj->htotal = adj->hsync_end + adj_hbp; 1576 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1577 adj->hsync_start, adj->hsync_end, adj->htotal); 1578 1579 return true; 1580 } 1581 1582 static void anx7625_bridge_enable(struct drm_bridge *bridge) 1583 { 1584 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1585 struct device *dev = &ctx->client->dev; 1586 1587 DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 1588 1589 anx7625_low_power_mode_check(ctx, 1); 1590 1591 if (WARN_ON(!atomic_read(&ctx->power_status))) 1592 return; 1593 1594 anx7625_dp_start(ctx); 1595 } 1596 1597 static void anx7625_bridge_disable(struct drm_bridge *bridge) 1598 { 1599 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1600 struct device *dev = &ctx->client->dev; 1601 1602 if (WARN_ON(!atomic_read(&ctx->power_status))) 1603 return; 1604 1605 DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 1606 1607 anx7625_dp_stop(ctx); 1608 1609 anx7625_low_power_mode_check(ctx, 0); 1610 } 1611 1612 static enum drm_connector_status 1613 anx7625_bridge_detect(struct drm_bridge *bridge) 1614 { 1615 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1616 struct device *dev = &ctx->client->dev; 1617 1618 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 1619 1620 return anx7625_sink_detect(ctx); 1621 } 1622 1623 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 1624 struct drm_connector *connector) 1625 { 1626 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1627 struct device *dev = &ctx->client->dev; 1628 1629 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 1630 1631 return anx7625_get_edid(ctx); 1632 } 1633 1634 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 1635 .attach = anx7625_bridge_attach, 1636 .detach = anx7625_bridge_detach, 1637 .disable = anx7625_bridge_disable, 1638 .mode_valid = anx7625_bridge_mode_valid, 1639 .mode_set = anx7625_bridge_mode_set, 1640 .mode_fixup = anx7625_bridge_mode_fixup, 1641 .enable = anx7625_bridge_enable, 1642 .detect = anx7625_bridge_detect, 1643 .get_edid = anx7625_bridge_get_edid, 1644 }; 1645 1646 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 1647 struct i2c_client *client) 1648 { 1649 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 1650 TX_P0_ADDR >> 1); 1651 if (!ctx->i2c.tx_p0_client) 1652 return -ENOMEM; 1653 1654 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 1655 TX_P1_ADDR >> 1); 1656 if (!ctx->i2c.tx_p1_client) 1657 goto free_tx_p0; 1658 1659 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 1660 TX_P2_ADDR >> 1); 1661 if (!ctx->i2c.tx_p2_client) 1662 goto free_tx_p1; 1663 1664 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 1665 RX_P0_ADDR >> 1); 1666 if (!ctx->i2c.rx_p0_client) 1667 goto free_tx_p2; 1668 1669 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 1670 RX_P1_ADDR >> 1); 1671 if (!ctx->i2c.rx_p1_client) 1672 goto free_rx_p0; 1673 1674 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 1675 RX_P2_ADDR >> 1); 1676 if (!ctx->i2c.rx_p2_client) 1677 goto free_rx_p1; 1678 1679 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 1680 TCPC_INTERFACE_ADDR >> 1); 1681 if (!ctx->i2c.tcpc_client) 1682 goto free_rx_p2; 1683 1684 return 0; 1685 1686 free_rx_p2: 1687 i2c_unregister_device(ctx->i2c.rx_p2_client); 1688 free_rx_p1: 1689 i2c_unregister_device(ctx->i2c.rx_p1_client); 1690 free_rx_p0: 1691 i2c_unregister_device(ctx->i2c.rx_p0_client); 1692 free_tx_p2: 1693 i2c_unregister_device(ctx->i2c.tx_p2_client); 1694 free_tx_p1: 1695 i2c_unregister_device(ctx->i2c.tx_p1_client); 1696 free_tx_p0: 1697 i2c_unregister_device(ctx->i2c.tx_p0_client); 1698 1699 return -ENOMEM; 1700 } 1701 1702 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 1703 { 1704 i2c_unregister_device(ctx->i2c.tx_p0_client); 1705 i2c_unregister_device(ctx->i2c.tx_p1_client); 1706 i2c_unregister_device(ctx->i2c.tx_p2_client); 1707 i2c_unregister_device(ctx->i2c.rx_p0_client); 1708 i2c_unregister_device(ctx->i2c.rx_p1_client); 1709 i2c_unregister_device(ctx->i2c.rx_p2_client); 1710 i2c_unregister_device(ctx->i2c.tcpc_client); 1711 } 1712 1713 static int anx7625_i2c_probe(struct i2c_client *client, 1714 const struct i2c_device_id *id) 1715 { 1716 struct anx7625_data *platform; 1717 struct anx7625_platform_data *pdata; 1718 int ret = 0; 1719 struct device *dev = &client->dev; 1720 1721 if (!i2c_check_functionality(client->adapter, 1722 I2C_FUNC_SMBUS_I2C_BLOCK)) { 1723 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 1724 return -ENODEV; 1725 } 1726 1727 platform = kzalloc(sizeof(*platform), GFP_KERNEL); 1728 if (!platform) { 1729 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 1730 return -ENOMEM; 1731 } 1732 1733 pdata = &platform->pdata; 1734 1735 ret = anx7625_parse_dt(dev, pdata); 1736 if (ret) { 1737 if (ret != -EPROBE_DEFER) 1738 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 1739 goto free_platform; 1740 } 1741 1742 platform->client = client; 1743 i2c_set_clientdata(client, platform); 1744 1745 anx7625_init_gpio(platform); 1746 1747 atomic_set(&platform->power_status, 0); 1748 1749 mutex_init(&platform->lock); 1750 1751 platform->pdata.intp_irq = client->irq; 1752 if (platform->pdata.intp_irq) { 1753 INIT_WORK(&platform->work, anx7625_work_func); 1754 platform->workqueue = create_workqueue("anx7625_work"); 1755 if (!platform->workqueue) { 1756 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 1757 ret = -ENOMEM; 1758 goto free_platform; 1759 } 1760 1761 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 1762 NULL, anx7625_intr_hpd_isr, 1763 IRQF_TRIGGER_FALLING | 1764 IRQF_ONESHOT, 1765 "anx7625-intp", platform); 1766 if (ret) { 1767 DRM_DEV_ERROR(dev, "fail to request irq\n"); 1768 goto free_wq; 1769 } 1770 } 1771 1772 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 1773 ret = -ENOMEM; 1774 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 1775 goto free_wq; 1776 } 1777 1778 if (platform->pdata.low_power_mode == 0) { 1779 anx7625_disable_pd_protocol(platform); 1780 atomic_set(&platform->power_status, 1); 1781 } 1782 1783 /* Add work function */ 1784 if (platform->pdata.intp_irq) 1785 queue_work(platform->workqueue, &platform->work); 1786 1787 platform->bridge.funcs = &anx7625_bridge_funcs; 1788 platform->bridge.of_node = client->dev.of_node; 1789 platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 1790 platform->bridge.type = DRM_MODE_CONNECTOR_eDP; 1791 drm_bridge_add(&platform->bridge); 1792 1793 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 1794 1795 return 0; 1796 1797 free_wq: 1798 if (platform->workqueue) 1799 destroy_workqueue(platform->workqueue); 1800 1801 free_platform: 1802 kfree(platform); 1803 1804 return ret; 1805 } 1806 1807 static int anx7625_i2c_remove(struct i2c_client *client) 1808 { 1809 struct anx7625_data *platform = i2c_get_clientdata(client); 1810 1811 drm_bridge_remove(&platform->bridge); 1812 1813 if (platform->pdata.intp_irq) 1814 destroy_workqueue(platform->workqueue); 1815 1816 anx7625_unregister_i2c_dummy_clients(platform); 1817 1818 kfree(platform); 1819 return 0; 1820 } 1821 1822 static const struct i2c_device_id anx7625_id[] = { 1823 {"anx7625", 0}, 1824 {} 1825 }; 1826 1827 MODULE_DEVICE_TABLE(i2c, anx7625_id); 1828 1829 static const struct of_device_id anx_match_table[] = { 1830 {.compatible = "analogix,anx7625",}, 1831 {}, 1832 }; 1833 1834 static struct i2c_driver anx7625_driver = { 1835 .driver = { 1836 .name = "anx7625", 1837 .of_match_table = anx_match_table, 1838 }, 1839 .probe = anx7625_i2c_probe, 1840 .remove = anx7625_i2c_remove, 1841 1842 .id_table = anx7625_id, 1843 }; 1844 1845 module_i2c_driver(anx7625_driver); 1846 1847 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 1848 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 1849 MODULE_LICENSE("GPL v2"); 1850 MODULE_VERSION(ANX7625_DRV_VERSION); 1851