1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_gpio.h> 21 #include <linux/of_graph.h> 22 #include <linux/of_platform.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/dp/drm_dp_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_hdcp.h> 30 #include <drm/drm_mipi_dsi.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_panel.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_probe_helper.h> 35 36 #include <media/v4l2-fwnode.h> 37 #include <sound/hdmi-codec.h> 38 #include <video/display_timing.h> 39 40 #include "anx7625.h" 41 42 /* 43 * There is a sync issue while access I2C register between AP(CPU) and 44 * internal firmware(OCM), to avoid the race condition, AP should access 45 * the reserved slave address before slave address occurs changes. 46 */ 47 static int i2c_access_workaround(struct anx7625_data *ctx, 48 struct i2c_client *client) 49 { 50 u8 offset; 51 struct device *dev = &client->dev; 52 int ret; 53 54 if (client == ctx->last_client) 55 return 0; 56 57 ctx->last_client = client; 58 59 if (client == ctx->i2c.tcpc_client) 60 offset = RSVD_00_ADDR; 61 else if (client == ctx->i2c.tx_p0_client) 62 offset = RSVD_D1_ADDR; 63 else if (client == ctx->i2c.tx_p1_client) 64 offset = RSVD_60_ADDR; 65 else if (client == ctx->i2c.rx_p0_client) 66 offset = RSVD_39_ADDR; 67 else if (client == ctx->i2c.rx_p1_client) 68 offset = RSVD_7F_ADDR; 69 else 70 offset = RSVD_00_ADDR; 71 72 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 73 if (ret < 0) 74 DRM_DEV_ERROR(dev, 75 "fail to access i2c id=%x\n:%x", 76 client->addr, offset); 77 78 return ret; 79 } 80 81 static int anx7625_reg_read(struct anx7625_data *ctx, 82 struct i2c_client *client, u8 reg_addr) 83 { 84 int ret; 85 struct device *dev = &client->dev; 86 87 i2c_access_workaround(ctx, client); 88 89 ret = i2c_smbus_read_byte_data(client, reg_addr); 90 if (ret < 0) 91 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 92 client->addr, reg_addr); 93 94 return ret; 95 } 96 97 static int anx7625_reg_block_read(struct anx7625_data *ctx, 98 struct i2c_client *client, 99 u8 reg_addr, u8 len, u8 *buf) 100 { 101 int ret; 102 struct device *dev = &client->dev; 103 104 i2c_access_workaround(ctx, client); 105 106 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 107 if (ret < 0) 108 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 109 client->addr, reg_addr); 110 111 return ret; 112 } 113 114 static int anx7625_reg_write(struct anx7625_data *ctx, 115 struct i2c_client *client, 116 u8 reg_addr, u8 reg_val) 117 { 118 int ret; 119 struct device *dev = &client->dev; 120 121 i2c_access_workaround(ctx, client); 122 123 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 124 125 if (ret < 0) 126 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 127 client->addr, reg_addr); 128 129 return ret; 130 } 131 132 static int anx7625_write_or(struct anx7625_data *ctx, 133 struct i2c_client *client, 134 u8 offset, u8 mask) 135 { 136 int val; 137 138 val = anx7625_reg_read(ctx, client, offset); 139 if (val < 0) 140 return val; 141 142 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 143 } 144 145 static int anx7625_write_and(struct anx7625_data *ctx, 146 struct i2c_client *client, 147 u8 offset, u8 mask) 148 { 149 int val; 150 151 val = anx7625_reg_read(ctx, client, offset); 152 if (val < 0) 153 return val; 154 155 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 156 } 157 158 static int anx7625_write_and_or(struct anx7625_data *ctx, 159 struct i2c_client *client, 160 u8 offset, u8 and_mask, u8 or_mask) 161 { 162 int val; 163 164 val = anx7625_reg_read(ctx, client, offset); 165 if (val < 0) 166 return val; 167 168 return anx7625_reg_write(ctx, client, 169 offset, (val & and_mask) | (or_mask)); 170 } 171 172 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 173 { 174 int i, ret; 175 176 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 177 AUDIO_CONTROL_REGISTER, 0x80); 178 for (i = 0; i < 13; i++) 179 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 180 VIDEO_BIT_MATRIX_12 + i, 181 0x18 + i); 182 183 return ret; 184 } 185 186 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 187 { 188 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 189 } 190 191 static int wait_aux_op_finish(struct anx7625_data *ctx) 192 { 193 struct device *dev = &ctx->client->dev; 194 int val; 195 int ret; 196 197 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 198 ctx, val, 199 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 200 2000, 201 2000 * 150); 202 if (ret) { 203 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 204 return -EIO; 205 } 206 207 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 208 AP_AUX_CTRL_STATUS); 209 if (val < 0 || (val & 0x0F)) { 210 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 211 return -EIO; 212 } 213 214 return 0; 215 } 216 217 static int anx7625_aux_dpcd_read(struct anx7625_data *ctx, 218 u32 address, u8 len, u8 *buf) 219 { 220 struct device *dev = &ctx->client->dev; 221 int ret; 222 u8 addrh, addrm, addrl; 223 u8 cmd; 224 225 if (len > MAX_DPCD_BUFFER_SIZE) { 226 dev_err(dev, "exceed aux buffer len.\n"); 227 return -EINVAL; 228 } 229 230 addrl = address & 0xFF; 231 addrm = (address >> 8) & 0xFF; 232 addrh = (address >> 16) & 0xFF; 233 234 cmd = DPCD_CMD(len, DPCD_READ); 235 cmd = ((len - 1) << 4) | 0x09; 236 237 /* Set command and length */ 238 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 239 AP_AUX_COMMAND, cmd); 240 241 /* Set aux access address */ 242 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 243 AP_AUX_ADDR_7_0, addrl); 244 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 245 AP_AUX_ADDR_15_8, addrm); 246 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 247 AP_AUX_ADDR_19_16, addrh); 248 249 /* Enable aux access */ 250 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 251 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 252 253 if (ret < 0) { 254 dev_err(dev, "cannot access aux related register.\n"); 255 return -EIO; 256 } 257 258 usleep_range(2000, 2100); 259 260 ret = wait_aux_op_finish(ctx); 261 if (ret) { 262 dev_err(dev, "aux IO error: wait aux op finish.\n"); 263 return ret; 264 } 265 266 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 267 AP_AUX_BUFF_START, len, buf); 268 if (ret < 0) { 269 dev_err(dev, "read dpcd register failed\n"); 270 return -EIO; 271 } 272 273 return 0; 274 } 275 276 static int anx7625_video_mute_control(struct anx7625_data *ctx, 277 u8 status) 278 { 279 int ret; 280 281 if (status) { 282 /* Set mute on flag */ 283 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 284 AP_AV_STATUS, AP_MIPI_MUTE); 285 /* Clear mipi RX en */ 286 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 287 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 288 } else { 289 /* Mute off flag */ 290 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 291 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 292 /* Set MIPI RX EN */ 293 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 294 AP_AV_STATUS, AP_MIPI_RX_EN); 295 } 296 297 return ret; 298 } 299 300 /* Reduction of fraction a/b */ 301 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 302 { 303 unsigned long gcd_num; 304 unsigned long tmp_a, tmp_b; 305 u32 i = 1; 306 307 gcd_num = gcd(*a, *b); 308 *a /= gcd_num; 309 *b /= gcd_num; 310 311 tmp_a = *a; 312 tmp_b = *b; 313 314 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 315 i++; 316 *a = tmp_a / i; 317 *b = tmp_b / i; 318 } 319 320 /* 321 * In the end, make a, b larger to have higher ODFC PLL 322 * output frequency accuracy 323 */ 324 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 325 *a <<= 1; 326 *b <<= 1; 327 } 328 329 *a >>= 1; 330 *b >>= 1; 331 } 332 333 static int anx7625_calculate_m_n(u32 pixelclock, 334 unsigned long *m, 335 unsigned long *n, 336 u8 *post_divider) 337 { 338 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 339 /* Pixel clock frequency is too high */ 340 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 341 pixelclock, 342 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 343 return -EINVAL; 344 } 345 346 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 347 /* Pixel clock frequency is too low */ 348 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 349 pixelclock, 350 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 351 return -EINVAL; 352 } 353 354 for (*post_divider = 1; 355 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 356 *post_divider += 1; 357 358 if (*post_divider > POST_DIVIDER_MAX) { 359 for (*post_divider = 1; 360 (pixelclock < 361 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 362 *post_divider += 1; 363 364 if (*post_divider > POST_DIVIDER_MAX) { 365 DRM_ERROR("cannot find property post_divider(%d)\n", 366 *post_divider); 367 return -EDOM; 368 } 369 } 370 371 /* Patch to improve the accuracy */ 372 if (*post_divider == 7) { 373 /* 27,000,000 is not divisible by 7 */ 374 *post_divider = 8; 375 } else if (*post_divider == 11) { 376 /* 27,000,000 is not divisible by 11 */ 377 *post_divider = 12; 378 } else if ((*post_divider == 13) || (*post_divider == 14)) { 379 /* 27,000,000 is not divisible by 13 or 14 */ 380 *post_divider = 15; 381 } 382 383 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 384 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 385 pixelclock * (*post_divider), 386 PLL_OUT_FREQ_ABS_MAX); 387 return -EDOM; 388 } 389 390 *m = pixelclock; 391 *n = XTAL_FRQ / (*post_divider); 392 393 anx7625_reduction_of_a_fraction(m, n); 394 395 return 0; 396 } 397 398 static int anx7625_odfc_config(struct anx7625_data *ctx, 399 u8 post_divider) 400 { 401 int ret; 402 struct device *dev = &ctx->client->dev; 403 404 /* Config input reference clock frequency 27MHz/19.2MHz */ 405 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 406 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 407 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 408 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 409 /* Post divider */ 410 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 411 MIPI_DIGITAL_PLL_8, 0x0f); 412 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 413 post_divider << 4); 414 415 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 416 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 417 ~MIPI_PLL_VCO_TUNE_REG_VAL); 418 419 /* Reset ODFC PLL */ 420 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 421 ~MIPI_PLL_RESET_N); 422 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 423 MIPI_PLL_RESET_N); 424 425 if (ret < 0) 426 DRM_DEV_ERROR(dev, "IO error.\n"); 427 428 return ret; 429 } 430 431 /* 432 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 433 * anx7625 defined K ratio for matching MIPI input video clock and 434 * DP output video clock. Increase K value can match bigger video data 435 * variation. IVO panel has small variation than DP CTS spec, need 436 * decrease the K value. 437 */ 438 static int anx7625_set_k_value(struct anx7625_data *ctx) 439 { 440 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 441 442 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 443 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 444 MIPI_DIGITAL_ADJ_1, 0x3B); 445 446 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 447 MIPI_DIGITAL_ADJ_1, 0x3D); 448 } 449 450 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 451 { 452 struct device *dev = &ctx->client->dev; 453 unsigned long m, n; 454 u16 htotal; 455 int ret; 456 u8 post_divider = 0; 457 458 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 459 &m, &n, &post_divider); 460 461 if (ret) { 462 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 463 return ret; 464 } 465 466 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 467 m, n, post_divider); 468 469 /* Configure pixel clock */ 470 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 471 (ctx->dt.pixelclock.min / 1000) & 0xFF); 472 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 473 (ctx->dt.pixelclock.min / 1000) >> 8); 474 /* Lane count */ 475 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 476 MIPI_LANE_CTRL_0, 0xfc); 477 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 478 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 479 480 /* Htotal */ 481 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 482 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 483 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 484 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 485 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 486 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 487 /* Hactive */ 488 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 489 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 490 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 491 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 492 /* HFP */ 493 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 494 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 495 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 496 HORIZONTAL_FRONT_PORCH_H, 497 ctx->dt.hfront_porch.min >> 8); 498 /* HWS */ 499 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 500 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 501 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 502 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 503 /* HBP */ 504 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 505 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 506 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 507 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 508 /* Vactive */ 509 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 510 ctx->dt.vactive.min); 511 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 512 ctx->dt.vactive.min >> 8); 513 /* VFP */ 514 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 515 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 516 /* VWS */ 517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 518 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 519 /* VBP */ 520 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 521 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 522 /* M value */ 523 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 524 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 525 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 526 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 527 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 528 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 529 /* N value */ 530 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 531 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 532 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 533 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 534 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 535 (n & 0xff)); 536 537 anx7625_set_k_value(ctx); 538 539 ret |= anx7625_odfc_config(ctx, post_divider - 1); 540 541 if (ret < 0) 542 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 543 544 return ret; 545 } 546 547 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 548 { 549 int val; 550 struct device *dev = &ctx->client->dev; 551 552 /* Swap MIPI-DSI data lane 3 P and N */ 553 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 554 if (val < 0) { 555 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 556 return -EIO; 557 } 558 559 val |= (1 << MIPI_SWAP_CH3); 560 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 561 } 562 563 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 564 565 { 566 int val, ret; 567 struct device *dev = &ctx->client->dev; 568 569 /* Swap MIPI-DSI data lane 3 P and N */ 570 ret = anx7625_swap_dsi_lane3(ctx); 571 if (ret < 0) { 572 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 573 return ret; 574 } 575 576 /* DSI clock settings */ 577 val = (0 << MIPI_HS_PWD_CLK) | 578 (0 << MIPI_HS_RT_CLK) | 579 (0 << MIPI_PD_CLK) | 580 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 581 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 582 (0 << MIPI_CLK_DET_DET_BYPASS) | 583 (0 << MIPI_CLK_MISS_CTRL) | 584 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 585 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 586 MIPI_PHY_CONTROL_3, val); 587 588 /* 589 * Decreased HS prepare timing delay from 160ns to 80ns work with 590 * a) Dragon board 810 series (Qualcomm AP) 591 * b) Moving Pixel DSI source (PG3A pattern generator + 592 * P332 D-PHY Probe) default D-PHY timing 593 * 5ns/step 594 */ 595 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 596 MIPI_TIME_HS_PRPR, 0x10); 597 598 /* Enable DSI mode*/ 599 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 600 SELECT_DSI << MIPI_DPI_SELECT); 601 602 ret |= anx7625_dsi_video_timing_config(ctx); 603 if (ret < 0) { 604 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 605 return ret; 606 } 607 608 /* Toggle m, n ready */ 609 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 610 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 611 usleep_range(1000, 1100); 612 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 613 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 614 615 /* Configure integer stable register */ 616 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 617 MIPI_VIDEO_STABLE_CNT, 0x02); 618 /* Power on MIPI RX */ 619 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 620 MIPI_LANE_CTRL_10, 0x00); 621 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 622 MIPI_LANE_CTRL_10, 0x80); 623 624 if (ret < 0) 625 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 626 627 return ret; 628 } 629 630 static int anx7625_dsi_config(struct anx7625_data *ctx) 631 { 632 struct device *dev = &ctx->client->dev; 633 int ret; 634 635 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 636 637 /* DSC disable */ 638 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 639 R_DSC_CTRL_0, ~DSC_EN); 640 641 ret |= anx7625_api_dsi_config(ctx); 642 643 if (ret < 0) { 644 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 645 return ret; 646 } 647 648 /* Set MIPI RX EN */ 649 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 650 AP_AV_STATUS, AP_MIPI_RX_EN); 651 /* Clear mute flag */ 652 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 653 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 654 if (ret < 0) 655 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 656 else 657 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 658 659 return ret; 660 } 661 662 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 663 { 664 struct device *dev = &ctx->client->dev; 665 u16 freq = ctx->dt.pixelclock.min / 1000; 666 int ret; 667 668 /* configure pixel clock */ 669 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 670 PIXEL_CLOCK_L, freq & 0xFF); 671 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 672 PIXEL_CLOCK_H, (freq >> 8)); 673 674 /* set DPI mode */ 675 /* set to DPI PLL module sel */ 676 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 677 MIPI_DIGITAL_PLL_9, 0x20); 678 /* power down MIPI */ 679 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 680 MIPI_LANE_CTRL_10, 0x08); 681 /* enable DPI mode */ 682 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 683 MIPI_DIGITAL_PLL_18, 0x1C); 684 /* set first edge */ 685 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 686 VIDEO_CONTROL_0, 0x06); 687 if (ret < 0) 688 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 689 690 return ret; 691 } 692 693 static int anx7625_dpi_config(struct anx7625_data *ctx) 694 { 695 struct device *dev = &ctx->client->dev; 696 int ret; 697 698 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 699 700 /* DSC disable */ 701 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 702 R_DSC_CTRL_0, ~DSC_EN); 703 if (ret < 0) { 704 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 705 return ret; 706 } 707 708 ret = anx7625_config_bit_matrix(ctx); 709 if (ret < 0) { 710 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 711 return ret; 712 } 713 714 ret = anx7625_api_dpi_config(ctx); 715 if (ret < 0) { 716 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 717 return ret; 718 } 719 720 /* set MIPI RX EN */ 721 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 722 AP_AV_STATUS, AP_MIPI_RX_EN); 723 /* clear mute flag */ 724 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 725 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 726 if (ret < 0) 727 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 728 729 return ret; 730 } 731 732 static int anx7625_read_flash_status(struct anx7625_data *ctx) 733 { 734 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 735 } 736 737 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 738 { 739 int ret, val; 740 struct device *dev = &ctx->client->dev; 741 u8 ident[FLASH_BUF_LEN]; 742 743 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 744 FLASH_ADDR_HIGH, 0x91); 745 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 746 FLASH_ADDR_LOW, 0xA0); 747 if (ret < 0) { 748 dev_err(dev, "IO error : set key flash address.\n"); 749 return ret; 750 } 751 752 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 753 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 754 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 755 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 756 if (ret < 0) { 757 dev_err(dev, "IO error : set key flash len.\n"); 758 return ret; 759 } 760 761 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 762 R_FLASH_RW_CTRL, FLASH_READ); 763 ret |= readx_poll_timeout(anx7625_read_flash_status, 764 ctx, val, 765 ((val & FLASH_DONE) || (val < 0)), 766 2000, 767 2000 * 150); 768 if (ret) { 769 dev_err(dev, "flash read access fail!\n"); 770 return -EIO; 771 } 772 773 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 774 FLASH_BUF_BASE_ADDR, 775 FLASH_BUF_LEN, ident); 776 if (ret < 0) { 777 dev_err(dev, "read flash data fail!\n"); 778 return -EIO; 779 } 780 781 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 782 return -EINVAL; 783 784 return 0; 785 } 786 787 static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 788 { 789 int ret; 790 struct device *dev = &ctx->client->dev; 791 792 /* Select HDCP 1.4 KEY */ 793 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 794 R_BOOT_RETRY, 0x12); 795 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 796 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 797 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 798 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 799 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 800 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 801 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 802 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 803 804 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 805 R_RAM_ADDR_H, 0); 806 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 807 R_RAM_ADDR_L, 0); 808 /* Enable HDCP 1.4 KEY load */ 809 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 810 R_RAM_CTRL, DECRYPT_EN | LOAD_START); 811 dev_dbg(dev, "load HDCP 1.4 key done\n"); 812 return ret; 813 } 814 815 static int anx7625_hdcp_disable(struct anx7625_data *ctx) 816 { 817 int ret; 818 struct device *dev = &ctx->client->dev; 819 820 dev_dbg(dev, "disable HDCP 1.4\n"); 821 822 /* Disable HDCP */ 823 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 824 /* Try auth flag */ 825 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 826 /* Interrupt for DRM */ 827 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 828 if (ret < 0) 829 dev_err(dev, "fail to disable HDCP\n"); 830 831 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 832 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 833 } 834 835 static int anx7625_hdcp_enable(struct anx7625_data *ctx) 836 { 837 u8 bcap; 838 int ret; 839 struct device *dev = &ctx->client->dev; 840 841 ret = anx7625_hdcp_key_probe(ctx); 842 if (ret) { 843 dev_dbg(dev, "no key found, not to do hdcp\n"); 844 return ret; 845 } 846 847 /* Read downstream capability */ 848 anx7625_aux_dpcd_read(ctx, 0x68028, 1, &bcap); 849 if (!(bcap & 0x01)) { 850 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 851 return 0; 852 } 853 854 dev_dbg(dev, "enable HDCP 1.4\n"); 855 856 /* First clear HDCP state */ 857 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 858 TX_HDCP_CTRL0, 859 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 860 usleep_range(1000, 1100); 861 /* Second clear HDCP state */ 862 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 863 TX_HDCP_CTRL0, 864 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 865 866 /* Set time for waiting KSVR */ 867 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 868 SP_TX_WAIT_KSVR_TIME, 0xc8); 869 /* Set time for waiting R0 */ 870 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 871 SP_TX_WAIT_R0_TIME, 0xb0); 872 ret |= anx7625_hdcp_key_load(ctx); 873 if (ret) { 874 pr_warn("prepare HDCP key failed.\n"); 875 return ret; 876 } 877 878 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 879 880 /* Try auth flag */ 881 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 882 /* Interrupt for DRM */ 883 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 884 if (ret < 0) 885 dev_err(dev, "fail to enable HDCP\n"); 886 887 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 888 TX_HDCP_CTRL0, HARD_AUTH_EN); 889 } 890 891 static void anx7625_dp_start(struct anx7625_data *ctx) 892 { 893 int ret; 894 struct device *dev = &ctx->client->dev; 895 896 if (!ctx->display_timing_valid) { 897 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 898 return; 899 } 900 901 /* Disable HDCP */ 902 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 903 904 if (ctx->pdata.is_dpi) 905 ret = anx7625_dpi_config(ctx); 906 else 907 ret = anx7625_dsi_config(ctx); 908 909 if (ret < 0) 910 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 911 912 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 913 914 ctx->dp_en = 1; 915 } 916 917 static void anx7625_dp_stop(struct anx7625_data *ctx) 918 { 919 struct device *dev = &ctx->client->dev; 920 int ret; 921 922 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 923 924 /* 925 * Video disable: 0x72:08 bit 7 = 0; 926 * Audio disable: 0x70:87 bit 0 = 0; 927 */ 928 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 929 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 930 931 ret |= anx7625_video_mute_control(ctx, 1); 932 if (ret < 0) 933 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 934 935 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 936 937 ctx->dp_en = 0; 938 } 939 940 static int sp_tx_rst_aux(struct anx7625_data *ctx) 941 { 942 int ret; 943 944 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 945 AUX_RST); 946 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 947 ~AUX_RST); 948 return ret; 949 } 950 951 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 952 { 953 int ret; 954 955 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 956 AP_AUX_BUFF_START, offset); 957 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 958 AP_AUX_COMMAND, 0x04); 959 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 960 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 961 return (ret | wait_aux_op_finish(ctx)); 962 } 963 964 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 965 { 966 int ret; 967 968 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 969 AP_AUX_COMMAND, len_cmd); 970 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 971 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 972 return (ret | wait_aux_op_finish(ctx)); 973 } 974 975 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 976 { 977 int c = 0; 978 struct device *dev = &ctx->client->dev; 979 980 sp_tx_aux_wr(ctx, 0x7e); 981 sp_tx_aux_rd(ctx, 0x01); 982 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 983 if (c < 0) { 984 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 985 return -EIO; 986 } 987 988 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 989 990 if (c > MAX_EDID_BLOCK) 991 c = 1; 992 993 return c; 994 } 995 996 static int edid_read(struct anx7625_data *ctx, 997 u8 offset, u8 *pblock_buf) 998 { 999 int ret, cnt; 1000 struct device *dev = &ctx->client->dev; 1001 1002 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1003 sp_tx_aux_wr(ctx, offset); 1004 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1005 ret = sp_tx_aux_rd(ctx, 0xf1); 1006 1007 if (ret) { 1008 ret = sp_tx_rst_aux(ctx); 1009 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 1010 } else { 1011 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1012 AP_AUX_BUFF_START, 1013 MAX_DPCD_BUFFER_SIZE, 1014 pblock_buf); 1015 if (ret > 0) 1016 break; 1017 } 1018 } 1019 1020 if (cnt > EDID_TRY_CNT) 1021 return -EIO; 1022 1023 return ret; 1024 } 1025 1026 static int segments_edid_read(struct anx7625_data *ctx, 1027 u8 segment, u8 *buf, u8 offset) 1028 { 1029 u8 cnt; 1030 int ret; 1031 struct device *dev = &ctx->client->dev; 1032 1033 /* Write address only */ 1034 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1035 AP_AUX_ADDR_7_0, 0x30); 1036 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1037 AP_AUX_COMMAND, 0x04); 1038 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1039 AP_AUX_CTRL_STATUS, 1040 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 1041 1042 ret |= wait_aux_op_finish(ctx); 1043 /* Write segment address */ 1044 ret |= sp_tx_aux_wr(ctx, segment); 1045 /* Data read */ 1046 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1047 AP_AUX_ADDR_7_0, 0x50); 1048 if (ret) { 1049 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 1050 return ret; 1051 } 1052 1053 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1054 sp_tx_aux_wr(ctx, offset); 1055 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1056 ret = sp_tx_aux_rd(ctx, 0xf1); 1057 1058 if (ret) { 1059 ret = sp_tx_rst_aux(ctx); 1060 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 1061 } else { 1062 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1063 AP_AUX_BUFF_START, 1064 MAX_DPCD_BUFFER_SIZE, buf); 1065 if (ret > 0) 1066 break; 1067 } 1068 } 1069 1070 if (cnt > EDID_TRY_CNT) 1071 return -EIO; 1072 1073 return ret; 1074 } 1075 1076 static int sp_tx_edid_read(struct anx7625_data *ctx, 1077 u8 *pedid_blocks_buf) 1078 { 1079 u8 offset, edid_pos; 1080 int count, blocks_num; 1081 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 1082 u8 i, j; 1083 int g_edid_break = 0; 1084 int ret; 1085 struct device *dev = &ctx->client->dev; 1086 1087 /* Address initial */ 1088 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1089 AP_AUX_ADDR_7_0, 0x50); 1090 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1091 AP_AUX_ADDR_15_8, 0); 1092 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 1093 AP_AUX_ADDR_19_16, 0xf0); 1094 if (ret < 0) { 1095 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 1096 return -EIO; 1097 } 1098 1099 blocks_num = sp_tx_get_edid_block(ctx); 1100 if (blocks_num < 0) 1101 return blocks_num; 1102 1103 count = 0; 1104 1105 do { 1106 switch (count) { 1107 case 0: 1108 case 1: 1109 for (i = 0; i < 8; i++) { 1110 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 1111 g_edid_break = edid_read(ctx, offset, 1112 pblock_buf); 1113 1114 if (g_edid_break < 0) 1115 break; 1116 1117 memcpy(&pedid_blocks_buf[offset], 1118 pblock_buf, 1119 MAX_DPCD_BUFFER_SIZE); 1120 } 1121 1122 break; 1123 case 2: 1124 offset = 0x00; 1125 1126 for (j = 0; j < 8; j++) { 1127 edid_pos = (j + count * 8) * 1128 MAX_DPCD_BUFFER_SIZE; 1129 1130 if (g_edid_break == 1) 1131 break; 1132 1133 ret = segments_edid_read(ctx, count / 2, 1134 pblock_buf, offset); 1135 if (ret < 0) 1136 return ret; 1137 1138 memcpy(&pedid_blocks_buf[edid_pos], 1139 pblock_buf, 1140 MAX_DPCD_BUFFER_SIZE); 1141 offset = offset + 0x10; 1142 } 1143 1144 break; 1145 case 3: 1146 offset = 0x80; 1147 1148 for (j = 0; j < 8; j++) { 1149 edid_pos = (j + count * 8) * 1150 MAX_DPCD_BUFFER_SIZE; 1151 if (g_edid_break == 1) 1152 break; 1153 1154 ret = segments_edid_read(ctx, count / 2, 1155 pblock_buf, offset); 1156 if (ret < 0) 1157 return ret; 1158 1159 memcpy(&pedid_blocks_buf[edid_pos], 1160 pblock_buf, 1161 MAX_DPCD_BUFFER_SIZE); 1162 offset = offset + 0x10; 1163 } 1164 1165 break; 1166 default: 1167 break; 1168 } 1169 1170 count++; 1171 1172 } while (blocks_num >= count); 1173 1174 /* Check edid data */ 1175 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 1176 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 1177 return -EINVAL; 1178 } 1179 1180 /* Reset aux channel */ 1181 ret = sp_tx_rst_aux(ctx); 1182 if (ret < 0) { 1183 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 1184 return ret; 1185 } 1186 1187 return (blocks_num + 1); 1188 } 1189 1190 static void anx7625_power_on(struct anx7625_data *ctx) 1191 { 1192 struct device *dev = &ctx->client->dev; 1193 int ret, i; 1194 1195 if (!ctx->pdata.low_power_mode) { 1196 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1197 return; 1198 } 1199 1200 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 1201 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 1202 if (ret < 0) { 1203 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 1204 i, ret); 1205 goto reg_err; 1206 } 1207 usleep_range(2000, 2100); 1208 } 1209 1210 usleep_range(11000, 12000); 1211 1212 /* Power on pin enable */ 1213 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 1214 usleep_range(10000, 11000); 1215 /* Power reset pin enable */ 1216 gpiod_set_value(ctx->pdata.gpio_reset, 1); 1217 usleep_range(10000, 11000); 1218 1219 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 1220 return; 1221 reg_err: 1222 for (--i; i >= 0; i--) 1223 regulator_disable(ctx->pdata.supplies[i].consumer); 1224 } 1225 1226 static void anx7625_power_standby(struct anx7625_data *ctx) 1227 { 1228 struct device *dev = &ctx->client->dev; 1229 int ret; 1230 1231 if (!ctx->pdata.low_power_mode) { 1232 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1233 return; 1234 } 1235 1236 gpiod_set_value(ctx->pdata.gpio_reset, 0); 1237 usleep_range(1000, 1100); 1238 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 1239 usleep_range(1000, 1100); 1240 1241 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1242 ctx->pdata.supplies); 1243 if (ret < 0) 1244 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1245 1246 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1247 } 1248 1249 /* Basic configurations of ANX7625 */ 1250 static void anx7625_config(struct anx7625_data *ctx) 1251 { 1252 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1253 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1254 } 1255 1256 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1257 { 1258 struct device *dev = &ctx->client->dev; 1259 int ret; 1260 1261 /* Reset main ocm */ 1262 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1263 /* Disable PD */ 1264 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1265 AP_AV_STATUS, AP_DISABLE_PD); 1266 /* Release main ocm */ 1267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1268 1269 if (ret < 0) 1270 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1271 else 1272 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1273 } 1274 1275 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1276 { 1277 int ret; 1278 struct device *dev = &ctx->client->dev; 1279 1280 /* Check interface workable */ 1281 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1282 FLASH_LOAD_STA); 1283 if (ret < 0) { 1284 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1285 return ret; 1286 } 1287 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1288 return -ENODEV; 1289 1290 anx7625_disable_pd_protocol(ctx); 1291 1292 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1293 anx7625_reg_read(ctx, 1294 ctx->i2c.rx_p0_client, 1295 OCM_FW_VERSION), 1296 anx7625_reg_read(ctx, 1297 ctx->i2c.rx_p0_client, 1298 OCM_FW_REVERSION)); 1299 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1300 ANX7625_DRV_VERSION); 1301 1302 return 0; 1303 } 1304 1305 static void anx7625_power_on_init(struct anx7625_data *ctx) 1306 { 1307 int retry_count, i; 1308 1309 for (retry_count = 0; retry_count < 3; retry_count++) { 1310 anx7625_power_on(ctx); 1311 anx7625_config(ctx); 1312 1313 for (i = 0; i < OCM_LOADING_TIME; i++) { 1314 if (!anx7625_ocm_loading_check(ctx)) 1315 return; 1316 usleep_range(1000, 1100); 1317 } 1318 anx7625_power_standby(ctx); 1319 } 1320 } 1321 1322 static void anx7625_init_gpio(struct anx7625_data *platform) 1323 { 1324 struct device *dev = &platform->client->dev; 1325 1326 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1327 1328 /* Gpio for chip power enable */ 1329 platform->pdata.gpio_p_on = 1330 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1331 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 1332 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 1333 platform->pdata.gpio_p_on = NULL; 1334 } 1335 1336 /* Gpio for chip reset */ 1337 platform->pdata.gpio_reset = 1338 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1339 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 1340 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 1341 platform->pdata.gpio_reset = NULL; 1342 } 1343 1344 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1345 platform->pdata.low_power_mode = 1; 1346 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1347 desc_to_gpio(platform->pdata.gpio_p_on), 1348 desc_to_gpio(platform->pdata.gpio_reset)); 1349 } else { 1350 platform->pdata.low_power_mode = 0; 1351 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1352 } 1353 } 1354 1355 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1356 { 1357 ctx->hpd_status = 0; 1358 ctx->hpd_high_cnt = 0; 1359 ctx->display_timing_valid = 0; 1360 } 1361 1362 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1363 { 1364 int ret; 1365 struct device *dev = &ctx->client->dev; 1366 1367 if (ctx->hpd_high_cnt >= 2) { 1368 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1369 return; 1370 } 1371 1372 ctx->hpd_status = 1; 1373 ctx->hpd_high_cnt++; 1374 1375 /* Not support HDCP */ 1376 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1377 1378 /* Try auth flag */ 1379 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1380 /* Interrupt for DRM */ 1381 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1382 if (ret < 0) { 1383 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1384 return; 1385 } 1386 1387 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1388 if (ret < 0) 1389 return; 1390 1391 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1392 } 1393 1394 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1395 { 1396 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1397 } 1398 1399 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1400 { 1401 int ret, val; 1402 struct device *dev = &ctx->client->dev; 1403 1404 /* Interrupt mode, no need poll HPD status, just return */ 1405 if (ctx->pdata.intp_irq) 1406 return; 1407 1408 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1409 ctx, val, 1410 ((val & HPD_STATUS) || (val < 0)), 1411 5000, 1412 5000 * 100); 1413 if (ret) { 1414 DRM_DEV_ERROR(dev, "no hpd.\n"); 1415 return; 1416 } 1417 1418 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1419 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1420 INTR_ALERT_1, 0xFF); 1421 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1422 INTERFACE_CHANGE_INT, 0); 1423 1424 anx7625_start_dp_work(ctx); 1425 1426 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1427 drm_helper_hpd_irq_event(ctx->bridge.dev); 1428 } 1429 1430 static void anx7625_remove_edid(struct anx7625_data *ctx) 1431 { 1432 ctx->slimport_edid_p.edid_block_num = -1; 1433 } 1434 1435 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1436 { 1437 int i; 1438 1439 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1440 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1441 DP_TX_LANE0_SWING_REG0 + i, 1442 ctx->pdata.lane0_reg_data[i] & 0xFF); 1443 1444 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1445 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1446 DP_TX_LANE1_SWING_REG0 + i, 1447 ctx->pdata.lane1_reg_data[i] & 0xFF); 1448 } 1449 1450 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1451 { 1452 struct device *dev = &ctx->client->dev; 1453 1454 /* HPD changed */ 1455 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1456 (u32)on); 1457 1458 if (on == 0) { 1459 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1460 anx7625_remove_edid(ctx); 1461 anx7625_stop_dp_work(ctx); 1462 } else { 1463 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1464 anx7625_start_dp_work(ctx); 1465 anx7625_dp_adjust_swing(ctx); 1466 } 1467 } 1468 1469 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1470 { 1471 int intr_vector, status; 1472 struct device *dev = &ctx->client->dev; 1473 1474 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1475 INTR_ALERT_1, 0xFF); 1476 if (status < 0) { 1477 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1478 return status; 1479 } 1480 1481 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1482 INTERFACE_CHANGE_INT); 1483 if (intr_vector < 0) { 1484 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1485 return intr_vector; 1486 } 1487 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1488 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1489 INTERFACE_CHANGE_INT, 1490 intr_vector & (~intr_vector)); 1491 if (status < 0) { 1492 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1493 return status; 1494 } 1495 1496 if (!(intr_vector & HPD_STATUS_CHANGE)) 1497 return -ENOENT; 1498 1499 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1500 SYSTEM_STSTUS); 1501 if (status < 0) { 1502 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1503 return status; 1504 } 1505 1506 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1507 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1508 1509 return 0; 1510 } 1511 1512 static void anx7625_work_func(struct work_struct *work) 1513 { 1514 int event; 1515 struct anx7625_data *ctx = container_of(work, 1516 struct anx7625_data, work); 1517 1518 mutex_lock(&ctx->lock); 1519 1520 if (pm_runtime_suspended(&ctx->client->dev)) 1521 goto unlock; 1522 1523 event = anx7625_hpd_change_detect(ctx); 1524 if (event < 0) 1525 goto unlock; 1526 1527 if (ctx->bridge_attached) 1528 drm_helper_hpd_irq_event(ctx->bridge.dev); 1529 1530 unlock: 1531 mutex_unlock(&ctx->lock); 1532 } 1533 1534 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1535 { 1536 struct anx7625_data *ctx = (struct anx7625_data *)data; 1537 1538 queue_work(ctx->workqueue, &ctx->work); 1539 1540 return IRQ_HANDLED; 1541 } 1542 1543 static int anx7625_get_swing_setting(struct device *dev, 1544 struct anx7625_platform_data *pdata) 1545 { 1546 int num_regs; 1547 1548 if (of_get_property(dev->of_node, 1549 "analogix,lane0-swing", &num_regs)) { 1550 if (num_regs > DP_TX_SWING_REG_CNT) 1551 num_regs = DP_TX_SWING_REG_CNT; 1552 1553 pdata->dp_lane0_swing_reg_cnt = num_regs; 1554 of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1555 pdata->lane0_reg_data, num_regs); 1556 } 1557 1558 if (of_get_property(dev->of_node, 1559 "analogix,lane1-swing", &num_regs)) { 1560 if (num_regs > DP_TX_SWING_REG_CNT) 1561 num_regs = DP_TX_SWING_REG_CNT; 1562 1563 pdata->dp_lane1_swing_reg_cnt = num_regs; 1564 of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1565 pdata->lane1_reg_data, num_regs); 1566 } 1567 1568 return 0; 1569 } 1570 1571 static int anx7625_parse_dt(struct device *dev, 1572 struct anx7625_platform_data *pdata) 1573 { 1574 struct device_node *np = dev->of_node, *ep0; 1575 struct drm_panel *panel; 1576 int ret; 1577 int bus_type, mipi_lanes; 1578 1579 anx7625_get_swing_setting(dev, pdata); 1580 1581 pdata->is_dpi = 1; /* default dpi mode */ 1582 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1583 if (!pdata->mipi_host_node) { 1584 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1585 return -ENODEV; 1586 } 1587 1588 bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1589 mipi_lanes = MAX_LANES_SUPPORT; 1590 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1591 if (ep0) { 1592 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1593 bus_type = 0; 1594 1595 mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1596 } 1597 1598 if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1599 pdata->is_dpi = 0; 1600 1601 pdata->mipi_lanes = mipi_lanes; 1602 if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1603 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1604 1605 if (pdata->is_dpi) 1606 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1607 else 1608 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1609 1610 if (of_property_read_bool(np, "analogix,audio-enable")) 1611 pdata->audio_en = 1; 1612 1613 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1614 if (ret < 0) { 1615 if (ret == -ENODEV) 1616 return 0; 1617 return ret; 1618 } 1619 if (!panel) 1620 return -ENODEV; 1621 1622 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1623 if (IS_ERR(pdata->panel_bridge)) 1624 return PTR_ERR(pdata->panel_bridge); 1625 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1626 1627 return 0; 1628 } 1629 1630 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1631 { 1632 return container_of(bridge, struct anx7625_data, bridge); 1633 } 1634 1635 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1636 { 1637 struct device *dev = &ctx->client->dev; 1638 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1639 int edid_num; 1640 u8 *edid; 1641 1642 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1643 if (!edid) { 1644 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1645 return NULL; 1646 } 1647 1648 if (ctx->slimport_edid_p.edid_block_num > 0) { 1649 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1650 FOUR_BLOCK_SIZE); 1651 return (struct edid *)edid; 1652 } 1653 1654 pm_runtime_get_sync(dev); 1655 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1656 pm_runtime_put_sync(dev); 1657 1658 if (edid_num < 1) { 1659 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1660 kfree(edid); 1661 return NULL; 1662 } 1663 1664 p_edid->edid_block_num = edid_num; 1665 1666 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1667 return (struct edid *)edid; 1668 } 1669 1670 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1671 { 1672 struct device *dev = &ctx->client->dev; 1673 1674 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1675 1676 if (ctx->pdata.panel_bridge) 1677 return connector_status_connected; 1678 1679 return ctx->hpd_status ? connector_status_connected : 1680 connector_status_disconnected; 1681 } 1682 1683 static int anx7625_audio_hw_params(struct device *dev, void *data, 1684 struct hdmi_codec_daifmt *fmt, 1685 struct hdmi_codec_params *params) 1686 { 1687 struct anx7625_data *ctx = dev_get_drvdata(dev); 1688 int wl, ch, rate; 1689 int ret = 0; 1690 1691 if (fmt->fmt != HDMI_DSP_A) { 1692 DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1693 return -EINVAL; 1694 } 1695 1696 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1697 params->sample_rate, params->sample_width, 1698 params->cea.channels); 1699 1700 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1701 AUDIO_CHANNEL_STATUS_6, 1702 ~I2S_SLAVE_MODE, 1703 TDM_SLAVE_MODE); 1704 1705 /* Word length */ 1706 switch (params->sample_width) { 1707 case 16: 1708 wl = AUDIO_W_LEN_16_20MAX; 1709 break; 1710 case 18: 1711 wl = AUDIO_W_LEN_18_20MAX; 1712 break; 1713 case 20: 1714 wl = AUDIO_W_LEN_20_20MAX; 1715 break; 1716 case 24: 1717 wl = AUDIO_W_LEN_24_24MAX; 1718 break; 1719 default: 1720 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1721 params->sample_width); 1722 return -EINVAL; 1723 } 1724 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1725 AUDIO_CHANNEL_STATUS_5, 1726 0xf0, wl); 1727 1728 /* Channel num */ 1729 switch (params->cea.channels) { 1730 case 2: 1731 ch = I2S_CH_2; 1732 break; 1733 case 4: 1734 ch = TDM_CH_4; 1735 break; 1736 case 6: 1737 ch = TDM_CH_6; 1738 break; 1739 case 8: 1740 ch = TDM_CH_8; 1741 break; 1742 default: 1743 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1744 params->cea.channels); 1745 return -EINVAL; 1746 } 1747 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1748 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1749 if (ch > I2S_CH_2) 1750 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1751 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1752 else 1753 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1754 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1755 1756 /* FS */ 1757 switch (params->sample_rate) { 1758 case 32000: 1759 rate = AUDIO_FS_32K; 1760 break; 1761 case 44100: 1762 rate = AUDIO_FS_441K; 1763 break; 1764 case 48000: 1765 rate = AUDIO_FS_48K; 1766 break; 1767 case 88200: 1768 rate = AUDIO_FS_882K; 1769 break; 1770 case 96000: 1771 rate = AUDIO_FS_96K; 1772 break; 1773 case 176400: 1774 rate = AUDIO_FS_1764K; 1775 break; 1776 case 192000: 1777 rate = AUDIO_FS_192K; 1778 break; 1779 default: 1780 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1781 params->sample_rate); 1782 return -EINVAL; 1783 } 1784 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1785 AUDIO_CHANNEL_STATUS_4, 1786 0xf0, rate); 1787 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1788 AP_AV_STATUS, AP_AUDIO_CHG); 1789 if (ret < 0) { 1790 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1791 return -EIO; 1792 } 1793 1794 return 0; 1795 } 1796 1797 static void anx7625_audio_shutdown(struct device *dev, void *data) 1798 { 1799 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1800 } 1801 1802 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1803 struct device_node *endpoint) 1804 { 1805 struct of_endpoint of_ep; 1806 int ret; 1807 1808 ret = of_graph_parse_endpoint(endpoint, &of_ep); 1809 if (ret < 0) 1810 return ret; 1811 1812 /* 1813 * HDMI sound should be located at external DPI port 1814 * Didn't have good way to check where is internal(DSI) 1815 * or external(DPI) bridge 1816 */ 1817 return 0; 1818 } 1819 1820 static void 1821 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1822 enum drm_connector_status status) 1823 { 1824 if (ctx->plugged_cb && ctx->codec_dev) { 1825 ctx->plugged_cb(ctx->codec_dev, 1826 status == connector_status_connected); 1827 } 1828 } 1829 1830 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1831 hdmi_codec_plugged_cb fn, 1832 struct device *codec_dev) 1833 { 1834 struct anx7625_data *ctx = data; 1835 1836 ctx->plugged_cb = fn; 1837 ctx->codec_dev = codec_dev; 1838 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1839 1840 return 0; 1841 } 1842 1843 static int anx7625_audio_get_eld(struct device *dev, void *data, 1844 u8 *buf, size_t len) 1845 { 1846 struct anx7625_data *ctx = dev_get_drvdata(dev); 1847 1848 if (!ctx->connector) { 1849 dev_err(dev, "connector not initial\n"); 1850 return -EINVAL; 1851 } 1852 1853 dev_dbg(dev, "audio copy eld\n"); 1854 memcpy(buf, ctx->connector->eld, 1855 min(sizeof(ctx->connector->eld), len)); 1856 1857 return 0; 1858 } 1859 1860 static const struct hdmi_codec_ops anx7625_codec_ops = { 1861 .hw_params = anx7625_audio_hw_params, 1862 .audio_shutdown = anx7625_audio_shutdown, 1863 .get_eld = anx7625_audio_get_eld, 1864 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1865 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1866 }; 1867 1868 static void anx7625_unregister_audio(struct anx7625_data *ctx) 1869 { 1870 struct device *dev = &ctx->client->dev; 1871 1872 if (ctx->audio_pdev) { 1873 platform_device_unregister(ctx->audio_pdev); 1874 ctx->audio_pdev = NULL; 1875 } 1876 1877 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1878 } 1879 1880 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1881 { 1882 struct hdmi_codec_pdata codec_data = { 1883 .ops = &anx7625_codec_ops, 1884 .max_i2s_channels = 8, 1885 .i2s = 1, 1886 .data = ctx, 1887 }; 1888 1889 ctx->audio_pdev = platform_device_register_data(dev, 1890 HDMI_CODEC_DRV_NAME, 1891 PLATFORM_DEVID_AUTO, 1892 &codec_data, 1893 sizeof(codec_data)); 1894 1895 if (IS_ERR(ctx->audio_pdev)) 1896 return PTR_ERR(ctx->audio_pdev); 1897 1898 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1899 1900 return 0; 1901 } 1902 1903 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1904 { 1905 struct mipi_dsi_device *dsi; 1906 struct device *dev = &ctx->client->dev; 1907 struct mipi_dsi_host *host; 1908 const struct mipi_dsi_device_info info = { 1909 .type = "anx7625", 1910 .channel = 0, 1911 .node = NULL, 1912 }; 1913 int ret; 1914 1915 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1916 1917 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1918 if (!host) { 1919 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1920 return -EPROBE_DEFER; 1921 } 1922 1923 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 1924 if (IS_ERR(dsi)) { 1925 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 1926 return -EINVAL; 1927 } 1928 1929 dsi->lanes = ctx->pdata.mipi_lanes; 1930 dsi->format = MIPI_DSI_FMT_RGB888; 1931 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1932 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1933 MIPI_DSI_MODE_VIDEO_HSE; 1934 1935 ret = devm_mipi_dsi_attach(dev, dsi); 1936 if (ret) { 1937 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 1938 return ret; 1939 } 1940 1941 ctx->dsi = dsi; 1942 1943 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 1944 1945 return 0; 1946 } 1947 1948 static void hdcp_check_work_func(struct work_struct *work) 1949 { 1950 u8 status; 1951 struct delayed_work *dwork; 1952 struct anx7625_data *ctx; 1953 struct device *dev; 1954 struct drm_device *drm_dev; 1955 1956 dwork = to_delayed_work(work); 1957 ctx = container_of(dwork, struct anx7625_data, hdcp_work); 1958 dev = &ctx->client->dev; 1959 1960 if (!ctx->connector) { 1961 dev_err(dev, "HDCP connector is null!"); 1962 return; 1963 } 1964 1965 drm_dev = ctx->connector->dev; 1966 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1967 mutex_lock(&ctx->hdcp_wq_lock); 1968 1969 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 1970 dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 1971 if (status & BIT(1)) { 1972 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 1973 drm_hdcp_update_content_protection(ctx->connector, 1974 ctx->hdcp_cp); 1975 dev_dbg(dev, "update CP to ENABLE\n"); 1976 } 1977 1978 mutex_unlock(&ctx->hdcp_wq_lock); 1979 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1980 } 1981 1982 static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 1983 struct drm_connector_state *state) 1984 { 1985 struct device *dev = &ctx->client->dev; 1986 int cp; 1987 1988 dev_dbg(dev, "hdcp state check\n"); 1989 cp = state->content_protection; 1990 1991 if (cp == ctx->hdcp_cp) 1992 return 0; 1993 1994 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 1995 if (ctx->dp_en) { 1996 dev_dbg(dev, "enable HDCP\n"); 1997 anx7625_hdcp_enable(ctx); 1998 1999 queue_delayed_work(ctx->hdcp_workqueue, 2000 &ctx->hdcp_work, 2001 msecs_to_jiffies(2000)); 2002 } 2003 } 2004 2005 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2006 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2007 dev_err(dev, "current CP is not ENABLED\n"); 2008 return -EINVAL; 2009 } 2010 anx7625_hdcp_disable(ctx); 2011 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2012 drm_hdcp_update_content_protection(ctx->connector, 2013 ctx->hdcp_cp); 2014 dev_dbg(dev, "update CP to UNDESIRE\n"); 2015 } 2016 2017 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2018 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2019 return -EINVAL; 2020 } 2021 2022 return 0; 2023 } 2024 2025 static int anx7625_bridge_attach(struct drm_bridge *bridge, 2026 enum drm_bridge_attach_flags flags) 2027 { 2028 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2029 int err; 2030 struct device *dev = &ctx->client->dev; 2031 2032 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 2033 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 2034 return -EINVAL; 2035 2036 if (!bridge->encoder) { 2037 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 2038 return -ENODEV; 2039 } 2040 2041 if (ctx->pdata.panel_bridge) { 2042 err = drm_bridge_attach(bridge->encoder, 2043 ctx->pdata.panel_bridge, 2044 &ctx->bridge, flags); 2045 if (err) 2046 return err; 2047 } 2048 2049 ctx->bridge_attached = 1; 2050 2051 return 0; 2052 } 2053 2054 static enum drm_mode_status 2055 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 2056 const struct drm_display_info *info, 2057 const struct drm_display_mode *mode) 2058 { 2059 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2060 struct device *dev = &ctx->client->dev; 2061 2062 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 2063 2064 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 2065 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 2066 DRM_DEV_DEBUG_DRIVER(dev, 2067 "drm mode invalid, pixelclock too high.\n"); 2068 return MODE_CLOCK_HIGH; 2069 } 2070 2071 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 2072 2073 return MODE_OK; 2074 } 2075 2076 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 2077 const struct drm_display_mode *old_mode, 2078 const struct drm_display_mode *mode) 2079 { 2080 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2081 struct device *dev = &ctx->client->dev; 2082 2083 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 2084 2085 ctx->dt.pixelclock.min = mode->clock; 2086 ctx->dt.hactive.min = mode->hdisplay; 2087 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 2088 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 2089 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 2090 ctx->dt.vactive.min = mode->vdisplay; 2091 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 2092 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 2093 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 2094 2095 ctx->display_timing_valid = 1; 2096 2097 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 2098 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 2099 ctx->dt.hactive.min, 2100 ctx->dt.hsync_len.min, 2101 ctx->dt.hfront_porch.min, 2102 ctx->dt.hback_porch.min); 2103 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 2104 ctx->dt.vactive.min, 2105 ctx->dt.vsync_len.min, 2106 ctx->dt.vfront_porch.min, 2107 ctx->dt.vback_porch.min); 2108 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 2109 mode->hdisplay, 2110 mode->hsync_start); 2111 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 2112 mode->hsync_end, 2113 mode->htotal); 2114 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 2115 mode->vdisplay, 2116 mode->vsync_start); 2117 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 2118 mode->vsync_end, 2119 mode->vtotal); 2120 } 2121 2122 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 2123 const struct drm_display_mode *mode, 2124 struct drm_display_mode *adj) 2125 { 2126 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2127 struct device *dev = &ctx->client->dev; 2128 u32 hsync, hfp, hbp, hblanking; 2129 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 2130 u32 vref, adj_clock; 2131 2132 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 2133 2134 /* No need fixup for external monitor */ 2135 if (!ctx->pdata.panel_bridge) 2136 return true; 2137 2138 hsync = mode->hsync_end - mode->hsync_start; 2139 hfp = mode->hsync_start - mode->hdisplay; 2140 hbp = mode->htotal - mode->hsync_end; 2141 hblanking = mode->htotal - mode->hdisplay; 2142 2143 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 2144 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2145 hsync, hfp, hbp, adj->clock); 2146 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2147 adj->hsync_start, adj->hsync_end, adj->htotal); 2148 2149 adj_hfp = hfp; 2150 adj_hsync = hsync; 2151 adj_hbp = hbp; 2152 adj_hblanking = hblanking; 2153 2154 /* HFP needs to be even */ 2155 if (hfp & 0x1) { 2156 adj_hfp += 1; 2157 adj_hblanking += 1; 2158 } 2159 2160 /* HBP needs to be even */ 2161 if (hbp & 0x1) { 2162 adj_hbp -= 1; 2163 adj_hblanking -= 1; 2164 } 2165 2166 /* HSYNC needs to be even */ 2167 if (hsync & 0x1) { 2168 if (adj_hblanking < hblanking) 2169 adj_hsync += 1; 2170 else 2171 adj_hsync -= 1; 2172 } 2173 2174 /* 2175 * Once illegal timing detected, use default HFP, HSYNC, HBP 2176 * This adjusting made for built-in eDP panel, for the externel 2177 * DP monitor, may need return false. 2178 */ 2179 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 2180 adj_hsync = SYNC_LEN_DEF; 2181 adj_hfp = HFP_HBP_DEF; 2182 adj_hbp = HFP_HBP_DEF; 2183 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 2184 if (hblanking < HBLANKING_MIN) { 2185 delta_adj = HBLANKING_MIN - hblanking; 2186 adj_clock = vref * delta_adj * adj->vtotal; 2187 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 2188 } else { 2189 delta_adj = hblanking - HBLANKING_MIN; 2190 adj_clock = vref * delta_adj * adj->vtotal; 2191 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 2192 } 2193 2194 DRM_WARN("illegal hblanking timing, use default.\n"); 2195 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 2196 } else if (adj_hfp < HP_MIN) { 2197 /* Adjust hfp if hfp less than HP_MIN */ 2198 delta_adj = HP_MIN - adj_hfp; 2199 adj_hfp = HP_MIN; 2200 2201 /* 2202 * Balance total HBlanking pixel, if HBP does not have enough 2203 * space, adjust HSYNC length, otherwise adjust HBP 2204 */ 2205 if ((adj_hbp - delta_adj) < HP_MIN) 2206 /* HBP not enough space */ 2207 adj_hsync -= delta_adj; 2208 else 2209 adj_hbp -= delta_adj; 2210 } else if (adj_hbp < HP_MIN) { 2211 delta_adj = HP_MIN - adj_hbp; 2212 adj_hbp = HP_MIN; 2213 2214 /* 2215 * Balance total HBlanking pixel, if HBP hasn't enough space, 2216 * adjust HSYNC length, otherwize adjust HBP 2217 */ 2218 if ((adj_hfp - delta_adj) < HP_MIN) 2219 /* HFP not enough space */ 2220 adj_hsync -= delta_adj; 2221 else 2222 adj_hfp -= delta_adj; 2223 } 2224 2225 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 2226 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2227 adj_hsync, adj_hfp, adj_hbp, adj->clock); 2228 2229 /* Reconstruct timing */ 2230 adj->hsync_start = adj->hdisplay + adj_hfp; 2231 adj->hsync_end = adj->hsync_start + adj_hsync; 2232 adj->htotal = adj->hsync_end + adj_hbp; 2233 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2234 adj->hsync_start, adj->hsync_end, adj->htotal); 2235 2236 return true; 2237 } 2238 2239 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2240 struct drm_bridge_state *bridge_state, 2241 struct drm_crtc_state *crtc_state, 2242 struct drm_connector_state *conn_state) 2243 { 2244 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2245 struct device *dev = &ctx->client->dev; 2246 2247 dev_dbg(dev, "drm bridge atomic check\n"); 2248 2249 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2250 &crtc_state->adjusted_mode); 2251 2252 return anx7625_connector_atomic_check(ctx, conn_state); 2253 } 2254 2255 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2256 struct drm_bridge_state *state) 2257 { 2258 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2259 struct device *dev = &ctx->client->dev; 2260 struct drm_connector *connector; 2261 2262 dev_dbg(dev, "drm atomic enable\n"); 2263 2264 if (!bridge->encoder) { 2265 dev_err(dev, "Parent encoder object not found"); 2266 return; 2267 } 2268 2269 connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2270 bridge->encoder); 2271 if (!connector) 2272 return; 2273 2274 ctx->connector = connector; 2275 2276 pm_runtime_get_sync(dev); 2277 2278 anx7625_dp_start(ctx); 2279 } 2280 2281 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2282 struct drm_bridge_state *old) 2283 { 2284 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2285 struct device *dev = &ctx->client->dev; 2286 2287 dev_dbg(dev, "drm atomic disable\n"); 2288 2289 ctx->connector = NULL; 2290 anx7625_dp_stop(ctx); 2291 2292 pm_runtime_put_sync(dev); 2293 } 2294 2295 static enum drm_connector_status 2296 anx7625_bridge_detect(struct drm_bridge *bridge) 2297 { 2298 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2299 struct device *dev = &ctx->client->dev; 2300 2301 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 2302 2303 return anx7625_sink_detect(ctx); 2304 } 2305 2306 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 2307 struct drm_connector *connector) 2308 { 2309 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2310 struct device *dev = &ctx->client->dev; 2311 2312 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 2313 2314 return anx7625_get_edid(ctx); 2315 } 2316 2317 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 2318 .attach = anx7625_bridge_attach, 2319 .mode_valid = anx7625_bridge_mode_valid, 2320 .mode_set = anx7625_bridge_mode_set, 2321 .atomic_check = anx7625_bridge_atomic_check, 2322 .atomic_enable = anx7625_bridge_atomic_enable, 2323 .atomic_disable = anx7625_bridge_atomic_disable, 2324 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2325 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2326 .atomic_reset = drm_atomic_helper_bridge_reset, 2327 .detect = anx7625_bridge_detect, 2328 .get_edid = anx7625_bridge_get_edid, 2329 }; 2330 2331 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 2332 struct i2c_client *client) 2333 { 2334 int err = 0; 2335 2336 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 2337 TX_P0_ADDR >> 1); 2338 if (IS_ERR(ctx->i2c.tx_p0_client)) 2339 return PTR_ERR(ctx->i2c.tx_p0_client); 2340 2341 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 2342 TX_P1_ADDR >> 1); 2343 if (IS_ERR(ctx->i2c.tx_p1_client)) { 2344 err = PTR_ERR(ctx->i2c.tx_p1_client); 2345 goto free_tx_p0; 2346 } 2347 2348 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 2349 TX_P2_ADDR >> 1); 2350 if (IS_ERR(ctx->i2c.tx_p2_client)) { 2351 err = PTR_ERR(ctx->i2c.tx_p2_client); 2352 goto free_tx_p1; 2353 } 2354 2355 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 2356 RX_P0_ADDR >> 1); 2357 if (IS_ERR(ctx->i2c.rx_p0_client)) { 2358 err = PTR_ERR(ctx->i2c.rx_p0_client); 2359 goto free_tx_p2; 2360 } 2361 2362 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 2363 RX_P1_ADDR >> 1); 2364 if (IS_ERR(ctx->i2c.rx_p1_client)) { 2365 err = PTR_ERR(ctx->i2c.rx_p1_client); 2366 goto free_rx_p0; 2367 } 2368 2369 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 2370 RX_P2_ADDR >> 1); 2371 if (IS_ERR(ctx->i2c.rx_p2_client)) { 2372 err = PTR_ERR(ctx->i2c.rx_p2_client); 2373 goto free_rx_p1; 2374 } 2375 2376 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 2377 TCPC_INTERFACE_ADDR >> 1); 2378 if (IS_ERR(ctx->i2c.tcpc_client)) { 2379 err = PTR_ERR(ctx->i2c.tcpc_client); 2380 goto free_rx_p2; 2381 } 2382 2383 return 0; 2384 2385 free_rx_p2: 2386 i2c_unregister_device(ctx->i2c.rx_p2_client); 2387 free_rx_p1: 2388 i2c_unregister_device(ctx->i2c.rx_p1_client); 2389 free_rx_p0: 2390 i2c_unregister_device(ctx->i2c.rx_p0_client); 2391 free_tx_p2: 2392 i2c_unregister_device(ctx->i2c.tx_p2_client); 2393 free_tx_p1: 2394 i2c_unregister_device(ctx->i2c.tx_p1_client); 2395 free_tx_p0: 2396 i2c_unregister_device(ctx->i2c.tx_p0_client); 2397 2398 return err; 2399 } 2400 2401 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 2402 { 2403 i2c_unregister_device(ctx->i2c.tx_p0_client); 2404 i2c_unregister_device(ctx->i2c.tx_p1_client); 2405 i2c_unregister_device(ctx->i2c.tx_p2_client); 2406 i2c_unregister_device(ctx->i2c.rx_p0_client); 2407 i2c_unregister_device(ctx->i2c.rx_p1_client); 2408 i2c_unregister_device(ctx->i2c.rx_p2_client); 2409 i2c_unregister_device(ctx->i2c.tcpc_client); 2410 } 2411 2412 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2413 { 2414 struct anx7625_data *ctx = dev_get_drvdata(dev); 2415 2416 mutex_lock(&ctx->lock); 2417 2418 anx7625_stop_dp_work(ctx); 2419 anx7625_power_standby(ctx); 2420 2421 mutex_unlock(&ctx->lock); 2422 2423 return 0; 2424 } 2425 2426 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2427 { 2428 struct anx7625_data *ctx = dev_get_drvdata(dev); 2429 2430 mutex_lock(&ctx->lock); 2431 2432 anx7625_power_on_init(ctx); 2433 anx7625_hpd_polling(ctx); 2434 2435 mutex_unlock(&ctx->lock); 2436 2437 return 0; 2438 } 2439 2440 static int __maybe_unused anx7625_resume(struct device *dev) 2441 { 2442 struct anx7625_data *ctx = dev_get_drvdata(dev); 2443 2444 if (!ctx->pdata.intp_irq) 2445 return 0; 2446 2447 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2448 enable_irq(ctx->pdata.intp_irq); 2449 anx7625_runtime_pm_resume(dev); 2450 } 2451 2452 return 0; 2453 } 2454 2455 static int __maybe_unused anx7625_suspend(struct device *dev) 2456 { 2457 struct anx7625_data *ctx = dev_get_drvdata(dev); 2458 2459 if (!ctx->pdata.intp_irq) 2460 return 0; 2461 2462 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2463 anx7625_runtime_pm_suspend(dev); 2464 disable_irq(ctx->pdata.intp_irq); 2465 } 2466 2467 return 0; 2468 } 2469 2470 static const struct dev_pm_ops anx7625_pm_ops = { 2471 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 2472 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2473 anx7625_runtime_pm_resume, NULL) 2474 }; 2475 2476 static int anx7625_i2c_probe(struct i2c_client *client, 2477 const struct i2c_device_id *id) 2478 { 2479 struct anx7625_data *platform; 2480 struct anx7625_platform_data *pdata; 2481 int ret = 0; 2482 struct device *dev = &client->dev; 2483 2484 if (!i2c_check_functionality(client->adapter, 2485 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2486 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2487 return -ENODEV; 2488 } 2489 2490 platform = kzalloc(sizeof(*platform), GFP_KERNEL); 2491 if (!platform) { 2492 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2493 return -ENOMEM; 2494 } 2495 2496 pdata = &platform->pdata; 2497 2498 ret = anx7625_parse_dt(dev, pdata); 2499 if (ret) { 2500 if (ret != -EPROBE_DEFER) 2501 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2502 goto free_platform; 2503 } 2504 2505 platform->client = client; 2506 i2c_set_clientdata(client, platform); 2507 2508 pdata->supplies[0].supply = "vdd10"; 2509 pdata->supplies[1].supply = "vdd18"; 2510 pdata->supplies[2].supply = "vdd33"; 2511 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2512 pdata->supplies); 2513 if (ret) { 2514 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2515 return ret; 2516 } 2517 anx7625_init_gpio(platform); 2518 2519 mutex_init(&platform->lock); 2520 mutex_init(&platform->hdcp_wq_lock); 2521 2522 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2523 platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2524 if (!platform->hdcp_workqueue) { 2525 dev_err(dev, "fail to create work queue\n"); 2526 ret = -ENOMEM; 2527 goto free_platform; 2528 } 2529 2530 platform->pdata.intp_irq = client->irq; 2531 if (platform->pdata.intp_irq) { 2532 INIT_WORK(&platform->work, anx7625_work_func); 2533 platform->workqueue = alloc_workqueue("anx7625_work", 2534 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2535 if (!platform->workqueue) { 2536 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2537 ret = -ENOMEM; 2538 goto free_hdcp_wq; 2539 } 2540 2541 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2542 NULL, anx7625_intr_hpd_isr, 2543 IRQF_TRIGGER_FALLING | 2544 IRQF_ONESHOT, 2545 "anx7625-intp", platform); 2546 if (ret) { 2547 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2548 goto free_wq; 2549 } 2550 } 2551 2552 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2553 ret = -ENOMEM; 2554 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2555 goto free_wq; 2556 } 2557 2558 pm_runtime_enable(dev); 2559 2560 if (!platform->pdata.low_power_mode) { 2561 anx7625_disable_pd_protocol(platform); 2562 pm_runtime_get_sync(dev); 2563 } 2564 2565 /* Add work function */ 2566 if (platform->pdata.intp_irq) 2567 queue_work(platform->workqueue, &platform->work); 2568 2569 platform->bridge.funcs = &anx7625_bridge_funcs; 2570 platform->bridge.of_node = client->dev.of_node; 2571 platform->bridge.ops = DRM_BRIDGE_OP_EDID; 2572 if (!platform->pdata.panel_bridge) 2573 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2574 DRM_BRIDGE_OP_DETECT; 2575 platform->bridge.type = platform->pdata.panel_bridge ? 2576 DRM_MODE_CONNECTOR_eDP : 2577 DRM_MODE_CONNECTOR_DisplayPort; 2578 2579 drm_bridge_add(&platform->bridge); 2580 2581 if (!platform->pdata.is_dpi) { 2582 ret = anx7625_attach_dsi(platform); 2583 if (ret) { 2584 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 2585 goto unregister_bridge; 2586 } 2587 } 2588 2589 if (platform->pdata.audio_en) 2590 anx7625_register_audio(dev, platform); 2591 2592 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2593 2594 return 0; 2595 2596 unregister_bridge: 2597 drm_bridge_remove(&platform->bridge); 2598 2599 if (!platform->pdata.low_power_mode) 2600 pm_runtime_put_sync_suspend(&client->dev); 2601 2602 anx7625_unregister_i2c_dummy_clients(platform); 2603 2604 free_wq: 2605 if (platform->workqueue) 2606 destroy_workqueue(platform->workqueue); 2607 2608 free_hdcp_wq: 2609 if (platform->hdcp_workqueue) 2610 destroy_workqueue(platform->hdcp_workqueue); 2611 2612 free_platform: 2613 kfree(platform); 2614 2615 return ret; 2616 } 2617 2618 static int anx7625_i2c_remove(struct i2c_client *client) 2619 { 2620 struct anx7625_data *platform = i2c_get_clientdata(client); 2621 2622 drm_bridge_remove(&platform->bridge); 2623 2624 if (platform->pdata.intp_irq) 2625 destroy_workqueue(platform->workqueue); 2626 2627 if (platform->hdcp_workqueue) { 2628 cancel_delayed_work(&platform->hdcp_work); 2629 flush_workqueue(platform->workqueue); 2630 destroy_workqueue(platform->workqueue); 2631 } 2632 2633 if (!platform->pdata.low_power_mode) 2634 pm_runtime_put_sync_suspend(&client->dev); 2635 2636 anx7625_unregister_i2c_dummy_clients(platform); 2637 2638 if (platform->pdata.audio_en) 2639 anx7625_unregister_audio(platform); 2640 2641 kfree(platform); 2642 return 0; 2643 } 2644 2645 static const struct i2c_device_id anx7625_id[] = { 2646 {"anx7625", 0}, 2647 {} 2648 }; 2649 2650 MODULE_DEVICE_TABLE(i2c, anx7625_id); 2651 2652 static const struct of_device_id anx_match_table[] = { 2653 {.compatible = "analogix,anx7625",}, 2654 {}, 2655 }; 2656 MODULE_DEVICE_TABLE(of, anx_match_table); 2657 2658 static struct i2c_driver anx7625_driver = { 2659 .driver = { 2660 .name = "anx7625", 2661 .of_match_table = anx_match_table, 2662 .pm = &anx7625_pm_ops, 2663 }, 2664 .probe = anx7625_i2c_probe, 2665 .remove = anx7625_i2c_remove, 2666 2667 .id_table = anx7625_id, 2668 }; 2669 2670 module_i2c_driver(anx7625_driver); 2671 2672 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 2673 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 2674 MODULE_LICENSE("GPL v2"); 2675 MODULE_VERSION(ANX7625_DRV_VERSION); 2676