1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/slab.h> 16 #include <linux/types.h> 17 #include <linux/workqueue.h> 18 19 #include <linux/of_gpio.h> 20 #include <linux/of_graph.h> 21 #include <linux/of_platform.h> 22 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_dp_helper.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_mipi_dsi.h> 29 #include <drm/drm_of.h> 30 #include <drm/drm_panel.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 34 #include <video/display_timing.h> 35 36 #include "anx7625.h" 37 38 /* 39 * There is a sync issue while access I2C register between AP(CPU) and 40 * internal firmware(OCM), to avoid the race condition, AP should access 41 * the reserved slave address before slave address occurs changes. 42 */ 43 static int i2c_access_workaround(struct anx7625_data *ctx, 44 struct i2c_client *client) 45 { 46 u8 offset; 47 struct device *dev = &client->dev; 48 int ret; 49 50 if (client == ctx->last_client) 51 return 0; 52 53 ctx->last_client = client; 54 55 if (client == ctx->i2c.tcpc_client) 56 offset = RSVD_00_ADDR; 57 else if (client == ctx->i2c.tx_p0_client) 58 offset = RSVD_D1_ADDR; 59 else if (client == ctx->i2c.tx_p1_client) 60 offset = RSVD_60_ADDR; 61 else if (client == ctx->i2c.rx_p0_client) 62 offset = RSVD_39_ADDR; 63 else if (client == ctx->i2c.rx_p1_client) 64 offset = RSVD_7F_ADDR; 65 else 66 offset = RSVD_00_ADDR; 67 68 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 69 if (ret < 0) 70 DRM_DEV_ERROR(dev, 71 "fail to access i2c id=%x\n:%x", 72 client->addr, offset); 73 74 return ret; 75 } 76 77 static int anx7625_reg_read(struct anx7625_data *ctx, 78 struct i2c_client *client, u8 reg_addr) 79 { 80 int ret; 81 struct device *dev = &client->dev; 82 83 i2c_access_workaround(ctx, client); 84 85 ret = i2c_smbus_read_byte_data(client, reg_addr); 86 if (ret < 0) 87 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 88 client->addr, reg_addr); 89 90 return ret; 91 } 92 93 static int anx7625_reg_block_read(struct anx7625_data *ctx, 94 struct i2c_client *client, 95 u8 reg_addr, u8 len, u8 *buf) 96 { 97 int ret; 98 struct device *dev = &client->dev; 99 100 i2c_access_workaround(ctx, client); 101 102 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 103 if (ret < 0) 104 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 105 client->addr, reg_addr); 106 107 return ret; 108 } 109 110 static int anx7625_reg_write(struct anx7625_data *ctx, 111 struct i2c_client *client, 112 u8 reg_addr, u8 reg_val) 113 { 114 int ret; 115 struct device *dev = &client->dev; 116 117 i2c_access_workaround(ctx, client); 118 119 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 120 121 if (ret < 0) 122 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 123 client->addr, reg_addr); 124 125 return ret; 126 } 127 128 static int anx7625_write_or(struct anx7625_data *ctx, 129 struct i2c_client *client, 130 u8 offset, u8 mask) 131 { 132 int val; 133 134 val = anx7625_reg_read(ctx, client, offset); 135 if (val < 0) 136 return val; 137 138 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 139 } 140 141 static int anx7625_write_and(struct anx7625_data *ctx, 142 struct i2c_client *client, 143 u8 offset, u8 mask) 144 { 145 int val; 146 147 val = anx7625_reg_read(ctx, client, offset); 148 if (val < 0) 149 return val; 150 151 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 152 } 153 154 static int anx7625_write_and_or(struct anx7625_data *ctx, 155 struct i2c_client *client, 156 u8 offset, u8 and_mask, u8 or_mask) 157 { 158 int val; 159 160 val = anx7625_reg_read(ctx, client, offset); 161 if (val < 0) 162 return val; 163 164 return anx7625_reg_write(ctx, client, 165 offset, (val & and_mask) | (or_mask)); 166 } 167 168 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 169 { 170 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 171 } 172 173 static int wait_aux_op_finish(struct anx7625_data *ctx) 174 { 175 struct device *dev = &ctx->client->dev; 176 int val; 177 int ret; 178 179 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 180 ctx, val, 181 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 182 2000, 183 2000 * 150); 184 if (ret) { 185 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 186 return -EIO; 187 } 188 189 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 190 AP_AUX_CTRL_STATUS); 191 if (val < 0 || (val & 0x0F)) { 192 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 193 val = -EIO; 194 } 195 196 return val; 197 } 198 199 static int anx7625_video_mute_control(struct anx7625_data *ctx, 200 u8 status) 201 { 202 int ret; 203 204 if (status) { 205 /* Set mute on flag */ 206 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 207 AP_AV_STATUS, AP_MIPI_MUTE); 208 /* Clear mipi RX en */ 209 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 210 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 211 } else { 212 /* Mute off flag */ 213 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 214 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 215 /* Set MIPI RX EN */ 216 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 217 AP_AV_STATUS, AP_MIPI_RX_EN); 218 } 219 220 return ret; 221 } 222 223 static int anx7625_config_audio_input(struct anx7625_data *ctx) 224 { 225 struct device *dev = &ctx->client->dev; 226 int ret; 227 228 /* Channel num */ 229 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 230 AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5); 231 232 /* FS */ 233 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 234 AUDIO_CHANNEL_STATUS_4, 235 0xf0, AUDIO_FS_48K); 236 /* Word length */ 237 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 238 AUDIO_CHANNEL_STATUS_5, 239 0xf0, AUDIO_W_LEN_24_24MAX); 240 /* I2S */ 241 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 242 AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE); 243 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 244 AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE); 245 /* Audio change flag */ 246 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 247 AP_AV_STATUS, AP_AUDIO_CHG); 248 249 if (ret < 0) 250 DRM_DEV_ERROR(dev, "fail to config audio.\n"); 251 252 return ret; 253 } 254 255 /* Reduction of fraction a/b */ 256 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 257 { 258 unsigned long gcd_num; 259 unsigned long tmp_a, tmp_b; 260 u32 i = 1; 261 262 gcd_num = gcd(*a, *b); 263 *a /= gcd_num; 264 *b /= gcd_num; 265 266 tmp_a = *a; 267 tmp_b = *b; 268 269 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 270 i++; 271 *a = tmp_a / i; 272 *b = tmp_b / i; 273 } 274 275 /* 276 * In the end, make a, b larger to have higher ODFC PLL 277 * output frequency accuracy 278 */ 279 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 280 *a <<= 1; 281 *b <<= 1; 282 } 283 284 *a >>= 1; 285 *b >>= 1; 286 } 287 288 static int anx7625_calculate_m_n(u32 pixelclock, 289 unsigned long *m, 290 unsigned long *n, 291 u8 *post_divider) 292 { 293 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 294 /* Pixel clock frequency is too high */ 295 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 296 pixelclock, 297 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 298 return -EINVAL; 299 } 300 301 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 302 /* Pixel clock frequency is too low */ 303 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 304 pixelclock, 305 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 306 return -EINVAL; 307 } 308 309 for (*post_divider = 1; 310 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 311 *post_divider += 1; 312 313 if (*post_divider > POST_DIVIDER_MAX) { 314 for (*post_divider = 1; 315 (pixelclock < 316 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 317 *post_divider += 1; 318 319 if (*post_divider > POST_DIVIDER_MAX) { 320 DRM_ERROR("cannot find property post_divider(%d)\n", 321 *post_divider); 322 return -EDOM; 323 } 324 } 325 326 /* Patch to improve the accuracy */ 327 if (*post_divider == 7) { 328 /* 27,000,000 is not divisible by 7 */ 329 *post_divider = 8; 330 } else if (*post_divider == 11) { 331 /* 27,000,000 is not divisible by 11 */ 332 *post_divider = 12; 333 } else if ((*post_divider == 13) || (*post_divider == 14)) { 334 /* 27,000,000 is not divisible by 13 or 14 */ 335 *post_divider = 15; 336 } 337 338 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 339 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 340 pixelclock * (*post_divider), 341 PLL_OUT_FREQ_ABS_MAX); 342 return -EDOM; 343 } 344 345 *m = pixelclock; 346 *n = XTAL_FRQ / (*post_divider); 347 348 anx7625_reduction_of_a_fraction(m, n); 349 350 return 0; 351 } 352 353 static int anx7625_odfc_config(struct anx7625_data *ctx, 354 u8 post_divider) 355 { 356 int ret; 357 struct device *dev = &ctx->client->dev; 358 359 /* Config input reference clock frequency 27MHz/19.2MHz */ 360 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 361 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 362 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 363 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 364 /* Post divider */ 365 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 366 MIPI_DIGITAL_PLL_8, 0x0f); 367 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 368 post_divider << 4); 369 370 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 371 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 372 ~MIPI_PLL_VCO_TUNE_REG_VAL); 373 374 /* Reset ODFC PLL */ 375 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 376 ~MIPI_PLL_RESET_N); 377 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 378 MIPI_PLL_RESET_N); 379 380 if (ret < 0) 381 DRM_DEV_ERROR(dev, "IO error.\n"); 382 383 return ret; 384 } 385 386 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 387 { 388 struct device *dev = &ctx->client->dev; 389 unsigned long m, n; 390 u16 htotal; 391 int ret; 392 u8 post_divider = 0; 393 394 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 395 &m, &n, &post_divider); 396 397 if (ret) { 398 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 399 return ret; 400 } 401 402 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 403 m, n, post_divider); 404 405 /* Configure pixel clock */ 406 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 407 (ctx->dt.pixelclock.min / 1000) & 0xFF); 408 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 409 (ctx->dt.pixelclock.min / 1000) >> 8); 410 /* Lane count */ 411 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 412 MIPI_LANE_CTRL_0, 0xfc); 413 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 414 MIPI_LANE_CTRL_0, 3); 415 416 /* Htotal */ 417 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 418 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 419 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 420 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 421 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 422 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 423 /* Hactive */ 424 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 425 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 426 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 427 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 428 /* HFP */ 429 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 430 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 431 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 432 HORIZONTAL_FRONT_PORCH_H, 433 ctx->dt.hfront_porch.min >> 8); 434 /* HWS */ 435 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 436 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 437 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 438 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 439 /* HBP */ 440 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 441 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 442 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 443 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 444 /* Vactive */ 445 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 446 ctx->dt.vactive.min); 447 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 448 ctx->dt.vactive.min >> 8); 449 /* VFP */ 450 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 451 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 452 /* VWS */ 453 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 454 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 455 /* VBP */ 456 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 457 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 458 /* M value */ 459 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 460 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 461 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 462 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 463 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 464 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 465 /* N value */ 466 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 467 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 468 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 469 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 470 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 471 (n & 0xff)); 472 /* Diff */ 473 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 474 MIPI_DIGITAL_ADJ_1, 0x3D); 475 476 ret |= anx7625_odfc_config(ctx, post_divider - 1); 477 478 if (ret < 0) 479 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 480 481 return ret; 482 } 483 484 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 485 { 486 int val; 487 struct device *dev = &ctx->client->dev; 488 489 /* Swap MIPI-DSI data lane 3 P and N */ 490 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 491 if (val < 0) { 492 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 493 return -EIO; 494 } 495 496 val |= (1 << MIPI_SWAP_CH3); 497 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 498 } 499 500 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 501 502 { 503 int val, ret; 504 struct device *dev = &ctx->client->dev; 505 506 /* Swap MIPI-DSI data lane 3 P and N */ 507 ret = anx7625_swap_dsi_lane3(ctx); 508 if (ret < 0) { 509 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 510 return ret; 511 } 512 513 /* DSI clock settings */ 514 val = (0 << MIPI_HS_PWD_CLK) | 515 (0 << MIPI_HS_RT_CLK) | 516 (0 << MIPI_PD_CLK) | 517 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 518 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 519 (0 << MIPI_CLK_DET_DET_BYPASS) | 520 (0 << MIPI_CLK_MISS_CTRL) | 521 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 522 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 523 MIPI_PHY_CONTROL_3, val); 524 525 /* 526 * Decreased HS prepare timing delay from 160ns to 80ns work with 527 * a) Dragon board 810 series (Qualcomm AP) 528 * b) Moving Pixel DSI source (PG3A pattern generator + 529 * P332 D-PHY Probe) default D-PHY timing 530 * 5ns/step 531 */ 532 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 533 MIPI_TIME_HS_PRPR, 0x10); 534 535 /* Enable DSI mode*/ 536 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 537 SELECT_DSI << MIPI_DPI_SELECT); 538 539 ret |= anx7625_dsi_video_timing_config(ctx); 540 if (ret < 0) { 541 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 542 return ret; 543 } 544 545 /* Toggle m, n ready */ 546 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 547 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 548 usleep_range(1000, 1100); 549 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 550 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 551 552 /* Configure integer stable register */ 553 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 554 MIPI_VIDEO_STABLE_CNT, 0x02); 555 /* Power on MIPI RX */ 556 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 557 MIPI_LANE_CTRL_10, 0x00); 558 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 559 MIPI_LANE_CTRL_10, 0x80); 560 561 if (ret < 0) 562 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 563 564 return ret; 565 } 566 567 static int anx7625_dsi_config(struct anx7625_data *ctx) 568 { 569 struct device *dev = &ctx->client->dev; 570 int ret; 571 572 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 573 574 /* DSC disable */ 575 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 576 R_DSC_CTRL_0, ~DSC_EN); 577 578 ret |= anx7625_api_dsi_config(ctx); 579 580 if (ret < 0) { 581 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 582 return ret; 583 } 584 585 /* Set MIPI RX EN */ 586 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 587 AP_AV_STATUS, AP_MIPI_RX_EN); 588 /* Clear mute flag */ 589 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 590 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 591 if (ret < 0) 592 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 593 else 594 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 595 596 return ret; 597 } 598 599 static void anx7625_dp_start(struct anx7625_data *ctx) 600 { 601 int ret; 602 struct device *dev = &ctx->client->dev; 603 604 if (!ctx->display_timing_valid) { 605 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 606 return; 607 } 608 609 anx7625_config_audio_input(ctx); 610 611 ret = anx7625_dsi_config(ctx); 612 613 if (ret < 0) 614 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 615 } 616 617 static void anx7625_dp_stop(struct anx7625_data *ctx) 618 { 619 struct device *dev = &ctx->client->dev; 620 int ret; 621 622 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 623 624 /* 625 * Video disable: 0x72:08 bit 7 = 0; 626 * Audio disable: 0x70:87 bit 0 = 0; 627 */ 628 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 629 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 630 631 ret |= anx7625_video_mute_control(ctx, 1); 632 if (ret < 0) 633 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 634 } 635 636 static int sp_tx_rst_aux(struct anx7625_data *ctx) 637 { 638 int ret; 639 640 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 641 AUX_RST); 642 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 643 ~AUX_RST); 644 return ret; 645 } 646 647 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 648 { 649 int ret; 650 651 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 652 AP_AUX_BUFF_START, offset); 653 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 654 AP_AUX_COMMAND, 0x04); 655 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 656 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 657 return (ret | wait_aux_op_finish(ctx)); 658 } 659 660 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 661 { 662 int ret; 663 664 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 665 AP_AUX_COMMAND, len_cmd); 666 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 667 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 668 return (ret | wait_aux_op_finish(ctx)); 669 } 670 671 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 672 { 673 int c = 0; 674 struct device *dev = &ctx->client->dev; 675 676 sp_tx_aux_wr(ctx, 0x7e); 677 sp_tx_aux_rd(ctx, 0x01); 678 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 679 if (c < 0) { 680 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 681 return -EIO; 682 } 683 684 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 685 686 if (c > MAX_EDID_BLOCK) 687 c = 1; 688 689 return c; 690 } 691 692 static int edid_read(struct anx7625_data *ctx, 693 u8 offset, u8 *pblock_buf) 694 { 695 int ret, cnt; 696 struct device *dev = &ctx->client->dev; 697 698 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 699 sp_tx_aux_wr(ctx, offset); 700 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 701 ret = sp_tx_aux_rd(ctx, 0xf1); 702 703 if (ret) { 704 sp_tx_rst_aux(ctx); 705 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 706 } else { 707 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 708 AP_AUX_BUFF_START, 709 MAX_DPCD_BUFFER_SIZE, 710 pblock_buf); 711 if (ret > 0) 712 break; 713 } 714 } 715 716 if (cnt > EDID_TRY_CNT) 717 return -EIO; 718 719 return 0; 720 } 721 722 static int segments_edid_read(struct anx7625_data *ctx, 723 u8 segment, u8 *buf, u8 offset) 724 { 725 u8 cnt; 726 int ret; 727 struct device *dev = &ctx->client->dev; 728 729 /* Write address only */ 730 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 731 AP_AUX_ADDR_7_0, 0x30); 732 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 733 AP_AUX_COMMAND, 0x04); 734 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 735 AP_AUX_CTRL_STATUS, 736 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 737 738 ret |= wait_aux_op_finish(ctx); 739 /* Write segment address */ 740 ret |= sp_tx_aux_wr(ctx, segment); 741 /* Data read */ 742 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 743 AP_AUX_ADDR_7_0, 0x50); 744 if (ret) { 745 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 746 return ret; 747 } 748 749 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 750 sp_tx_aux_wr(ctx, offset); 751 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 752 ret = sp_tx_aux_rd(ctx, 0xf1); 753 754 if (ret) { 755 ret = sp_tx_rst_aux(ctx); 756 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 757 } else { 758 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 759 AP_AUX_BUFF_START, 760 MAX_DPCD_BUFFER_SIZE, buf); 761 if (ret > 0) 762 break; 763 } 764 } 765 766 if (cnt > EDID_TRY_CNT) 767 return -EIO; 768 769 return 0; 770 } 771 772 static int sp_tx_edid_read(struct anx7625_data *ctx, 773 u8 *pedid_blocks_buf) 774 { 775 u8 offset, edid_pos; 776 int count, blocks_num; 777 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 778 u8 i, j; 779 u8 g_edid_break = 0; 780 int ret; 781 struct device *dev = &ctx->client->dev; 782 783 /* Address initial */ 784 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 785 AP_AUX_ADDR_7_0, 0x50); 786 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 787 AP_AUX_ADDR_15_8, 0); 788 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 789 AP_AUX_ADDR_19_16, 0xf0); 790 if (ret < 0) { 791 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 792 return -EIO; 793 } 794 795 blocks_num = sp_tx_get_edid_block(ctx); 796 if (blocks_num < 0) 797 return blocks_num; 798 799 count = 0; 800 801 do { 802 switch (count) { 803 case 0: 804 case 1: 805 for (i = 0; i < 8; i++) { 806 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 807 g_edid_break = edid_read(ctx, offset, 808 pblock_buf); 809 810 if (g_edid_break) 811 break; 812 813 memcpy(&pedid_blocks_buf[offset], 814 pblock_buf, 815 MAX_DPCD_BUFFER_SIZE); 816 } 817 818 break; 819 case 2: 820 offset = 0x00; 821 822 for (j = 0; j < 8; j++) { 823 edid_pos = (j + count * 8) * 824 MAX_DPCD_BUFFER_SIZE; 825 826 if (g_edid_break == 1) 827 break; 828 829 segments_edid_read(ctx, count / 2, 830 pblock_buf, offset); 831 memcpy(&pedid_blocks_buf[edid_pos], 832 pblock_buf, 833 MAX_DPCD_BUFFER_SIZE); 834 offset = offset + 0x10; 835 } 836 837 break; 838 case 3: 839 offset = 0x80; 840 841 for (j = 0; j < 8; j++) { 842 edid_pos = (j + count * 8) * 843 MAX_DPCD_BUFFER_SIZE; 844 if (g_edid_break == 1) 845 break; 846 847 segments_edid_read(ctx, count / 2, 848 pblock_buf, offset); 849 memcpy(&pedid_blocks_buf[edid_pos], 850 pblock_buf, 851 MAX_DPCD_BUFFER_SIZE); 852 offset = offset + 0x10; 853 } 854 855 break; 856 default: 857 break; 858 } 859 860 count++; 861 862 } while (blocks_num >= count); 863 864 /* Check edid data */ 865 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 866 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 867 return -EINVAL; 868 } 869 870 /* Reset aux channel */ 871 sp_tx_rst_aux(ctx); 872 873 return (blocks_num + 1); 874 } 875 876 static void anx7625_power_on(struct anx7625_data *ctx) 877 { 878 struct device *dev = &ctx->client->dev; 879 int ret, i; 880 881 if (!ctx->pdata.low_power_mode) { 882 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 883 return; 884 } 885 886 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 887 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 888 if (ret < 0) { 889 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 890 i, ret); 891 goto reg_err; 892 } 893 usleep_range(2000, 2100); 894 } 895 896 usleep_range(11000, 12000); 897 898 /* Power on pin enable */ 899 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 900 usleep_range(10000, 11000); 901 /* Power reset pin enable */ 902 gpiod_set_value(ctx->pdata.gpio_reset, 1); 903 usleep_range(10000, 11000); 904 905 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 906 return; 907 reg_err: 908 for (--i; i >= 0; i--) 909 regulator_disable(ctx->pdata.supplies[i].consumer); 910 } 911 912 static void anx7625_power_standby(struct anx7625_data *ctx) 913 { 914 struct device *dev = &ctx->client->dev; 915 int ret; 916 917 if (!ctx->pdata.low_power_mode) { 918 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 919 return; 920 } 921 922 gpiod_set_value(ctx->pdata.gpio_reset, 0); 923 usleep_range(1000, 1100); 924 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 925 usleep_range(1000, 1100); 926 927 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 928 ctx->pdata.supplies); 929 if (ret < 0) 930 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 931 932 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 933 } 934 935 /* Basic configurations of ANX7625 */ 936 static void anx7625_config(struct anx7625_data *ctx) 937 { 938 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 939 XTAL_FRQ_SEL, XTAL_FRQ_27M); 940 } 941 942 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 943 { 944 struct device *dev = &ctx->client->dev; 945 int ret; 946 947 /* Reset main ocm */ 948 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 949 /* Disable PD */ 950 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 951 AP_AV_STATUS, AP_DISABLE_PD); 952 /* Release main ocm */ 953 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 954 955 if (ret < 0) 956 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 957 else 958 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 959 } 960 961 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 962 { 963 int ret; 964 struct device *dev = &ctx->client->dev; 965 966 /* Check interface workable */ 967 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 968 FLASH_LOAD_STA); 969 if (ret < 0) { 970 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 971 return ret; 972 } 973 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 974 return -ENODEV; 975 976 anx7625_disable_pd_protocol(ctx); 977 978 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 979 anx7625_reg_read(ctx, 980 ctx->i2c.rx_p0_client, 981 OCM_FW_VERSION), 982 anx7625_reg_read(ctx, 983 ctx->i2c.rx_p0_client, 984 OCM_FW_REVERSION)); 985 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 986 ANX7625_DRV_VERSION); 987 988 return 0; 989 } 990 991 static void anx7625_power_on_init(struct anx7625_data *ctx) 992 { 993 int retry_count, i; 994 995 for (retry_count = 0; retry_count < 3; retry_count++) { 996 anx7625_power_on(ctx); 997 anx7625_config(ctx); 998 999 for (i = 0; i < OCM_LOADING_TIME; i++) { 1000 if (!anx7625_ocm_loading_check(ctx)) 1001 return; 1002 usleep_range(1000, 1100); 1003 } 1004 anx7625_power_standby(ctx); 1005 } 1006 } 1007 1008 static void anx7625_chip_control(struct anx7625_data *ctx, int state) 1009 { 1010 struct device *dev = &ctx->client->dev; 1011 1012 DRM_DEV_DEBUG_DRIVER(dev, "before set, power_state(%d).\n", 1013 atomic_read(&ctx->power_status)); 1014 1015 if (!ctx->pdata.low_power_mode) 1016 return; 1017 1018 if (state) { 1019 atomic_inc(&ctx->power_status); 1020 if (atomic_read(&ctx->power_status) == 1) 1021 anx7625_power_on_init(ctx); 1022 } else { 1023 if (atomic_read(&ctx->power_status)) { 1024 atomic_dec(&ctx->power_status); 1025 1026 if (atomic_read(&ctx->power_status) == 0) 1027 anx7625_power_standby(ctx); 1028 } 1029 } 1030 1031 DRM_DEV_DEBUG_DRIVER(dev, "after set, power_state(%d).\n", 1032 atomic_read(&ctx->power_status)); 1033 } 1034 1035 static void anx7625_init_gpio(struct anx7625_data *platform) 1036 { 1037 struct device *dev = &platform->client->dev; 1038 1039 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1040 1041 /* Gpio for chip power enable */ 1042 platform->pdata.gpio_p_on = 1043 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1044 /* Gpio for chip reset */ 1045 platform->pdata.gpio_reset = 1046 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1047 1048 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1049 platform->pdata.low_power_mode = 1; 1050 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1051 desc_to_gpio(platform->pdata.gpio_p_on), 1052 desc_to_gpio(platform->pdata.gpio_reset)); 1053 } else { 1054 platform->pdata.low_power_mode = 0; 1055 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1056 } 1057 } 1058 1059 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1060 { 1061 ctx->hpd_status = 0; 1062 ctx->hpd_high_cnt = 0; 1063 ctx->display_timing_valid = 0; 1064 1065 if (ctx->pdata.low_power_mode == 0) 1066 anx7625_disable_pd_protocol(ctx); 1067 } 1068 1069 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1070 { 1071 int ret; 1072 struct device *dev = &ctx->client->dev; 1073 1074 if (ctx->hpd_high_cnt >= 2) { 1075 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1076 return; 1077 } 1078 1079 ctx->hpd_high_cnt++; 1080 1081 /* Not support HDCP */ 1082 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1083 1084 /* Try auth flag */ 1085 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1086 /* Interrupt for DRM */ 1087 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1088 if (ret < 0) 1089 return; 1090 1091 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1092 if (ret < 0) 1093 return; 1094 1095 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1096 } 1097 1098 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1099 { 1100 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1101 } 1102 1103 static void anx7625_hpd_polling(struct anx7625_data *ctx) 1104 { 1105 int ret, val; 1106 struct device *dev = &ctx->client->dev; 1107 1108 if (atomic_read(&ctx->power_status) != 1) { 1109 DRM_DEV_DEBUG_DRIVER(dev, "No need to poling HPD status.\n"); 1110 return; 1111 } 1112 1113 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1114 ctx, val, 1115 ((val & HPD_STATUS) || (val < 0)), 1116 5000, 1117 5000 * 100); 1118 if (ret) { 1119 DRM_DEV_ERROR(dev, "HPD polling timeout!\n"); 1120 } else { 1121 DRM_DEV_DEBUG_DRIVER(dev, "HPD raise up.\n"); 1122 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1123 INTR_ALERT_1, 0xFF); 1124 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1125 INTERFACE_CHANGE_INT, 0); 1126 } 1127 1128 anx7625_start_dp_work(ctx); 1129 } 1130 1131 static void anx7625_disconnect_check(struct anx7625_data *ctx) 1132 { 1133 if (atomic_read(&ctx->power_status) == 0) 1134 anx7625_stop_dp_work(ctx); 1135 } 1136 1137 static void anx7625_low_power_mode_check(struct anx7625_data *ctx, 1138 int state) 1139 { 1140 struct device *dev = &ctx->client->dev; 1141 1142 DRM_DEV_DEBUG_DRIVER(dev, "low power mode check, state(%d).\n", state); 1143 1144 if (ctx->pdata.low_power_mode) { 1145 anx7625_chip_control(ctx, state); 1146 if (state) 1147 anx7625_hpd_polling(ctx); 1148 else 1149 anx7625_disconnect_check(ctx); 1150 } 1151 } 1152 1153 static void anx7625_remove_edid(struct anx7625_data *ctx) 1154 { 1155 ctx->slimport_edid_p.edid_block_num = -1; 1156 } 1157 1158 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1159 { 1160 struct device *dev = &ctx->client->dev; 1161 1162 /* HPD changed */ 1163 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1164 (u32)on); 1165 1166 if (on == 0) { 1167 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1168 anx7625_remove_edid(ctx); 1169 anx7625_stop_dp_work(ctx); 1170 } else { 1171 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1172 anx7625_start_dp_work(ctx); 1173 } 1174 1175 ctx->hpd_status = 1; 1176 } 1177 1178 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1179 { 1180 int intr_vector, status; 1181 struct device *dev = &ctx->client->dev; 1182 1183 DRM_DEV_DEBUG_DRIVER(dev, "power_status=%d\n", 1184 (u32)atomic_read(&ctx->power_status)); 1185 1186 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1187 INTR_ALERT_1, 0xFF); 1188 if (status < 0) { 1189 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1190 return status; 1191 } 1192 1193 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1194 INTERFACE_CHANGE_INT); 1195 if (intr_vector < 0) { 1196 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1197 return intr_vector; 1198 } 1199 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1200 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1201 INTERFACE_CHANGE_INT, 1202 intr_vector & (~intr_vector)); 1203 if (status < 0) { 1204 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1205 return status; 1206 } 1207 1208 if (!(intr_vector & HPD_STATUS_CHANGE)) 1209 return -ENOENT; 1210 1211 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1212 SYSTEM_STSTUS); 1213 if (status < 0) { 1214 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1215 return status; 1216 } 1217 1218 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1219 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1220 1221 return 0; 1222 } 1223 1224 static void anx7625_work_func(struct work_struct *work) 1225 { 1226 int event; 1227 struct anx7625_data *ctx = container_of(work, 1228 struct anx7625_data, work); 1229 1230 mutex_lock(&ctx->lock); 1231 event = anx7625_hpd_change_detect(ctx); 1232 mutex_unlock(&ctx->lock); 1233 if (event < 0) 1234 return; 1235 1236 if (ctx->bridge_attached) 1237 drm_helper_hpd_irq_event(ctx->bridge.dev); 1238 } 1239 1240 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1241 { 1242 struct anx7625_data *ctx = (struct anx7625_data *)data; 1243 1244 if (atomic_read(&ctx->power_status) != 1) 1245 return IRQ_NONE; 1246 1247 queue_work(ctx->workqueue, &ctx->work); 1248 1249 return IRQ_HANDLED; 1250 } 1251 1252 static int anx7625_parse_dt(struct device *dev, 1253 struct anx7625_platform_data *pdata) 1254 { 1255 struct device_node *np = dev->of_node; 1256 struct drm_panel *panel; 1257 int ret; 1258 1259 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1260 if (!pdata->mipi_host_node) { 1261 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1262 return -ENODEV; 1263 } 1264 1265 DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n"); 1266 1267 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1268 if (ret < 0) { 1269 if (ret == -ENODEV) 1270 return 0; 1271 return ret; 1272 } 1273 if (!panel) 1274 return -ENODEV; 1275 1276 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1277 if (IS_ERR(pdata->panel_bridge)) 1278 return PTR_ERR(pdata->panel_bridge); 1279 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1280 1281 return 0; 1282 } 1283 1284 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1285 { 1286 return container_of(bridge, struct anx7625_data, bridge); 1287 } 1288 1289 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1290 { 1291 struct device *dev = &ctx->client->dev; 1292 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1293 int edid_num; 1294 u8 *edid; 1295 1296 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1297 if (!edid) { 1298 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1299 return NULL; 1300 } 1301 1302 if (ctx->slimport_edid_p.edid_block_num > 0) { 1303 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1304 FOUR_BLOCK_SIZE); 1305 return (struct edid *)edid; 1306 } 1307 1308 anx7625_low_power_mode_check(ctx, 1); 1309 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1310 anx7625_low_power_mode_check(ctx, 0); 1311 1312 if (edid_num < 1) { 1313 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1314 kfree(edid); 1315 return NULL; 1316 } 1317 1318 p_edid->edid_block_num = edid_num; 1319 1320 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1321 return (struct edid *)edid; 1322 } 1323 1324 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1325 { 1326 struct device *dev = &ctx->client->dev; 1327 1328 DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n"); 1329 1330 return connector_status_connected; 1331 } 1332 1333 static int anx7625_attach_dsi(struct anx7625_data *ctx) 1334 { 1335 struct mipi_dsi_device *dsi; 1336 struct device *dev = &ctx->client->dev; 1337 struct mipi_dsi_host *host; 1338 const struct mipi_dsi_device_info info = { 1339 .type = "anx7625", 1340 .channel = 0, 1341 .node = NULL, 1342 }; 1343 1344 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1345 1346 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1347 if (!host) { 1348 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1349 return -EINVAL; 1350 } 1351 1352 dsi = mipi_dsi_device_register_full(host, &info); 1353 if (IS_ERR(dsi)) { 1354 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 1355 return -EINVAL; 1356 } 1357 1358 dsi->lanes = 4; 1359 dsi->format = MIPI_DSI_FMT_RGB888; 1360 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1361 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1362 MIPI_DSI_MODE_EOT_PACKET | 1363 MIPI_DSI_MODE_VIDEO_HSE; 1364 1365 if (mipi_dsi_attach(dsi) < 0) { 1366 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 1367 mipi_dsi_device_unregister(dsi); 1368 return -EINVAL; 1369 } 1370 1371 ctx->dsi = dsi; 1372 1373 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 1374 1375 return 0; 1376 } 1377 1378 static void anx7625_bridge_detach(struct drm_bridge *bridge) 1379 { 1380 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1381 1382 if (ctx->dsi) { 1383 mipi_dsi_detach(ctx->dsi); 1384 mipi_dsi_device_unregister(ctx->dsi); 1385 } 1386 } 1387 1388 static int anx7625_bridge_attach(struct drm_bridge *bridge, 1389 enum drm_bridge_attach_flags flags) 1390 { 1391 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1392 int err; 1393 struct device *dev = &ctx->client->dev; 1394 1395 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 1396 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 1397 return -EINVAL; 1398 1399 if (!bridge->encoder) { 1400 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 1401 return -ENODEV; 1402 } 1403 1404 err = anx7625_attach_dsi(ctx); 1405 if (err) { 1406 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); 1407 return err; 1408 } 1409 1410 if (ctx->pdata.panel_bridge) { 1411 err = drm_bridge_attach(bridge->encoder, 1412 ctx->pdata.panel_bridge, 1413 &ctx->bridge, flags); 1414 if (err) { 1415 DRM_DEV_ERROR(dev, 1416 "Fail to attach panel bridge: %d\n", err); 1417 return err; 1418 } 1419 } 1420 1421 ctx->bridge_attached = 1; 1422 1423 return 0; 1424 } 1425 1426 static enum drm_mode_status 1427 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 1428 const struct drm_display_info *info, 1429 const struct drm_display_mode *mode) 1430 { 1431 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1432 struct device *dev = &ctx->client->dev; 1433 1434 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 1435 1436 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 1437 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 1438 DRM_DEV_DEBUG_DRIVER(dev, 1439 "drm mode invalid, pixelclock too high.\n"); 1440 return MODE_CLOCK_HIGH; 1441 } 1442 1443 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 1444 1445 return MODE_OK; 1446 } 1447 1448 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 1449 const struct drm_display_mode *old_mode, 1450 const struct drm_display_mode *mode) 1451 { 1452 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1453 struct device *dev = &ctx->client->dev; 1454 1455 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 1456 1457 ctx->dt.pixelclock.min = mode->clock; 1458 ctx->dt.hactive.min = mode->hdisplay; 1459 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 1460 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 1461 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 1462 ctx->dt.vactive.min = mode->vdisplay; 1463 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 1464 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 1465 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 1466 1467 ctx->display_timing_valid = 1; 1468 1469 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 1470 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 1471 ctx->dt.hactive.min, 1472 ctx->dt.hsync_len.min, 1473 ctx->dt.hfront_porch.min, 1474 ctx->dt.hback_porch.min); 1475 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 1476 ctx->dt.vactive.min, 1477 ctx->dt.vsync_len.min, 1478 ctx->dt.vfront_porch.min, 1479 ctx->dt.vback_porch.min); 1480 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 1481 mode->hdisplay, 1482 mode->hsync_start); 1483 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 1484 mode->hsync_end, 1485 mode->htotal); 1486 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 1487 mode->vdisplay, 1488 mode->vsync_start); 1489 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 1490 mode->vsync_end, 1491 mode->vtotal); 1492 } 1493 1494 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 1495 const struct drm_display_mode *mode, 1496 struct drm_display_mode *adj) 1497 { 1498 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1499 struct device *dev = &ctx->client->dev; 1500 u32 hsync, hfp, hbp, hblanking; 1501 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 1502 u32 vref, adj_clock; 1503 1504 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 1505 1506 hsync = mode->hsync_end - mode->hsync_start; 1507 hfp = mode->hsync_start - mode->hdisplay; 1508 hbp = mode->htotal - mode->hsync_end; 1509 hblanking = mode->htotal - mode->hdisplay; 1510 1511 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 1512 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1513 hsync, hfp, hbp, adj->clock); 1514 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1515 adj->hsync_start, adj->hsync_end, adj->htotal); 1516 1517 adj_hfp = hfp; 1518 adj_hsync = hsync; 1519 adj_hbp = hbp; 1520 adj_hblanking = hblanking; 1521 1522 /* HFP needs to be even */ 1523 if (hfp & 0x1) { 1524 adj_hfp += 1; 1525 adj_hblanking += 1; 1526 } 1527 1528 /* HBP needs to be even */ 1529 if (hbp & 0x1) { 1530 adj_hbp -= 1; 1531 adj_hblanking -= 1; 1532 } 1533 1534 /* HSYNC needs to be even */ 1535 if (hsync & 0x1) { 1536 if (adj_hblanking < hblanking) 1537 adj_hsync += 1; 1538 else 1539 adj_hsync -= 1; 1540 } 1541 1542 /* 1543 * Once illegal timing detected, use default HFP, HSYNC, HBP 1544 * This adjusting made for built-in eDP panel, for the externel 1545 * DP monitor, may need return false. 1546 */ 1547 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 1548 adj_hsync = SYNC_LEN_DEF; 1549 adj_hfp = HFP_HBP_DEF; 1550 adj_hbp = HFP_HBP_DEF; 1551 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 1552 if (hblanking < HBLANKING_MIN) { 1553 delta_adj = HBLANKING_MIN - hblanking; 1554 adj_clock = vref * delta_adj * adj->vtotal; 1555 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 1556 } else { 1557 delta_adj = hblanking - HBLANKING_MIN; 1558 adj_clock = vref * delta_adj * adj->vtotal; 1559 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 1560 } 1561 1562 DRM_WARN("illegal hblanking timing, use default.\n"); 1563 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 1564 } else if (adj_hfp < HP_MIN) { 1565 /* Adjust hfp if hfp less than HP_MIN */ 1566 delta_adj = HP_MIN - adj_hfp; 1567 adj_hfp = HP_MIN; 1568 1569 /* 1570 * Balance total HBlanking pixel, if HBP does not have enough 1571 * space, adjust HSYNC length, otherwise adjust HBP 1572 */ 1573 if ((adj_hbp - delta_adj) < HP_MIN) 1574 /* HBP not enough space */ 1575 adj_hsync -= delta_adj; 1576 else 1577 adj_hbp -= delta_adj; 1578 } else if (adj_hbp < HP_MIN) { 1579 delta_adj = HP_MIN - adj_hbp; 1580 adj_hbp = HP_MIN; 1581 1582 /* 1583 * Balance total HBlanking pixel, if HBP hasn't enough space, 1584 * adjust HSYNC length, otherwize adjust HBP 1585 */ 1586 if ((adj_hfp - delta_adj) < HP_MIN) 1587 /* HFP not enough space */ 1588 adj_hsync -= delta_adj; 1589 else 1590 adj_hfp -= delta_adj; 1591 } 1592 1593 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 1594 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1595 adj_hsync, adj_hfp, adj_hbp, adj->clock); 1596 1597 /* Reconstruct timing */ 1598 adj->hsync_start = adj->hdisplay + adj_hfp; 1599 adj->hsync_end = adj->hsync_start + adj_hsync; 1600 adj->htotal = adj->hsync_end + adj_hbp; 1601 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1602 adj->hsync_start, adj->hsync_end, adj->htotal); 1603 1604 return true; 1605 } 1606 1607 static void anx7625_bridge_enable(struct drm_bridge *bridge) 1608 { 1609 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1610 struct device *dev = &ctx->client->dev; 1611 1612 DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 1613 1614 anx7625_low_power_mode_check(ctx, 1); 1615 1616 if (WARN_ON(!atomic_read(&ctx->power_status))) 1617 return; 1618 1619 anx7625_dp_start(ctx); 1620 } 1621 1622 static void anx7625_bridge_disable(struct drm_bridge *bridge) 1623 { 1624 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1625 struct device *dev = &ctx->client->dev; 1626 1627 if (WARN_ON(!atomic_read(&ctx->power_status))) 1628 return; 1629 1630 DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 1631 1632 anx7625_dp_stop(ctx); 1633 1634 anx7625_low_power_mode_check(ctx, 0); 1635 } 1636 1637 static enum drm_connector_status 1638 anx7625_bridge_detect(struct drm_bridge *bridge) 1639 { 1640 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1641 struct device *dev = &ctx->client->dev; 1642 1643 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 1644 1645 return anx7625_sink_detect(ctx); 1646 } 1647 1648 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 1649 struct drm_connector *connector) 1650 { 1651 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1652 struct device *dev = &ctx->client->dev; 1653 1654 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 1655 1656 return anx7625_get_edid(ctx); 1657 } 1658 1659 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 1660 .attach = anx7625_bridge_attach, 1661 .detach = anx7625_bridge_detach, 1662 .disable = anx7625_bridge_disable, 1663 .mode_valid = anx7625_bridge_mode_valid, 1664 .mode_set = anx7625_bridge_mode_set, 1665 .mode_fixup = anx7625_bridge_mode_fixup, 1666 .enable = anx7625_bridge_enable, 1667 .detect = anx7625_bridge_detect, 1668 .get_edid = anx7625_bridge_get_edid, 1669 }; 1670 1671 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 1672 struct i2c_client *client) 1673 { 1674 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 1675 TX_P0_ADDR >> 1); 1676 if (!ctx->i2c.tx_p0_client) 1677 return -ENOMEM; 1678 1679 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 1680 TX_P1_ADDR >> 1); 1681 if (!ctx->i2c.tx_p1_client) 1682 goto free_tx_p0; 1683 1684 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 1685 TX_P2_ADDR >> 1); 1686 if (!ctx->i2c.tx_p2_client) 1687 goto free_tx_p1; 1688 1689 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 1690 RX_P0_ADDR >> 1); 1691 if (!ctx->i2c.rx_p0_client) 1692 goto free_tx_p2; 1693 1694 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 1695 RX_P1_ADDR >> 1); 1696 if (!ctx->i2c.rx_p1_client) 1697 goto free_rx_p0; 1698 1699 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 1700 RX_P2_ADDR >> 1); 1701 if (!ctx->i2c.rx_p2_client) 1702 goto free_rx_p1; 1703 1704 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 1705 TCPC_INTERFACE_ADDR >> 1); 1706 if (!ctx->i2c.tcpc_client) 1707 goto free_rx_p2; 1708 1709 return 0; 1710 1711 free_rx_p2: 1712 i2c_unregister_device(ctx->i2c.rx_p2_client); 1713 free_rx_p1: 1714 i2c_unregister_device(ctx->i2c.rx_p1_client); 1715 free_rx_p0: 1716 i2c_unregister_device(ctx->i2c.rx_p0_client); 1717 free_tx_p2: 1718 i2c_unregister_device(ctx->i2c.tx_p2_client); 1719 free_tx_p1: 1720 i2c_unregister_device(ctx->i2c.tx_p1_client); 1721 free_tx_p0: 1722 i2c_unregister_device(ctx->i2c.tx_p0_client); 1723 1724 return -ENOMEM; 1725 } 1726 1727 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 1728 { 1729 i2c_unregister_device(ctx->i2c.tx_p0_client); 1730 i2c_unregister_device(ctx->i2c.tx_p1_client); 1731 i2c_unregister_device(ctx->i2c.tx_p2_client); 1732 i2c_unregister_device(ctx->i2c.rx_p0_client); 1733 i2c_unregister_device(ctx->i2c.rx_p1_client); 1734 i2c_unregister_device(ctx->i2c.rx_p2_client); 1735 i2c_unregister_device(ctx->i2c.tcpc_client); 1736 } 1737 1738 static int anx7625_i2c_probe(struct i2c_client *client, 1739 const struct i2c_device_id *id) 1740 { 1741 struct anx7625_data *platform; 1742 struct anx7625_platform_data *pdata; 1743 int ret = 0; 1744 struct device *dev = &client->dev; 1745 1746 if (!i2c_check_functionality(client->adapter, 1747 I2C_FUNC_SMBUS_I2C_BLOCK)) { 1748 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 1749 return -ENODEV; 1750 } 1751 1752 platform = kzalloc(sizeof(*platform), GFP_KERNEL); 1753 if (!platform) { 1754 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 1755 return -ENOMEM; 1756 } 1757 1758 pdata = &platform->pdata; 1759 1760 ret = anx7625_parse_dt(dev, pdata); 1761 if (ret) { 1762 if (ret != -EPROBE_DEFER) 1763 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 1764 goto free_platform; 1765 } 1766 1767 platform->client = client; 1768 i2c_set_clientdata(client, platform); 1769 1770 pdata->supplies[0].supply = "vdd10"; 1771 pdata->supplies[1].supply = "vdd18"; 1772 pdata->supplies[2].supply = "vdd33"; 1773 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 1774 pdata->supplies); 1775 if (ret) { 1776 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 1777 return ret; 1778 } 1779 anx7625_init_gpio(platform); 1780 1781 atomic_set(&platform->power_status, 0); 1782 1783 mutex_init(&platform->lock); 1784 1785 platform->pdata.intp_irq = client->irq; 1786 if (platform->pdata.intp_irq) { 1787 INIT_WORK(&platform->work, anx7625_work_func); 1788 platform->workqueue = create_workqueue("anx7625_work"); 1789 if (!platform->workqueue) { 1790 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 1791 ret = -ENOMEM; 1792 goto free_platform; 1793 } 1794 1795 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 1796 NULL, anx7625_intr_hpd_isr, 1797 IRQF_TRIGGER_FALLING | 1798 IRQF_ONESHOT, 1799 "anx7625-intp", platform); 1800 if (ret) { 1801 DRM_DEV_ERROR(dev, "fail to request irq\n"); 1802 goto free_wq; 1803 } 1804 } 1805 1806 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 1807 ret = -ENOMEM; 1808 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 1809 goto free_wq; 1810 } 1811 1812 if (platform->pdata.low_power_mode == 0) { 1813 anx7625_disable_pd_protocol(platform); 1814 atomic_set(&platform->power_status, 1); 1815 } 1816 1817 /* Add work function */ 1818 if (platform->pdata.intp_irq) 1819 queue_work(platform->workqueue, &platform->work); 1820 1821 platform->bridge.funcs = &anx7625_bridge_funcs; 1822 platform->bridge.of_node = client->dev.of_node; 1823 platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 1824 platform->bridge.type = DRM_MODE_CONNECTOR_eDP; 1825 drm_bridge_add(&platform->bridge); 1826 1827 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 1828 1829 return 0; 1830 1831 free_wq: 1832 if (platform->workqueue) 1833 destroy_workqueue(platform->workqueue); 1834 1835 free_platform: 1836 kfree(platform); 1837 1838 return ret; 1839 } 1840 1841 static int anx7625_i2c_remove(struct i2c_client *client) 1842 { 1843 struct anx7625_data *platform = i2c_get_clientdata(client); 1844 1845 drm_bridge_remove(&platform->bridge); 1846 1847 if (platform->pdata.intp_irq) 1848 destroy_workqueue(platform->workqueue); 1849 1850 anx7625_unregister_i2c_dummy_clients(platform); 1851 1852 kfree(platform); 1853 return 0; 1854 } 1855 1856 static const struct i2c_device_id anx7625_id[] = { 1857 {"anx7625", 0}, 1858 {} 1859 }; 1860 1861 MODULE_DEVICE_TABLE(i2c, anx7625_id); 1862 1863 static const struct of_device_id anx_match_table[] = { 1864 {.compatible = "analogix,anx7625",}, 1865 {}, 1866 }; 1867 1868 static struct i2c_driver anx7625_driver = { 1869 .driver = { 1870 .name = "anx7625", 1871 .of_match_table = anx_match_table, 1872 }, 1873 .probe = anx7625_i2c_probe, 1874 .remove = anx7625_i2c_remove, 1875 1876 .id_table = anx7625_id, 1877 }; 1878 1879 module_i2c_driver(anx7625_driver); 1880 1881 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 1882 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 1883 MODULE_LICENSE("GPL v2"); 1884 MODULE_VERSION(ANX7625_DRV_VERSION); 1885