1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/gcd.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/of_graph.h> 21 #include <linux/of_platform.h> 22 23 #include <drm/display/drm_dp_aux_bus.h> 24 #include <drm/display/drm_dp_helper.h> 25 #include <drm/display/drm_hdcp_helper.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_bridge.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_mipi_dsi.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_panel.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 35 #include <media/v4l2-fwnode.h> 36 #include <sound/hdmi-codec.h> 37 #include <video/display_timing.h> 38 39 #include "anx7625.h" 40 41 /* 42 * There is a sync issue while access I2C register between AP(CPU) and 43 * internal firmware(OCM), to avoid the race condition, AP should access 44 * the reserved slave address before slave address occurs changes. 45 */ 46 static int i2c_access_workaround(struct anx7625_data *ctx, 47 struct i2c_client *client) 48 { 49 u8 offset; 50 struct device *dev = &client->dev; 51 int ret; 52 53 if (client == ctx->last_client) 54 return 0; 55 56 ctx->last_client = client; 57 58 if (client == ctx->i2c.tcpc_client) 59 offset = RSVD_00_ADDR; 60 else if (client == ctx->i2c.tx_p0_client) 61 offset = RSVD_D1_ADDR; 62 else if (client == ctx->i2c.tx_p1_client) 63 offset = RSVD_60_ADDR; 64 else if (client == ctx->i2c.rx_p0_client) 65 offset = RSVD_39_ADDR; 66 else if (client == ctx->i2c.rx_p1_client) 67 offset = RSVD_7F_ADDR; 68 else 69 offset = RSVD_00_ADDR; 70 71 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 72 if (ret < 0) 73 DRM_DEV_ERROR(dev, 74 "fail to access i2c id=%x\n:%x", 75 client->addr, offset); 76 77 return ret; 78 } 79 80 static int anx7625_reg_read(struct anx7625_data *ctx, 81 struct i2c_client *client, u8 reg_addr) 82 { 83 int ret; 84 struct device *dev = &client->dev; 85 86 i2c_access_workaround(ctx, client); 87 88 ret = i2c_smbus_read_byte_data(client, reg_addr); 89 if (ret < 0) 90 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 91 client->addr, reg_addr); 92 93 return ret; 94 } 95 96 static int anx7625_reg_block_read(struct anx7625_data *ctx, 97 struct i2c_client *client, 98 u8 reg_addr, u8 len, u8 *buf) 99 { 100 int ret; 101 struct device *dev = &client->dev; 102 103 i2c_access_workaround(ctx, client); 104 105 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 106 if (ret < 0) 107 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 108 client->addr, reg_addr); 109 110 return ret; 111 } 112 113 static int anx7625_reg_write(struct anx7625_data *ctx, 114 struct i2c_client *client, 115 u8 reg_addr, u8 reg_val) 116 { 117 int ret; 118 struct device *dev = &client->dev; 119 120 i2c_access_workaround(ctx, client); 121 122 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 123 124 if (ret < 0) 125 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 126 client->addr, reg_addr); 127 128 return ret; 129 } 130 131 static int anx7625_reg_block_write(struct anx7625_data *ctx, 132 struct i2c_client *client, 133 u8 reg_addr, u8 len, u8 *buf) 134 { 135 int ret; 136 struct device *dev = &client->dev; 137 138 i2c_access_workaround(ctx, client); 139 140 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 141 if (ret < 0) 142 dev_err(dev, "write i2c block failed id=%x\n:%x", 143 client->addr, reg_addr); 144 145 return ret; 146 } 147 148 static int anx7625_write_or(struct anx7625_data *ctx, 149 struct i2c_client *client, 150 u8 offset, u8 mask) 151 { 152 int val; 153 154 val = anx7625_reg_read(ctx, client, offset); 155 if (val < 0) 156 return val; 157 158 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 159 } 160 161 static int anx7625_write_and(struct anx7625_data *ctx, 162 struct i2c_client *client, 163 u8 offset, u8 mask) 164 { 165 int val; 166 167 val = anx7625_reg_read(ctx, client, offset); 168 if (val < 0) 169 return val; 170 171 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 172 } 173 174 static int anx7625_write_and_or(struct anx7625_data *ctx, 175 struct i2c_client *client, 176 u8 offset, u8 and_mask, u8 or_mask) 177 { 178 int val; 179 180 val = anx7625_reg_read(ctx, client, offset); 181 if (val < 0) 182 return val; 183 184 return anx7625_reg_write(ctx, client, 185 offset, (val & and_mask) | (or_mask)); 186 } 187 188 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 189 { 190 int i, ret; 191 192 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 193 AUDIO_CONTROL_REGISTER, 0x80); 194 for (i = 0; i < 13; i++) 195 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 196 VIDEO_BIT_MATRIX_12 + i, 197 0x18 + i); 198 199 return ret; 200 } 201 202 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 203 { 204 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 205 } 206 207 static int wait_aux_op_finish(struct anx7625_data *ctx) 208 { 209 struct device *dev = ctx->dev; 210 int val; 211 int ret; 212 213 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 214 ctx, val, 215 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 216 2000, 217 2000 * 150); 218 if (ret) { 219 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 220 return -EIO; 221 } 222 223 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 224 AP_AUX_CTRL_STATUS); 225 if (val < 0 || (val & 0x0F)) { 226 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 227 return -EIO; 228 } 229 230 return 0; 231 } 232 233 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 234 u8 len, u8 *buf) 235 { 236 struct device *dev = ctx->dev; 237 int ret; 238 u8 addrh, addrm, addrl; 239 u8 cmd; 240 bool is_write = !(op & DP_AUX_I2C_READ); 241 242 if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 243 dev_err(dev, "exceed aux buffer len.\n"); 244 return -EINVAL; 245 } 246 247 if (!len) 248 return len; 249 250 addrl = address & 0xFF; 251 addrm = (address >> 8) & 0xFF; 252 addrh = (address >> 16) & 0xFF; 253 254 if (!is_write) 255 op &= ~DP_AUX_I2C_MOT; 256 cmd = DPCD_CMD(len, op); 257 258 /* Set command and length */ 259 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 260 AP_AUX_COMMAND, cmd); 261 262 /* Set aux access address */ 263 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 264 AP_AUX_ADDR_7_0, addrl); 265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 266 AP_AUX_ADDR_15_8, addrm); 267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 268 AP_AUX_ADDR_19_16, addrh); 269 270 if (is_write) 271 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 272 AP_AUX_BUFF_START, len, buf); 273 /* Enable aux access */ 274 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 275 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 276 277 if (ret < 0) { 278 dev_err(dev, "cannot access aux related register.\n"); 279 return -EIO; 280 } 281 282 ret = wait_aux_op_finish(ctx); 283 if (ret < 0) { 284 dev_err(dev, "aux IO error: wait aux op finish.\n"); 285 return ret; 286 } 287 288 /* Write done */ 289 if (is_write) 290 return len; 291 292 /* Read done, read out dpcd data */ 293 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 294 AP_AUX_BUFF_START, len, buf); 295 if (ret < 0) { 296 dev_err(dev, "read dpcd register failed\n"); 297 return -EIO; 298 } 299 300 return len; 301 } 302 303 static int anx7625_video_mute_control(struct anx7625_data *ctx, 304 u8 status) 305 { 306 int ret; 307 308 if (status) { 309 /* Set mute on flag */ 310 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 311 AP_AV_STATUS, AP_MIPI_MUTE); 312 /* Clear mipi RX en */ 313 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 314 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 315 } else { 316 /* Mute off flag */ 317 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 318 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 319 /* Set MIPI RX EN */ 320 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 321 AP_AV_STATUS, AP_MIPI_RX_EN); 322 } 323 324 return ret; 325 } 326 327 /* Reduction of fraction a/b */ 328 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 329 { 330 unsigned long gcd_num; 331 unsigned long tmp_a, tmp_b; 332 u32 i = 1; 333 334 gcd_num = gcd(*a, *b); 335 *a /= gcd_num; 336 *b /= gcd_num; 337 338 tmp_a = *a; 339 tmp_b = *b; 340 341 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 342 i++; 343 *a = tmp_a / i; 344 *b = tmp_b / i; 345 } 346 347 /* 348 * In the end, make a, b larger to have higher ODFC PLL 349 * output frequency accuracy 350 */ 351 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 352 *a <<= 1; 353 *b <<= 1; 354 } 355 356 *a >>= 1; 357 *b >>= 1; 358 } 359 360 static int anx7625_calculate_m_n(u32 pixelclock, 361 unsigned long *m, 362 unsigned long *n, 363 u8 *post_divider) 364 { 365 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 366 /* Pixel clock frequency is too high */ 367 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 368 pixelclock, 369 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 370 return -EINVAL; 371 } 372 373 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 374 /* Pixel clock frequency is too low */ 375 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 376 pixelclock, 377 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 378 return -EINVAL; 379 } 380 381 for (*post_divider = 1; 382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 383 *post_divider += 1; 384 385 if (*post_divider > POST_DIVIDER_MAX) { 386 for (*post_divider = 1; 387 (pixelclock < 388 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 389 *post_divider += 1; 390 391 if (*post_divider > POST_DIVIDER_MAX) { 392 DRM_ERROR("cannot find property post_divider(%d)\n", 393 *post_divider); 394 return -EDOM; 395 } 396 } 397 398 /* Patch to improve the accuracy */ 399 if (*post_divider == 7) { 400 /* 27,000,000 is not divisible by 7 */ 401 *post_divider = 8; 402 } else if (*post_divider == 11) { 403 /* 27,000,000 is not divisible by 11 */ 404 *post_divider = 12; 405 } else if ((*post_divider == 13) || (*post_divider == 14)) { 406 /* 27,000,000 is not divisible by 13 or 14 */ 407 *post_divider = 15; 408 } 409 410 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 411 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 412 pixelclock * (*post_divider), 413 PLL_OUT_FREQ_ABS_MAX); 414 return -EDOM; 415 } 416 417 *m = pixelclock; 418 *n = XTAL_FRQ / (*post_divider); 419 420 anx7625_reduction_of_a_fraction(m, n); 421 422 return 0; 423 } 424 425 static int anx7625_odfc_config(struct anx7625_data *ctx, 426 u8 post_divider) 427 { 428 int ret; 429 struct device *dev = ctx->dev; 430 431 /* Config input reference clock frequency 27MHz/19.2MHz */ 432 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 433 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 434 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 435 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 436 /* Post divider */ 437 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 438 MIPI_DIGITAL_PLL_8, 0x0f); 439 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 440 post_divider << 4); 441 442 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 443 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 444 ~MIPI_PLL_VCO_TUNE_REG_VAL); 445 446 /* Reset ODFC PLL */ 447 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 448 ~MIPI_PLL_RESET_N); 449 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 450 MIPI_PLL_RESET_N); 451 452 if (ret < 0) 453 DRM_DEV_ERROR(dev, "IO error.\n"); 454 455 return ret; 456 } 457 458 /* 459 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 460 * anx7625 defined K ratio for matching MIPI input video clock and 461 * DP output video clock. Increase K value can match bigger video data 462 * variation. IVO panel has small variation than DP CTS spec, need 463 * decrease the K value. 464 */ 465 static int anx7625_set_k_value(struct anx7625_data *ctx) 466 { 467 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 468 469 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 470 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 471 MIPI_DIGITAL_ADJ_1, 0x3B); 472 473 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 474 MIPI_DIGITAL_ADJ_1, 0x3D); 475 } 476 477 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 478 { 479 struct device *dev = ctx->dev; 480 unsigned long m, n; 481 u16 htotal; 482 int ret; 483 u8 post_divider = 0; 484 485 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 486 &m, &n, &post_divider); 487 488 if (ret) { 489 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 490 return ret; 491 } 492 493 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 494 m, n, post_divider); 495 496 /* Configure pixel clock */ 497 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 498 (ctx->dt.pixelclock.min / 1000) & 0xFF); 499 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 500 (ctx->dt.pixelclock.min / 1000) >> 8); 501 /* Lane count */ 502 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 503 MIPI_LANE_CTRL_0, 0xfc); 504 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 505 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 506 507 /* Htotal */ 508 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 509 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 510 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 511 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 513 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 514 /* Hactive */ 515 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 516 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 518 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 519 /* HFP */ 520 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 521 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 523 HORIZONTAL_FRONT_PORCH_H, 524 ctx->dt.hfront_porch.min >> 8); 525 /* HWS */ 526 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 527 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 529 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 530 /* HBP */ 531 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 532 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 534 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 535 /* Vactive */ 536 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 537 ctx->dt.vactive.min); 538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 539 ctx->dt.vactive.min >> 8); 540 /* VFP */ 541 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 542 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 543 /* VWS */ 544 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 545 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 546 /* VBP */ 547 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 548 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 549 /* M value */ 550 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 551 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 553 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 555 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 556 /* N value */ 557 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 558 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 560 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 562 (n & 0xff)); 563 564 anx7625_set_k_value(ctx); 565 566 ret |= anx7625_odfc_config(ctx, post_divider - 1); 567 568 if (ret < 0) 569 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 570 571 return ret; 572 } 573 574 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 575 { 576 int val; 577 struct device *dev = ctx->dev; 578 579 /* Swap MIPI-DSI data lane 3 P and N */ 580 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 581 if (val < 0) { 582 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 583 return -EIO; 584 } 585 586 val |= (1 << MIPI_SWAP_CH3); 587 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 588 } 589 590 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 591 592 { 593 int val, ret; 594 struct device *dev = ctx->dev; 595 596 /* Swap MIPI-DSI data lane 3 P and N */ 597 ret = anx7625_swap_dsi_lane3(ctx); 598 if (ret < 0) { 599 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 600 return ret; 601 } 602 603 /* DSI clock settings */ 604 val = (0 << MIPI_HS_PWD_CLK) | 605 (0 << MIPI_HS_RT_CLK) | 606 (0 << MIPI_PD_CLK) | 607 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 608 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 609 (0 << MIPI_CLK_DET_DET_BYPASS) | 610 (0 << MIPI_CLK_MISS_CTRL) | 611 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 612 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 613 MIPI_PHY_CONTROL_3, val); 614 615 /* 616 * Decreased HS prepare timing delay from 160ns to 80ns work with 617 * a) Dragon board 810 series (Qualcomm AP) 618 * b) Moving Pixel DSI source (PG3A pattern generator + 619 * P332 D-PHY Probe) default D-PHY timing 620 * 5ns/step 621 */ 622 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 623 MIPI_TIME_HS_PRPR, 0x10); 624 625 /* Enable DSI mode*/ 626 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 627 SELECT_DSI << MIPI_DPI_SELECT); 628 629 ret |= anx7625_dsi_video_timing_config(ctx); 630 if (ret < 0) { 631 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 632 return ret; 633 } 634 635 /* Toggle m, n ready */ 636 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 637 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 638 usleep_range(1000, 1100); 639 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 640 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 641 642 /* Configure integer stable register */ 643 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 644 MIPI_VIDEO_STABLE_CNT, 0x02); 645 /* Power on MIPI RX */ 646 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 647 MIPI_LANE_CTRL_10, 0x00); 648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 649 MIPI_LANE_CTRL_10, 0x80); 650 651 if (ret < 0) 652 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 653 654 return ret; 655 } 656 657 static int anx7625_dsi_config(struct anx7625_data *ctx) 658 { 659 struct device *dev = ctx->dev; 660 int ret; 661 662 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 663 664 /* DSC disable */ 665 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 666 R_DSC_CTRL_0, ~DSC_EN); 667 668 ret |= anx7625_api_dsi_config(ctx); 669 670 if (ret < 0) { 671 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 672 return ret; 673 } 674 675 /* Set MIPI RX EN */ 676 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 677 AP_AV_STATUS, AP_MIPI_RX_EN); 678 /* Clear mute flag */ 679 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 680 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 681 if (ret < 0) 682 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 683 else 684 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 685 686 return ret; 687 } 688 689 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 690 { 691 struct device *dev = ctx->dev; 692 u16 freq = ctx->dt.pixelclock.min / 1000; 693 int ret; 694 695 /* configure pixel clock */ 696 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 697 PIXEL_CLOCK_L, freq & 0xFF); 698 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 699 PIXEL_CLOCK_H, (freq >> 8)); 700 701 /* set DPI mode */ 702 /* set to DPI PLL module sel */ 703 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 704 MIPI_DIGITAL_PLL_9, 0x20); 705 /* power down MIPI */ 706 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 707 MIPI_LANE_CTRL_10, 0x08); 708 /* enable DPI mode */ 709 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 710 MIPI_DIGITAL_PLL_18, 0x1C); 711 /* set first edge */ 712 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 713 VIDEO_CONTROL_0, 0x06); 714 if (ret < 0) 715 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 716 717 return ret; 718 } 719 720 static int anx7625_dpi_config(struct anx7625_data *ctx) 721 { 722 struct device *dev = ctx->dev; 723 int ret; 724 725 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 726 727 /* DSC disable */ 728 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 729 R_DSC_CTRL_0, ~DSC_EN); 730 if (ret < 0) { 731 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 732 return ret; 733 } 734 735 ret = anx7625_config_bit_matrix(ctx); 736 if (ret < 0) { 737 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 738 return ret; 739 } 740 741 ret = anx7625_api_dpi_config(ctx); 742 if (ret < 0) { 743 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 744 return ret; 745 } 746 747 /* set MIPI RX EN */ 748 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 749 AP_AV_STATUS, AP_MIPI_RX_EN); 750 /* clear mute flag */ 751 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 752 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 753 if (ret < 0) 754 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 755 756 return ret; 757 } 758 759 static int anx7625_read_flash_status(struct anx7625_data *ctx) 760 { 761 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 762 } 763 764 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 765 { 766 int ret, val; 767 struct device *dev = ctx->dev; 768 u8 ident[FLASH_BUF_LEN]; 769 770 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 771 FLASH_ADDR_HIGH, 0x91); 772 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 773 FLASH_ADDR_LOW, 0xA0); 774 if (ret < 0) { 775 dev_err(dev, "IO error : set key flash address.\n"); 776 return ret; 777 } 778 779 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 780 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 781 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 782 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 783 if (ret < 0) { 784 dev_err(dev, "IO error : set key flash len.\n"); 785 return ret; 786 } 787 788 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 789 R_FLASH_RW_CTRL, FLASH_READ); 790 ret |= readx_poll_timeout(anx7625_read_flash_status, 791 ctx, val, 792 ((val & FLASH_DONE) || (val < 0)), 793 2000, 794 2000 * 150); 795 if (ret) { 796 dev_err(dev, "flash read access fail!\n"); 797 return -EIO; 798 } 799 800 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 801 FLASH_BUF_BASE_ADDR, 802 FLASH_BUF_LEN, ident); 803 if (ret < 0) { 804 dev_err(dev, "read flash data fail!\n"); 805 return -EIO; 806 } 807 808 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 809 return -EINVAL; 810 811 return 0; 812 } 813 814 static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 815 { 816 int ret; 817 struct device *dev = ctx->dev; 818 819 /* Select HDCP 1.4 KEY */ 820 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 821 R_BOOT_RETRY, 0x12); 822 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 823 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 825 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 830 831 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 832 R_RAM_ADDR_H, 0); 833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 834 R_RAM_ADDR_L, 0); 835 /* Enable HDCP 1.4 KEY load */ 836 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 837 R_RAM_CTRL, DECRYPT_EN | LOAD_START); 838 dev_dbg(dev, "load HDCP 1.4 key done\n"); 839 return ret; 840 } 841 842 static int anx7625_hdcp_disable(struct anx7625_data *ctx) 843 { 844 int ret; 845 struct device *dev = ctx->dev; 846 847 dev_dbg(dev, "disable HDCP 1.4\n"); 848 849 /* Disable HDCP */ 850 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 851 /* Try auth flag */ 852 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 853 /* Interrupt for DRM */ 854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 855 if (ret < 0) 856 dev_err(dev, "fail to disable HDCP\n"); 857 858 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 859 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 860 } 861 862 static int anx7625_hdcp_enable(struct anx7625_data *ctx) 863 { 864 u8 bcap; 865 int ret; 866 struct device *dev = ctx->dev; 867 868 ret = anx7625_hdcp_key_probe(ctx); 869 if (ret) { 870 dev_dbg(dev, "no key found, not to do hdcp\n"); 871 return ret; 872 } 873 874 /* Read downstream capability */ 875 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, DP_AUX_HDCP_BCAPS, 1, &bcap); 876 if (ret < 0) 877 return ret; 878 879 if (!(bcap & DP_BCAPS_HDCP_CAPABLE)) { 880 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 881 return 0; 882 } 883 884 dev_dbg(dev, "enable HDCP 1.4\n"); 885 886 /* First clear HDCP state */ 887 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 888 TX_HDCP_CTRL0, 889 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 890 usleep_range(1000, 1100); 891 /* Second clear HDCP state */ 892 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 893 TX_HDCP_CTRL0, 894 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 895 896 /* Set time for waiting KSVR */ 897 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 898 SP_TX_WAIT_KSVR_TIME, 0xc8); 899 /* Set time for waiting R0 */ 900 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 901 SP_TX_WAIT_R0_TIME, 0xb0); 902 ret |= anx7625_hdcp_key_load(ctx); 903 if (ret) { 904 pr_warn("prepare HDCP key failed.\n"); 905 return ret; 906 } 907 908 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 909 910 /* Try auth flag */ 911 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 912 /* Interrupt for DRM */ 913 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 914 if (ret < 0) 915 dev_err(dev, "fail to enable HDCP\n"); 916 917 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 918 TX_HDCP_CTRL0, HARD_AUTH_EN); 919 } 920 921 static void anx7625_dp_start(struct anx7625_data *ctx) 922 { 923 int ret; 924 struct device *dev = ctx->dev; 925 u8 data; 926 927 if (!ctx->display_timing_valid) { 928 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 929 return; 930 } 931 932 dev_dbg(dev, "set downstream sink into normal\n"); 933 /* Downstream sink enter into normal mode */ 934 data = DP_SET_POWER_D0; 935 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data); 936 if (ret < 0) 937 dev_err(dev, "IO error : set sink into normal mode fail\n"); 938 939 /* Disable HDCP */ 940 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 941 942 if (ctx->pdata.is_dpi) 943 ret = anx7625_dpi_config(ctx); 944 else 945 ret = anx7625_dsi_config(ctx); 946 947 if (ret < 0) 948 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 949 950 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 951 952 ctx->dp_en = 1; 953 } 954 955 static void anx7625_dp_stop(struct anx7625_data *ctx) 956 { 957 struct device *dev = ctx->dev; 958 int ret; 959 u8 data; 960 961 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 962 963 /* 964 * Video disable: 0x72:08 bit 7 = 0; 965 * Audio disable: 0x70:87 bit 0 = 0; 966 */ 967 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 968 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 969 970 ret |= anx7625_video_mute_control(ctx, 1); 971 972 dev_dbg(dev, "notify downstream enter into standby\n"); 973 /* Downstream monitor enter into standby mode */ 974 data = DP_SET_POWER_D3; 975 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data); 976 if (ret < 0) 977 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 978 979 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 980 981 ctx->dp_en = 0; 982 } 983 984 static int sp_tx_rst_aux(struct anx7625_data *ctx) 985 { 986 int ret; 987 988 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 989 AUX_RST); 990 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 991 ~AUX_RST); 992 return ret; 993 } 994 995 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 996 { 997 int ret; 998 999 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1000 AP_AUX_BUFF_START, offset); 1001 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1002 AP_AUX_COMMAND, 0x04); 1003 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1004 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1005 return (ret | wait_aux_op_finish(ctx)); 1006 } 1007 1008 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 1009 { 1010 int ret; 1011 1012 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1013 AP_AUX_COMMAND, len_cmd); 1014 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1015 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1016 return (ret | wait_aux_op_finish(ctx)); 1017 } 1018 1019 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 1020 { 1021 int c = 0; 1022 struct device *dev = ctx->dev; 1023 1024 sp_tx_aux_wr(ctx, 0x7e); 1025 sp_tx_aux_rd(ctx, 0x01); 1026 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 1027 if (c < 0) { 1028 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 1029 return -EIO; 1030 } 1031 1032 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 1033 1034 if (c > MAX_EDID_BLOCK) 1035 c = 1; 1036 1037 return c; 1038 } 1039 1040 static int edid_read(struct anx7625_data *ctx, 1041 u8 offset, u8 *pblock_buf) 1042 { 1043 int ret, cnt; 1044 struct device *dev = ctx->dev; 1045 1046 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1047 sp_tx_aux_wr(ctx, offset); 1048 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1049 ret = sp_tx_aux_rd(ctx, 0xf1); 1050 1051 if (ret) { 1052 ret = sp_tx_rst_aux(ctx); 1053 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 1054 } else { 1055 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1056 AP_AUX_BUFF_START, 1057 MAX_DPCD_BUFFER_SIZE, 1058 pblock_buf); 1059 if (ret > 0) 1060 break; 1061 } 1062 } 1063 1064 if (cnt > EDID_TRY_CNT) 1065 return -EIO; 1066 1067 return ret; 1068 } 1069 1070 static int segments_edid_read(struct anx7625_data *ctx, 1071 u8 segment, u8 *buf, u8 offset) 1072 { 1073 u8 cnt; 1074 int ret; 1075 struct device *dev = ctx->dev; 1076 1077 /* Write address only */ 1078 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1079 AP_AUX_ADDR_7_0, 0x30); 1080 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1081 AP_AUX_COMMAND, 0x04); 1082 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1083 AP_AUX_CTRL_STATUS, 1084 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 1085 1086 ret |= wait_aux_op_finish(ctx); 1087 /* Write segment address */ 1088 ret |= sp_tx_aux_wr(ctx, segment); 1089 /* Data read */ 1090 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1091 AP_AUX_ADDR_7_0, 0x50); 1092 if (ret) { 1093 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 1094 return ret; 1095 } 1096 1097 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1098 sp_tx_aux_wr(ctx, offset); 1099 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1100 ret = sp_tx_aux_rd(ctx, 0xf1); 1101 1102 if (ret) { 1103 ret = sp_tx_rst_aux(ctx); 1104 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 1105 } else { 1106 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1107 AP_AUX_BUFF_START, 1108 MAX_DPCD_BUFFER_SIZE, buf); 1109 if (ret > 0) 1110 break; 1111 } 1112 } 1113 1114 if (cnt > EDID_TRY_CNT) 1115 return -EIO; 1116 1117 return ret; 1118 } 1119 1120 static int sp_tx_edid_read(struct anx7625_data *ctx, 1121 u8 *pedid_blocks_buf) 1122 { 1123 u8 offset; 1124 int edid_pos; 1125 int count, blocks_num; 1126 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 1127 u8 i, j; 1128 int g_edid_break = 0; 1129 int ret; 1130 struct device *dev = ctx->dev; 1131 1132 /* Address initial */ 1133 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1134 AP_AUX_ADDR_7_0, 0x50); 1135 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1136 AP_AUX_ADDR_15_8, 0); 1137 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 1138 AP_AUX_ADDR_19_16, 0xf0); 1139 if (ret < 0) { 1140 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 1141 return -EIO; 1142 } 1143 1144 blocks_num = sp_tx_get_edid_block(ctx); 1145 if (blocks_num < 0) 1146 return blocks_num; 1147 1148 count = 0; 1149 1150 do { 1151 switch (count) { 1152 case 0: 1153 case 1: 1154 for (i = 0; i < 8; i++) { 1155 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 1156 g_edid_break = edid_read(ctx, offset, 1157 pblock_buf); 1158 1159 if (g_edid_break < 0) 1160 break; 1161 1162 memcpy(&pedid_blocks_buf[offset], 1163 pblock_buf, 1164 MAX_DPCD_BUFFER_SIZE); 1165 } 1166 1167 break; 1168 case 2: 1169 offset = 0x00; 1170 1171 for (j = 0; j < 8; j++) { 1172 edid_pos = (j + count * 8) * 1173 MAX_DPCD_BUFFER_SIZE; 1174 1175 if (g_edid_break == 1) 1176 break; 1177 1178 ret = segments_edid_read(ctx, count / 2, 1179 pblock_buf, offset); 1180 if (ret < 0) 1181 return ret; 1182 1183 memcpy(&pedid_blocks_buf[edid_pos], 1184 pblock_buf, 1185 MAX_DPCD_BUFFER_SIZE); 1186 offset = offset + 0x10; 1187 } 1188 1189 break; 1190 case 3: 1191 offset = 0x80; 1192 1193 for (j = 0; j < 8; j++) { 1194 edid_pos = (j + count * 8) * 1195 MAX_DPCD_BUFFER_SIZE; 1196 if (g_edid_break == 1) 1197 break; 1198 1199 ret = segments_edid_read(ctx, count / 2, 1200 pblock_buf, offset); 1201 if (ret < 0) 1202 return ret; 1203 1204 memcpy(&pedid_blocks_buf[edid_pos], 1205 pblock_buf, 1206 MAX_DPCD_BUFFER_SIZE); 1207 offset = offset + 0x10; 1208 } 1209 1210 break; 1211 default: 1212 break; 1213 } 1214 1215 count++; 1216 1217 } while (blocks_num >= count); 1218 1219 /* Check edid data */ 1220 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 1221 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 1222 return -EINVAL; 1223 } 1224 1225 /* Reset aux channel */ 1226 ret = sp_tx_rst_aux(ctx); 1227 if (ret < 0) { 1228 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 1229 return ret; 1230 } 1231 1232 return (blocks_num + 1); 1233 } 1234 1235 static void anx7625_power_on(struct anx7625_data *ctx) 1236 { 1237 struct device *dev = ctx->dev; 1238 int ret, i; 1239 1240 if (!ctx->pdata.low_power_mode) { 1241 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1242 return; 1243 } 1244 1245 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 1246 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 1247 if (ret < 0) { 1248 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 1249 i, ret); 1250 goto reg_err; 1251 } 1252 usleep_range(2000, 2100); 1253 } 1254 1255 usleep_range(11000, 12000); 1256 1257 /* Power on pin enable */ 1258 gpiod_set_value(ctx->pdata.gpio_p_on, 1); 1259 usleep_range(10000, 11000); 1260 /* Power reset pin enable */ 1261 gpiod_set_value(ctx->pdata.gpio_reset, 1); 1262 usleep_range(10000, 11000); 1263 1264 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 1265 return; 1266 reg_err: 1267 for (--i; i >= 0; i--) 1268 regulator_disable(ctx->pdata.supplies[i].consumer); 1269 } 1270 1271 static void anx7625_power_standby(struct anx7625_data *ctx) 1272 { 1273 struct device *dev = ctx->dev; 1274 int ret; 1275 1276 if (!ctx->pdata.low_power_mode) { 1277 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1278 return; 1279 } 1280 1281 gpiod_set_value(ctx->pdata.gpio_reset, 0); 1282 usleep_range(1000, 1100); 1283 gpiod_set_value(ctx->pdata.gpio_p_on, 0); 1284 usleep_range(1000, 1100); 1285 1286 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1287 ctx->pdata.supplies); 1288 if (ret < 0) 1289 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1290 1291 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1292 } 1293 1294 /* Basic configurations of ANX7625 */ 1295 static void anx7625_config(struct anx7625_data *ctx) 1296 { 1297 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1298 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1299 } 1300 1301 static int anx7625_hpd_timer_config(struct anx7625_data *ctx) 1302 { 1303 int ret; 1304 1305 /* Set irq detect window to 2ms */ 1306 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1307 HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF); 1308 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1309 HPD_DET_TIMER_BIT8_15, 1310 (HPD_TIME >> 8) & 0xFF); 1311 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1312 HPD_DET_TIMER_BIT16_23, 1313 (HPD_TIME >> 16) & 0xFF); 1314 1315 return ret; 1316 } 1317 1318 static int anx7625_read_hpd_gpio_config_status(struct anx7625_data *ctx) 1319 { 1320 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, GPIO_CTRL_2); 1321 } 1322 1323 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1324 { 1325 struct device *dev = ctx->dev; 1326 int ret, val; 1327 1328 /* Reset main ocm */ 1329 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1330 /* Disable PD */ 1331 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1332 AP_AV_STATUS, AP_DISABLE_PD); 1333 /* Release main ocm */ 1334 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1335 1336 if (ret < 0) 1337 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1338 else 1339 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1340 1341 /* 1342 * Make sure the HPD GPIO already be configured after OCM release before 1343 * setting HPD detect window register. Here we poll the status register 1344 * at maximum 40ms, then config HPD irq detect window register 1345 */ 1346 readx_poll_timeout(anx7625_read_hpd_gpio_config_status, 1347 ctx, val, 1348 ((val & HPD_SOURCE) || (val < 0)), 1349 2000, 2000 * 20); 1350 1351 /* Set HPD irq detect window to 2ms */ 1352 anx7625_hpd_timer_config(ctx); 1353 } 1354 1355 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1356 { 1357 int ret; 1358 struct device *dev = ctx->dev; 1359 1360 /* Check interface workable */ 1361 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1362 FLASH_LOAD_STA); 1363 if (ret < 0) { 1364 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1365 return ret; 1366 } 1367 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1368 return -ENODEV; 1369 1370 anx7625_disable_pd_protocol(ctx); 1371 1372 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1373 anx7625_reg_read(ctx, 1374 ctx->i2c.rx_p0_client, 1375 OCM_FW_VERSION), 1376 anx7625_reg_read(ctx, 1377 ctx->i2c.rx_p0_client, 1378 OCM_FW_REVERSION)); 1379 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1380 ANX7625_DRV_VERSION); 1381 1382 return 0; 1383 } 1384 1385 static void anx7625_power_on_init(struct anx7625_data *ctx) 1386 { 1387 int retry_count, i; 1388 1389 for (retry_count = 0; retry_count < 3; retry_count++) { 1390 anx7625_power_on(ctx); 1391 anx7625_config(ctx); 1392 1393 for (i = 0; i < OCM_LOADING_TIME; i++) { 1394 if (!anx7625_ocm_loading_check(ctx)) 1395 return; 1396 usleep_range(1000, 1100); 1397 } 1398 anx7625_power_standby(ctx); 1399 } 1400 } 1401 1402 static void anx7625_init_gpio(struct anx7625_data *platform) 1403 { 1404 struct device *dev = platform->dev; 1405 1406 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1407 1408 /* Gpio for chip power enable */ 1409 platform->pdata.gpio_p_on = 1410 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1411 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 1412 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 1413 platform->pdata.gpio_p_on = NULL; 1414 } 1415 1416 /* Gpio for chip reset */ 1417 platform->pdata.gpio_reset = 1418 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1419 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 1420 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 1421 platform->pdata.gpio_reset = NULL; 1422 } 1423 1424 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1425 platform->pdata.low_power_mode = 1; 1426 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1427 desc_to_gpio(platform->pdata.gpio_p_on), 1428 desc_to_gpio(platform->pdata.gpio_reset)); 1429 } else { 1430 platform->pdata.low_power_mode = 0; 1431 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1432 } 1433 } 1434 1435 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1436 { 1437 ctx->hpd_status = 0; 1438 ctx->hpd_high_cnt = 0; 1439 } 1440 1441 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1442 { 1443 int ret; 1444 struct device *dev = ctx->dev; 1445 1446 if (ctx->hpd_high_cnt >= 2) { 1447 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1448 return; 1449 } 1450 1451 ctx->hpd_status = 1; 1452 ctx->hpd_high_cnt++; 1453 1454 /* Not support HDCP */ 1455 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1456 1457 /* Try auth flag */ 1458 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1459 /* Interrupt for DRM */ 1460 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1461 if (ret < 0) { 1462 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1463 return; 1464 } 1465 1466 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1467 if (ret < 0) 1468 return; 1469 1470 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1471 } 1472 1473 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1474 { 1475 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1476 } 1477 1478 static int _anx7625_hpd_polling(struct anx7625_data *ctx, 1479 unsigned long wait_us) 1480 { 1481 int ret, val; 1482 struct device *dev = ctx->dev; 1483 1484 /* Interrupt mode, no need poll HPD status, just return */ 1485 if (ctx->pdata.intp_irq) 1486 return 0; 1487 1488 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1489 ctx, val, 1490 ((val & HPD_STATUS) || (val < 0)), 1491 wait_us / 100, 1492 wait_us); 1493 if (ret) { 1494 DRM_DEV_ERROR(dev, "no hpd.\n"); 1495 return ret; 1496 } 1497 1498 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1499 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1500 INTR_ALERT_1, 0xFF); 1501 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1502 INTERFACE_CHANGE_INT, 0); 1503 1504 anx7625_start_dp_work(ctx); 1505 1506 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1507 drm_helper_hpd_irq_event(ctx->bridge.dev); 1508 1509 return 0; 1510 } 1511 1512 static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux, 1513 unsigned long wait_us) 1514 { 1515 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1516 struct device *dev = ctx->dev; 1517 int ret; 1518 1519 pm_runtime_get_sync(dev); 1520 ret = _anx7625_hpd_polling(ctx, wait_us); 1521 pm_runtime_mark_last_busy(dev); 1522 pm_runtime_put_autosuspend(dev); 1523 1524 return ret; 1525 } 1526 1527 static void anx7625_remove_edid(struct anx7625_data *ctx) 1528 { 1529 ctx->slimport_edid_p.edid_block_num = -1; 1530 } 1531 1532 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1533 { 1534 int i; 1535 1536 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1537 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1538 DP_TX_LANE0_SWING_REG0 + i, 1539 ctx->pdata.lane0_reg_data[i]); 1540 1541 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1542 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1543 DP_TX_LANE1_SWING_REG0 + i, 1544 ctx->pdata.lane1_reg_data[i]); 1545 } 1546 1547 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1548 { 1549 struct device *dev = ctx->dev; 1550 1551 /* HPD changed */ 1552 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1553 (u32)on); 1554 1555 if (on == 0) { 1556 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1557 anx7625_remove_edid(ctx); 1558 anx7625_stop_dp_work(ctx); 1559 } else { 1560 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1561 anx7625_start_dp_work(ctx); 1562 anx7625_dp_adjust_swing(ctx); 1563 } 1564 } 1565 1566 static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1567 { 1568 int intr_vector, status; 1569 struct device *dev = ctx->dev; 1570 1571 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1572 INTR_ALERT_1, 0xFF); 1573 if (status < 0) { 1574 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1575 return status; 1576 } 1577 1578 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1579 INTERFACE_CHANGE_INT); 1580 if (intr_vector < 0) { 1581 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1582 return intr_vector; 1583 } 1584 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1585 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1586 INTERFACE_CHANGE_INT, 1587 intr_vector & (~intr_vector)); 1588 if (status < 0) { 1589 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1590 return status; 1591 } 1592 1593 if (!(intr_vector & HPD_STATUS_CHANGE)) 1594 return -ENOENT; 1595 1596 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1597 SYSTEM_STSTUS); 1598 if (status < 0) { 1599 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1600 return status; 1601 } 1602 1603 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1604 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1605 1606 return 0; 1607 } 1608 1609 static void anx7625_work_func(struct work_struct *work) 1610 { 1611 int event; 1612 struct anx7625_data *ctx = container_of(work, 1613 struct anx7625_data, work); 1614 1615 mutex_lock(&ctx->lock); 1616 1617 if (pm_runtime_suspended(ctx->dev)) { 1618 mutex_unlock(&ctx->lock); 1619 return; 1620 } 1621 1622 event = anx7625_hpd_change_detect(ctx); 1623 1624 mutex_unlock(&ctx->lock); 1625 1626 if (event < 0) 1627 return; 1628 1629 if (ctx->bridge_attached) 1630 drm_helper_hpd_irq_event(ctx->bridge.dev); 1631 } 1632 1633 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1634 { 1635 struct anx7625_data *ctx = (struct anx7625_data *)data; 1636 1637 queue_work(ctx->workqueue, &ctx->work); 1638 1639 return IRQ_HANDLED; 1640 } 1641 1642 static int anx7625_get_swing_setting(struct device *dev, 1643 struct anx7625_platform_data *pdata) 1644 { 1645 int num_regs; 1646 1647 if (of_get_property(dev->of_node, 1648 "analogix,lane0-swing", &num_regs)) { 1649 if (num_regs > DP_TX_SWING_REG_CNT) 1650 num_regs = DP_TX_SWING_REG_CNT; 1651 1652 pdata->dp_lane0_swing_reg_cnt = num_regs; 1653 of_property_read_u8_array(dev->of_node, "analogix,lane0-swing", 1654 pdata->lane0_reg_data, num_regs); 1655 } 1656 1657 if (of_get_property(dev->of_node, 1658 "analogix,lane1-swing", &num_regs)) { 1659 if (num_regs > DP_TX_SWING_REG_CNT) 1660 num_regs = DP_TX_SWING_REG_CNT; 1661 1662 pdata->dp_lane1_swing_reg_cnt = num_regs; 1663 of_property_read_u8_array(dev->of_node, "analogix,lane1-swing", 1664 pdata->lane1_reg_data, num_regs); 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int anx7625_parse_dt(struct device *dev, 1671 struct anx7625_platform_data *pdata) 1672 { 1673 struct device_node *np = dev->of_node, *ep0; 1674 int bus_type, mipi_lanes; 1675 1676 anx7625_get_swing_setting(dev, pdata); 1677 1678 pdata->is_dpi = 0; /* default dsi mode */ 1679 of_node_put(pdata->mipi_host_node); 1680 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1681 if (!pdata->mipi_host_node) { 1682 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1683 return -ENODEV; 1684 } 1685 1686 bus_type = 0; 1687 mipi_lanes = MAX_LANES_SUPPORT; 1688 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1689 if (ep0) { 1690 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1691 bus_type = 0; 1692 1693 mipi_lanes = drm_of_get_data_lanes_count(ep0, 1, MAX_LANES_SUPPORT); 1694 of_node_put(ep0); 1695 } 1696 1697 if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */ 1698 pdata->is_dpi = 1; 1699 1700 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1701 if (mipi_lanes > 0) 1702 pdata->mipi_lanes = mipi_lanes; 1703 1704 if (pdata->is_dpi) 1705 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1706 else 1707 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1708 1709 if (of_property_read_bool(np, "analogix,audio-enable")) 1710 pdata->audio_en = 1; 1711 1712 return 0; 1713 } 1714 1715 static int anx7625_parse_dt_panel(struct device *dev, 1716 struct anx7625_platform_data *pdata) 1717 { 1718 struct device_node *np = dev->of_node; 1719 1720 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); 1721 if (IS_ERR(pdata->panel_bridge)) { 1722 if (PTR_ERR(pdata->panel_bridge) == -ENODEV) { 1723 pdata->panel_bridge = NULL; 1724 return 0; 1725 } 1726 1727 return PTR_ERR(pdata->panel_bridge); 1728 } 1729 1730 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1731 1732 return 0; 1733 } 1734 1735 static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1736 { 1737 struct device_node *bus, *panel; 1738 1739 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1740 if (!bus) 1741 return false; 1742 1743 panel = of_get_child_by_name(bus, "panel"); 1744 of_node_put(bus); 1745 if (!panel) 1746 return false; 1747 of_node_put(panel); 1748 1749 return true; 1750 } 1751 1752 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1753 { 1754 return container_of(bridge, struct anx7625_data, bridge); 1755 } 1756 1757 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1758 struct drm_dp_aux_msg *msg) 1759 { 1760 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1761 struct device *dev = ctx->dev; 1762 u8 request = msg->request & ~DP_AUX_I2C_MOT; 1763 int ret = 0; 1764 1765 mutex_lock(&ctx->aux_lock); 1766 pm_runtime_get_sync(dev); 1767 msg->reply = 0; 1768 switch (request) { 1769 case DP_AUX_NATIVE_WRITE: 1770 case DP_AUX_I2C_WRITE: 1771 case DP_AUX_NATIVE_READ: 1772 case DP_AUX_I2C_READ: 1773 break; 1774 default: 1775 ret = -EINVAL; 1776 } 1777 if (!ret) 1778 ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1779 msg->size, msg->buffer); 1780 pm_runtime_mark_last_busy(dev); 1781 pm_runtime_put_autosuspend(dev); 1782 mutex_unlock(&ctx->aux_lock); 1783 1784 return ret; 1785 } 1786 1787 static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1788 { 1789 struct device *dev = ctx->dev; 1790 struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1791 int edid_num; 1792 u8 *edid; 1793 1794 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1795 if (!edid) { 1796 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1797 return NULL; 1798 } 1799 1800 if (ctx->slimport_edid_p.edid_block_num > 0) { 1801 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1802 FOUR_BLOCK_SIZE); 1803 return (struct edid *)edid; 1804 } 1805 1806 pm_runtime_get_sync(dev); 1807 _anx7625_hpd_polling(ctx, 5000 * 100); 1808 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1809 pm_runtime_put_sync(dev); 1810 1811 if (edid_num < 1) { 1812 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1813 kfree(edid); 1814 return NULL; 1815 } 1816 1817 p_edid->edid_block_num = edid_num; 1818 1819 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1820 return (struct edid *)edid; 1821 } 1822 1823 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1824 { 1825 struct device *dev = ctx->dev; 1826 1827 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1828 1829 if (ctx->pdata.panel_bridge) 1830 return connector_status_connected; 1831 1832 return ctx->hpd_status ? connector_status_connected : 1833 connector_status_disconnected; 1834 } 1835 1836 static int anx7625_audio_hw_params(struct device *dev, void *data, 1837 struct hdmi_codec_daifmt *fmt, 1838 struct hdmi_codec_params *params) 1839 { 1840 struct anx7625_data *ctx = dev_get_drvdata(dev); 1841 int wl, ch, rate; 1842 int ret = 0; 1843 1844 if (anx7625_sink_detect(ctx) == connector_status_disconnected) { 1845 DRM_DEV_DEBUG_DRIVER(dev, "DP not connected\n"); 1846 return 0; 1847 } 1848 1849 if (fmt->fmt != HDMI_DSP_A && fmt->fmt != HDMI_I2S) { 1850 DRM_DEV_ERROR(dev, "only supports DSP_A & I2S\n"); 1851 return -EINVAL; 1852 } 1853 1854 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1855 params->sample_rate, params->sample_width, 1856 params->cea.channels); 1857 1858 if (fmt->fmt == HDMI_DSP_A) 1859 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1860 AUDIO_CHANNEL_STATUS_6, 1861 ~I2S_SLAVE_MODE, 1862 TDM_SLAVE_MODE); 1863 else 1864 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1865 AUDIO_CHANNEL_STATUS_6, 1866 ~TDM_SLAVE_MODE, 1867 I2S_SLAVE_MODE); 1868 1869 /* Word length */ 1870 switch (params->sample_width) { 1871 case 16: 1872 wl = AUDIO_W_LEN_16_20MAX; 1873 break; 1874 case 18: 1875 wl = AUDIO_W_LEN_18_20MAX; 1876 break; 1877 case 20: 1878 wl = AUDIO_W_LEN_20_20MAX; 1879 break; 1880 case 24: 1881 wl = AUDIO_W_LEN_24_24MAX; 1882 break; 1883 default: 1884 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1885 params->sample_width); 1886 return -EINVAL; 1887 } 1888 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1889 AUDIO_CHANNEL_STATUS_5, 1890 0xf0, wl); 1891 1892 /* Channel num */ 1893 switch (params->cea.channels) { 1894 case 2: 1895 ch = I2S_CH_2; 1896 break; 1897 case 4: 1898 ch = TDM_CH_4; 1899 break; 1900 case 6: 1901 ch = TDM_CH_6; 1902 break; 1903 case 8: 1904 ch = TDM_CH_8; 1905 break; 1906 default: 1907 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1908 params->cea.channels); 1909 return -EINVAL; 1910 } 1911 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1912 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1913 if (ch > I2S_CH_2) 1914 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1915 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1916 else 1917 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1918 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1919 1920 /* FS */ 1921 switch (params->sample_rate) { 1922 case 32000: 1923 rate = AUDIO_FS_32K; 1924 break; 1925 case 44100: 1926 rate = AUDIO_FS_441K; 1927 break; 1928 case 48000: 1929 rate = AUDIO_FS_48K; 1930 break; 1931 case 88200: 1932 rate = AUDIO_FS_882K; 1933 break; 1934 case 96000: 1935 rate = AUDIO_FS_96K; 1936 break; 1937 case 176400: 1938 rate = AUDIO_FS_1764K; 1939 break; 1940 case 192000: 1941 rate = AUDIO_FS_192K; 1942 break; 1943 default: 1944 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1945 params->sample_rate); 1946 return -EINVAL; 1947 } 1948 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1949 AUDIO_CHANNEL_STATUS_4, 1950 0xf0, rate); 1951 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1952 AP_AV_STATUS, AP_AUDIO_CHG); 1953 if (ret < 0) { 1954 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1955 return -EIO; 1956 } 1957 1958 return 0; 1959 } 1960 1961 static void anx7625_audio_shutdown(struct device *dev, void *data) 1962 { 1963 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1964 } 1965 1966 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1967 struct device_node *endpoint) 1968 { 1969 struct of_endpoint of_ep; 1970 int ret; 1971 1972 ret = of_graph_parse_endpoint(endpoint, &of_ep); 1973 if (ret < 0) 1974 return ret; 1975 1976 /* 1977 * HDMI sound should be located at external DPI port 1978 * Didn't have good way to check where is internal(DSI) 1979 * or external(DPI) bridge 1980 */ 1981 return 0; 1982 } 1983 1984 static void 1985 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1986 enum drm_connector_status status) 1987 { 1988 if (ctx->plugged_cb && ctx->codec_dev) { 1989 ctx->plugged_cb(ctx->codec_dev, 1990 status == connector_status_connected); 1991 } 1992 } 1993 1994 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1995 hdmi_codec_plugged_cb fn, 1996 struct device *codec_dev) 1997 { 1998 struct anx7625_data *ctx = data; 1999 2000 ctx->plugged_cb = fn; 2001 ctx->codec_dev = codec_dev; 2002 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 2003 2004 return 0; 2005 } 2006 2007 static int anx7625_audio_get_eld(struct device *dev, void *data, 2008 u8 *buf, size_t len) 2009 { 2010 struct anx7625_data *ctx = dev_get_drvdata(dev); 2011 2012 if (!ctx->connector) { 2013 /* Pass en empty ELD if connector not available */ 2014 memset(buf, 0, len); 2015 } else { 2016 dev_dbg(dev, "audio copy eld\n"); 2017 memcpy(buf, ctx->connector->eld, 2018 min(sizeof(ctx->connector->eld), len)); 2019 } 2020 2021 return 0; 2022 } 2023 2024 static const struct hdmi_codec_ops anx7625_codec_ops = { 2025 .hw_params = anx7625_audio_hw_params, 2026 .audio_shutdown = anx7625_audio_shutdown, 2027 .get_eld = anx7625_audio_get_eld, 2028 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 2029 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 2030 }; 2031 2032 static void anx7625_unregister_audio(struct anx7625_data *ctx) 2033 { 2034 struct device *dev = ctx->dev; 2035 2036 if (ctx->audio_pdev) { 2037 platform_device_unregister(ctx->audio_pdev); 2038 ctx->audio_pdev = NULL; 2039 } 2040 2041 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 2042 } 2043 2044 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 2045 { 2046 struct hdmi_codec_pdata codec_data = { 2047 .ops = &anx7625_codec_ops, 2048 .max_i2s_channels = 8, 2049 .i2s = 1, 2050 .data = ctx, 2051 }; 2052 2053 ctx->audio_pdev = platform_device_register_data(dev, 2054 HDMI_CODEC_DRV_NAME, 2055 PLATFORM_DEVID_AUTO, 2056 &codec_data, 2057 sizeof(codec_data)); 2058 2059 if (IS_ERR(ctx->audio_pdev)) 2060 return PTR_ERR(ctx->audio_pdev); 2061 2062 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 2063 2064 return 0; 2065 } 2066 2067 static int anx7625_setup_dsi_device(struct anx7625_data *ctx) 2068 { 2069 struct mipi_dsi_device *dsi; 2070 struct device *dev = ctx->dev; 2071 struct mipi_dsi_host *host; 2072 const struct mipi_dsi_device_info info = { 2073 .type = "anx7625", 2074 .channel = 0, 2075 .node = NULL, 2076 }; 2077 2078 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 2079 if (!host) { 2080 DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 2081 return -EPROBE_DEFER; 2082 } 2083 2084 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2085 if (IS_ERR(dsi)) { 2086 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 2087 return -EINVAL; 2088 } 2089 2090 dsi->lanes = ctx->pdata.mipi_lanes; 2091 dsi->format = MIPI_DSI_FMT_RGB888; 2092 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 2093 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2094 MIPI_DSI_MODE_VIDEO_HSE | 2095 MIPI_DSI_HS_PKT_END_ALIGNED; 2096 2097 ctx->dsi = dsi; 2098 2099 return 0; 2100 } 2101 2102 static int anx7625_attach_dsi(struct anx7625_data *ctx) 2103 { 2104 struct device *dev = ctx->dev; 2105 int ret; 2106 2107 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 2108 2109 ret = devm_mipi_dsi_attach(dev, ctx->dsi); 2110 if (ret) { 2111 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 2112 return ret; 2113 } 2114 2115 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 2116 2117 return 0; 2118 } 2119 2120 static void hdcp_check_work_func(struct work_struct *work) 2121 { 2122 u8 status; 2123 struct delayed_work *dwork; 2124 struct anx7625_data *ctx; 2125 struct device *dev; 2126 struct drm_device *drm_dev; 2127 2128 dwork = to_delayed_work(work); 2129 ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2130 dev = ctx->dev; 2131 2132 if (!ctx->connector) { 2133 dev_err(dev, "HDCP connector is null!"); 2134 return; 2135 } 2136 2137 drm_dev = ctx->connector->dev; 2138 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2139 mutex_lock(&ctx->hdcp_wq_lock); 2140 2141 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2142 dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2143 if (status & BIT(1)) { 2144 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2145 drm_hdcp_update_content_protection(ctx->connector, 2146 ctx->hdcp_cp); 2147 dev_dbg(dev, "update CP to ENABLE\n"); 2148 } 2149 2150 mutex_unlock(&ctx->hdcp_wq_lock); 2151 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2152 } 2153 2154 static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2155 struct drm_connector_state *state) 2156 { 2157 struct device *dev = ctx->dev; 2158 int cp; 2159 2160 dev_dbg(dev, "hdcp state check\n"); 2161 cp = state->content_protection; 2162 2163 if (cp == ctx->hdcp_cp) 2164 return 0; 2165 2166 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2167 if (ctx->dp_en) { 2168 dev_dbg(dev, "enable HDCP\n"); 2169 anx7625_hdcp_enable(ctx); 2170 2171 queue_delayed_work(ctx->hdcp_workqueue, 2172 &ctx->hdcp_work, 2173 msecs_to_jiffies(2000)); 2174 } 2175 } 2176 2177 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2178 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2179 dev_err(dev, "current CP is not ENABLED\n"); 2180 return -EINVAL; 2181 } 2182 anx7625_hdcp_disable(ctx); 2183 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2184 drm_hdcp_update_content_protection(ctx->connector, 2185 ctx->hdcp_cp); 2186 dev_dbg(dev, "update CP to UNDESIRE\n"); 2187 } 2188 2189 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2190 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2191 return -EINVAL; 2192 } 2193 2194 return 0; 2195 } 2196 2197 static int anx7625_bridge_attach(struct drm_bridge *bridge, 2198 enum drm_bridge_attach_flags flags) 2199 { 2200 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2201 int err; 2202 struct device *dev = ctx->dev; 2203 2204 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 2205 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 2206 return -EINVAL; 2207 2208 if (!bridge->encoder) { 2209 DRM_DEV_ERROR(dev, "Parent encoder object not found"); 2210 return -ENODEV; 2211 } 2212 2213 ctx->aux.drm_dev = bridge->dev; 2214 err = drm_dp_aux_register(&ctx->aux); 2215 if (err) { 2216 dev_err(dev, "failed to register aux channel: %d\n", err); 2217 return err; 2218 } 2219 2220 if (ctx->pdata.panel_bridge) { 2221 err = drm_bridge_attach(bridge->encoder, 2222 ctx->pdata.panel_bridge, 2223 &ctx->bridge, flags); 2224 if (err) 2225 return err; 2226 } 2227 2228 ctx->bridge_attached = 1; 2229 2230 return 0; 2231 } 2232 2233 static void anx7625_bridge_detach(struct drm_bridge *bridge) 2234 { 2235 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2236 2237 drm_dp_aux_unregister(&ctx->aux); 2238 } 2239 2240 static enum drm_mode_status 2241 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 2242 const struct drm_display_info *info, 2243 const struct drm_display_mode *mode) 2244 { 2245 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2246 struct device *dev = ctx->dev; 2247 2248 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 2249 2250 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 2251 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 2252 DRM_DEV_DEBUG_DRIVER(dev, 2253 "drm mode invalid, pixelclock too high.\n"); 2254 return MODE_CLOCK_HIGH; 2255 } 2256 2257 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 2258 2259 return MODE_OK; 2260 } 2261 2262 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 2263 const struct drm_display_mode *old_mode, 2264 const struct drm_display_mode *mode) 2265 { 2266 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2267 struct device *dev = ctx->dev; 2268 2269 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 2270 2271 ctx->dt.pixelclock.min = mode->clock; 2272 ctx->dt.hactive.min = mode->hdisplay; 2273 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 2274 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 2275 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 2276 ctx->dt.vactive.min = mode->vdisplay; 2277 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 2278 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 2279 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 2280 2281 ctx->display_timing_valid = 1; 2282 2283 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 2284 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 2285 ctx->dt.hactive.min, 2286 ctx->dt.hsync_len.min, 2287 ctx->dt.hfront_porch.min, 2288 ctx->dt.hback_porch.min); 2289 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 2290 ctx->dt.vactive.min, 2291 ctx->dt.vsync_len.min, 2292 ctx->dt.vfront_porch.min, 2293 ctx->dt.vback_porch.min); 2294 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 2295 mode->hdisplay, 2296 mode->hsync_start); 2297 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 2298 mode->hsync_end, 2299 mode->htotal); 2300 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 2301 mode->vdisplay, 2302 mode->vsync_start); 2303 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 2304 mode->vsync_end, 2305 mode->vtotal); 2306 } 2307 2308 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 2309 const struct drm_display_mode *mode, 2310 struct drm_display_mode *adj) 2311 { 2312 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2313 struct device *dev = ctx->dev; 2314 u32 hsync, hfp, hbp, hblanking; 2315 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 2316 u32 vref, adj_clock; 2317 2318 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 2319 2320 /* No need fixup for external monitor */ 2321 if (!ctx->pdata.panel_bridge) 2322 return true; 2323 2324 hsync = mode->hsync_end - mode->hsync_start; 2325 hfp = mode->hsync_start - mode->hdisplay; 2326 hbp = mode->htotal - mode->hsync_end; 2327 hblanking = mode->htotal - mode->hdisplay; 2328 2329 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 2330 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2331 hsync, hfp, hbp, adj->clock); 2332 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2333 adj->hsync_start, adj->hsync_end, adj->htotal); 2334 2335 adj_hfp = hfp; 2336 adj_hsync = hsync; 2337 adj_hbp = hbp; 2338 adj_hblanking = hblanking; 2339 2340 /* HFP needs to be even */ 2341 if (hfp & 0x1) { 2342 adj_hfp += 1; 2343 adj_hblanking += 1; 2344 } 2345 2346 /* HBP needs to be even */ 2347 if (hbp & 0x1) { 2348 adj_hbp -= 1; 2349 adj_hblanking -= 1; 2350 } 2351 2352 /* HSYNC needs to be even */ 2353 if (hsync & 0x1) { 2354 if (adj_hblanking < hblanking) 2355 adj_hsync += 1; 2356 else 2357 adj_hsync -= 1; 2358 } 2359 2360 /* 2361 * Once illegal timing detected, use default HFP, HSYNC, HBP 2362 * This adjusting made for built-in eDP panel, for the externel 2363 * DP monitor, may need return false. 2364 */ 2365 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 2366 adj_hsync = SYNC_LEN_DEF; 2367 adj_hfp = HFP_HBP_DEF; 2368 adj_hbp = HFP_HBP_DEF; 2369 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 2370 if (hblanking < HBLANKING_MIN) { 2371 delta_adj = HBLANKING_MIN - hblanking; 2372 adj_clock = vref * delta_adj * adj->vtotal; 2373 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 2374 } else { 2375 delta_adj = hblanking - HBLANKING_MIN; 2376 adj_clock = vref * delta_adj * adj->vtotal; 2377 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 2378 } 2379 2380 DRM_WARN("illegal hblanking timing, use default.\n"); 2381 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 2382 } else if (adj_hfp < HP_MIN) { 2383 /* Adjust hfp if hfp less than HP_MIN */ 2384 delta_adj = HP_MIN - adj_hfp; 2385 adj_hfp = HP_MIN; 2386 2387 /* 2388 * Balance total HBlanking pixel, if HBP does not have enough 2389 * space, adjust HSYNC length, otherwise adjust HBP 2390 */ 2391 if ((adj_hbp - delta_adj) < HP_MIN) 2392 /* HBP not enough space */ 2393 adj_hsync -= delta_adj; 2394 else 2395 adj_hbp -= delta_adj; 2396 } else if (adj_hbp < HP_MIN) { 2397 delta_adj = HP_MIN - adj_hbp; 2398 adj_hbp = HP_MIN; 2399 2400 /* 2401 * Balance total HBlanking pixel, if HBP hasn't enough space, 2402 * adjust HSYNC length, otherwize adjust HBP 2403 */ 2404 if ((adj_hfp - delta_adj) < HP_MIN) 2405 /* HFP not enough space */ 2406 adj_hsync -= delta_adj; 2407 else 2408 adj_hfp -= delta_adj; 2409 } 2410 2411 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 2412 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2413 adj_hsync, adj_hfp, adj_hbp, adj->clock); 2414 2415 /* Reconstruct timing */ 2416 adj->hsync_start = adj->hdisplay + adj_hfp; 2417 adj->hsync_end = adj->hsync_start + adj_hsync; 2418 adj->htotal = adj->hsync_end + adj_hbp; 2419 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2420 adj->hsync_start, adj->hsync_end, adj->htotal); 2421 2422 return true; 2423 } 2424 2425 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2426 struct drm_bridge_state *bridge_state, 2427 struct drm_crtc_state *crtc_state, 2428 struct drm_connector_state *conn_state) 2429 { 2430 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2431 struct device *dev = ctx->dev; 2432 2433 dev_dbg(dev, "drm bridge atomic check\n"); 2434 2435 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2436 &crtc_state->adjusted_mode); 2437 2438 return anx7625_connector_atomic_check(ctx, conn_state); 2439 } 2440 2441 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2442 struct drm_bridge_state *state) 2443 { 2444 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2445 struct device *dev = ctx->dev; 2446 struct drm_connector *connector; 2447 2448 dev_dbg(dev, "drm atomic enable\n"); 2449 2450 if (!bridge->encoder) { 2451 dev_err(dev, "Parent encoder object not found"); 2452 return; 2453 } 2454 2455 connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2456 bridge->encoder); 2457 if (!connector) 2458 return; 2459 2460 ctx->connector = connector; 2461 2462 pm_runtime_get_sync(dev); 2463 _anx7625_hpd_polling(ctx, 5000 * 100); 2464 2465 anx7625_dp_start(ctx); 2466 } 2467 2468 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2469 struct drm_bridge_state *old) 2470 { 2471 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2472 struct device *dev = ctx->dev; 2473 2474 dev_dbg(dev, "drm atomic disable\n"); 2475 2476 ctx->connector = NULL; 2477 anx7625_dp_stop(ctx); 2478 2479 mutex_lock(&ctx->aux_lock); 2480 pm_runtime_put_sync_suspend(dev); 2481 mutex_unlock(&ctx->aux_lock); 2482 } 2483 2484 static enum drm_connector_status 2485 anx7625_bridge_detect(struct drm_bridge *bridge) 2486 { 2487 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2488 struct device *dev = ctx->dev; 2489 2490 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 2491 2492 return anx7625_sink_detect(ctx); 2493 } 2494 2495 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 2496 struct drm_connector *connector) 2497 { 2498 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2499 struct device *dev = ctx->dev; 2500 2501 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 2502 2503 return anx7625_get_edid(ctx); 2504 } 2505 2506 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 2507 .attach = anx7625_bridge_attach, 2508 .detach = anx7625_bridge_detach, 2509 .mode_valid = anx7625_bridge_mode_valid, 2510 .mode_set = anx7625_bridge_mode_set, 2511 .atomic_check = anx7625_bridge_atomic_check, 2512 .atomic_enable = anx7625_bridge_atomic_enable, 2513 .atomic_disable = anx7625_bridge_atomic_disable, 2514 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2515 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2516 .atomic_reset = drm_atomic_helper_bridge_reset, 2517 .detect = anx7625_bridge_detect, 2518 .get_edid = anx7625_bridge_get_edid, 2519 }; 2520 2521 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 2522 struct i2c_client *client) 2523 { 2524 struct device *dev = ctx->dev; 2525 2526 ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter, 2527 TX_P0_ADDR >> 1); 2528 if (IS_ERR(ctx->i2c.tx_p0_client)) 2529 return PTR_ERR(ctx->i2c.tx_p0_client); 2530 2531 ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter, 2532 TX_P1_ADDR >> 1); 2533 if (IS_ERR(ctx->i2c.tx_p1_client)) 2534 return PTR_ERR(ctx->i2c.tx_p1_client); 2535 2536 ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter, 2537 TX_P2_ADDR >> 1); 2538 if (IS_ERR(ctx->i2c.tx_p2_client)) 2539 return PTR_ERR(ctx->i2c.tx_p2_client); 2540 2541 ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter, 2542 RX_P0_ADDR >> 1); 2543 if (IS_ERR(ctx->i2c.rx_p0_client)) 2544 return PTR_ERR(ctx->i2c.rx_p0_client); 2545 2546 ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter, 2547 RX_P1_ADDR >> 1); 2548 if (IS_ERR(ctx->i2c.rx_p1_client)) 2549 return PTR_ERR(ctx->i2c.rx_p1_client); 2550 2551 ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter, 2552 RX_P2_ADDR >> 1); 2553 if (IS_ERR(ctx->i2c.rx_p2_client)) 2554 return PTR_ERR(ctx->i2c.rx_p2_client); 2555 2556 ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter, 2557 TCPC_INTERFACE_ADDR >> 1); 2558 if (IS_ERR(ctx->i2c.tcpc_client)) 2559 return PTR_ERR(ctx->i2c.tcpc_client); 2560 2561 return 0; 2562 } 2563 2564 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2565 { 2566 struct anx7625_data *ctx = dev_get_drvdata(dev); 2567 2568 mutex_lock(&ctx->lock); 2569 2570 anx7625_stop_dp_work(ctx); 2571 anx7625_power_standby(ctx); 2572 2573 mutex_unlock(&ctx->lock); 2574 2575 return 0; 2576 } 2577 2578 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2579 { 2580 struct anx7625_data *ctx = dev_get_drvdata(dev); 2581 2582 mutex_lock(&ctx->lock); 2583 2584 anx7625_power_on_init(ctx); 2585 2586 mutex_unlock(&ctx->lock); 2587 2588 return 0; 2589 } 2590 2591 static const struct dev_pm_ops anx7625_pm_ops = { 2592 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2593 pm_runtime_force_resume) 2594 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2595 anx7625_runtime_pm_resume, NULL) 2596 }; 2597 2598 static void anx7625_runtime_disable(void *data) 2599 { 2600 pm_runtime_dont_use_autosuspend(data); 2601 pm_runtime_disable(data); 2602 } 2603 2604 static int anx7625_link_bridge(struct drm_dp_aux *aux) 2605 { 2606 struct anx7625_data *platform = container_of(aux, struct anx7625_data, aux); 2607 struct device *dev = aux->dev; 2608 int ret; 2609 2610 ret = anx7625_parse_dt_panel(dev, &platform->pdata); 2611 if (ret) { 2612 DRM_DEV_ERROR(dev, "fail to parse DT for panel : %d\n", ret); 2613 return ret; 2614 } 2615 2616 platform->bridge.funcs = &anx7625_bridge_funcs; 2617 platform->bridge.of_node = dev->of_node; 2618 if (!anx7625_of_panel_on_aux_bus(dev)) 2619 platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 2620 if (!platform->pdata.panel_bridge) 2621 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2622 DRM_BRIDGE_OP_DETECT; 2623 platform->bridge.type = platform->pdata.panel_bridge ? 2624 DRM_MODE_CONNECTOR_eDP : 2625 DRM_MODE_CONNECTOR_DisplayPort; 2626 2627 drm_bridge_add(&platform->bridge); 2628 2629 if (!platform->pdata.is_dpi) { 2630 ret = anx7625_attach_dsi(platform); 2631 if (ret) 2632 drm_bridge_remove(&platform->bridge); 2633 } 2634 2635 return ret; 2636 } 2637 2638 static int anx7625_i2c_probe(struct i2c_client *client) 2639 { 2640 struct anx7625_data *platform; 2641 struct anx7625_platform_data *pdata; 2642 int ret = 0; 2643 struct device *dev = &client->dev; 2644 2645 if (!i2c_check_functionality(client->adapter, 2646 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2647 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2648 return -ENODEV; 2649 } 2650 2651 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL); 2652 if (!platform) { 2653 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2654 return -ENOMEM; 2655 } 2656 2657 pdata = &platform->pdata; 2658 2659 platform->dev = &client->dev; 2660 i2c_set_clientdata(client, platform); 2661 2662 pdata->supplies[0].supply = "vdd10"; 2663 pdata->supplies[1].supply = "vdd18"; 2664 pdata->supplies[2].supply = "vdd33"; 2665 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2666 pdata->supplies); 2667 if (ret) { 2668 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2669 return ret; 2670 } 2671 anx7625_init_gpio(platform); 2672 2673 mutex_init(&platform->lock); 2674 mutex_init(&platform->hdcp_wq_lock); 2675 mutex_init(&platform->aux_lock); 2676 2677 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2678 platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2679 if (!platform->hdcp_workqueue) { 2680 dev_err(dev, "fail to create work queue\n"); 2681 ret = -ENOMEM; 2682 return ret; 2683 } 2684 2685 platform->pdata.intp_irq = client->irq; 2686 if (platform->pdata.intp_irq) { 2687 INIT_WORK(&platform->work, anx7625_work_func); 2688 platform->workqueue = alloc_workqueue("anx7625_work", 2689 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2690 if (!platform->workqueue) { 2691 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2692 ret = -ENOMEM; 2693 goto free_hdcp_wq; 2694 } 2695 2696 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2697 NULL, anx7625_intr_hpd_isr, 2698 IRQF_TRIGGER_FALLING | 2699 IRQF_ONESHOT, 2700 "anx7625-intp", platform); 2701 if (ret) { 2702 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2703 goto free_wq; 2704 } 2705 } 2706 2707 platform->aux.name = "anx7625-aux"; 2708 platform->aux.dev = dev; 2709 platform->aux.transfer = anx7625_aux_transfer; 2710 platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted; 2711 drm_dp_aux_init(&platform->aux); 2712 2713 ret = anx7625_parse_dt(dev, pdata); 2714 if (ret) { 2715 if (ret != -EPROBE_DEFER) 2716 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2717 goto free_wq; 2718 } 2719 2720 if (!platform->pdata.is_dpi) { 2721 ret = anx7625_setup_dsi_device(platform); 2722 if (ret < 0) 2723 goto free_wq; 2724 } 2725 2726 /* 2727 * Registering the i2c devices will retrigger deferred probe, so it 2728 * needs to be done after calls that might return EPROBE_DEFER, 2729 * otherwise we can get an infinite loop. 2730 */ 2731 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2732 ret = -ENOMEM; 2733 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2734 goto free_wq; 2735 } 2736 2737 pm_runtime_enable(dev); 2738 pm_runtime_set_autosuspend_delay(dev, 1000); 2739 pm_runtime_use_autosuspend(dev); 2740 pm_suspend_ignore_children(dev, true); 2741 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev); 2742 if (ret) 2743 goto free_wq; 2744 2745 /* 2746 * Populating the aux bus will retrigger deferred probe, so it needs to 2747 * be done after calls that might return EPROBE_DEFER, otherwise we can 2748 * get an infinite loop. 2749 */ 2750 ret = devm_of_dp_aux_populate_bus(&platform->aux, anx7625_link_bridge); 2751 if (ret) { 2752 if (ret != -ENODEV) { 2753 DRM_DEV_ERROR(dev, "failed to populate aux bus : %d\n", ret); 2754 goto free_wq; 2755 } 2756 2757 ret = anx7625_link_bridge(&platform->aux); 2758 if (ret) 2759 goto free_wq; 2760 } 2761 2762 if (!platform->pdata.low_power_mode) { 2763 anx7625_disable_pd_protocol(platform); 2764 pm_runtime_get_sync(dev); 2765 _anx7625_hpd_polling(platform, 5000 * 100); 2766 } 2767 2768 /* Add work function */ 2769 if (platform->pdata.intp_irq) 2770 queue_work(platform->workqueue, &platform->work); 2771 2772 if (platform->pdata.audio_en) 2773 anx7625_register_audio(dev, platform); 2774 2775 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2776 2777 return 0; 2778 2779 free_wq: 2780 if (platform->workqueue) 2781 destroy_workqueue(platform->workqueue); 2782 2783 free_hdcp_wq: 2784 if (platform->hdcp_workqueue) 2785 destroy_workqueue(platform->hdcp_workqueue); 2786 2787 return ret; 2788 } 2789 2790 static void anx7625_i2c_remove(struct i2c_client *client) 2791 { 2792 struct anx7625_data *platform = i2c_get_clientdata(client); 2793 2794 drm_bridge_remove(&platform->bridge); 2795 2796 if (platform->pdata.intp_irq) 2797 destroy_workqueue(platform->workqueue); 2798 2799 if (platform->hdcp_workqueue) { 2800 cancel_delayed_work(&platform->hdcp_work); 2801 flush_workqueue(platform->hdcp_workqueue); 2802 destroy_workqueue(platform->hdcp_workqueue); 2803 } 2804 2805 if (!platform->pdata.low_power_mode) 2806 pm_runtime_put_sync_suspend(&client->dev); 2807 2808 if (platform->pdata.audio_en) 2809 anx7625_unregister_audio(platform); 2810 } 2811 2812 static const struct i2c_device_id anx7625_id[] = { 2813 {"anx7625", 0}, 2814 {} 2815 }; 2816 2817 MODULE_DEVICE_TABLE(i2c, anx7625_id); 2818 2819 static const struct of_device_id anx_match_table[] = { 2820 {.compatible = "analogix,anx7625",}, 2821 {}, 2822 }; 2823 MODULE_DEVICE_TABLE(of, anx_match_table); 2824 2825 static struct i2c_driver anx7625_driver = { 2826 .driver = { 2827 .name = "anx7625", 2828 .of_match_table = anx_match_table, 2829 .pm = &anx7625_pm_ops, 2830 }, 2831 .probe = anx7625_i2c_probe, 2832 .remove = anx7625_i2c_remove, 2833 2834 .id_table = anx7625_id, 2835 }; 2836 2837 module_i2c_driver(anx7625_driver); 2838 2839 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 2840 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 2841 MODULE_LICENSE("GPL v2"); 2842 MODULE_VERSION(ANX7625_DRV_VERSION); 2843