18bdfc5daSXin Ji // SPDX-License-Identifier: GPL-2.0-only 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji #include <linux/gcd.h> 78bdfc5daSXin Ji #include <linux/gpio/consumer.h> 88bdfc5daSXin Ji #include <linux/i2c.h> 98bdfc5daSXin Ji #include <linux/interrupt.h> 108bdfc5daSXin Ji #include <linux/iopoll.h> 118bdfc5daSXin Ji #include <linux/kernel.h> 128bdfc5daSXin Ji #include <linux/module.h> 138bdfc5daSXin Ji #include <linux/mutex.h> 1460487584SPi-Hsun Shih #include <linux/pm_runtime.h> 156c744983SHsin-Yi Wang #include <linux/regulator/consumer.h> 168bdfc5daSXin Ji #include <linux/slab.h> 178bdfc5daSXin Ji #include <linux/types.h> 188bdfc5daSXin Ji #include <linux/workqueue.h> 198bdfc5daSXin Ji 208bdfc5daSXin Ji #include <linux/of_gpio.h> 218bdfc5daSXin Ji #include <linux/of_graph.h> 228bdfc5daSXin Ji #include <linux/of_platform.h> 238bdfc5daSXin Ji 248bdfc5daSXin Ji #include <drm/drm_atomic_helper.h> 258bdfc5daSXin Ji #include <drm/drm_bridge.h> 268bdfc5daSXin Ji #include <drm/drm_crtc_helper.h> 278bdfc5daSXin Ji #include <drm/drm_dp_helper.h> 288bdfc5daSXin Ji #include <drm/drm_edid.h> 298bdfc5daSXin Ji #include <drm/drm_mipi_dsi.h> 308bdfc5daSXin Ji #include <drm/drm_of.h> 318bdfc5daSXin Ji #include <drm/drm_panel.h> 328bdfc5daSXin Ji #include <drm/drm_print.h> 338bdfc5daSXin Ji #include <drm/drm_probe_helper.h> 348bdfc5daSXin Ji 35*fd0310b6SXin Ji #include <media/v4l2-fwnode.h> 368bdfc5daSXin Ji #include <video/display_timing.h> 378bdfc5daSXin Ji 388bdfc5daSXin Ji #include "anx7625.h" 398bdfc5daSXin Ji 408bdfc5daSXin Ji /* 418bdfc5daSXin Ji * There is a sync issue while access I2C register between AP(CPU) and 428bdfc5daSXin Ji * internal firmware(OCM), to avoid the race condition, AP should access 438bdfc5daSXin Ji * the reserved slave address before slave address occurs changes. 448bdfc5daSXin Ji */ 458bdfc5daSXin Ji static int i2c_access_workaround(struct anx7625_data *ctx, 468bdfc5daSXin Ji struct i2c_client *client) 478bdfc5daSXin Ji { 488bdfc5daSXin Ji u8 offset; 498bdfc5daSXin Ji struct device *dev = &client->dev; 508bdfc5daSXin Ji int ret; 518bdfc5daSXin Ji 528bdfc5daSXin Ji if (client == ctx->last_client) 538bdfc5daSXin Ji return 0; 548bdfc5daSXin Ji 558bdfc5daSXin Ji ctx->last_client = client; 568bdfc5daSXin Ji 578bdfc5daSXin Ji if (client == ctx->i2c.tcpc_client) 588bdfc5daSXin Ji offset = RSVD_00_ADDR; 598bdfc5daSXin Ji else if (client == ctx->i2c.tx_p0_client) 608bdfc5daSXin Ji offset = RSVD_D1_ADDR; 618bdfc5daSXin Ji else if (client == ctx->i2c.tx_p1_client) 628bdfc5daSXin Ji offset = RSVD_60_ADDR; 638bdfc5daSXin Ji else if (client == ctx->i2c.rx_p0_client) 648bdfc5daSXin Ji offset = RSVD_39_ADDR; 658bdfc5daSXin Ji else if (client == ctx->i2c.rx_p1_client) 668bdfc5daSXin Ji offset = RSVD_7F_ADDR; 678bdfc5daSXin Ji else 688bdfc5daSXin Ji offset = RSVD_00_ADDR; 698bdfc5daSXin Ji 708bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, offset, 0x00); 718bdfc5daSXin Ji if (ret < 0) 728bdfc5daSXin Ji DRM_DEV_ERROR(dev, 738bdfc5daSXin Ji "fail to access i2c id=%x\n:%x", 748bdfc5daSXin Ji client->addr, offset); 758bdfc5daSXin Ji 768bdfc5daSXin Ji return ret; 778bdfc5daSXin Ji } 788bdfc5daSXin Ji 798bdfc5daSXin Ji static int anx7625_reg_read(struct anx7625_data *ctx, 808bdfc5daSXin Ji struct i2c_client *client, u8 reg_addr) 818bdfc5daSXin Ji { 828bdfc5daSXin Ji int ret; 838bdfc5daSXin Ji struct device *dev = &client->dev; 848bdfc5daSXin Ji 858bdfc5daSXin Ji i2c_access_workaround(ctx, client); 868bdfc5daSXin Ji 878bdfc5daSXin Ji ret = i2c_smbus_read_byte_data(client, reg_addr); 888bdfc5daSXin Ji if (ret < 0) 898bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 908bdfc5daSXin Ji client->addr, reg_addr); 918bdfc5daSXin Ji 928bdfc5daSXin Ji return ret; 938bdfc5daSXin Ji } 948bdfc5daSXin Ji 958bdfc5daSXin Ji static int anx7625_reg_block_read(struct anx7625_data *ctx, 968bdfc5daSXin Ji struct i2c_client *client, 978bdfc5daSXin Ji u8 reg_addr, u8 len, u8 *buf) 988bdfc5daSXin Ji { 998bdfc5daSXin Ji int ret; 1008bdfc5daSXin Ji struct device *dev = &client->dev; 1018bdfc5daSXin Ji 1028bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1038bdfc5daSXin Ji 1048bdfc5daSXin Ji ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 1058bdfc5daSXin Ji if (ret < 0) 1068bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 1078bdfc5daSXin Ji client->addr, reg_addr); 1088bdfc5daSXin Ji 1098bdfc5daSXin Ji return ret; 1108bdfc5daSXin Ji } 1118bdfc5daSXin Ji 1128bdfc5daSXin Ji static int anx7625_reg_write(struct anx7625_data *ctx, 1138bdfc5daSXin Ji struct i2c_client *client, 1148bdfc5daSXin Ji u8 reg_addr, u8 reg_val) 1158bdfc5daSXin Ji { 1168bdfc5daSXin Ji int ret; 1178bdfc5daSXin Ji struct device *dev = &client->dev; 1188bdfc5daSXin Ji 1198bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1208bdfc5daSXin Ji 1218bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 1228bdfc5daSXin Ji 1238bdfc5daSXin Ji if (ret < 0) 1248bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 1258bdfc5daSXin Ji client->addr, reg_addr); 1268bdfc5daSXin Ji 1278bdfc5daSXin Ji return ret; 1288bdfc5daSXin Ji } 1298bdfc5daSXin Ji 1308bdfc5daSXin Ji static int anx7625_write_or(struct anx7625_data *ctx, 1318bdfc5daSXin Ji struct i2c_client *client, 1328bdfc5daSXin Ji u8 offset, u8 mask) 1338bdfc5daSXin Ji { 1348bdfc5daSXin Ji int val; 1358bdfc5daSXin Ji 1368bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1378bdfc5daSXin Ji if (val < 0) 1388bdfc5daSXin Ji return val; 1398bdfc5daSXin Ji 1408bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val | (mask))); 1418bdfc5daSXin Ji } 1428bdfc5daSXin Ji 1438bdfc5daSXin Ji static int anx7625_write_and(struct anx7625_data *ctx, 1448bdfc5daSXin Ji struct i2c_client *client, 1458bdfc5daSXin Ji u8 offset, u8 mask) 1468bdfc5daSXin Ji { 1478bdfc5daSXin Ji int val; 1488bdfc5daSXin Ji 1498bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1508bdfc5daSXin Ji if (val < 0) 1518bdfc5daSXin Ji return val; 1528bdfc5daSXin Ji 1538bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val & (mask))); 1548bdfc5daSXin Ji } 1558bdfc5daSXin Ji 156*fd0310b6SXin Ji static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 1578bdfc5daSXin Ji { 158*fd0310b6SXin Ji int i, ret; 1598bdfc5daSXin Ji 160*fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 161*fd0310b6SXin Ji AUDIO_CONTROL_REGISTER, 0x80); 162*fd0310b6SXin Ji for (i = 0; i < 13; i++) 163*fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 164*fd0310b6SXin Ji VIDEO_BIT_MATRIX_12 + i, 165*fd0310b6SXin Ji 0x18 + i); 1668bdfc5daSXin Ji 167*fd0310b6SXin Ji return ret; 1688bdfc5daSXin Ji } 1698bdfc5daSXin Ji 1708bdfc5daSXin Ji static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 1718bdfc5daSXin Ji { 1728bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 1738bdfc5daSXin Ji } 1748bdfc5daSXin Ji 1758bdfc5daSXin Ji static int wait_aux_op_finish(struct anx7625_data *ctx) 1768bdfc5daSXin Ji { 1778bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1788bdfc5daSXin Ji int val; 1798bdfc5daSXin Ji int ret; 1808bdfc5daSXin Ji 1818bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 1828bdfc5daSXin Ji ctx, val, 1838bdfc5daSXin Ji (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 1848bdfc5daSXin Ji 2000, 1858bdfc5daSXin Ji 2000 * 150); 1868bdfc5daSXin Ji if (ret) { 1878bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux operation fail!\n"); 1888bdfc5daSXin Ji return -EIO; 1898bdfc5daSXin Ji } 1908bdfc5daSXin Ji 1918bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1928bdfc5daSXin Ji AP_AUX_CTRL_STATUS); 1938bdfc5daSXin Ji if (val < 0 || (val & 0x0F)) { 1948bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux status %02x\n", val); 1959a7e49bdSXin Ji return -EIO; 1968bdfc5daSXin Ji } 1978bdfc5daSXin Ji 1989a7e49bdSXin Ji return 0; 1998bdfc5daSXin Ji } 2008bdfc5daSXin Ji 2018bdfc5daSXin Ji static int anx7625_video_mute_control(struct anx7625_data *ctx, 2028bdfc5daSXin Ji u8 status) 2038bdfc5daSXin Ji { 2048bdfc5daSXin Ji int ret; 2058bdfc5daSXin Ji 2068bdfc5daSXin Ji if (status) { 2078bdfc5daSXin Ji /* Set mute on flag */ 2088bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2098bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_MUTE); 2108bdfc5daSXin Ji /* Clear mipi RX en */ 2118bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 2128bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 2138bdfc5daSXin Ji } else { 2148bdfc5daSXin Ji /* Mute off flag */ 2158bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 2168bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 2178bdfc5daSXin Ji /* Set MIPI RX EN */ 2188bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2198bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 2208bdfc5daSXin Ji } 2218bdfc5daSXin Ji 2228bdfc5daSXin Ji return ret; 2238bdfc5daSXin Ji } 2248bdfc5daSXin Ji 2258bdfc5daSXin Ji /* Reduction of fraction a/b */ 2268bdfc5daSXin Ji static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 2278bdfc5daSXin Ji { 2288bdfc5daSXin Ji unsigned long gcd_num; 2298bdfc5daSXin Ji unsigned long tmp_a, tmp_b; 2308bdfc5daSXin Ji u32 i = 1; 2318bdfc5daSXin Ji 2328bdfc5daSXin Ji gcd_num = gcd(*a, *b); 2338bdfc5daSXin Ji *a /= gcd_num; 2348bdfc5daSXin Ji *b /= gcd_num; 2358bdfc5daSXin Ji 2368bdfc5daSXin Ji tmp_a = *a; 2378bdfc5daSXin Ji tmp_b = *b; 2388bdfc5daSXin Ji 2398bdfc5daSXin Ji while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 2408bdfc5daSXin Ji i++; 2418bdfc5daSXin Ji *a = tmp_a / i; 2428bdfc5daSXin Ji *b = tmp_b / i; 2438bdfc5daSXin Ji } 2448bdfc5daSXin Ji 2458bdfc5daSXin Ji /* 2468bdfc5daSXin Ji * In the end, make a, b larger to have higher ODFC PLL 2478bdfc5daSXin Ji * output frequency accuracy 2488bdfc5daSXin Ji */ 2498bdfc5daSXin Ji while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 2508bdfc5daSXin Ji *a <<= 1; 2518bdfc5daSXin Ji *b <<= 1; 2528bdfc5daSXin Ji } 2538bdfc5daSXin Ji 2548bdfc5daSXin Ji *a >>= 1; 2558bdfc5daSXin Ji *b >>= 1; 2568bdfc5daSXin Ji } 2578bdfc5daSXin Ji 2588bdfc5daSXin Ji static int anx7625_calculate_m_n(u32 pixelclock, 2598bdfc5daSXin Ji unsigned long *m, 2608bdfc5daSXin Ji unsigned long *n, 2618bdfc5daSXin Ji u8 *post_divider) 2628bdfc5daSXin Ji { 2638bdfc5daSXin Ji if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 2648bdfc5daSXin Ji /* Pixel clock frequency is too high */ 2658bdfc5daSXin Ji DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 2668bdfc5daSXin Ji pixelclock, 2678bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 2688bdfc5daSXin Ji return -EINVAL; 2698bdfc5daSXin Ji } 2708bdfc5daSXin Ji 2718bdfc5daSXin Ji if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 2728bdfc5daSXin Ji /* Pixel clock frequency is too low */ 2738bdfc5daSXin Ji DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 2748bdfc5daSXin Ji pixelclock, 2758bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 2768bdfc5daSXin Ji return -EINVAL; 2778bdfc5daSXin Ji } 2788bdfc5daSXin Ji 2798bdfc5daSXin Ji for (*post_divider = 1; 2808bdfc5daSXin Ji pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 2818bdfc5daSXin Ji *post_divider += 1; 2828bdfc5daSXin Ji 2838bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 2848bdfc5daSXin Ji for (*post_divider = 1; 2858bdfc5daSXin Ji (pixelclock < 2868bdfc5daSXin Ji (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 2878bdfc5daSXin Ji *post_divider += 1; 2888bdfc5daSXin Ji 2898bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 2908bdfc5daSXin Ji DRM_ERROR("cannot find property post_divider(%d)\n", 2918bdfc5daSXin Ji *post_divider); 2928bdfc5daSXin Ji return -EDOM; 2938bdfc5daSXin Ji } 2948bdfc5daSXin Ji } 2958bdfc5daSXin Ji 2968bdfc5daSXin Ji /* Patch to improve the accuracy */ 2978bdfc5daSXin Ji if (*post_divider == 7) { 2988bdfc5daSXin Ji /* 27,000,000 is not divisible by 7 */ 2998bdfc5daSXin Ji *post_divider = 8; 3008bdfc5daSXin Ji } else if (*post_divider == 11) { 3018bdfc5daSXin Ji /* 27,000,000 is not divisible by 11 */ 3028bdfc5daSXin Ji *post_divider = 12; 3038bdfc5daSXin Ji } else if ((*post_divider == 13) || (*post_divider == 14)) { 3048bdfc5daSXin Ji /* 27,000,000 is not divisible by 13 or 14 */ 3058bdfc5daSXin Ji *post_divider = 15; 3068bdfc5daSXin Ji } 3078bdfc5daSXin Ji 3088bdfc5daSXin Ji if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 3098bdfc5daSXin Ji DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 3108bdfc5daSXin Ji pixelclock * (*post_divider), 3118bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX); 3128bdfc5daSXin Ji return -EDOM; 3138bdfc5daSXin Ji } 3148bdfc5daSXin Ji 3158bdfc5daSXin Ji *m = pixelclock; 3168bdfc5daSXin Ji *n = XTAL_FRQ / (*post_divider); 3178bdfc5daSXin Ji 3188bdfc5daSXin Ji anx7625_reduction_of_a_fraction(m, n); 3198bdfc5daSXin Ji 3208bdfc5daSXin Ji return 0; 3218bdfc5daSXin Ji } 3228bdfc5daSXin Ji 3238bdfc5daSXin Ji static int anx7625_odfc_config(struct anx7625_data *ctx, 3248bdfc5daSXin Ji u8 post_divider) 3258bdfc5daSXin Ji { 3268bdfc5daSXin Ji int ret; 3278bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 3288bdfc5daSXin Ji 3298bdfc5daSXin Ji /* Config input reference clock frequency 27MHz/19.2MHz */ 3308bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 3318bdfc5daSXin Ji ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 3328bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 3338bdfc5daSXin Ji (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 3348bdfc5daSXin Ji /* Post divider */ 3358bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 3368bdfc5daSXin Ji MIPI_DIGITAL_PLL_8, 0x0f); 3378bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 3388bdfc5daSXin Ji post_divider << 4); 3398bdfc5daSXin Ji 3408bdfc5daSXin Ji /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 3418bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3428bdfc5daSXin Ji ~MIPI_PLL_VCO_TUNE_REG_VAL); 3438bdfc5daSXin Ji 3448bdfc5daSXin Ji /* Reset ODFC PLL */ 3458bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3468bdfc5daSXin Ji ~MIPI_PLL_RESET_N); 3478bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3488bdfc5daSXin Ji MIPI_PLL_RESET_N); 3498bdfc5daSXin Ji 3508bdfc5daSXin Ji if (ret < 0) 3518bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error.\n"); 3528bdfc5daSXin Ji 3538bdfc5daSXin Ji return ret; 3548bdfc5daSXin Ji } 3558bdfc5daSXin Ji 3567d066dc7SXin Ji /* 3577d066dc7SXin Ji * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 3587d066dc7SXin Ji * anx7625 defined K ratio for matching MIPI input video clock and 3597d066dc7SXin Ji * DP output video clock. Increase K value can match bigger video data 3607d066dc7SXin Ji * variation. IVO panel has small variation than DP CTS spec, need 3617d066dc7SXin Ji * decrease the K value. 3627d066dc7SXin Ji */ 3637d066dc7SXin Ji static int anx7625_set_k_value(struct anx7625_data *ctx) 3647d066dc7SXin Ji { 3657d066dc7SXin Ji struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 3667d066dc7SXin Ji 3677d066dc7SXin Ji if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 3687d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 3697d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3B); 3707d066dc7SXin Ji 3717d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 3727d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3D); 3737d066dc7SXin Ji } 3747d066dc7SXin Ji 3758bdfc5daSXin Ji static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 3768bdfc5daSXin Ji { 3778bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 3788bdfc5daSXin Ji unsigned long m, n; 3798bdfc5daSXin Ji u16 htotal; 3808bdfc5daSXin Ji int ret; 3818bdfc5daSXin Ji u8 post_divider = 0; 3828bdfc5daSXin Ji 3838bdfc5daSXin Ji ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 3848bdfc5daSXin Ji &m, &n, &post_divider); 3858bdfc5daSXin Ji 3868bdfc5daSXin Ji if (ret) { 3878bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 3888bdfc5daSXin Ji return ret; 3898bdfc5daSXin Ji } 3908bdfc5daSXin Ji 3918bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 3928bdfc5daSXin Ji m, n, post_divider); 3938bdfc5daSXin Ji 3948bdfc5daSXin Ji /* Configure pixel clock */ 3958bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 3968bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) & 0xFF); 3978bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 3988bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) >> 8); 3998bdfc5daSXin Ji /* Lane count */ 4008bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4018bdfc5daSXin Ji MIPI_LANE_CTRL_0, 0xfc); 4028bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 403*fd0310b6SXin Ji MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 4048bdfc5daSXin Ji 4058bdfc5daSXin Ji /* Htotal */ 4068bdfc5daSXin Ji htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 4078bdfc5daSXin Ji ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 4088bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4098bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 4108bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4118bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 4128bdfc5daSXin Ji /* Hactive */ 4138bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4148bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 4158bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4168bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 4178bdfc5daSXin Ji /* HFP */ 4188bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4198bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 4208bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4218bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_H, 4228bdfc5daSXin Ji ctx->dt.hfront_porch.min >> 8); 4238bdfc5daSXin Ji /* HWS */ 4248bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4258bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 4268bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4278bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 4288bdfc5daSXin Ji /* HBP */ 4298bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4308bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 4318bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4328bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 4338bdfc5daSXin Ji /* Vactive */ 4348bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 4358bdfc5daSXin Ji ctx->dt.vactive.min); 4368bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 4378bdfc5daSXin Ji ctx->dt.vactive.min >> 8); 4388bdfc5daSXin Ji /* VFP */ 4398bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4408bdfc5daSXin Ji VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 4418bdfc5daSXin Ji /* VWS */ 4428bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4438bdfc5daSXin Ji VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 4448bdfc5daSXin Ji /* VBP */ 4458bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4468bdfc5daSXin Ji VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 4478bdfc5daSXin Ji /* M value */ 4488bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4498bdfc5daSXin Ji MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 4508bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4518bdfc5daSXin Ji MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 4528bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4538bdfc5daSXin Ji MIPI_PLL_M_NUM_7_0, (m & 0xff)); 4548bdfc5daSXin Ji /* N value */ 4558bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4568bdfc5daSXin Ji MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 4578bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4588bdfc5daSXin Ji MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 4598bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 4608bdfc5daSXin Ji (n & 0xff)); 4617d066dc7SXin Ji 4627d066dc7SXin Ji anx7625_set_k_value(ctx); 4638bdfc5daSXin Ji 4648bdfc5daSXin Ji ret |= anx7625_odfc_config(ctx, post_divider - 1); 4658bdfc5daSXin Ji 4668bdfc5daSXin Ji if (ret < 0) 4678bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 4688bdfc5daSXin Ji 4698bdfc5daSXin Ji return ret; 4708bdfc5daSXin Ji } 4718bdfc5daSXin Ji 4728bdfc5daSXin Ji static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 4738bdfc5daSXin Ji { 4748bdfc5daSXin Ji int val; 4758bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4768bdfc5daSXin Ji 4778bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 4788bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 4798bdfc5daSXin Ji if (val < 0) { 4808bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 4818bdfc5daSXin Ji return -EIO; 4828bdfc5daSXin Ji } 4838bdfc5daSXin Ji 4848bdfc5daSXin Ji val |= (1 << MIPI_SWAP_CH3); 4858bdfc5daSXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 4868bdfc5daSXin Ji } 4878bdfc5daSXin Ji 4888bdfc5daSXin Ji static int anx7625_api_dsi_config(struct anx7625_data *ctx) 4898bdfc5daSXin Ji 4908bdfc5daSXin Ji { 4918bdfc5daSXin Ji int val, ret; 4928bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4938bdfc5daSXin Ji 4948bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 4958bdfc5daSXin Ji ret = anx7625_swap_dsi_lane3(ctx); 4968bdfc5daSXin Ji if (ret < 0) { 4978bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 4988bdfc5daSXin Ji return ret; 4998bdfc5daSXin Ji } 5008bdfc5daSXin Ji 5018bdfc5daSXin Ji /* DSI clock settings */ 5028bdfc5daSXin Ji val = (0 << MIPI_HS_PWD_CLK) | 5038bdfc5daSXin Ji (0 << MIPI_HS_RT_CLK) | 5048bdfc5daSXin Ji (0 << MIPI_PD_CLK) | 5058bdfc5daSXin Ji (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 5068bdfc5daSXin Ji (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 5078bdfc5daSXin Ji (0 << MIPI_CLK_DET_DET_BYPASS) | 5088bdfc5daSXin Ji (0 << MIPI_CLK_MISS_CTRL) | 5098bdfc5daSXin Ji (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 5108bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5118bdfc5daSXin Ji MIPI_PHY_CONTROL_3, val); 5128bdfc5daSXin Ji 5138bdfc5daSXin Ji /* 5148bdfc5daSXin Ji * Decreased HS prepare timing delay from 160ns to 80ns work with 5158bdfc5daSXin Ji * a) Dragon board 810 series (Qualcomm AP) 5168bdfc5daSXin Ji * b) Moving Pixel DSI source (PG3A pattern generator + 5178bdfc5daSXin Ji * P332 D-PHY Probe) default D-PHY timing 5188bdfc5daSXin Ji * 5ns/step 5198bdfc5daSXin Ji */ 5208bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5218bdfc5daSXin Ji MIPI_TIME_HS_PRPR, 0x10); 5228bdfc5daSXin Ji 5238bdfc5daSXin Ji /* Enable DSI mode*/ 5248bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 5258bdfc5daSXin Ji SELECT_DSI << MIPI_DPI_SELECT); 5268bdfc5daSXin Ji 5278bdfc5daSXin Ji ret |= anx7625_dsi_video_timing_config(ctx); 5288bdfc5daSXin Ji if (ret < 0) { 5298bdfc5daSXin Ji DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 5308bdfc5daSXin Ji return ret; 5318bdfc5daSXin Ji } 5328bdfc5daSXin Ji 5338bdfc5daSXin Ji /* Toggle m, n ready */ 5348bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 5358bdfc5daSXin Ji ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 5368bdfc5daSXin Ji usleep_range(1000, 1100); 5378bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 5388bdfc5daSXin Ji MIPI_M_NUM_READY | MIPI_N_NUM_READY); 5398bdfc5daSXin Ji 5408bdfc5daSXin Ji /* Configure integer stable register */ 5418bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5428bdfc5daSXin Ji MIPI_VIDEO_STABLE_CNT, 0x02); 5438bdfc5daSXin Ji /* Power on MIPI RX */ 5448bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5458bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x00); 5468bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5478bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x80); 5488bdfc5daSXin Ji 5498bdfc5daSXin Ji if (ret < 0) 5508bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 5518bdfc5daSXin Ji 5528bdfc5daSXin Ji return ret; 5538bdfc5daSXin Ji } 5548bdfc5daSXin Ji 5558bdfc5daSXin Ji static int anx7625_dsi_config(struct anx7625_data *ctx) 5568bdfc5daSXin Ji { 5578bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5588bdfc5daSXin Ji int ret; 5598bdfc5daSXin Ji 5608bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 5618bdfc5daSXin Ji 5628bdfc5daSXin Ji /* DSC disable */ 5638bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 5648bdfc5daSXin Ji R_DSC_CTRL_0, ~DSC_EN); 5658bdfc5daSXin Ji 5668bdfc5daSXin Ji ret |= anx7625_api_dsi_config(ctx); 5678bdfc5daSXin Ji 5688bdfc5daSXin Ji if (ret < 0) { 5698bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 5708bdfc5daSXin Ji return ret; 5718bdfc5daSXin Ji } 5728bdfc5daSXin Ji 5738bdfc5daSXin Ji /* Set MIPI RX EN */ 5748bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 5758bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 5768bdfc5daSXin Ji /* Clear mute flag */ 5778bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 5788bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 5798bdfc5daSXin Ji if (ret < 0) 5808bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 5818bdfc5daSXin Ji else 5828bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 5838bdfc5daSXin Ji 5848bdfc5daSXin Ji return ret; 5858bdfc5daSXin Ji } 5868bdfc5daSXin Ji 587*fd0310b6SXin Ji static int anx7625_api_dpi_config(struct anx7625_data *ctx) 588*fd0310b6SXin Ji { 589*fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 590*fd0310b6SXin Ji u16 freq = ctx->dt.pixelclock.min / 1000; 591*fd0310b6SXin Ji int ret; 592*fd0310b6SXin Ji 593*fd0310b6SXin Ji /* configure pixel clock */ 594*fd0310b6SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 595*fd0310b6SXin Ji PIXEL_CLOCK_L, freq & 0xFF); 596*fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 597*fd0310b6SXin Ji PIXEL_CLOCK_H, (freq >> 8)); 598*fd0310b6SXin Ji 599*fd0310b6SXin Ji /* set DPI mode */ 600*fd0310b6SXin Ji /* set to DPI PLL module sel */ 601*fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 602*fd0310b6SXin Ji MIPI_DIGITAL_PLL_9, 0x20); 603*fd0310b6SXin Ji /* power down MIPI */ 604*fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 605*fd0310b6SXin Ji MIPI_LANE_CTRL_10, 0x08); 606*fd0310b6SXin Ji /* enable DPI mode */ 607*fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 608*fd0310b6SXin Ji MIPI_DIGITAL_PLL_18, 0x1C); 609*fd0310b6SXin Ji /* set first edge */ 610*fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 611*fd0310b6SXin Ji VIDEO_CONTROL_0, 0x06); 612*fd0310b6SXin Ji if (ret < 0) 613*fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 614*fd0310b6SXin Ji 615*fd0310b6SXin Ji return ret; 616*fd0310b6SXin Ji } 617*fd0310b6SXin Ji 618*fd0310b6SXin Ji static int anx7625_dpi_config(struct anx7625_data *ctx) 619*fd0310b6SXin Ji { 620*fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 621*fd0310b6SXin Ji int ret; 622*fd0310b6SXin Ji 623*fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 624*fd0310b6SXin Ji 625*fd0310b6SXin Ji /* DSC disable */ 626*fd0310b6SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 627*fd0310b6SXin Ji R_DSC_CTRL_0, ~DSC_EN); 628*fd0310b6SXin Ji if (ret < 0) { 629*fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 630*fd0310b6SXin Ji return ret; 631*fd0310b6SXin Ji } 632*fd0310b6SXin Ji 633*fd0310b6SXin Ji ret = anx7625_config_bit_matrix(ctx); 634*fd0310b6SXin Ji if (ret < 0) { 635*fd0310b6SXin Ji DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 636*fd0310b6SXin Ji return ret; 637*fd0310b6SXin Ji } 638*fd0310b6SXin Ji 639*fd0310b6SXin Ji ret = anx7625_api_dpi_config(ctx); 640*fd0310b6SXin Ji if (ret < 0) { 641*fd0310b6SXin Ji DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 642*fd0310b6SXin Ji return ret; 643*fd0310b6SXin Ji } 644*fd0310b6SXin Ji 645*fd0310b6SXin Ji /* set MIPI RX EN */ 646*fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 647*fd0310b6SXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 648*fd0310b6SXin Ji /* clear mute flag */ 649*fd0310b6SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 650*fd0310b6SXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 651*fd0310b6SXin Ji if (ret < 0) 652*fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 653*fd0310b6SXin Ji 654*fd0310b6SXin Ji return ret; 655*fd0310b6SXin Ji } 656*fd0310b6SXin Ji 6578bdfc5daSXin Ji static void anx7625_dp_start(struct anx7625_data *ctx) 6588bdfc5daSXin Ji { 6598bdfc5daSXin Ji int ret; 6608bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6618bdfc5daSXin Ji 6628bdfc5daSXin Ji if (!ctx->display_timing_valid) { 6638bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 6648bdfc5daSXin Ji return; 6658bdfc5daSXin Ji } 6668bdfc5daSXin Ji 667*fd0310b6SXin Ji if (ctx->pdata.is_dpi) 668*fd0310b6SXin Ji ret = anx7625_dpi_config(ctx); 669*fd0310b6SXin Ji else 6708bdfc5daSXin Ji ret = anx7625_dsi_config(ctx); 6718bdfc5daSXin Ji 6728bdfc5daSXin Ji if (ret < 0) 6738bdfc5daSXin Ji DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 6748bdfc5daSXin Ji } 6758bdfc5daSXin Ji 6768bdfc5daSXin Ji static void anx7625_dp_stop(struct anx7625_data *ctx) 6778bdfc5daSXin Ji { 6788bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6798bdfc5daSXin Ji int ret; 6808bdfc5daSXin Ji 6818bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 6828bdfc5daSXin Ji 6838bdfc5daSXin Ji /* 6848bdfc5daSXin Ji * Video disable: 0x72:08 bit 7 = 0; 6858bdfc5daSXin Ji * Audio disable: 0x70:87 bit 0 = 0; 6868bdfc5daSXin Ji */ 6878bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 6888bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 6898bdfc5daSXin Ji 6908bdfc5daSXin Ji ret |= anx7625_video_mute_control(ctx, 1); 6918bdfc5daSXin Ji if (ret < 0) 6928bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 6938bdfc5daSXin Ji } 6948bdfc5daSXin Ji 6958bdfc5daSXin Ji static int sp_tx_rst_aux(struct anx7625_data *ctx) 6968bdfc5daSXin Ji { 6978bdfc5daSXin Ji int ret; 6988bdfc5daSXin Ji 6998bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 7008bdfc5daSXin Ji AUX_RST); 7018bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 7028bdfc5daSXin Ji ~AUX_RST); 7038bdfc5daSXin Ji return ret; 7048bdfc5daSXin Ji } 7058bdfc5daSXin Ji 7068bdfc5daSXin Ji static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 7078bdfc5daSXin Ji { 7088bdfc5daSXin Ji int ret; 7098bdfc5daSXin Ji 7108bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7118bdfc5daSXin Ji AP_AUX_BUFF_START, offset); 7128bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7138bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 7148bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 7158bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 7168bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 7178bdfc5daSXin Ji } 7188bdfc5daSXin Ji 7198bdfc5daSXin Ji static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 7208bdfc5daSXin Ji { 7218bdfc5daSXin Ji int ret; 7228bdfc5daSXin Ji 7238bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7248bdfc5daSXin Ji AP_AUX_COMMAND, len_cmd); 7258bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 7268bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 7278bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 7288bdfc5daSXin Ji } 7298bdfc5daSXin Ji 7308bdfc5daSXin Ji static int sp_tx_get_edid_block(struct anx7625_data *ctx) 7318bdfc5daSXin Ji { 7328bdfc5daSXin Ji int c = 0; 7338bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 7348bdfc5daSXin Ji 7358bdfc5daSXin Ji sp_tx_aux_wr(ctx, 0x7e); 7368bdfc5daSXin Ji sp_tx_aux_rd(ctx, 0x01); 7378bdfc5daSXin Ji c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 7388bdfc5daSXin Ji if (c < 0) { 7398bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 7408bdfc5daSXin Ji return -EIO; 7418bdfc5daSXin Ji } 7428bdfc5daSXin Ji 7438bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 7448bdfc5daSXin Ji 7458bdfc5daSXin Ji if (c > MAX_EDID_BLOCK) 7468bdfc5daSXin Ji c = 1; 7478bdfc5daSXin Ji 7488bdfc5daSXin Ji return c; 7498bdfc5daSXin Ji } 7508bdfc5daSXin Ji 7518bdfc5daSXin Ji static int edid_read(struct anx7625_data *ctx, 7528bdfc5daSXin Ji u8 offset, u8 *pblock_buf) 7538bdfc5daSXin Ji { 7548bdfc5daSXin Ji int ret, cnt; 7558bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 7568bdfc5daSXin Ji 7578bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 7588bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 7598bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 7608bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 7618bdfc5daSXin Ji 7628bdfc5daSXin Ji if (ret) { 7637f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 7648bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 7658bdfc5daSXin Ji } else { 7668bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 7678bdfc5daSXin Ji AP_AUX_BUFF_START, 7688bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, 7698bdfc5daSXin Ji pblock_buf); 7708bdfc5daSXin Ji if (ret > 0) 7718bdfc5daSXin Ji break; 7728bdfc5daSXin Ji } 7738bdfc5daSXin Ji } 7748bdfc5daSXin Ji 7758bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 7768bdfc5daSXin Ji return -EIO; 7778bdfc5daSXin Ji 7787f16d0f3SRobert Foss return ret; 7798bdfc5daSXin Ji } 7808bdfc5daSXin Ji 7818bdfc5daSXin Ji static int segments_edid_read(struct anx7625_data *ctx, 7828bdfc5daSXin Ji u8 segment, u8 *buf, u8 offset) 7838bdfc5daSXin Ji { 7848bdfc5daSXin Ji u8 cnt; 7858bdfc5daSXin Ji int ret; 7868bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 7878bdfc5daSXin Ji 7888bdfc5daSXin Ji /* Write address only */ 7898bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7908bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x30); 7918bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7928bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 7938bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7948bdfc5daSXin Ji AP_AUX_CTRL_STATUS, 7958bdfc5daSXin Ji AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 7968bdfc5daSXin Ji 7978bdfc5daSXin Ji ret |= wait_aux_op_finish(ctx); 7988bdfc5daSXin Ji /* Write segment address */ 7998bdfc5daSXin Ji ret |= sp_tx_aux_wr(ctx, segment); 8008bdfc5daSXin Ji /* Data read */ 8018bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8028bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 8038bdfc5daSXin Ji if (ret) { 8048bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 8058bdfc5daSXin Ji return ret; 8068bdfc5daSXin Ji } 8078bdfc5daSXin Ji 8088bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 8098bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 8108bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 8118bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 8128bdfc5daSXin Ji 8138bdfc5daSXin Ji if (ret) { 8148bdfc5daSXin Ji ret = sp_tx_rst_aux(ctx); 8158bdfc5daSXin Ji DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 8168bdfc5daSXin Ji } else { 8178bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 8188bdfc5daSXin Ji AP_AUX_BUFF_START, 8198bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, buf); 8208bdfc5daSXin Ji if (ret > 0) 8218bdfc5daSXin Ji break; 8228bdfc5daSXin Ji } 8238bdfc5daSXin Ji } 8248bdfc5daSXin Ji 8258bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 8268bdfc5daSXin Ji return -EIO; 8278bdfc5daSXin Ji 8287f16d0f3SRobert Foss return ret; 8298bdfc5daSXin Ji } 8308bdfc5daSXin Ji 8318bdfc5daSXin Ji static int sp_tx_edid_read(struct anx7625_data *ctx, 8328bdfc5daSXin Ji u8 *pedid_blocks_buf) 8338bdfc5daSXin Ji { 8348bdfc5daSXin Ji u8 offset, edid_pos; 8358bdfc5daSXin Ji int count, blocks_num; 8368bdfc5daSXin Ji u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 8378bdfc5daSXin Ji u8 i, j; 8388bdfc5daSXin Ji u8 g_edid_break = 0; 8398bdfc5daSXin Ji int ret; 8408bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 8418bdfc5daSXin Ji 8428bdfc5daSXin Ji /* Address initial */ 8438bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8448bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 8458bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8468bdfc5daSXin Ji AP_AUX_ADDR_15_8, 0); 8478bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 8488bdfc5daSXin Ji AP_AUX_ADDR_19_16, 0xf0); 8498bdfc5daSXin Ji if (ret < 0) { 8508bdfc5daSXin Ji DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 8518bdfc5daSXin Ji return -EIO; 8528bdfc5daSXin Ji } 8538bdfc5daSXin Ji 8548bdfc5daSXin Ji blocks_num = sp_tx_get_edid_block(ctx); 8558bdfc5daSXin Ji if (blocks_num < 0) 8568bdfc5daSXin Ji return blocks_num; 8578bdfc5daSXin Ji 8588bdfc5daSXin Ji count = 0; 8598bdfc5daSXin Ji 8608bdfc5daSXin Ji do { 8618bdfc5daSXin Ji switch (count) { 8628bdfc5daSXin Ji case 0: 8638bdfc5daSXin Ji case 1: 8648bdfc5daSXin Ji for (i = 0; i < 8; i++) { 8658bdfc5daSXin Ji offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 8668bdfc5daSXin Ji g_edid_break = edid_read(ctx, offset, 8678bdfc5daSXin Ji pblock_buf); 8688bdfc5daSXin Ji 8698bdfc5daSXin Ji if (g_edid_break) 8708bdfc5daSXin Ji break; 8718bdfc5daSXin Ji 8728bdfc5daSXin Ji memcpy(&pedid_blocks_buf[offset], 8738bdfc5daSXin Ji pblock_buf, 8748bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 8758bdfc5daSXin Ji } 8768bdfc5daSXin Ji 8778bdfc5daSXin Ji break; 8788bdfc5daSXin Ji case 2: 8798bdfc5daSXin Ji offset = 0x00; 8808bdfc5daSXin Ji 8818bdfc5daSXin Ji for (j = 0; j < 8; j++) { 8828bdfc5daSXin Ji edid_pos = (j + count * 8) * 8838bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 8848bdfc5daSXin Ji 8858bdfc5daSXin Ji if (g_edid_break == 1) 8868bdfc5daSXin Ji break; 8878bdfc5daSXin Ji 888a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 8898bdfc5daSXin Ji pblock_buf, offset); 890a23e0a2aSRobert Foss if (ret < 0) 891a23e0a2aSRobert Foss return ret; 892a23e0a2aSRobert Foss 8938bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 8948bdfc5daSXin Ji pblock_buf, 8958bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 8968bdfc5daSXin Ji offset = offset + 0x10; 8978bdfc5daSXin Ji } 8988bdfc5daSXin Ji 8998bdfc5daSXin Ji break; 9008bdfc5daSXin Ji case 3: 9018bdfc5daSXin Ji offset = 0x80; 9028bdfc5daSXin Ji 9038bdfc5daSXin Ji for (j = 0; j < 8; j++) { 9048bdfc5daSXin Ji edid_pos = (j + count * 8) * 9058bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 9068bdfc5daSXin Ji if (g_edid_break == 1) 9078bdfc5daSXin Ji break; 9088bdfc5daSXin Ji 909a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 9108bdfc5daSXin Ji pblock_buf, offset); 911a23e0a2aSRobert Foss if (ret < 0) 912a23e0a2aSRobert Foss return ret; 913a23e0a2aSRobert Foss 9148bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 9158bdfc5daSXin Ji pblock_buf, 9168bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 9178bdfc5daSXin Ji offset = offset + 0x10; 9188bdfc5daSXin Ji } 9198bdfc5daSXin Ji 9208bdfc5daSXin Ji break; 9218bdfc5daSXin Ji default: 9228bdfc5daSXin Ji break; 9238bdfc5daSXin Ji } 9248bdfc5daSXin Ji 9258bdfc5daSXin Ji count++; 9268bdfc5daSXin Ji 9278bdfc5daSXin Ji } while (blocks_num >= count); 9288bdfc5daSXin Ji 9298bdfc5daSXin Ji /* Check edid data */ 9308bdfc5daSXin Ji if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 9318bdfc5daSXin Ji DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 9328bdfc5daSXin Ji return -EINVAL; 9338bdfc5daSXin Ji } 9348bdfc5daSXin Ji 9358bdfc5daSXin Ji /* Reset aux channel */ 9367f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 9377f16d0f3SRobert Foss if (ret < 0) { 9387f16d0f3SRobert Foss DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 9397f16d0f3SRobert Foss return ret; 9407f16d0f3SRobert Foss } 9418bdfc5daSXin Ji 9428bdfc5daSXin Ji return (blocks_num + 1); 9438bdfc5daSXin Ji } 9448bdfc5daSXin Ji 9458bdfc5daSXin Ji static void anx7625_power_on(struct anx7625_data *ctx) 9468bdfc5daSXin Ji { 9478bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9486c744983SHsin-Yi Wang int ret, i; 9498bdfc5daSXin Ji 9508bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 9518bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 9528bdfc5daSXin Ji return; 9538bdfc5daSXin Ji } 9548bdfc5daSXin Ji 9556c744983SHsin-Yi Wang for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 9566c744983SHsin-Yi Wang ret = regulator_enable(ctx->pdata.supplies[i].consumer); 9576c744983SHsin-Yi Wang if (ret < 0) { 9586c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 9596c744983SHsin-Yi Wang i, ret); 9606c744983SHsin-Yi Wang goto reg_err; 9616c744983SHsin-Yi Wang } 9626c744983SHsin-Yi Wang usleep_range(2000, 2100); 9636c744983SHsin-Yi Wang } 9646c744983SHsin-Yi Wang 9651fcf24fbSHsin-Yi Wang usleep_range(11000, 12000); 9666c744983SHsin-Yi Wang 9678bdfc5daSXin Ji /* Power on pin enable */ 9688bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 1); 9698bdfc5daSXin Ji usleep_range(10000, 11000); 9708bdfc5daSXin Ji /* Power reset pin enable */ 9718bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 1); 9728bdfc5daSXin Ji usleep_range(10000, 11000); 9738bdfc5daSXin Ji 9748bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 9756c744983SHsin-Yi Wang return; 9766c744983SHsin-Yi Wang reg_err: 9776c744983SHsin-Yi Wang for (--i; i >= 0; i--) 9786c744983SHsin-Yi Wang regulator_disable(ctx->pdata.supplies[i].consumer); 9798bdfc5daSXin Ji } 9808bdfc5daSXin Ji 9818bdfc5daSXin Ji static void anx7625_power_standby(struct anx7625_data *ctx) 9828bdfc5daSXin Ji { 9838bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9846c744983SHsin-Yi Wang int ret; 9858bdfc5daSXin Ji 9868bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 9878bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 9888bdfc5daSXin Ji return; 9898bdfc5daSXin Ji } 9908bdfc5daSXin Ji 9918bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 0); 9928bdfc5daSXin Ji usleep_range(1000, 1100); 9938bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 0); 9948bdfc5daSXin Ji usleep_range(1000, 1100); 9956c744983SHsin-Yi Wang 9966c744983SHsin-Yi Wang ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 9976c744983SHsin-Yi Wang ctx->pdata.supplies); 9986c744983SHsin-Yi Wang if (ret < 0) 9996c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 10006c744983SHsin-Yi Wang 10018bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 10028bdfc5daSXin Ji } 10038bdfc5daSXin Ji 10048bdfc5daSXin Ji /* Basic configurations of ANX7625 */ 10058bdfc5daSXin Ji static void anx7625_config(struct anx7625_data *ctx) 10068bdfc5daSXin Ji { 10078bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10088bdfc5daSXin Ji XTAL_FRQ_SEL, XTAL_FRQ_27M); 10098bdfc5daSXin Ji } 10108bdfc5daSXin Ji 10118bdfc5daSXin Ji static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 10128bdfc5daSXin Ji { 10138bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10148bdfc5daSXin Ji int ret; 10158bdfc5daSXin Ji 10168bdfc5daSXin Ji /* Reset main ocm */ 10178bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 10188bdfc5daSXin Ji /* Disable PD */ 10198bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10208bdfc5daSXin Ji AP_AV_STATUS, AP_DISABLE_PD); 10218bdfc5daSXin Ji /* Release main ocm */ 10228bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 10238bdfc5daSXin Ji 10248bdfc5daSXin Ji if (ret < 0) 10258bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 10268bdfc5daSXin Ji else 10278bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 10288bdfc5daSXin Ji } 10298bdfc5daSXin Ji 10308bdfc5daSXin Ji static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 10318bdfc5daSXin Ji { 10328bdfc5daSXin Ji int ret; 10338bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10348bdfc5daSXin Ji 10358bdfc5daSXin Ji /* Check interface workable */ 10368bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 10378bdfc5daSXin Ji FLASH_LOAD_STA); 10388bdfc5daSXin Ji if (ret < 0) { 10398bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 10408bdfc5daSXin Ji return ret; 10418bdfc5daSXin Ji } 10428bdfc5daSXin Ji if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 10438bdfc5daSXin Ji return -ENODEV; 10448bdfc5daSXin Ji 10458bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 10468bdfc5daSXin Ji 10478bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 10488bdfc5daSXin Ji anx7625_reg_read(ctx, 10498bdfc5daSXin Ji ctx->i2c.rx_p0_client, 10508bdfc5daSXin Ji OCM_FW_VERSION), 10518bdfc5daSXin Ji anx7625_reg_read(ctx, 10528bdfc5daSXin Ji ctx->i2c.rx_p0_client, 10538bdfc5daSXin Ji OCM_FW_REVERSION)); 10548bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 10558bdfc5daSXin Ji ANX7625_DRV_VERSION); 10568bdfc5daSXin Ji 10578bdfc5daSXin Ji return 0; 10588bdfc5daSXin Ji } 10598bdfc5daSXin Ji 10608bdfc5daSXin Ji static void anx7625_power_on_init(struct anx7625_data *ctx) 10618bdfc5daSXin Ji { 10628bdfc5daSXin Ji int retry_count, i; 10638bdfc5daSXin Ji 10648bdfc5daSXin Ji for (retry_count = 0; retry_count < 3; retry_count++) { 10658bdfc5daSXin Ji anx7625_power_on(ctx); 10668bdfc5daSXin Ji anx7625_config(ctx); 10678bdfc5daSXin Ji 10688bdfc5daSXin Ji for (i = 0; i < OCM_LOADING_TIME; i++) { 10698bdfc5daSXin Ji if (!anx7625_ocm_loading_check(ctx)) 10708bdfc5daSXin Ji return; 10718bdfc5daSXin Ji usleep_range(1000, 1100); 10728bdfc5daSXin Ji } 10738bdfc5daSXin Ji anx7625_power_standby(ctx); 10748bdfc5daSXin Ji } 10758bdfc5daSXin Ji } 10768bdfc5daSXin Ji 10778bdfc5daSXin Ji static void anx7625_init_gpio(struct anx7625_data *platform) 10788bdfc5daSXin Ji { 10798bdfc5daSXin Ji struct device *dev = &platform->client->dev; 10808bdfc5daSXin Ji 10818bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 10828bdfc5daSXin Ji 10838bdfc5daSXin Ji /* Gpio for chip power enable */ 10848bdfc5daSXin Ji platform->pdata.gpio_p_on = 10858bdfc5daSXin Ji devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 10868bdfc5daSXin Ji /* Gpio for chip reset */ 10878bdfc5daSXin Ji platform->pdata.gpio_reset = 10888bdfc5daSXin Ji devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 10898bdfc5daSXin Ji 10908bdfc5daSXin Ji if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 10918bdfc5daSXin Ji platform->pdata.low_power_mode = 1; 10928bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 10938bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_p_on), 10948bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_reset)); 10958bdfc5daSXin Ji } else { 10968bdfc5daSXin Ji platform->pdata.low_power_mode = 0; 10978bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 10988bdfc5daSXin Ji } 10998bdfc5daSXin Ji } 11008bdfc5daSXin Ji 11018bdfc5daSXin Ji static void anx7625_stop_dp_work(struct anx7625_data *ctx) 11028bdfc5daSXin Ji { 11038bdfc5daSXin Ji ctx->hpd_status = 0; 11048bdfc5daSXin Ji ctx->hpd_high_cnt = 0; 11058bdfc5daSXin Ji ctx->display_timing_valid = 0; 11068bdfc5daSXin Ji } 11078bdfc5daSXin Ji 11088bdfc5daSXin Ji static void anx7625_start_dp_work(struct anx7625_data *ctx) 11098bdfc5daSXin Ji { 11108bdfc5daSXin Ji int ret; 11118bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11128bdfc5daSXin Ji 11138bdfc5daSXin Ji if (ctx->hpd_high_cnt >= 2) { 11148bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 11158bdfc5daSXin Ji return; 11168bdfc5daSXin Ji } 11178bdfc5daSXin Ji 1118*fd0310b6SXin Ji ctx->hpd_status = 1; 11198bdfc5daSXin Ji ctx->hpd_high_cnt++; 11208bdfc5daSXin Ji 11218bdfc5daSXin Ji /* Not support HDCP */ 11228bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 11238bdfc5daSXin Ji 11248bdfc5daSXin Ji /* Try auth flag */ 11258bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 11268bdfc5daSXin Ji /* Interrupt for DRM */ 11278bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1128*fd0310b6SXin Ji if (ret < 0) { 1129*fd0310b6SXin Ji DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 11308bdfc5daSXin Ji return; 1131*fd0310b6SXin Ji } 11328bdfc5daSXin Ji 11338bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 11348bdfc5daSXin Ji if (ret < 0) 11358bdfc5daSXin Ji return; 11368bdfc5daSXin Ji 11378bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 11388bdfc5daSXin Ji } 11398bdfc5daSXin Ji 11408bdfc5daSXin Ji static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 11418bdfc5daSXin Ji { 11428bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 11438bdfc5daSXin Ji } 11448bdfc5daSXin Ji 11458bdfc5daSXin Ji static void anx7625_hpd_polling(struct anx7625_data *ctx) 11468bdfc5daSXin Ji { 11478bdfc5daSXin Ji int ret, val; 11488bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11498bdfc5daSXin Ji 1150*fd0310b6SXin Ji /* Interrupt mode, no need poll HPD status, just return */ 1151*fd0310b6SXin Ji if (ctx->pdata.intp_irq) 1152*fd0310b6SXin Ji return; 1153*fd0310b6SXin Ji 11548bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 11558bdfc5daSXin Ji ctx, val, 11568bdfc5daSXin Ji ((val & HPD_STATUS) || (val < 0)), 11578bdfc5daSXin Ji 5000, 11588bdfc5daSXin Ji 5000 * 100); 11598bdfc5daSXin Ji if (ret) { 116060487584SPi-Hsun Shih DRM_DEV_ERROR(dev, "no hpd.\n"); 116160487584SPi-Hsun Shih return; 116260487584SPi-Hsun Shih } 116360487584SPi-Hsun Shih 116460487584SPi-Hsun Shih DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 11658bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 11668bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 11678bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11688bdfc5daSXin Ji INTERFACE_CHANGE_INT, 0); 11698bdfc5daSXin Ji 11708bdfc5daSXin Ji anx7625_start_dp_work(ctx); 11718bdfc5daSXin Ji 117260487584SPi-Hsun Shih if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 117360487584SPi-Hsun Shih drm_helper_hpd_irq_event(ctx->bridge.dev); 11748bdfc5daSXin Ji } 11758bdfc5daSXin Ji 11768bdfc5daSXin Ji static void anx7625_remove_edid(struct anx7625_data *ctx) 11778bdfc5daSXin Ji { 11788bdfc5daSXin Ji ctx->slimport_edid_p.edid_block_num = -1; 11798bdfc5daSXin Ji } 11808bdfc5daSXin Ji 1181*fd0310b6SXin Ji static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1182*fd0310b6SXin Ji { 1183*fd0310b6SXin Ji int i; 1184*fd0310b6SXin Ji 1185*fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1186*fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1187*fd0310b6SXin Ji DP_TX_LANE0_SWING_REG0 + i, 1188*fd0310b6SXin Ji ctx->pdata.lane0_reg_data[i] & 0xFF); 1189*fd0310b6SXin Ji 1190*fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1191*fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1192*fd0310b6SXin Ji DP_TX_LANE1_SWING_REG0 + i, 1193*fd0310b6SXin Ji ctx->pdata.lane1_reg_data[i] & 0xFF); 1194*fd0310b6SXin Ji } 1195*fd0310b6SXin Ji 11968bdfc5daSXin Ji static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 11978bdfc5daSXin Ji { 11988bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11998bdfc5daSXin Ji 12008bdfc5daSXin Ji /* HPD changed */ 12018bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 12028bdfc5daSXin Ji (u32)on); 12038bdfc5daSXin Ji 12048bdfc5daSXin Ji if (on == 0) { 12058bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 12068bdfc5daSXin Ji anx7625_remove_edid(ctx); 12078bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 12088bdfc5daSXin Ji } else { 12098bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 12108bdfc5daSXin Ji anx7625_start_dp_work(ctx); 1211*fd0310b6SXin Ji anx7625_dp_adjust_swing(ctx); 12128bdfc5daSXin Ji } 12138bdfc5daSXin Ji } 12148bdfc5daSXin Ji 12158bdfc5daSXin Ji static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 12168bdfc5daSXin Ji { 12178bdfc5daSXin Ji int intr_vector, status; 12188bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12198bdfc5daSXin Ji 12208bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 12218bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 12228bdfc5daSXin Ji if (status < 0) { 12238bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 12248bdfc5daSXin Ji return status; 12258bdfc5daSXin Ji } 12268bdfc5daSXin Ji 12278bdfc5daSXin Ji intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 12288bdfc5daSXin Ji INTERFACE_CHANGE_INT); 12298bdfc5daSXin Ji if (intr_vector < 0) { 12308bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 12318bdfc5daSXin Ji return intr_vector; 12328bdfc5daSXin Ji } 12338bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 12348bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12358bdfc5daSXin Ji INTERFACE_CHANGE_INT, 12368bdfc5daSXin Ji intr_vector & (~intr_vector)); 12378bdfc5daSXin Ji if (status < 0) { 12388bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 12398bdfc5daSXin Ji return status; 12408bdfc5daSXin Ji } 12418bdfc5daSXin Ji 12428bdfc5daSXin Ji if (!(intr_vector & HPD_STATUS_CHANGE)) 12438bdfc5daSXin Ji return -ENOENT; 12448bdfc5daSXin Ji 12458bdfc5daSXin Ji status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 12468bdfc5daSXin Ji SYSTEM_STSTUS); 12478bdfc5daSXin Ji if (status < 0) { 12488bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 12498bdfc5daSXin Ji return status; 12508bdfc5daSXin Ji } 12518bdfc5daSXin Ji 12528bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 12538bdfc5daSXin Ji dp_hpd_change_handler(ctx, status & HPD_STATUS); 12548bdfc5daSXin Ji 12558bdfc5daSXin Ji return 0; 12568bdfc5daSXin Ji } 12578bdfc5daSXin Ji 12588bdfc5daSXin Ji static void anx7625_work_func(struct work_struct *work) 12598bdfc5daSXin Ji { 12608bdfc5daSXin Ji int event; 12618bdfc5daSXin Ji struct anx7625_data *ctx = container_of(work, 12628bdfc5daSXin Ji struct anx7625_data, work); 12638bdfc5daSXin Ji 12648bdfc5daSXin Ji mutex_lock(&ctx->lock); 126560487584SPi-Hsun Shih 126660487584SPi-Hsun Shih if (pm_runtime_suspended(&ctx->client->dev)) 126760487584SPi-Hsun Shih goto unlock; 126860487584SPi-Hsun Shih 12698bdfc5daSXin Ji event = anx7625_hpd_change_detect(ctx); 12708bdfc5daSXin Ji if (event < 0) 127160487584SPi-Hsun Shih goto unlock; 12728bdfc5daSXin Ji 12738bdfc5daSXin Ji if (ctx->bridge_attached) 12748bdfc5daSXin Ji drm_helper_hpd_irq_event(ctx->bridge.dev); 127560487584SPi-Hsun Shih 127660487584SPi-Hsun Shih unlock: 127760487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 12788bdfc5daSXin Ji } 12798bdfc5daSXin Ji 12808bdfc5daSXin Ji static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 12818bdfc5daSXin Ji { 12828bdfc5daSXin Ji struct anx7625_data *ctx = (struct anx7625_data *)data; 12838bdfc5daSXin Ji 12848bdfc5daSXin Ji queue_work(ctx->workqueue, &ctx->work); 12858bdfc5daSXin Ji 12868bdfc5daSXin Ji return IRQ_HANDLED; 12878bdfc5daSXin Ji } 12888bdfc5daSXin Ji 1289*fd0310b6SXin Ji static int anx7625_get_swing_setting(struct device *dev, 1290*fd0310b6SXin Ji struct anx7625_platform_data *pdata) 1291*fd0310b6SXin Ji { 1292*fd0310b6SXin Ji int num_regs; 1293*fd0310b6SXin Ji 1294*fd0310b6SXin Ji if (of_get_property(dev->of_node, 1295*fd0310b6SXin Ji "analogix,lane0-swing", &num_regs)) { 1296*fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1297*fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1298*fd0310b6SXin Ji 1299*fd0310b6SXin Ji pdata->dp_lane0_swing_reg_cnt = num_regs; 1300*fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1301*fd0310b6SXin Ji pdata->lane0_reg_data, num_regs); 1302*fd0310b6SXin Ji } 1303*fd0310b6SXin Ji 1304*fd0310b6SXin Ji if (of_get_property(dev->of_node, 1305*fd0310b6SXin Ji "analogix,lane1-swing", &num_regs)) { 1306*fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1307*fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1308*fd0310b6SXin Ji 1309*fd0310b6SXin Ji pdata->dp_lane1_swing_reg_cnt = num_regs; 1310*fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1311*fd0310b6SXin Ji pdata->lane1_reg_data, num_regs); 1312*fd0310b6SXin Ji } 1313*fd0310b6SXin Ji 1314*fd0310b6SXin Ji return 0; 1315*fd0310b6SXin Ji } 1316*fd0310b6SXin Ji 13178bdfc5daSXin Ji static int anx7625_parse_dt(struct device *dev, 13188bdfc5daSXin Ji struct anx7625_platform_data *pdata) 13198bdfc5daSXin Ji { 1320*fd0310b6SXin Ji struct device_node *np = dev->of_node, *ep0; 13218bdfc5daSXin Ji struct drm_panel *panel; 13228bdfc5daSXin Ji int ret; 1323*fd0310b6SXin Ji int bus_type, mipi_lanes; 13248bdfc5daSXin Ji 1325*fd0310b6SXin Ji anx7625_get_swing_setting(dev, pdata); 1326*fd0310b6SXin Ji 1327*fd0310b6SXin Ji pdata->is_dpi = 1; /* default dpi mode */ 13288bdfc5daSXin Ji pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 13298bdfc5daSXin Ji if (!pdata->mipi_host_node) { 13308bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 13318bdfc5daSXin Ji return -ENODEV; 13328bdfc5daSXin Ji } 13338bdfc5daSXin Ji 1334*fd0310b6SXin Ji bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1335*fd0310b6SXin Ji mipi_lanes = MAX_LANES_SUPPORT; 1336*fd0310b6SXin Ji ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1337*fd0310b6SXin Ji if (ep0) { 1338*fd0310b6SXin Ji if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1339*fd0310b6SXin Ji bus_type = 0; 1340*fd0310b6SXin Ji 1341*fd0310b6SXin Ji mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1342*fd0310b6SXin Ji } 1343*fd0310b6SXin Ji 1344*fd0310b6SXin Ji if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1345*fd0310b6SXin Ji pdata->is_dpi = 0; 1346*fd0310b6SXin Ji 1347*fd0310b6SXin Ji pdata->mipi_lanes = mipi_lanes; 1348*fd0310b6SXin Ji if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1349*fd0310b6SXin Ji pdata->mipi_lanes = MAX_LANES_SUPPORT; 1350*fd0310b6SXin Ji 1351*fd0310b6SXin Ji if (pdata->is_dpi) 1352*fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1353*fd0310b6SXin Ji else 1354*fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 13558bdfc5daSXin Ji 13568bdfc5daSXin Ji ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 13578bdfc5daSXin Ji if (ret < 0) { 13588bdfc5daSXin Ji if (ret == -ENODEV) 13598bdfc5daSXin Ji return 0; 13608bdfc5daSXin Ji return ret; 13618bdfc5daSXin Ji } 13628bdfc5daSXin Ji if (!panel) 13638bdfc5daSXin Ji return -ENODEV; 13648bdfc5daSXin Ji 13658bdfc5daSXin Ji pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 13668bdfc5daSXin Ji if (IS_ERR(pdata->panel_bridge)) 13678bdfc5daSXin Ji return PTR_ERR(pdata->panel_bridge); 13688bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 13698bdfc5daSXin Ji 13708bdfc5daSXin Ji return 0; 13718bdfc5daSXin Ji } 13728bdfc5daSXin Ji 13738bdfc5daSXin Ji static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 13748bdfc5daSXin Ji { 13758bdfc5daSXin Ji return container_of(bridge, struct anx7625_data, bridge); 13768bdfc5daSXin Ji } 13778bdfc5daSXin Ji 13788bdfc5daSXin Ji static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 13798bdfc5daSXin Ji { 13808bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13818bdfc5daSXin Ji struct s_edid_data *p_edid = &ctx->slimport_edid_p; 13828bdfc5daSXin Ji int edid_num; 13838bdfc5daSXin Ji u8 *edid; 13848bdfc5daSXin Ji 13858bdfc5daSXin Ji edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 13868bdfc5daSXin Ji if (!edid) { 13878bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 13888bdfc5daSXin Ji return NULL; 13898bdfc5daSXin Ji } 13908bdfc5daSXin Ji 13918bdfc5daSXin Ji if (ctx->slimport_edid_p.edid_block_num > 0) { 13928bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 13938bdfc5daSXin Ji FOUR_BLOCK_SIZE); 13948bdfc5daSXin Ji return (struct edid *)edid; 13958bdfc5daSXin Ji } 13968bdfc5daSXin Ji 139760487584SPi-Hsun Shih pm_runtime_get_sync(dev); 13988bdfc5daSXin Ji edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 13993203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 14008bdfc5daSXin Ji 14018bdfc5daSXin Ji if (edid_num < 1) { 14028bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 14038bdfc5daSXin Ji kfree(edid); 14048bdfc5daSXin Ji return NULL; 14058bdfc5daSXin Ji } 14068bdfc5daSXin Ji 14078bdfc5daSXin Ji p_edid->edid_block_num = edid_num; 14088bdfc5daSXin Ji 14098bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 14108bdfc5daSXin Ji return (struct edid *)edid; 14118bdfc5daSXin Ji } 14128bdfc5daSXin Ji 14138bdfc5daSXin Ji static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 14148bdfc5daSXin Ji { 14158bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14168bdfc5daSXin Ji 1417*fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 14188bdfc5daSXin Ji 1419*fd0310b6SXin Ji if (ctx->pdata.panel_bridge) 14208bdfc5daSXin Ji return connector_status_connected; 1421*fd0310b6SXin Ji 1422*fd0310b6SXin Ji return ctx->hpd_status ? connector_status_connected : 1423*fd0310b6SXin Ji connector_status_disconnected; 14248bdfc5daSXin Ji } 14258bdfc5daSXin Ji 14268bdfc5daSXin Ji static int anx7625_attach_dsi(struct anx7625_data *ctx) 14278bdfc5daSXin Ji { 14288bdfc5daSXin Ji struct mipi_dsi_device *dsi; 14298bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14308bdfc5daSXin Ji struct mipi_dsi_host *host; 14318bdfc5daSXin Ji const struct mipi_dsi_device_info info = { 14328bdfc5daSXin Ji .type = "anx7625", 14338bdfc5daSXin Ji .channel = 0, 14348bdfc5daSXin Ji .node = NULL, 14358bdfc5daSXin Ji }; 143625a390a9SMaxime Ripard int ret; 14378bdfc5daSXin Ji 14388bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 14398bdfc5daSXin Ji 14408bdfc5daSXin Ji host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 14418bdfc5daSXin Ji if (!host) { 14428bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 14438bdfc5daSXin Ji return -EINVAL; 14448bdfc5daSXin Ji } 14458bdfc5daSXin Ji 144625a390a9SMaxime Ripard dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 14478bdfc5daSXin Ji if (IS_ERR(dsi)) { 14488bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 14498bdfc5daSXin Ji return -EINVAL; 14508bdfc5daSXin Ji } 14518bdfc5daSXin Ji 1452*fd0310b6SXin Ji dsi->lanes = ctx->pdata.mipi_lanes; 14538bdfc5daSXin Ji dsi->format = MIPI_DSI_FMT_RGB888; 14548bdfc5daSXin Ji dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 14558bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 14568bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_HSE; 14578bdfc5daSXin Ji 145825a390a9SMaxime Ripard ret = devm_mipi_dsi_attach(dev, dsi); 145925a390a9SMaxime Ripard if (ret) { 14608bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 146125a390a9SMaxime Ripard return ret; 14628bdfc5daSXin Ji } 14638bdfc5daSXin Ji 14648bdfc5daSXin Ji ctx->dsi = dsi; 14658bdfc5daSXin Ji 14668bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 14678bdfc5daSXin Ji 14688bdfc5daSXin Ji return 0; 14698bdfc5daSXin Ji } 14708bdfc5daSXin Ji 14718bdfc5daSXin Ji static int anx7625_bridge_attach(struct drm_bridge *bridge, 14728bdfc5daSXin Ji enum drm_bridge_attach_flags flags) 14738bdfc5daSXin Ji { 14748bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 14758bdfc5daSXin Ji int err; 14768bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14778bdfc5daSXin Ji 14788bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 14798bdfc5daSXin Ji if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 14808bdfc5daSXin Ji return -EINVAL; 14818bdfc5daSXin Ji 14828bdfc5daSXin Ji if (!bridge->encoder) { 14838bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Parent encoder object not found"); 14848bdfc5daSXin Ji return -ENODEV; 14858bdfc5daSXin Ji } 14868bdfc5daSXin Ji 14878bdfc5daSXin Ji if (ctx->pdata.panel_bridge) { 14888bdfc5daSXin Ji err = drm_bridge_attach(bridge->encoder, 14898bdfc5daSXin Ji ctx->pdata.panel_bridge, 14908bdfc5daSXin Ji &ctx->bridge, flags); 1491fb8d617fSLaurent Pinchart if (err) 14928bdfc5daSXin Ji return err; 14938bdfc5daSXin Ji } 14948bdfc5daSXin Ji 14958bdfc5daSXin Ji ctx->bridge_attached = 1; 14968bdfc5daSXin Ji 14978bdfc5daSXin Ji return 0; 14988bdfc5daSXin Ji } 14998bdfc5daSXin Ji 15008bdfc5daSXin Ji static enum drm_mode_status 15018bdfc5daSXin Ji anx7625_bridge_mode_valid(struct drm_bridge *bridge, 15028bdfc5daSXin Ji const struct drm_display_info *info, 15038bdfc5daSXin Ji const struct drm_display_mode *mode) 15048bdfc5daSXin Ji { 15058bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 15068bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15078bdfc5daSXin Ji 15088bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 15098bdfc5daSXin Ji 15108bdfc5daSXin Ji /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 15118bdfc5daSXin Ji if (mode->clock > SUPPORT_PIXEL_CLOCK) { 15128bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, 15138bdfc5daSXin Ji "drm mode invalid, pixelclock too high.\n"); 15148bdfc5daSXin Ji return MODE_CLOCK_HIGH; 15158bdfc5daSXin Ji } 15168bdfc5daSXin Ji 15178bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 15188bdfc5daSXin Ji 15198bdfc5daSXin Ji return MODE_OK; 15208bdfc5daSXin Ji } 15218bdfc5daSXin Ji 15228bdfc5daSXin Ji static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 15238bdfc5daSXin Ji const struct drm_display_mode *old_mode, 15248bdfc5daSXin Ji const struct drm_display_mode *mode) 15258bdfc5daSXin Ji { 15268bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 15278bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15288bdfc5daSXin Ji 15298bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 15308bdfc5daSXin Ji 15318bdfc5daSXin Ji ctx->dt.pixelclock.min = mode->clock; 15328bdfc5daSXin Ji ctx->dt.hactive.min = mode->hdisplay; 15338bdfc5daSXin Ji ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 15348bdfc5daSXin Ji ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 15358bdfc5daSXin Ji ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 15368bdfc5daSXin Ji ctx->dt.vactive.min = mode->vdisplay; 15378bdfc5daSXin Ji ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 15388bdfc5daSXin Ji ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 15398bdfc5daSXin Ji ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 15408bdfc5daSXin Ji 15418bdfc5daSXin Ji ctx->display_timing_valid = 1; 15428bdfc5daSXin Ji 15438bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 15448bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 15458bdfc5daSXin Ji ctx->dt.hactive.min, 15468bdfc5daSXin Ji ctx->dt.hsync_len.min, 15478bdfc5daSXin Ji ctx->dt.hfront_porch.min, 15488bdfc5daSXin Ji ctx->dt.hback_porch.min); 15498bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 15508bdfc5daSXin Ji ctx->dt.vactive.min, 15518bdfc5daSXin Ji ctx->dt.vsync_len.min, 15528bdfc5daSXin Ji ctx->dt.vfront_porch.min, 15538bdfc5daSXin Ji ctx->dt.vback_porch.min); 15548bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 15558bdfc5daSXin Ji mode->hdisplay, 15568bdfc5daSXin Ji mode->hsync_start); 15578bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 15588bdfc5daSXin Ji mode->hsync_end, 15598bdfc5daSXin Ji mode->htotal); 15608bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 15618bdfc5daSXin Ji mode->vdisplay, 15628bdfc5daSXin Ji mode->vsync_start); 15638bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 15648bdfc5daSXin Ji mode->vsync_end, 15658bdfc5daSXin Ji mode->vtotal); 15668bdfc5daSXin Ji } 15678bdfc5daSXin Ji 15688bdfc5daSXin Ji static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 15698bdfc5daSXin Ji const struct drm_display_mode *mode, 15708bdfc5daSXin Ji struct drm_display_mode *adj) 15718bdfc5daSXin Ji { 15728bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 15738bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15748bdfc5daSXin Ji u32 hsync, hfp, hbp, hblanking; 15758bdfc5daSXin Ji u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 15768bdfc5daSXin Ji u32 vref, adj_clock; 15778bdfc5daSXin Ji 15788bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 15798bdfc5daSXin Ji 1580*fd0310b6SXin Ji /* No need fixup for external monitor */ 1581*fd0310b6SXin Ji if (!ctx->pdata.panel_bridge) 1582*fd0310b6SXin Ji return true; 1583*fd0310b6SXin Ji 15848bdfc5daSXin Ji hsync = mode->hsync_end - mode->hsync_start; 15858bdfc5daSXin Ji hfp = mode->hsync_start - mode->hdisplay; 15868bdfc5daSXin Ji hbp = mode->htotal - mode->hsync_end; 15878bdfc5daSXin Ji hblanking = mode->htotal - mode->hdisplay; 15888bdfc5daSXin Ji 15898bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 15908bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 15918bdfc5daSXin Ji hsync, hfp, hbp, adj->clock); 15928bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 15938bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 15948bdfc5daSXin Ji 15958bdfc5daSXin Ji adj_hfp = hfp; 15968bdfc5daSXin Ji adj_hsync = hsync; 15978bdfc5daSXin Ji adj_hbp = hbp; 15988bdfc5daSXin Ji adj_hblanking = hblanking; 15998bdfc5daSXin Ji 16008bdfc5daSXin Ji /* HFP needs to be even */ 16018bdfc5daSXin Ji if (hfp & 0x1) { 16028bdfc5daSXin Ji adj_hfp += 1; 16038bdfc5daSXin Ji adj_hblanking += 1; 16048bdfc5daSXin Ji } 16058bdfc5daSXin Ji 16068bdfc5daSXin Ji /* HBP needs to be even */ 16078bdfc5daSXin Ji if (hbp & 0x1) { 16088bdfc5daSXin Ji adj_hbp -= 1; 16098bdfc5daSXin Ji adj_hblanking -= 1; 16108bdfc5daSXin Ji } 16118bdfc5daSXin Ji 16128bdfc5daSXin Ji /* HSYNC needs to be even */ 16138bdfc5daSXin Ji if (hsync & 0x1) { 16148bdfc5daSXin Ji if (adj_hblanking < hblanking) 16158bdfc5daSXin Ji adj_hsync += 1; 16168bdfc5daSXin Ji else 16178bdfc5daSXin Ji adj_hsync -= 1; 16188bdfc5daSXin Ji } 16198bdfc5daSXin Ji 16208bdfc5daSXin Ji /* 16218bdfc5daSXin Ji * Once illegal timing detected, use default HFP, HSYNC, HBP 16228bdfc5daSXin Ji * This adjusting made for built-in eDP panel, for the externel 16238bdfc5daSXin Ji * DP monitor, may need return false. 16248bdfc5daSXin Ji */ 16258bdfc5daSXin Ji if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 16268bdfc5daSXin Ji adj_hsync = SYNC_LEN_DEF; 16278bdfc5daSXin Ji adj_hfp = HFP_HBP_DEF; 16288bdfc5daSXin Ji adj_hbp = HFP_HBP_DEF; 16298bdfc5daSXin Ji vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 16308bdfc5daSXin Ji if (hblanking < HBLANKING_MIN) { 16318bdfc5daSXin Ji delta_adj = HBLANKING_MIN - hblanking; 16328bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 16338bdfc5daSXin Ji adj->clock += DIV_ROUND_UP(adj_clock, 1000); 16348bdfc5daSXin Ji } else { 16358bdfc5daSXin Ji delta_adj = hblanking - HBLANKING_MIN; 16368bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 16378bdfc5daSXin Ji adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 16388bdfc5daSXin Ji } 16398bdfc5daSXin Ji 16408bdfc5daSXin Ji DRM_WARN("illegal hblanking timing, use default.\n"); 16418bdfc5daSXin Ji DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 16428bdfc5daSXin Ji } else if (adj_hfp < HP_MIN) { 16438bdfc5daSXin Ji /* Adjust hfp if hfp less than HP_MIN */ 16448bdfc5daSXin Ji delta_adj = HP_MIN - adj_hfp; 16458bdfc5daSXin Ji adj_hfp = HP_MIN; 16468bdfc5daSXin Ji 16478bdfc5daSXin Ji /* 16488bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP does not have enough 16498bdfc5daSXin Ji * space, adjust HSYNC length, otherwise adjust HBP 16508bdfc5daSXin Ji */ 16518bdfc5daSXin Ji if ((adj_hbp - delta_adj) < HP_MIN) 16528bdfc5daSXin Ji /* HBP not enough space */ 16538bdfc5daSXin Ji adj_hsync -= delta_adj; 16548bdfc5daSXin Ji else 16558bdfc5daSXin Ji adj_hbp -= delta_adj; 16568bdfc5daSXin Ji } else if (adj_hbp < HP_MIN) { 16578bdfc5daSXin Ji delta_adj = HP_MIN - adj_hbp; 16588bdfc5daSXin Ji adj_hbp = HP_MIN; 16598bdfc5daSXin Ji 16608bdfc5daSXin Ji /* 16618bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP hasn't enough space, 16628bdfc5daSXin Ji * adjust HSYNC length, otherwize adjust HBP 16638bdfc5daSXin Ji */ 16648bdfc5daSXin Ji if ((adj_hfp - delta_adj) < HP_MIN) 16658bdfc5daSXin Ji /* HFP not enough space */ 16668bdfc5daSXin Ji adj_hsync -= delta_adj; 16678bdfc5daSXin Ji else 16688bdfc5daSXin Ji adj_hfp -= delta_adj; 16698bdfc5daSXin Ji } 16708bdfc5daSXin Ji 16718bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 16728bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 16738bdfc5daSXin Ji adj_hsync, adj_hfp, adj_hbp, adj->clock); 16748bdfc5daSXin Ji 16758bdfc5daSXin Ji /* Reconstruct timing */ 16768bdfc5daSXin Ji adj->hsync_start = adj->hdisplay + adj_hfp; 16778bdfc5daSXin Ji adj->hsync_end = adj->hsync_start + adj_hsync; 16788bdfc5daSXin Ji adj->htotal = adj->hsync_end + adj_hbp; 16798bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 16808bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 16818bdfc5daSXin Ji 16828bdfc5daSXin Ji return true; 16838bdfc5daSXin Ji } 16848bdfc5daSXin Ji 16858bdfc5daSXin Ji static void anx7625_bridge_enable(struct drm_bridge *bridge) 16868bdfc5daSXin Ji { 16878bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 16888bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 16898bdfc5daSXin Ji 16908bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 16918bdfc5daSXin Ji 169260487584SPi-Hsun Shih pm_runtime_get_sync(dev); 16938bdfc5daSXin Ji 16948bdfc5daSXin Ji anx7625_dp_start(ctx); 16958bdfc5daSXin Ji } 16968bdfc5daSXin Ji 16978bdfc5daSXin Ji static void anx7625_bridge_disable(struct drm_bridge *bridge) 16988bdfc5daSXin Ji { 16998bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 17008bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17018bdfc5daSXin Ji 17028bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 17038bdfc5daSXin Ji 17048bdfc5daSXin Ji anx7625_dp_stop(ctx); 17058bdfc5daSXin Ji 17063203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 17078bdfc5daSXin Ji } 17088bdfc5daSXin Ji 17098bdfc5daSXin Ji static enum drm_connector_status 17108bdfc5daSXin Ji anx7625_bridge_detect(struct drm_bridge *bridge) 17118bdfc5daSXin Ji { 17128bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 17138bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17148bdfc5daSXin Ji 17158bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 17168bdfc5daSXin Ji 17178bdfc5daSXin Ji return anx7625_sink_detect(ctx); 17188bdfc5daSXin Ji } 17198bdfc5daSXin Ji 17208bdfc5daSXin Ji static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 17218bdfc5daSXin Ji struct drm_connector *connector) 17228bdfc5daSXin Ji { 17238bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 17248bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17258bdfc5daSXin Ji 17268bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 17278bdfc5daSXin Ji 17288bdfc5daSXin Ji return anx7625_get_edid(ctx); 17298bdfc5daSXin Ji } 17308bdfc5daSXin Ji 17318bdfc5daSXin Ji static const struct drm_bridge_funcs anx7625_bridge_funcs = { 17328bdfc5daSXin Ji .attach = anx7625_bridge_attach, 17338bdfc5daSXin Ji .disable = anx7625_bridge_disable, 17348bdfc5daSXin Ji .mode_valid = anx7625_bridge_mode_valid, 17358bdfc5daSXin Ji .mode_set = anx7625_bridge_mode_set, 17368bdfc5daSXin Ji .mode_fixup = anx7625_bridge_mode_fixup, 17378bdfc5daSXin Ji .enable = anx7625_bridge_enable, 17388bdfc5daSXin Ji .detect = anx7625_bridge_detect, 17398bdfc5daSXin Ji .get_edid = anx7625_bridge_get_edid, 17408bdfc5daSXin Ji }; 17418bdfc5daSXin Ji 17428bdfc5daSXin Ji static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 17438bdfc5daSXin Ji struct i2c_client *client) 17448bdfc5daSXin Ji { 17458bdfc5daSXin Ji ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 17468bdfc5daSXin Ji TX_P0_ADDR >> 1); 17478bdfc5daSXin Ji if (!ctx->i2c.tx_p0_client) 17488bdfc5daSXin Ji return -ENOMEM; 17498bdfc5daSXin Ji 17508bdfc5daSXin Ji ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 17518bdfc5daSXin Ji TX_P1_ADDR >> 1); 17528bdfc5daSXin Ji if (!ctx->i2c.tx_p1_client) 17538bdfc5daSXin Ji goto free_tx_p0; 17548bdfc5daSXin Ji 17558bdfc5daSXin Ji ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 17568bdfc5daSXin Ji TX_P2_ADDR >> 1); 17578bdfc5daSXin Ji if (!ctx->i2c.tx_p2_client) 17588bdfc5daSXin Ji goto free_tx_p1; 17598bdfc5daSXin Ji 17608bdfc5daSXin Ji ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 17618bdfc5daSXin Ji RX_P0_ADDR >> 1); 17628bdfc5daSXin Ji if (!ctx->i2c.rx_p0_client) 17638bdfc5daSXin Ji goto free_tx_p2; 17648bdfc5daSXin Ji 17658bdfc5daSXin Ji ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 17668bdfc5daSXin Ji RX_P1_ADDR >> 1); 17678bdfc5daSXin Ji if (!ctx->i2c.rx_p1_client) 17688bdfc5daSXin Ji goto free_rx_p0; 17698bdfc5daSXin Ji 17708bdfc5daSXin Ji ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 17718bdfc5daSXin Ji RX_P2_ADDR >> 1); 17728bdfc5daSXin Ji if (!ctx->i2c.rx_p2_client) 17738bdfc5daSXin Ji goto free_rx_p1; 17748bdfc5daSXin Ji 17758bdfc5daSXin Ji ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 17768bdfc5daSXin Ji TCPC_INTERFACE_ADDR >> 1); 17778bdfc5daSXin Ji if (!ctx->i2c.tcpc_client) 17788bdfc5daSXin Ji goto free_rx_p2; 17798bdfc5daSXin Ji 17808bdfc5daSXin Ji return 0; 17818bdfc5daSXin Ji 17828bdfc5daSXin Ji free_rx_p2: 17838bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 17848bdfc5daSXin Ji free_rx_p1: 17858bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 17868bdfc5daSXin Ji free_rx_p0: 17878bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 17888bdfc5daSXin Ji free_tx_p2: 17898bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 17908bdfc5daSXin Ji free_tx_p1: 17918bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 17928bdfc5daSXin Ji free_tx_p0: 17938bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 17948bdfc5daSXin Ji 17958bdfc5daSXin Ji return -ENOMEM; 17968bdfc5daSXin Ji } 17978bdfc5daSXin Ji 17988bdfc5daSXin Ji static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 17998bdfc5daSXin Ji { 18008bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 18018bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 18028bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 18038bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 18048bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 18058bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 18068bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tcpc_client); 18078bdfc5daSXin Ji } 18088bdfc5daSXin Ji 180960487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 181060487584SPi-Hsun Shih { 181160487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 181260487584SPi-Hsun Shih 181360487584SPi-Hsun Shih mutex_lock(&ctx->lock); 181460487584SPi-Hsun Shih 181560487584SPi-Hsun Shih anx7625_stop_dp_work(ctx); 181660487584SPi-Hsun Shih anx7625_power_standby(ctx); 181760487584SPi-Hsun Shih 181860487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 181960487584SPi-Hsun Shih 182060487584SPi-Hsun Shih return 0; 182160487584SPi-Hsun Shih } 182260487584SPi-Hsun Shih 182360487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 182460487584SPi-Hsun Shih { 182560487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 182660487584SPi-Hsun Shih 182760487584SPi-Hsun Shih mutex_lock(&ctx->lock); 182860487584SPi-Hsun Shih 182960487584SPi-Hsun Shih anx7625_power_on_init(ctx); 183060487584SPi-Hsun Shih anx7625_hpd_polling(ctx); 183160487584SPi-Hsun Shih 183260487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 183360487584SPi-Hsun Shih 183460487584SPi-Hsun Shih return 0; 183560487584SPi-Hsun Shih } 183660487584SPi-Hsun Shih 1837409776faSPi-Hsun Shih static int __maybe_unused anx7625_resume(struct device *dev) 1838409776faSPi-Hsun Shih { 1839409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 1840409776faSPi-Hsun Shih 1841409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 1842409776faSPi-Hsun Shih return 0; 1843409776faSPi-Hsun Shih 1844409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1845409776faSPi-Hsun Shih enable_irq(ctx->pdata.intp_irq); 1846409776faSPi-Hsun Shih anx7625_runtime_pm_resume(dev); 1847409776faSPi-Hsun Shih } 1848409776faSPi-Hsun Shih 1849409776faSPi-Hsun Shih return 0; 1850409776faSPi-Hsun Shih } 1851409776faSPi-Hsun Shih 1852409776faSPi-Hsun Shih static int __maybe_unused anx7625_suspend(struct device *dev) 1853409776faSPi-Hsun Shih { 1854409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 1855409776faSPi-Hsun Shih 1856409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 1857409776faSPi-Hsun Shih return 0; 1858409776faSPi-Hsun Shih 1859409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1860409776faSPi-Hsun Shih anx7625_runtime_pm_suspend(dev); 1861409776faSPi-Hsun Shih disable_irq(ctx->pdata.intp_irq); 1862409776faSPi-Hsun Shih } 1863409776faSPi-Hsun Shih 1864409776faSPi-Hsun Shih return 0; 1865409776faSPi-Hsun Shih } 1866409776faSPi-Hsun Shih 186760487584SPi-Hsun Shih static const struct dev_pm_ops anx7625_pm_ops = { 1868409776faSPi-Hsun Shih SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 186960487584SPi-Hsun Shih SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 187060487584SPi-Hsun Shih anx7625_runtime_pm_resume, NULL) 187160487584SPi-Hsun Shih }; 187260487584SPi-Hsun Shih 18738bdfc5daSXin Ji static int anx7625_i2c_probe(struct i2c_client *client, 18748bdfc5daSXin Ji const struct i2c_device_id *id) 18758bdfc5daSXin Ji { 18768bdfc5daSXin Ji struct anx7625_data *platform; 18778bdfc5daSXin Ji struct anx7625_platform_data *pdata; 18788bdfc5daSXin Ji int ret = 0; 18798bdfc5daSXin Ji struct device *dev = &client->dev; 18808bdfc5daSXin Ji 18818bdfc5daSXin Ji if (!i2c_check_functionality(client->adapter, 18828bdfc5daSXin Ji I2C_FUNC_SMBUS_I2C_BLOCK)) { 18838bdfc5daSXin Ji DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 18848bdfc5daSXin Ji return -ENODEV; 18858bdfc5daSXin Ji } 18868bdfc5daSXin Ji 18878bdfc5daSXin Ji platform = kzalloc(sizeof(*platform), GFP_KERNEL); 18888bdfc5daSXin Ji if (!platform) { 18898bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 18908bdfc5daSXin Ji return -ENOMEM; 18918bdfc5daSXin Ji } 18928bdfc5daSXin Ji 18938bdfc5daSXin Ji pdata = &platform->pdata; 18948bdfc5daSXin Ji 18958bdfc5daSXin Ji ret = anx7625_parse_dt(dev, pdata); 18968bdfc5daSXin Ji if (ret) { 18978bdfc5daSXin Ji if (ret != -EPROBE_DEFER) 18988bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 18998bdfc5daSXin Ji goto free_platform; 19008bdfc5daSXin Ji } 19018bdfc5daSXin Ji 19028bdfc5daSXin Ji platform->client = client; 19038bdfc5daSXin Ji i2c_set_clientdata(client, platform); 19048bdfc5daSXin Ji 19056c744983SHsin-Yi Wang pdata->supplies[0].supply = "vdd10"; 19066c744983SHsin-Yi Wang pdata->supplies[1].supply = "vdd18"; 19076c744983SHsin-Yi Wang pdata->supplies[2].supply = "vdd33"; 19086c744983SHsin-Yi Wang ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 19096c744983SHsin-Yi Wang pdata->supplies); 19106c744983SHsin-Yi Wang if (ret) { 19116c744983SHsin-Yi Wang DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 19126c744983SHsin-Yi Wang return ret; 19136c744983SHsin-Yi Wang } 19148bdfc5daSXin Ji anx7625_init_gpio(platform); 19158bdfc5daSXin Ji 19168bdfc5daSXin Ji mutex_init(&platform->lock); 19178bdfc5daSXin Ji 19188bdfc5daSXin Ji platform->pdata.intp_irq = client->irq; 19198bdfc5daSXin Ji if (platform->pdata.intp_irq) { 19208bdfc5daSXin Ji INIT_WORK(&platform->work, anx7625_work_func); 1921f03ab662SPi-Hsun Shih platform->workqueue = alloc_workqueue("anx7625_work", 1922f03ab662SPi-Hsun Shih WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 19238bdfc5daSXin Ji if (!platform->workqueue) { 19248bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create work queue\n"); 19258bdfc5daSXin Ji ret = -ENOMEM; 19268bdfc5daSXin Ji goto free_platform; 19278bdfc5daSXin Ji } 19288bdfc5daSXin Ji 19298bdfc5daSXin Ji ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 19308bdfc5daSXin Ji NULL, anx7625_intr_hpd_isr, 19318bdfc5daSXin Ji IRQF_TRIGGER_FALLING | 19328bdfc5daSXin Ji IRQF_ONESHOT, 19338bdfc5daSXin Ji "anx7625-intp", platform); 19348bdfc5daSXin Ji if (ret) { 19358bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to request irq\n"); 19368bdfc5daSXin Ji goto free_wq; 19378bdfc5daSXin Ji } 19388bdfc5daSXin Ji } 19398bdfc5daSXin Ji 19408bdfc5daSXin Ji if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 19418bdfc5daSXin Ji ret = -ENOMEM; 19428bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 19438bdfc5daSXin Ji goto free_wq; 19448bdfc5daSXin Ji } 19458bdfc5daSXin Ji 194660487584SPi-Hsun Shih pm_runtime_enable(dev); 194760487584SPi-Hsun Shih 194860487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) { 19498bdfc5daSXin Ji anx7625_disable_pd_protocol(platform); 195060487584SPi-Hsun Shih pm_runtime_get_sync(dev); 19518bdfc5daSXin Ji } 19528bdfc5daSXin Ji 19538bdfc5daSXin Ji /* Add work function */ 19548bdfc5daSXin Ji if (platform->pdata.intp_irq) 19558bdfc5daSXin Ji queue_work(platform->workqueue, &platform->work); 19568bdfc5daSXin Ji 19578bdfc5daSXin Ji platform->bridge.funcs = &anx7625_bridge_funcs; 19588bdfc5daSXin Ji platform->bridge.of_node = client->dev.of_node; 1959*fd0310b6SXin Ji platform->bridge.ops = DRM_BRIDGE_OP_EDID; 1960*fd0310b6SXin Ji if (!platform->pdata.panel_bridge) 1961*fd0310b6SXin Ji platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 1962*fd0310b6SXin Ji DRM_BRIDGE_OP_DETECT; 1963*fd0310b6SXin Ji platform->bridge.type = platform->pdata.panel_bridge ? 1964*fd0310b6SXin Ji DRM_MODE_CONNECTOR_eDP : 1965*fd0310b6SXin Ji DRM_MODE_CONNECTOR_DisplayPort; 1966*fd0310b6SXin Ji 19678bdfc5daSXin Ji drm_bridge_add(&platform->bridge); 19688bdfc5daSXin Ji 1969*fd0310b6SXin Ji if (!platform->pdata.is_dpi) { 197049e61beeSMaxime Ripard ret = anx7625_attach_dsi(platform); 197149e61beeSMaxime Ripard if (ret) { 197249e61beeSMaxime Ripard DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 197349e61beeSMaxime Ripard goto unregister_bridge; 197449e61beeSMaxime Ripard } 1975*fd0310b6SXin Ji } 197649e61beeSMaxime Ripard 19778bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 19788bdfc5daSXin Ji 19798bdfc5daSXin Ji return 0; 19808bdfc5daSXin Ji 198149e61beeSMaxime Ripard unregister_bridge: 198249e61beeSMaxime Ripard drm_bridge_remove(&platform->bridge); 198349e61beeSMaxime Ripard 198449e61beeSMaxime Ripard if (!platform->pdata.low_power_mode) 198549e61beeSMaxime Ripard pm_runtime_put_sync_suspend(&client->dev); 198649e61beeSMaxime Ripard 198749e61beeSMaxime Ripard anx7625_unregister_i2c_dummy_clients(platform); 198849e61beeSMaxime Ripard 19898bdfc5daSXin Ji free_wq: 19908bdfc5daSXin Ji if (platform->workqueue) 19918bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 19928bdfc5daSXin Ji 19938bdfc5daSXin Ji free_platform: 19948bdfc5daSXin Ji kfree(platform); 19958bdfc5daSXin Ji 19968bdfc5daSXin Ji return ret; 19978bdfc5daSXin Ji } 19988bdfc5daSXin Ji 19998bdfc5daSXin Ji static int anx7625_i2c_remove(struct i2c_client *client) 20008bdfc5daSXin Ji { 20018bdfc5daSXin Ji struct anx7625_data *platform = i2c_get_clientdata(client); 20028bdfc5daSXin Ji 20038bdfc5daSXin Ji drm_bridge_remove(&platform->bridge); 20048bdfc5daSXin Ji 20058bdfc5daSXin Ji if (platform->pdata.intp_irq) 20068bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 20078bdfc5daSXin Ji 200860487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) 200960487584SPi-Hsun Shih pm_runtime_put_sync_suspend(&client->dev); 201060487584SPi-Hsun Shih 20118bdfc5daSXin Ji anx7625_unregister_i2c_dummy_clients(platform); 20128bdfc5daSXin Ji 20138bdfc5daSXin Ji kfree(platform); 20148bdfc5daSXin Ji return 0; 20158bdfc5daSXin Ji } 20168bdfc5daSXin Ji 20178bdfc5daSXin Ji static const struct i2c_device_id anx7625_id[] = { 20188bdfc5daSXin Ji {"anx7625", 0}, 20198bdfc5daSXin Ji {} 20208bdfc5daSXin Ji }; 20218bdfc5daSXin Ji 20228bdfc5daSXin Ji MODULE_DEVICE_TABLE(i2c, anx7625_id); 20238bdfc5daSXin Ji 20248bdfc5daSXin Ji static const struct of_device_id anx_match_table[] = { 20258bdfc5daSXin Ji {.compatible = "analogix,anx7625",}, 20268bdfc5daSXin Ji {}, 20278bdfc5daSXin Ji }; 2028ad5fd900SYu Jiahua MODULE_DEVICE_TABLE(of, anx_match_table); 20298bdfc5daSXin Ji 20308bdfc5daSXin Ji static struct i2c_driver anx7625_driver = { 20318bdfc5daSXin Ji .driver = { 20328bdfc5daSXin Ji .name = "anx7625", 20338bdfc5daSXin Ji .of_match_table = anx_match_table, 203460487584SPi-Hsun Shih .pm = &anx7625_pm_ops, 20358bdfc5daSXin Ji }, 20368bdfc5daSXin Ji .probe = anx7625_i2c_probe, 20378bdfc5daSXin Ji .remove = anx7625_i2c_remove, 20388bdfc5daSXin Ji 20398bdfc5daSXin Ji .id_table = anx7625_id, 20408bdfc5daSXin Ji }; 20418bdfc5daSXin Ji 20428bdfc5daSXin Ji module_i2c_driver(anx7625_driver); 20438bdfc5daSXin Ji 20448bdfc5daSXin Ji MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 20458bdfc5daSXin Ji MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 20468bdfc5daSXin Ji MODULE_LICENSE("GPL v2"); 20478bdfc5daSXin Ji MODULE_VERSION(ANX7625_DRV_VERSION); 2048