18bdfc5daSXin Ji // SPDX-License-Identifier: GPL-2.0-only 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji #include <linux/gcd.h> 78bdfc5daSXin Ji #include <linux/gpio/consumer.h> 88bdfc5daSXin Ji #include <linux/i2c.h> 98bdfc5daSXin Ji #include <linux/interrupt.h> 108bdfc5daSXin Ji #include <linux/iopoll.h> 118bdfc5daSXin Ji #include <linux/kernel.h> 128bdfc5daSXin Ji #include <linux/module.h> 138bdfc5daSXin Ji #include <linux/mutex.h> 1460487584SPi-Hsun Shih #include <linux/pm_runtime.h> 156c744983SHsin-Yi Wang #include <linux/regulator/consumer.h> 168bdfc5daSXin Ji #include <linux/slab.h> 178bdfc5daSXin Ji #include <linux/types.h> 188bdfc5daSXin Ji #include <linux/workqueue.h> 198bdfc5daSXin Ji 208bdfc5daSXin Ji #include <linux/of_gpio.h> 218bdfc5daSXin Ji #include <linux/of_graph.h> 228bdfc5daSXin Ji #include <linux/of_platform.h> 238bdfc5daSXin Ji 248bdfc5daSXin Ji #include <drm/drm_atomic_helper.h> 258bdfc5daSXin Ji #include <drm/drm_bridge.h> 268bdfc5daSXin Ji #include <drm/drm_crtc_helper.h> 278bdfc5daSXin Ji #include <drm/drm_dp_helper.h> 288bdfc5daSXin Ji #include <drm/drm_edid.h> 298bdfc5daSXin Ji #include <drm/drm_mipi_dsi.h> 308bdfc5daSXin Ji #include <drm/drm_of.h> 318bdfc5daSXin Ji #include <drm/drm_panel.h> 328bdfc5daSXin Ji #include <drm/drm_print.h> 338bdfc5daSXin Ji #include <drm/drm_probe_helper.h> 348bdfc5daSXin Ji 358bdfc5daSXin Ji #include <video/display_timing.h> 368bdfc5daSXin Ji 378bdfc5daSXin Ji #include "anx7625.h" 388bdfc5daSXin Ji 398bdfc5daSXin Ji /* 408bdfc5daSXin Ji * There is a sync issue while access I2C register between AP(CPU) and 418bdfc5daSXin Ji * internal firmware(OCM), to avoid the race condition, AP should access 428bdfc5daSXin Ji * the reserved slave address before slave address occurs changes. 438bdfc5daSXin Ji */ 448bdfc5daSXin Ji static int i2c_access_workaround(struct anx7625_data *ctx, 458bdfc5daSXin Ji struct i2c_client *client) 468bdfc5daSXin Ji { 478bdfc5daSXin Ji u8 offset; 488bdfc5daSXin Ji struct device *dev = &client->dev; 498bdfc5daSXin Ji int ret; 508bdfc5daSXin Ji 518bdfc5daSXin Ji if (client == ctx->last_client) 528bdfc5daSXin Ji return 0; 538bdfc5daSXin Ji 548bdfc5daSXin Ji ctx->last_client = client; 558bdfc5daSXin Ji 568bdfc5daSXin Ji if (client == ctx->i2c.tcpc_client) 578bdfc5daSXin Ji offset = RSVD_00_ADDR; 588bdfc5daSXin Ji else if (client == ctx->i2c.tx_p0_client) 598bdfc5daSXin Ji offset = RSVD_D1_ADDR; 608bdfc5daSXin Ji else if (client == ctx->i2c.tx_p1_client) 618bdfc5daSXin Ji offset = RSVD_60_ADDR; 628bdfc5daSXin Ji else if (client == ctx->i2c.rx_p0_client) 638bdfc5daSXin Ji offset = RSVD_39_ADDR; 648bdfc5daSXin Ji else if (client == ctx->i2c.rx_p1_client) 658bdfc5daSXin Ji offset = RSVD_7F_ADDR; 668bdfc5daSXin Ji else 678bdfc5daSXin Ji offset = RSVD_00_ADDR; 688bdfc5daSXin Ji 698bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, offset, 0x00); 708bdfc5daSXin Ji if (ret < 0) 718bdfc5daSXin Ji DRM_DEV_ERROR(dev, 728bdfc5daSXin Ji "fail to access i2c id=%x\n:%x", 738bdfc5daSXin Ji client->addr, offset); 748bdfc5daSXin Ji 758bdfc5daSXin Ji return ret; 768bdfc5daSXin Ji } 778bdfc5daSXin Ji 788bdfc5daSXin Ji static int anx7625_reg_read(struct anx7625_data *ctx, 798bdfc5daSXin Ji struct i2c_client *client, u8 reg_addr) 808bdfc5daSXin Ji { 818bdfc5daSXin Ji int ret; 828bdfc5daSXin Ji struct device *dev = &client->dev; 838bdfc5daSXin Ji 848bdfc5daSXin Ji i2c_access_workaround(ctx, client); 858bdfc5daSXin Ji 868bdfc5daSXin Ji ret = i2c_smbus_read_byte_data(client, reg_addr); 878bdfc5daSXin Ji if (ret < 0) 888bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 898bdfc5daSXin Ji client->addr, reg_addr); 908bdfc5daSXin Ji 918bdfc5daSXin Ji return ret; 928bdfc5daSXin Ji } 938bdfc5daSXin Ji 948bdfc5daSXin Ji static int anx7625_reg_block_read(struct anx7625_data *ctx, 958bdfc5daSXin Ji struct i2c_client *client, 968bdfc5daSXin Ji u8 reg_addr, u8 len, u8 *buf) 978bdfc5daSXin Ji { 988bdfc5daSXin Ji int ret; 998bdfc5daSXin Ji struct device *dev = &client->dev; 1008bdfc5daSXin Ji 1018bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1028bdfc5daSXin Ji 1038bdfc5daSXin Ji ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 1048bdfc5daSXin Ji if (ret < 0) 1058bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 1068bdfc5daSXin Ji client->addr, reg_addr); 1078bdfc5daSXin Ji 1088bdfc5daSXin Ji return ret; 1098bdfc5daSXin Ji } 1108bdfc5daSXin Ji 1118bdfc5daSXin Ji static int anx7625_reg_write(struct anx7625_data *ctx, 1128bdfc5daSXin Ji struct i2c_client *client, 1138bdfc5daSXin Ji u8 reg_addr, u8 reg_val) 1148bdfc5daSXin Ji { 1158bdfc5daSXin Ji int ret; 1168bdfc5daSXin Ji struct device *dev = &client->dev; 1178bdfc5daSXin Ji 1188bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1198bdfc5daSXin Ji 1208bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 1218bdfc5daSXin Ji 1228bdfc5daSXin Ji if (ret < 0) 1238bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 1248bdfc5daSXin Ji client->addr, reg_addr); 1258bdfc5daSXin Ji 1268bdfc5daSXin Ji return ret; 1278bdfc5daSXin Ji } 1288bdfc5daSXin Ji 1298bdfc5daSXin Ji static int anx7625_write_or(struct anx7625_data *ctx, 1308bdfc5daSXin Ji struct i2c_client *client, 1318bdfc5daSXin Ji u8 offset, u8 mask) 1328bdfc5daSXin Ji { 1338bdfc5daSXin Ji int val; 1348bdfc5daSXin Ji 1358bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1368bdfc5daSXin Ji if (val < 0) 1378bdfc5daSXin Ji return val; 1388bdfc5daSXin Ji 1398bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val | (mask))); 1408bdfc5daSXin Ji } 1418bdfc5daSXin Ji 1428bdfc5daSXin Ji static int anx7625_write_and(struct anx7625_data *ctx, 1438bdfc5daSXin Ji struct i2c_client *client, 1448bdfc5daSXin Ji u8 offset, u8 mask) 1458bdfc5daSXin Ji { 1468bdfc5daSXin Ji int val; 1478bdfc5daSXin Ji 1488bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1498bdfc5daSXin Ji if (val < 0) 1508bdfc5daSXin Ji return val; 1518bdfc5daSXin Ji 1528bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val & (mask))); 1538bdfc5daSXin Ji } 1548bdfc5daSXin Ji 1558bdfc5daSXin Ji static int anx7625_write_and_or(struct anx7625_data *ctx, 1568bdfc5daSXin Ji struct i2c_client *client, 1578bdfc5daSXin Ji u8 offset, u8 and_mask, u8 or_mask) 1588bdfc5daSXin Ji { 1598bdfc5daSXin Ji int val; 1608bdfc5daSXin Ji 1618bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1628bdfc5daSXin Ji if (val < 0) 1638bdfc5daSXin Ji return val; 1648bdfc5daSXin Ji 1658bdfc5daSXin Ji return anx7625_reg_write(ctx, client, 1668bdfc5daSXin Ji offset, (val & and_mask) | (or_mask)); 1678bdfc5daSXin Ji } 1688bdfc5daSXin Ji 1698bdfc5daSXin Ji static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 1708bdfc5daSXin Ji { 1718bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 1728bdfc5daSXin Ji } 1738bdfc5daSXin Ji 1748bdfc5daSXin Ji static int wait_aux_op_finish(struct anx7625_data *ctx) 1758bdfc5daSXin Ji { 1768bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1778bdfc5daSXin Ji int val; 1788bdfc5daSXin Ji int ret; 1798bdfc5daSXin Ji 1808bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 1818bdfc5daSXin Ji ctx, val, 1828bdfc5daSXin Ji (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 1838bdfc5daSXin Ji 2000, 1848bdfc5daSXin Ji 2000 * 150); 1858bdfc5daSXin Ji if (ret) { 1868bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux operation fail!\n"); 1878bdfc5daSXin Ji return -EIO; 1888bdfc5daSXin Ji } 1898bdfc5daSXin Ji 1908bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1918bdfc5daSXin Ji AP_AUX_CTRL_STATUS); 1928bdfc5daSXin Ji if (val < 0 || (val & 0x0F)) { 1938bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux status %02x\n", val); 1948bdfc5daSXin Ji val = -EIO; 1958bdfc5daSXin Ji } 1968bdfc5daSXin Ji 1978bdfc5daSXin Ji return val; 1988bdfc5daSXin Ji } 1998bdfc5daSXin Ji 2008bdfc5daSXin Ji static int anx7625_video_mute_control(struct anx7625_data *ctx, 2018bdfc5daSXin Ji u8 status) 2028bdfc5daSXin Ji { 2038bdfc5daSXin Ji int ret; 2048bdfc5daSXin Ji 2058bdfc5daSXin Ji if (status) { 2068bdfc5daSXin Ji /* Set mute on flag */ 2078bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2088bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_MUTE); 2098bdfc5daSXin Ji /* Clear mipi RX en */ 2108bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 2118bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 2128bdfc5daSXin Ji } else { 2138bdfc5daSXin Ji /* Mute off flag */ 2148bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 2158bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 2168bdfc5daSXin Ji /* Set MIPI RX EN */ 2178bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2188bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 2198bdfc5daSXin Ji } 2208bdfc5daSXin Ji 2218bdfc5daSXin Ji return ret; 2228bdfc5daSXin Ji } 2238bdfc5daSXin Ji 2248bdfc5daSXin Ji static int anx7625_config_audio_input(struct anx7625_data *ctx) 2258bdfc5daSXin Ji { 2268bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 2278bdfc5daSXin Ji int ret; 2288bdfc5daSXin Ji 2298bdfc5daSXin Ji /* Channel num */ 2308bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 2318bdfc5daSXin Ji AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5); 2328bdfc5daSXin Ji 2338bdfc5daSXin Ji /* FS */ 2348bdfc5daSXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 2358bdfc5daSXin Ji AUDIO_CHANNEL_STATUS_4, 2368bdfc5daSXin Ji 0xf0, AUDIO_FS_48K); 2378bdfc5daSXin Ji /* Word length */ 2388bdfc5daSXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 2398bdfc5daSXin Ji AUDIO_CHANNEL_STATUS_5, 2408bdfc5daSXin Ji 0xf0, AUDIO_W_LEN_24_24MAX); 2418bdfc5daSXin Ji /* I2S */ 2428bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 2438bdfc5daSXin Ji AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE); 2448bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 2458bdfc5daSXin Ji AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE); 2468bdfc5daSXin Ji /* Audio change flag */ 2478bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2488bdfc5daSXin Ji AP_AV_STATUS, AP_AUDIO_CHG); 2498bdfc5daSXin Ji 2508bdfc5daSXin Ji if (ret < 0) 2518bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to config audio.\n"); 2528bdfc5daSXin Ji 2538bdfc5daSXin Ji return ret; 2548bdfc5daSXin Ji } 2558bdfc5daSXin Ji 2568bdfc5daSXin Ji /* Reduction of fraction a/b */ 2578bdfc5daSXin Ji static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 2588bdfc5daSXin Ji { 2598bdfc5daSXin Ji unsigned long gcd_num; 2608bdfc5daSXin Ji unsigned long tmp_a, tmp_b; 2618bdfc5daSXin Ji u32 i = 1; 2628bdfc5daSXin Ji 2638bdfc5daSXin Ji gcd_num = gcd(*a, *b); 2648bdfc5daSXin Ji *a /= gcd_num; 2658bdfc5daSXin Ji *b /= gcd_num; 2668bdfc5daSXin Ji 2678bdfc5daSXin Ji tmp_a = *a; 2688bdfc5daSXin Ji tmp_b = *b; 2698bdfc5daSXin Ji 2708bdfc5daSXin Ji while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 2718bdfc5daSXin Ji i++; 2728bdfc5daSXin Ji *a = tmp_a / i; 2738bdfc5daSXin Ji *b = tmp_b / i; 2748bdfc5daSXin Ji } 2758bdfc5daSXin Ji 2768bdfc5daSXin Ji /* 2778bdfc5daSXin Ji * In the end, make a, b larger to have higher ODFC PLL 2788bdfc5daSXin Ji * output frequency accuracy 2798bdfc5daSXin Ji */ 2808bdfc5daSXin Ji while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 2818bdfc5daSXin Ji *a <<= 1; 2828bdfc5daSXin Ji *b <<= 1; 2838bdfc5daSXin Ji } 2848bdfc5daSXin Ji 2858bdfc5daSXin Ji *a >>= 1; 2868bdfc5daSXin Ji *b >>= 1; 2878bdfc5daSXin Ji } 2888bdfc5daSXin Ji 2898bdfc5daSXin Ji static int anx7625_calculate_m_n(u32 pixelclock, 2908bdfc5daSXin Ji unsigned long *m, 2918bdfc5daSXin Ji unsigned long *n, 2928bdfc5daSXin Ji u8 *post_divider) 2938bdfc5daSXin Ji { 2948bdfc5daSXin Ji if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 2958bdfc5daSXin Ji /* Pixel clock frequency is too high */ 2968bdfc5daSXin Ji DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 2978bdfc5daSXin Ji pixelclock, 2988bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 2998bdfc5daSXin Ji return -EINVAL; 3008bdfc5daSXin Ji } 3018bdfc5daSXin Ji 3028bdfc5daSXin Ji if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 3038bdfc5daSXin Ji /* Pixel clock frequency is too low */ 3048bdfc5daSXin Ji DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 3058bdfc5daSXin Ji pixelclock, 3068bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 3078bdfc5daSXin Ji return -EINVAL; 3088bdfc5daSXin Ji } 3098bdfc5daSXin Ji 3108bdfc5daSXin Ji for (*post_divider = 1; 3118bdfc5daSXin Ji pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 3128bdfc5daSXin Ji *post_divider += 1; 3138bdfc5daSXin Ji 3148bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3158bdfc5daSXin Ji for (*post_divider = 1; 3168bdfc5daSXin Ji (pixelclock < 3178bdfc5daSXin Ji (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 3188bdfc5daSXin Ji *post_divider += 1; 3198bdfc5daSXin Ji 3208bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3218bdfc5daSXin Ji DRM_ERROR("cannot find property post_divider(%d)\n", 3228bdfc5daSXin Ji *post_divider); 3238bdfc5daSXin Ji return -EDOM; 3248bdfc5daSXin Ji } 3258bdfc5daSXin Ji } 3268bdfc5daSXin Ji 3278bdfc5daSXin Ji /* Patch to improve the accuracy */ 3288bdfc5daSXin Ji if (*post_divider == 7) { 3298bdfc5daSXin Ji /* 27,000,000 is not divisible by 7 */ 3308bdfc5daSXin Ji *post_divider = 8; 3318bdfc5daSXin Ji } else if (*post_divider == 11) { 3328bdfc5daSXin Ji /* 27,000,000 is not divisible by 11 */ 3338bdfc5daSXin Ji *post_divider = 12; 3348bdfc5daSXin Ji } else if ((*post_divider == 13) || (*post_divider == 14)) { 3358bdfc5daSXin Ji /* 27,000,000 is not divisible by 13 or 14 */ 3368bdfc5daSXin Ji *post_divider = 15; 3378bdfc5daSXin Ji } 3388bdfc5daSXin Ji 3398bdfc5daSXin Ji if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 3408bdfc5daSXin Ji DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 3418bdfc5daSXin Ji pixelclock * (*post_divider), 3428bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX); 3438bdfc5daSXin Ji return -EDOM; 3448bdfc5daSXin Ji } 3458bdfc5daSXin Ji 3468bdfc5daSXin Ji *m = pixelclock; 3478bdfc5daSXin Ji *n = XTAL_FRQ / (*post_divider); 3488bdfc5daSXin Ji 3498bdfc5daSXin Ji anx7625_reduction_of_a_fraction(m, n); 3508bdfc5daSXin Ji 3518bdfc5daSXin Ji return 0; 3528bdfc5daSXin Ji } 3538bdfc5daSXin Ji 3548bdfc5daSXin Ji static int anx7625_odfc_config(struct anx7625_data *ctx, 3558bdfc5daSXin Ji u8 post_divider) 3568bdfc5daSXin Ji { 3578bdfc5daSXin Ji int ret; 3588bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 3598bdfc5daSXin Ji 3608bdfc5daSXin Ji /* Config input reference clock frequency 27MHz/19.2MHz */ 3618bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 3628bdfc5daSXin Ji ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 3638bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 3648bdfc5daSXin Ji (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 3658bdfc5daSXin Ji /* Post divider */ 3668bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 3678bdfc5daSXin Ji MIPI_DIGITAL_PLL_8, 0x0f); 3688bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 3698bdfc5daSXin Ji post_divider << 4); 3708bdfc5daSXin Ji 3718bdfc5daSXin Ji /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 3728bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3738bdfc5daSXin Ji ~MIPI_PLL_VCO_TUNE_REG_VAL); 3748bdfc5daSXin Ji 3758bdfc5daSXin Ji /* Reset ODFC PLL */ 3768bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3778bdfc5daSXin Ji ~MIPI_PLL_RESET_N); 3788bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3798bdfc5daSXin Ji MIPI_PLL_RESET_N); 3808bdfc5daSXin Ji 3818bdfc5daSXin Ji if (ret < 0) 3828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error.\n"); 3838bdfc5daSXin Ji 3848bdfc5daSXin Ji return ret; 3858bdfc5daSXin Ji } 3868bdfc5daSXin Ji 3878bdfc5daSXin Ji static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 3888bdfc5daSXin Ji { 3898bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 3908bdfc5daSXin Ji unsigned long m, n; 3918bdfc5daSXin Ji u16 htotal; 3928bdfc5daSXin Ji int ret; 3938bdfc5daSXin Ji u8 post_divider = 0; 3948bdfc5daSXin Ji 3958bdfc5daSXin Ji ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 3968bdfc5daSXin Ji &m, &n, &post_divider); 3978bdfc5daSXin Ji 3988bdfc5daSXin Ji if (ret) { 3998bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 4008bdfc5daSXin Ji return ret; 4018bdfc5daSXin Ji } 4028bdfc5daSXin Ji 4038bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 4048bdfc5daSXin Ji m, n, post_divider); 4058bdfc5daSXin Ji 4068bdfc5daSXin Ji /* Configure pixel clock */ 4078bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 4088bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) & 0xFF); 4098bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 4108bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) >> 8); 4118bdfc5daSXin Ji /* Lane count */ 4128bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4138bdfc5daSXin Ji MIPI_LANE_CTRL_0, 0xfc); 4148bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 4158bdfc5daSXin Ji MIPI_LANE_CTRL_0, 3); 4168bdfc5daSXin Ji 4178bdfc5daSXin Ji /* Htotal */ 4188bdfc5daSXin Ji htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 4198bdfc5daSXin Ji ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 4208bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4218bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 4228bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4238bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 4248bdfc5daSXin Ji /* Hactive */ 4258bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4268bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 4278bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4288bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 4298bdfc5daSXin Ji /* HFP */ 4308bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4318bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 4328bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4338bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_H, 4348bdfc5daSXin Ji ctx->dt.hfront_porch.min >> 8); 4358bdfc5daSXin Ji /* HWS */ 4368bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4378bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 4388bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4398bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 4408bdfc5daSXin Ji /* HBP */ 4418bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4428bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 4438bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4448bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 4458bdfc5daSXin Ji /* Vactive */ 4468bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 4478bdfc5daSXin Ji ctx->dt.vactive.min); 4488bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 4498bdfc5daSXin Ji ctx->dt.vactive.min >> 8); 4508bdfc5daSXin Ji /* VFP */ 4518bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4528bdfc5daSXin Ji VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 4538bdfc5daSXin Ji /* VWS */ 4548bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4558bdfc5daSXin Ji VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 4568bdfc5daSXin Ji /* VBP */ 4578bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4588bdfc5daSXin Ji VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 4598bdfc5daSXin Ji /* M value */ 4608bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4618bdfc5daSXin Ji MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 4628bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4638bdfc5daSXin Ji MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 4648bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4658bdfc5daSXin Ji MIPI_PLL_M_NUM_7_0, (m & 0xff)); 4668bdfc5daSXin Ji /* N value */ 4678bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4688bdfc5daSXin Ji MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 4698bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4708bdfc5daSXin Ji MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 4718bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 4728bdfc5daSXin Ji (n & 0xff)); 4738bdfc5daSXin Ji /* Diff */ 4748bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4758bdfc5daSXin Ji MIPI_DIGITAL_ADJ_1, 0x3D); 4768bdfc5daSXin Ji 4778bdfc5daSXin Ji ret |= anx7625_odfc_config(ctx, post_divider - 1); 4788bdfc5daSXin Ji 4798bdfc5daSXin Ji if (ret < 0) 4808bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 4818bdfc5daSXin Ji 4828bdfc5daSXin Ji return ret; 4838bdfc5daSXin Ji } 4848bdfc5daSXin Ji 4858bdfc5daSXin Ji static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 4868bdfc5daSXin Ji { 4878bdfc5daSXin Ji int val; 4888bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4898bdfc5daSXin Ji 4908bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 4918bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 4928bdfc5daSXin Ji if (val < 0) { 4938bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 4948bdfc5daSXin Ji return -EIO; 4958bdfc5daSXin Ji } 4968bdfc5daSXin Ji 4978bdfc5daSXin Ji val |= (1 << MIPI_SWAP_CH3); 4988bdfc5daSXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 4998bdfc5daSXin Ji } 5008bdfc5daSXin Ji 5018bdfc5daSXin Ji static int anx7625_api_dsi_config(struct anx7625_data *ctx) 5028bdfc5daSXin Ji 5038bdfc5daSXin Ji { 5048bdfc5daSXin Ji int val, ret; 5058bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5068bdfc5daSXin Ji 5078bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5088bdfc5daSXin Ji ret = anx7625_swap_dsi_lane3(ctx); 5098bdfc5daSXin Ji if (ret < 0) { 5108bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 5118bdfc5daSXin Ji return ret; 5128bdfc5daSXin Ji } 5138bdfc5daSXin Ji 5148bdfc5daSXin Ji /* DSI clock settings */ 5158bdfc5daSXin Ji val = (0 << MIPI_HS_PWD_CLK) | 5168bdfc5daSXin Ji (0 << MIPI_HS_RT_CLK) | 5178bdfc5daSXin Ji (0 << MIPI_PD_CLK) | 5188bdfc5daSXin Ji (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 5198bdfc5daSXin Ji (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 5208bdfc5daSXin Ji (0 << MIPI_CLK_DET_DET_BYPASS) | 5218bdfc5daSXin Ji (0 << MIPI_CLK_MISS_CTRL) | 5228bdfc5daSXin Ji (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 5238bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5248bdfc5daSXin Ji MIPI_PHY_CONTROL_3, val); 5258bdfc5daSXin Ji 5268bdfc5daSXin Ji /* 5278bdfc5daSXin Ji * Decreased HS prepare timing delay from 160ns to 80ns work with 5288bdfc5daSXin Ji * a) Dragon board 810 series (Qualcomm AP) 5298bdfc5daSXin Ji * b) Moving Pixel DSI source (PG3A pattern generator + 5308bdfc5daSXin Ji * P332 D-PHY Probe) default D-PHY timing 5318bdfc5daSXin Ji * 5ns/step 5328bdfc5daSXin Ji */ 5338bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5348bdfc5daSXin Ji MIPI_TIME_HS_PRPR, 0x10); 5358bdfc5daSXin Ji 5368bdfc5daSXin Ji /* Enable DSI mode*/ 5378bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 5388bdfc5daSXin Ji SELECT_DSI << MIPI_DPI_SELECT); 5398bdfc5daSXin Ji 5408bdfc5daSXin Ji ret |= anx7625_dsi_video_timing_config(ctx); 5418bdfc5daSXin Ji if (ret < 0) { 5428bdfc5daSXin Ji DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 5438bdfc5daSXin Ji return ret; 5448bdfc5daSXin Ji } 5458bdfc5daSXin Ji 5468bdfc5daSXin Ji /* Toggle m, n ready */ 5478bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 5488bdfc5daSXin Ji ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 5498bdfc5daSXin Ji usleep_range(1000, 1100); 5508bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 5518bdfc5daSXin Ji MIPI_M_NUM_READY | MIPI_N_NUM_READY); 5528bdfc5daSXin Ji 5538bdfc5daSXin Ji /* Configure integer stable register */ 5548bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5558bdfc5daSXin Ji MIPI_VIDEO_STABLE_CNT, 0x02); 5568bdfc5daSXin Ji /* Power on MIPI RX */ 5578bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5588bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x00); 5598bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5608bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x80); 5618bdfc5daSXin Ji 5628bdfc5daSXin Ji if (ret < 0) 5638bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 5648bdfc5daSXin Ji 5658bdfc5daSXin Ji return ret; 5668bdfc5daSXin Ji } 5678bdfc5daSXin Ji 5688bdfc5daSXin Ji static int anx7625_dsi_config(struct anx7625_data *ctx) 5698bdfc5daSXin Ji { 5708bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5718bdfc5daSXin Ji int ret; 5728bdfc5daSXin Ji 5738bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 5748bdfc5daSXin Ji 5758bdfc5daSXin Ji /* DSC disable */ 5768bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 5778bdfc5daSXin Ji R_DSC_CTRL_0, ~DSC_EN); 5788bdfc5daSXin Ji 5798bdfc5daSXin Ji ret |= anx7625_api_dsi_config(ctx); 5808bdfc5daSXin Ji 5818bdfc5daSXin Ji if (ret < 0) { 5828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 5838bdfc5daSXin Ji return ret; 5848bdfc5daSXin Ji } 5858bdfc5daSXin Ji 5868bdfc5daSXin Ji /* Set MIPI RX EN */ 5878bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 5888bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 5898bdfc5daSXin Ji /* Clear mute flag */ 5908bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 5918bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 5928bdfc5daSXin Ji if (ret < 0) 5938bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 5948bdfc5daSXin Ji else 5958bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 5968bdfc5daSXin Ji 5978bdfc5daSXin Ji return ret; 5988bdfc5daSXin Ji } 5998bdfc5daSXin Ji 6008bdfc5daSXin Ji static void anx7625_dp_start(struct anx7625_data *ctx) 6018bdfc5daSXin Ji { 6028bdfc5daSXin Ji int ret; 6038bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6048bdfc5daSXin Ji 6058bdfc5daSXin Ji if (!ctx->display_timing_valid) { 6068bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 6078bdfc5daSXin Ji return; 6088bdfc5daSXin Ji } 6098bdfc5daSXin Ji 6108bdfc5daSXin Ji anx7625_config_audio_input(ctx); 6118bdfc5daSXin Ji 6128bdfc5daSXin Ji ret = anx7625_dsi_config(ctx); 6138bdfc5daSXin Ji 6148bdfc5daSXin Ji if (ret < 0) 6158bdfc5daSXin Ji DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 6168bdfc5daSXin Ji } 6178bdfc5daSXin Ji 6188bdfc5daSXin Ji static void anx7625_dp_stop(struct anx7625_data *ctx) 6198bdfc5daSXin Ji { 6208bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6218bdfc5daSXin Ji int ret; 6228bdfc5daSXin Ji 6238bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 6248bdfc5daSXin Ji 6258bdfc5daSXin Ji /* 6268bdfc5daSXin Ji * Video disable: 0x72:08 bit 7 = 0; 6278bdfc5daSXin Ji * Audio disable: 0x70:87 bit 0 = 0; 6288bdfc5daSXin Ji */ 6298bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 6308bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 6318bdfc5daSXin Ji 6328bdfc5daSXin Ji ret |= anx7625_video_mute_control(ctx, 1); 6338bdfc5daSXin Ji if (ret < 0) 6348bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 6358bdfc5daSXin Ji } 6368bdfc5daSXin Ji 6378bdfc5daSXin Ji static int sp_tx_rst_aux(struct anx7625_data *ctx) 6388bdfc5daSXin Ji { 6398bdfc5daSXin Ji int ret; 6408bdfc5daSXin Ji 6418bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 6428bdfc5daSXin Ji AUX_RST); 6438bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 6448bdfc5daSXin Ji ~AUX_RST); 6458bdfc5daSXin Ji return ret; 6468bdfc5daSXin Ji } 6478bdfc5daSXin Ji 6488bdfc5daSXin Ji static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 6498bdfc5daSXin Ji { 6508bdfc5daSXin Ji int ret; 6518bdfc5daSXin Ji 6528bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 6538bdfc5daSXin Ji AP_AUX_BUFF_START, offset); 6548bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 6558bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 6568bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 6578bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 6588bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 6598bdfc5daSXin Ji } 6608bdfc5daSXin Ji 6618bdfc5daSXin Ji static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 6628bdfc5daSXin Ji { 6638bdfc5daSXin Ji int ret; 6648bdfc5daSXin Ji 6658bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 6668bdfc5daSXin Ji AP_AUX_COMMAND, len_cmd); 6678bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 6688bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 6698bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 6708bdfc5daSXin Ji } 6718bdfc5daSXin Ji 6728bdfc5daSXin Ji static int sp_tx_get_edid_block(struct anx7625_data *ctx) 6738bdfc5daSXin Ji { 6748bdfc5daSXin Ji int c = 0; 6758bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6768bdfc5daSXin Ji 6778bdfc5daSXin Ji sp_tx_aux_wr(ctx, 0x7e); 6788bdfc5daSXin Ji sp_tx_aux_rd(ctx, 0x01); 6798bdfc5daSXin Ji c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 6808bdfc5daSXin Ji if (c < 0) { 6818bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 6828bdfc5daSXin Ji return -EIO; 6838bdfc5daSXin Ji } 6848bdfc5daSXin Ji 6858bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 6868bdfc5daSXin Ji 6878bdfc5daSXin Ji if (c > MAX_EDID_BLOCK) 6888bdfc5daSXin Ji c = 1; 6898bdfc5daSXin Ji 6908bdfc5daSXin Ji return c; 6918bdfc5daSXin Ji } 6928bdfc5daSXin Ji 6938bdfc5daSXin Ji static int edid_read(struct anx7625_data *ctx, 6948bdfc5daSXin Ji u8 offset, u8 *pblock_buf) 6958bdfc5daSXin Ji { 6968bdfc5daSXin Ji int ret, cnt; 6978bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6988bdfc5daSXin Ji 6998bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 7008bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 7018bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 7028bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 7038bdfc5daSXin Ji 7048bdfc5daSXin Ji if (ret) { 7058bdfc5daSXin Ji sp_tx_rst_aux(ctx); 7068bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 7078bdfc5daSXin Ji } else { 7088bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 7098bdfc5daSXin Ji AP_AUX_BUFF_START, 7108bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, 7118bdfc5daSXin Ji pblock_buf); 7128bdfc5daSXin Ji if (ret > 0) 7138bdfc5daSXin Ji break; 7148bdfc5daSXin Ji } 7158bdfc5daSXin Ji } 7168bdfc5daSXin Ji 7178bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 7188bdfc5daSXin Ji return -EIO; 7198bdfc5daSXin Ji 7208bdfc5daSXin Ji return 0; 7218bdfc5daSXin Ji } 7228bdfc5daSXin Ji 7238bdfc5daSXin Ji static int segments_edid_read(struct anx7625_data *ctx, 7248bdfc5daSXin Ji u8 segment, u8 *buf, u8 offset) 7258bdfc5daSXin Ji { 7268bdfc5daSXin Ji u8 cnt; 7278bdfc5daSXin Ji int ret; 7288bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 7298bdfc5daSXin Ji 7308bdfc5daSXin Ji /* Write address only */ 7318bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7328bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x30); 7338bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7348bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 7358bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7368bdfc5daSXin Ji AP_AUX_CTRL_STATUS, 7378bdfc5daSXin Ji AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 7388bdfc5daSXin Ji 7398bdfc5daSXin Ji ret |= wait_aux_op_finish(ctx); 7408bdfc5daSXin Ji /* Write segment address */ 7418bdfc5daSXin Ji ret |= sp_tx_aux_wr(ctx, segment); 7428bdfc5daSXin Ji /* Data read */ 7438bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7448bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 7458bdfc5daSXin Ji if (ret) { 7468bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 7478bdfc5daSXin Ji return ret; 7488bdfc5daSXin Ji } 7498bdfc5daSXin Ji 7508bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 7518bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 7528bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 7538bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 7548bdfc5daSXin Ji 7558bdfc5daSXin Ji if (ret) { 7568bdfc5daSXin Ji ret = sp_tx_rst_aux(ctx); 7578bdfc5daSXin Ji DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 7588bdfc5daSXin Ji } else { 7598bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 7608bdfc5daSXin Ji AP_AUX_BUFF_START, 7618bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, buf); 7628bdfc5daSXin Ji if (ret > 0) 7638bdfc5daSXin Ji break; 7648bdfc5daSXin Ji } 7658bdfc5daSXin Ji } 7668bdfc5daSXin Ji 7678bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 7688bdfc5daSXin Ji return -EIO; 7698bdfc5daSXin Ji 7708bdfc5daSXin Ji return 0; 7718bdfc5daSXin Ji } 7728bdfc5daSXin Ji 7738bdfc5daSXin Ji static int sp_tx_edid_read(struct anx7625_data *ctx, 7748bdfc5daSXin Ji u8 *pedid_blocks_buf) 7758bdfc5daSXin Ji { 7768bdfc5daSXin Ji u8 offset, edid_pos; 7778bdfc5daSXin Ji int count, blocks_num; 7788bdfc5daSXin Ji u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 7798bdfc5daSXin Ji u8 i, j; 7808bdfc5daSXin Ji u8 g_edid_break = 0; 7818bdfc5daSXin Ji int ret; 7828bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 7838bdfc5daSXin Ji 7848bdfc5daSXin Ji /* Address initial */ 7858bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7868bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 7878bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7888bdfc5daSXin Ji AP_AUX_ADDR_15_8, 0); 7898bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 7908bdfc5daSXin Ji AP_AUX_ADDR_19_16, 0xf0); 7918bdfc5daSXin Ji if (ret < 0) { 7928bdfc5daSXin Ji DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 7938bdfc5daSXin Ji return -EIO; 7948bdfc5daSXin Ji } 7958bdfc5daSXin Ji 7968bdfc5daSXin Ji blocks_num = sp_tx_get_edid_block(ctx); 7978bdfc5daSXin Ji if (blocks_num < 0) 7988bdfc5daSXin Ji return blocks_num; 7998bdfc5daSXin Ji 8008bdfc5daSXin Ji count = 0; 8018bdfc5daSXin Ji 8028bdfc5daSXin Ji do { 8038bdfc5daSXin Ji switch (count) { 8048bdfc5daSXin Ji case 0: 8058bdfc5daSXin Ji case 1: 8068bdfc5daSXin Ji for (i = 0; i < 8; i++) { 8078bdfc5daSXin Ji offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 8088bdfc5daSXin Ji g_edid_break = edid_read(ctx, offset, 8098bdfc5daSXin Ji pblock_buf); 8108bdfc5daSXin Ji 8118bdfc5daSXin Ji if (g_edid_break) 8128bdfc5daSXin Ji break; 8138bdfc5daSXin Ji 8148bdfc5daSXin Ji memcpy(&pedid_blocks_buf[offset], 8158bdfc5daSXin Ji pblock_buf, 8168bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 8178bdfc5daSXin Ji } 8188bdfc5daSXin Ji 8198bdfc5daSXin Ji break; 8208bdfc5daSXin Ji case 2: 8218bdfc5daSXin Ji offset = 0x00; 8228bdfc5daSXin Ji 8238bdfc5daSXin Ji for (j = 0; j < 8; j++) { 8248bdfc5daSXin Ji edid_pos = (j + count * 8) * 8258bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 8268bdfc5daSXin Ji 8278bdfc5daSXin Ji if (g_edid_break == 1) 8288bdfc5daSXin Ji break; 8298bdfc5daSXin Ji 8308bdfc5daSXin Ji segments_edid_read(ctx, count / 2, 8318bdfc5daSXin Ji pblock_buf, offset); 8328bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 8338bdfc5daSXin Ji pblock_buf, 8348bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 8358bdfc5daSXin Ji offset = offset + 0x10; 8368bdfc5daSXin Ji } 8378bdfc5daSXin Ji 8388bdfc5daSXin Ji break; 8398bdfc5daSXin Ji case 3: 8408bdfc5daSXin Ji offset = 0x80; 8418bdfc5daSXin Ji 8428bdfc5daSXin Ji for (j = 0; j < 8; j++) { 8438bdfc5daSXin Ji edid_pos = (j + count * 8) * 8448bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 8458bdfc5daSXin Ji if (g_edid_break == 1) 8468bdfc5daSXin Ji break; 8478bdfc5daSXin Ji 8488bdfc5daSXin Ji segments_edid_read(ctx, count / 2, 8498bdfc5daSXin Ji pblock_buf, offset); 8508bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 8518bdfc5daSXin Ji pblock_buf, 8528bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 8538bdfc5daSXin Ji offset = offset + 0x10; 8548bdfc5daSXin Ji } 8558bdfc5daSXin Ji 8568bdfc5daSXin Ji break; 8578bdfc5daSXin Ji default: 8588bdfc5daSXin Ji break; 8598bdfc5daSXin Ji } 8608bdfc5daSXin Ji 8618bdfc5daSXin Ji count++; 8628bdfc5daSXin Ji 8638bdfc5daSXin Ji } while (blocks_num >= count); 8648bdfc5daSXin Ji 8658bdfc5daSXin Ji /* Check edid data */ 8668bdfc5daSXin Ji if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 8678bdfc5daSXin Ji DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 8688bdfc5daSXin Ji return -EINVAL; 8698bdfc5daSXin Ji } 8708bdfc5daSXin Ji 8718bdfc5daSXin Ji /* Reset aux channel */ 8728bdfc5daSXin Ji sp_tx_rst_aux(ctx); 8738bdfc5daSXin Ji 8748bdfc5daSXin Ji return (blocks_num + 1); 8758bdfc5daSXin Ji } 8768bdfc5daSXin Ji 8778bdfc5daSXin Ji static void anx7625_power_on(struct anx7625_data *ctx) 8788bdfc5daSXin Ji { 8798bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 8806c744983SHsin-Yi Wang int ret, i; 8818bdfc5daSXin Ji 8828bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 8838bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 8848bdfc5daSXin Ji return; 8858bdfc5daSXin Ji } 8868bdfc5daSXin Ji 8876c744983SHsin-Yi Wang for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 8886c744983SHsin-Yi Wang ret = regulator_enable(ctx->pdata.supplies[i].consumer); 8896c744983SHsin-Yi Wang if (ret < 0) { 8906c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 8916c744983SHsin-Yi Wang i, ret); 8926c744983SHsin-Yi Wang goto reg_err; 8936c744983SHsin-Yi Wang } 8946c744983SHsin-Yi Wang usleep_range(2000, 2100); 8956c744983SHsin-Yi Wang } 8966c744983SHsin-Yi Wang 8971fcf24fbSHsin-Yi Wang usleep_range(11000, 12000); 8986c744983SHsin-Yi Wang 8998bdfc5daSXin Ji /* Power on pin enable */ 9008bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 1); 9018bdfc5daSXin Ji usleep_range(10000, 11000); 9028bdfc5daSXin Ji /* Power reset pin enable */ 9038bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 1); 9048bdfc5daSXin Ji usleep_range(10000, 11000); 9058bdfc5daSXin Ji 9068bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 9076c744983SHsin-Yi Wang return; 9086c744983SHsin-Yi Wang reg_err: 9096c744983SHsin-Yi Wang for (--i; i >= 0; i--) 9106c744983SHsin-Yi Wang regulator_disable(ctx->pdata.supplies[i].consumer); 9118bdfc5daSXin Ji } 9128bdfc5daSXin Ji 9138bdfc5daSXin Ji static void anx7625_power_standby(struct anx7625_data *ctx) 9148bdfc5daSXin Ji { 9158bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9166c744983SHsin-Yi Wang int ret; 9178bdfc5daSXin Ji 9188bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 9198bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 9208bdfc5daSXin Ji return; 9218bdfc5daSXin Ji } 9228bdfc5daSXin Ji 9238bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 0); 9248bdfc5daSXin Ji usleep_range(1000, 1100); 9258bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 0); 9268bdfc5daSXin Ji usleep_range(1000, 1100); 9276c744983SHsin-Yi Wang 9286c744983SHsin-Yi Wang ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 9296c744983SHsin-Yi Wang ctx->pdata.supplies); 9306c744983SHsin-Yi Wang if (ret < 0) 9316c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 9326c744983SHsin-Yi Wang 9338bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 9348bdfc5daSXin Ji } 9358bdfc5daSXin Ji 9368bdfc5daSXin Ji /* Basic configurations of ANX7625 */ 9378bdfc5daSXin Ji static void anx7625_config(struct anx7625_data *ctx) 9388bdfc5daSXin Ji { 9398bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9408bdfc5daSXin Ji XTAL_FRQ_SEL, XTAL_FRQ_27M); 9418bdfc5daSXin Ji } 9428bdfc5daSXin Ji 9438bdfc5daSXin Ji static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 9448bdfc5daSXin Ji { 9458bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9468bdfc5daSXin Ji int ret; 9478bdfc5daSXin Ji 9488bdfc5daSXin Ji /* Reset main ocm */ 9498bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 9508bdfc5daSXin Ji /* Disable PD */ 9518bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9528bdfc5daSXin Ji AP_AV_STATUS, AP_DISABLE_PD); 9538bdfc5daSXin Ji /* Release main ocm */ 9548bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 9558bdfc5daSXin Ji 9568bdfc5daSXin Ji if (ret < 0) 9578bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 9588bdfc5daSXin Ji else 9598bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 9608bdfc5daSXin Ji } 9618bdfc5daSXin Ji 9628bdfc5daSXin Ji static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 9638bdfc5daSXin Ji { 9648bdfc5daSXin Ji int ret; 9658bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9668bdfc5daSXin Ji 9678bdfc5daSXin Ji /* Check interface workable */ 9688bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 9698bdfc5daSXin Ji FLASH_LOAD_STA); 9708bdfc5daSXin Ji if (ret < 0) { 9718bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 9728bdfc5daSXin Ji return ret; 9738bdfc5daSXin Ji } 9748bdfc5daSXin Ji if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 9758bdfc5daSXin Ji return -ENODEV; 9768bdfc5daSXin Ji 9778bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 9788bdfc5daSXin Ji 9798bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 9808bdfc5daSXin Ji anx7625_reg_read(ctx, 9818bdfc5daSXin Ji ctx->i2c.rx_p0_client, 9828bdfc5daSXin Ji OCM_FW_VERSION), 9838bdfc5daSXin Ji anx7625_reg_read(ctx, 9848bdfc5daSXin Ji ctx->i2c.rx_p0_client, 9858bdfc5daSXin Ji OCM_FW_REVERSION)); 9868bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 9878bdfc5daSXin Ji ANX7625_DRV_VERSION); 9888bdfc5daSXin Ji 9898bdfc5daSXin Ji return 0; 9908bdfc5daSXin Ji } 9918bdfc5daSXin Ji 9928bdfc5daSXin Ji static void anx7625_power_on_init(struct anx7625_data *ctx) 9938bdfc5daSXin Ji { 9948bdfc5daSXin Ji int retry_count, i; 9958bdfc5daSXin Ji 9968bdfc5daSXin Ji for (retry_count = 0; retry_count < 3; retry_count++) { 9978bdfc5daSXin Ji anx7625_power_on(ctx); 9988bdfc5daSXin Ji anx7625_config(ctx); 9998bdfc5daSXin Ji 10008bdfc5daSXin Ji for (i = 0; i < OCM_LOADING_TIME; i++) { 10018bdfc5daSXin Ji if (!anx7625_ocm_loading_check(ctx)) 10028bdfc5daSXin Ji return; 10038bdfc5daSXin Ji usleep_range(1000, 1100); 10048bdfc5daSXin Ji } 10058bdfc5daSXin Ji anx7625_power_standby(ctx); 10068bdfc5daSXin Ji } 10078bdfc5daSXin Ji } 10088bdfc5daSXin Ji 10098bdfc5daSXin Ji static void anx7625_init_gpio(struct anx7625_data *platform) 10108bdfc5daSXin Ji { 10118bdfc5daSXin Ji struct device *dev = &platform->client->dev; 10128bdfc5daSXin Ji 10138bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 10148bdfc5daSXin Ji 10158bdfc5daSXin Ji /* Gpio for chip power enable */ 10168bdfc5daSXin Ji platform->pdata.gpio_p_on = 10178bdfc5daSXin Ji devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 10188bdfc5daSXin Ji /* Gpio for chip reset */ 10198bdfc5daSXin Ji platform->pdata.gpio_reset = 10208bdfc5daSXin Ji devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 10218bdfc5daSXin Ji 10228bdfc5daSXin Ji if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 10238bdfc5daSXin Ji platform->pdata.low_power_mode = 1; 10248bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 10258bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_p_on), 10268bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_reset)); 10278bdfc5daSXin Ji } else { 10288bdfc5daSXin Ji platform->pdata.low_power_mode = 0; 10298bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 10308bdfc5daSXin Ji } 10318bdfc5daSXin Ji } 10328bdfc5daSXin Ji 10338bdfc5daSXin Ji static void anx7625_stop_dp_work(struct anx7625_data *ctx) 10348bdfc5daSXin Ji { 10358bdfc5daSXin Ji ctx->hpd_status = 0; 10368bdfc5daSXin Ji ctx->hpd_high_cnt = 0; 10378bdfc5daSXin Ji ctx->display_timing_valid = 0; 10388bdfc5daSXin Ji } 10398bdfc5daSXin Ji 10408bdfc5daSXin Ji static void anx7625_start_dp_work(struct anx7625_data *ctx) 10418bdfc5daSXin Ji { 10428bdfc5daSXin Ji int ret; 10438bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10448bdfc5daSXin Ji 10458bdfc5daSXin Ji if (ctx->hpd_high_cnt >= 2) { 10468bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 10478bdfc5daSXin Ji return; 10488bdfc5daSXin Ji } 10498bdfc5daSXin Ji 10508bdfc5daSXin Ji ctx->hpd_high_cnt++; 10518bdfc5daSXin Ji 10528bdfc5daSXin Ji /* Not support HDCP */ 10538bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 10548bdfc5daSXin Ji 10558bdfc5daSXin Ji /* Try auth flag */ 10568bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 10578bdfc5daSXin Ji /* Interrupt for DRM */ 10588bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 10598bdfc5daSXin Ji if (ret < 0) 10608bdfc5daSXin Ji return; 10618bdfc5daSXin Ji 10628bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 10638bdfc5daSXin Ji if (ret < 0) 10648bdfc5daSXin Ji return; 10658bdfc5daSXin Ji 10668bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 10678bdfc5daSXin Ji } 10688bdfc5daSXin Ji 10698bdfc5daSXin Ji static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 10708bdfc5daSXin Ji { 10718bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 10728bdfc5daSXin Ji } 10738bdfc5daSXin Ji 10748bdfc5daSXin Ji static void anx7625_hpd_polling(struct anx7625_data *ctx) 10758bdfc5daSXin Ji { 10768bdfc5daSXin Ji int ret, val; 10778bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10788bdfc5daSXin Ji 10798bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 10808bdfc5daSXin Ji ctx, val, 10818bdfc5daSXin Ji ((val & HPD_STATUS) || (val < 0)), 10828bdfc5daSXin Ji 5000, 10838bdfc5daSXin Ji 5000 * 100); 10848bdfc5daSXin Ji if (ret) { 108560487584SPi-Hsun Shih DRM_DEV_ERROR(dev, "no hpd.\n"); 108660487584SPi-Hsun Shih return; 108760487584SPi-Hsun Shih } 108860487584SPi-Hsun Shih 108960487584SPi-Hsun Shih DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 10908bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 10918bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 10928bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10938bdfc5daSXin Ji INTERFACE_CHANGE_INT, 0); 10948bdfc5daSXin Ji 10958bdfc5daSXin Ji anx7625_start_dp_work(ctx); 10968bdfc5daSXin Ji 109760487584SPi-Hsun Shih if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 109860487584SPi-Hsun Shih drm_helper_hpd_irq_event(ctx->bridge.dev); 10998bdfc5daSXin Ji } 11008bdfc5daSXin Ji 11018bdfc5daSXin Ji static void anx7625_remove_edid(struct anx7625_data *ctx) 11028bdfc5daSXin Ji { 11038bdfc5daSXin Ji ctx->slimport_edid_p.edid_block_num = -1; 11048bdfc5daSXin Ji } 11058bdfc5daSXin Ji 11068bdfc5daSXin Ji static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 11078bdfc5daSXin Ji { 11088bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11098bdfc5daSXin Ji 11108bdfc5daSXin Ji /* HPD changed */ 11118bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 11128bdfc5daSXin Ji (u32)on); 11138bdfc5daSXin Ji 11148bdfc5daSXin Ji if (on == 0) { 11158bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 11168bdfc5daSXin Ji anx7625_remove_edid(ctx); 11178bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 11188bdfc5daSXin Ji } else { 11198bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 11208bdfc5daSXin Ji anx7625_start_dp_work(ctx); 11218bdfc5daSXin Ji } 11228bdfc5daSXin Ji 11238bdfc5daSXin Ji ctx->hpd_status = 1; 11248bdfc5daSXin Ji } 11258bdfc5daSXin Ji 11268bdfc5daSXin Ji static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 11278bdfc5daSXin Ji { 11288bdfc5daSXin Ji int intr_vector, status; 11298bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11308bdfc5daSXin Ji 11318bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 11328bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 11338bdfc5daSXin Ji if (status < 0) { 11348bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 11358bdfc5daSXin Ji return status; 11368bdfc5daSXin Ji } 11378bdfc5daSXin Ji 11388bdfc5daSXin Ji intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 11398bdfc5daSXin Ji INTERFACE_CHANGE_INT); 11408bdfc5daSXin Ji if (intr_vector < 0) { 11418bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 11428bdfc5daSXin Ji return intr_vector; 11438bdfc5daSXin Ji } 11448bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 11458bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11468bdfc5daSXin Ji INTERFACE_CHANGE_INT, 11478bdfc5daSXin Ji intr_vector & (~intr_vector)); 11488bdfc5daSXin Ji if (status < 0) { 11498bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 11508bdfc5daSXin Ji return status; 11518bdfc5daSXin Ji } 11528bdfc5daSXin Ji 11538bdfc5daSXin Ji if (!(intr_vector & HPD_STATUS_CHANGE)) 11548bdfc5daSXin Ji return -ENOENT; 11558bdfc5daSXin Ji 11568bdfc5daSXin Ji status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 11578bdfc5daSXin Ji SYSTEM_STSTUS); 11588bdfc5daSXin Ji if (status < 0) { 11598bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 11608bdfc5daSXin Ji return status; 11618bdfc5daSXin Ji } 11628bdfc5daSXin Ji 11638bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 11648bdfc5daSXin Ji dp_hpd_change_handler(ctx, status & HPD_STATUS); 11658bdfc5daSXin Ji 11668bdfc5daSXin Ji return 0; 11678bdfc5daSXin Ji } 11688bdfc5daSXin Ji 11698bdfc5daSXin Ji static void anx7625_work_func(struct work_struct *work) 11708bdfc5daSXin Ji { 11718bdfc5daSXin Ji int event; 11728bdfc5daSXin Ji struct anx7625_data *ctx = container_of(work, 11738bdfc5daSXin Ji struct anx7625_data, work); 11748bdfc5daSXin Ji 11758bdfc5daSXin Ji mutex_lock(&ctx->lock); 117660487584SPi-Hsun Shih 117760487584SPi-Hsun Shih if (pm_runtime_suspended(&ctx->client->dev)) 117860487584SPi-Hsun Shih goto unlock; 117960487584SPi-Hsun Shih 11808bdfc5daSXin Ji event = anx7625_hpd_change_detect(ctx); 11818bdfc5daSXin Ji if (event < 0) 118260487584SPi-Hsun Shih goto unlock; 11838bdfc5daSXin Ji 11848bdfc5daSXin Ji if (ctx->bridge_attached) 11858bdfc5daSXin Ji drm_helper_hpd_irq_event(ctx->bridge.dev); 118660487584SPi-Hsun Shih 118760487584SPi-Hsun Shih unlock: 118860487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 11898bdfc5daSXin Ji } 11908bdfc5daSXin Ji 11918bdfc5daSXin Ji static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 11928bdfc5daSXin Ji { 11938bdfc5daSXin Ji struct anx7625_data *ctx = (struct anx7625_data *)data; 11948bdfc5daSXin Ji 11958bdfc5daSXin Ji queue_work(ctx->workqueue, &ctx->work); 11968bdfc5daSXin Ji 11978bdfc5daSXin Ji return IRQ_HANDLED; 11988bdfc5daSXin Ji } 11998bdfc5daSXin Ji 12008bdfc5daSXin Ji static int anx7625_parse_dt(struct device *dev, 12018bdfc5daSXin Ji struct anx7625_platform_data *pdata) 12028bdfc5daSXin Ji { 12038bdfc5daSXin Ji struct device_node *np = dev->of_node; 12048bdfc5daSXin Ji struct drm_panel *panel; 12058bdfc5daSXin Ji int ret; 12068bdfc5daSXin Ji 12078bdfc5daSXin Ji pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 12088bdfc5daSXin Ji if (!pdata->mipi_host_node) { 12098bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 12108bdfc5daSXin Ji return -ENODEV; 12118bdfc5daSXin Ji } 12128bdfc5daSXin Ji 12138bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n"); 12148bdfc5daSXin Ji 12158bdfc5daSXin Ji ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 12168bdfc5daSXin Ji if (ret < 0) { 12178bdfc5daSXin Ji if (ret == -ENODEV) 12188bdfc5daSXin Ji return 0; 12198bdfc5daSXin Ji return ret; 12208bdfc5daSXin Ji } 12218bdfc5daSXin Ji if (!panel) 12228bdfc5daSXin Ji return -ENODEV; 12238bdfc5daSXin Ji 12248bdfc5daSXin Ji pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 12258bdfc5daSXin Ji if (IS_ERR(pdata->panel_bridge)) 12268bdfc5daSXin Ji return PTR_ERR(pdata->panel_bridge); 12278bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 12288bdfc5daSXin Ji 12298bdfc5daSXin Ji return 0; 12308bdfc5daSXin Ji } 12318bdfc5daSXin Ji 12328bdfc5daSXin Ji static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 12338bdfc5daSXin Ji { 12348bdfc5daSXin Ji return container_of(bridge, struct anx7625_data, bridge); 12358bdfc5daSXin Ji } 12368bdfc5daSXin Ji 12378bdfc5daSXin Ji static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 12388bdfc5daSXin Ji { 12398bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12408bdfc5daSXin Ji struct s_edid_data *p_edid = &ctx->slimport_edid_p; 12418bdfc5daSXin Ji int edid_num; 12428bdfc5daSXin Ji u8 *edid; 12438bdfc5daSXin Ji 12448bdfc5daSXin Ji edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 12458bdfc5daSXin Ji if (!edid) { 12468bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 12478bdfc5daSXin Ji return NULL; 12488bdfc5daSXin Ji } 12498bdfc5daSXin Ji 12508bdfc5daSXin Ji if (ctx->slimport_edid_p.edid_block_num > 0) { 12518bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 12528bdfc5daSXin Ji FOUR_BLOCK_SIZE); 12538bdfc5daSXin Ji return (struct edid *)edid; 12548bdfc5daSXin Ji } 12558bdfc5daSXin Ji 125660487584SPi-Hsun Shih pm_runtime_get_sync(dev); 12578bdfc5daSXin Ji edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 12583203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 12598bdfc5daSXin Ji 12608bdfc5daSXin Ji if (edid_num < 1) { 12618bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 12628bdfc5daSXin Ji kfree(edid); 12638bdfc5daSXin Ji return NULL; 12648bdfc5daSXin Ji } 12658bdfc5daSXin Ji 12668bdfc5daSXin Ji p_edid->edid_block_num = edid_num; 12678bdfc5daSXin Ji 12688bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 12698bdfc5daSXin Ji return (struct edid *)edid; 12708bdfc5daSXin Ji } 12718bdfc5daSXin Ji 12728bdfc5daSXin Ji static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 12738bdfc5daSXin Ji { 12748bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12758bdfc5daSXin Ji 12768bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n"); 12778bdfc5daSXin Ji 12788bdfc5daSXin Ji return connector_status_connected; 12798bdfc5daSXin Ji } 12808bdfc5daSXin Ji 12818bdfc5daSXin Ji static int anx7625_attach_dsi(struct anx7625_data *ctx) 12828bdfc5daSXin Ji { 12838bdfc5daSXin Ji struct mipi_dsi_device *dsi; 12848bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12858bdfc5daSXin Ji struct mipi_dsi_host *host; 12868bdfc5daSXin Ji const struct mipi_dsi_device_info info = { 12878bdfc5daSXin Ji .type = "anx7625", 12888bdfc5daSXin Ji .channel = 0, 12898bdfc5daSXin Ji .node = NULL, 12908bdfc5daSXin Ji }; 12918bdfc5daSXin Ji 12928bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 12938bdfc5daSXin Ji 12948bdfc5daSXin Ji host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 12958bdfc5daSXin Ji if (!host) { 12968bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 12978bdfc5daSXin Ji return -EINVAL; 12988bdfc5daSXin Ji } 12998bdfc5daSXin Ji 13008bdfc5daSXin Ji dsi = mipi_dsi_device_register_full(host, &info); 13018bdfc5daSXin Ji if (IS_ERR(dsi)) { 13028bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 13038bdfc5daSXin Ji return -EINVAL; 13048bdfc5daSXin Ji } 13058bdfc5daSXin Ji 13068bdfc5daSXin Ji dsi->lanes = 4; 13078bdfc5daSXin Ji dsi->format = MIPI_DSI_FMT_RGB888; 13088bdfc5daSXin Ji dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 13098bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 13108bdfc5daSXin Ji MIPI_DSI_MODE_EOT_PACKET | 13118bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_HSE; 13128bdfc5daSXin Ji 13138bdfc5daSXin Ji if (mipi_dsi_attach(dsi) < 0) { 13148bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 13158bdfc5daSXin Ji mipi_dsi_device_unregister(dsi); 13168bdfc5daSXin Ji return -EINVAL; 13178bdfc5daSXin Ji } 13188bdfc5daSXin Ji 13198bdfc5daSXin Ji ctx->dsi = dsi; 13208bdfc5daSXin Ji 13218bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 13228bdfc5daSXin Ji 13238bdfc5daSXin Ji return 0; 13248bdfc5daSXin Ji } 13258bdfc5daSXin Ji 13268bdfc5daSXin Ji static void anx7625_bridge_detach(struct drm_bridge *bridge) 13278bdfc5daSXin Ji { 13288bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 13298bdfc5daSXin Ji 13308bdfc5daSXin Ji if (ctx->dsi) { 13318bdfc5daSXin Ji mipi_dsi_detach(ctx->dsi); 13328bdfc5daSXin Ji mipi_dsi_device_unregister(ctx->dsi); 13338bdfc5daSXin Ji } 13348bdfc5daSXin Ji } 13358bdfc5daSXin Ji 13368bdfc5daSXin Ji static int anx7625_bridge_attach(struct drm_bridge *bridge, 13378bdfc5daSXin Ji enum drm_bridge_attach_flags flags) 13388bdfc5daSXin Ji { 13398bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 13408bdfc5daSXin Ji int err; 13418bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13428bdfc5daSXin Ji 13438bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 13448bdfc5daSXin Ji if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 13458bdfc5daSXin Ji return -EINVAL; 13468bdfc5daSXin Ji 13478bdfc5daSXin Ji if (!bridge->encoder) { 13488bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Parent encoder object not found"); 13498bdfc5daSXin Ji return -ENODEV; 13508bdfc5daSXin Ji } 13518bdfc5daSXin Ji 13528bdfc5daSXin Ji err = anx7625_attach_dsi(ctx); 13538bdfc5daSXin Ji if (err) { 13548bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); 13558bdfc5daSXin Ji return err; 13568bdfc5daSXin Ji } 13578bdfc5daSXin Ji 13588bdfc5daSXin Ji if (ctx->pdata.panel_bridge) { 13598bdfc5daSXin Ji err = drm_bridge_attach(bridge->encoder, 13608bdfc5daSXin Ji ctx->pdata.panel_bridge, 13618bdfc5daSXin Ji &ctx->bridge, flags); 1362*fb8d617fSLaurent Pinchart if (err) 13638bdfc5daSXin Ji return err; 13648bdfc5daSXin Ji } 13658bdfc5daSXin Ji 13668bdfc5daSXin Ji ctx->bridge_attached = 1; 13678bdfc5daSXin Ji 13688bdfc5daSXin Ji return 0; 13698bdfc5daSXin Ji } 13708bdfc5daSXin Ji 13718bdfc5daSXin Ji static enum drm_mode_status 13728bdfc5daSXin Ji anx7625_bridge_mode_valid(struct drm_bridge *bridge, 13738bdfc5daSXin Ji const struct drm_display_info *info, 13748bdfc5daSXin Ji const struct drm_display_mode *mode) 13758bdfc5daSXin Ji { 13768bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 13778bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13788bdfc5daSXin Ji 13798bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 13808bdfc5daSXin Ji 13818bdfc5daSXin Ji /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 13828bdfc5daSXin Ji if (mode->clock > SUPPORT_PIXEL_CLOCK) { 13838bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, 13848bdfc5daSXin Ji "drm mode invalid, pixelclock too high.\n"); 13858bdfc5daSXin Ji return MODE_CLOCK_HIGH; 13868bdfc5daSXin Ji } 13878bdfc5daSXin Ji 13888bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 13898bdfc5daSXin Ji 13908bdfc5daSXin Ji return MODE_OK; 13918bdfc5daSXin Ji } 13928bdfc5daSXin Ji 13938bdfc5daSXin Ji static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 13948bdfc5daSXin Ji const struct drm_display_mode *old_mode, 13958bdfc5daSXin Ji const struct drm_display_mode *mode) 13968bdfc5daSXin Ji { 13978bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 13988bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13998bdfc5daSXin Ji 14008bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 14018bdfc5daSXin Ji 14028bdfc5daSXin Ji ctx->dt.pixelclock.min = mode->clock; 14038bdfc5daSXin Ji ctx->dt.hactive.min = mode->hdisplay; 14048bdfc5daSXin Ji ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 14058bdfc5daSXin Ji ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 14068bdfc5daSXin Ji ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 14078bdfc5daSXin Ji ctx->dt.vactive.min = mode->vdisplay; 14088bdfc5daSXin Ji ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 14098bdfc5daSXin Ji ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 14108bdfc5daSXin Ji ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 14118bdfc5daSXin Ji 14128bdfc5daSXin Ji ctx->display_timing_valid = 1; 14138bdfc5daSXin Ji 14148bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 14158bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 14168bdfc5daSXin Ji ctx->dt.hactive.min, 14178bdfc5daSXin Ji ctx->dt.hsync_len.min, 14188bdfc5daSXin Ji ctx->dt.hfront_porch.min, 14198bdfc5daSXin Ji ctx->dt.hback_porch.min); 14208bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 14218bdfc5daSXin Ji ctx->dt.vactive.min, 14228bdfc5daSXin Ji ctx->dt.vsync_len.min, 14238bdfc5daSXin Ji ctx->dt.vfront_porch.min, 14248bdfc5daSXin Ji ctx->dt.vback_porch.min); 14258bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 14268bdfc5daSXin Ji mode->hdisplay, 14278bdfc5daSXin Ji mode->hsync_start); 14288bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 14298bdfc5daSXin Ji mode->hsync_end, 14308bdfc5daSXin Ji mode->htotal); 14318bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 14328bdfc5daSXin Ji mode->vdisplay, 14338bdfc5daSXin Ji mode->vsync_start); 14348bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 14358bdfc5daSXin Ji mode->vsync_end, 14368bdfc5daSXin Ji mode->vtotal); 14378bdfc5daSXin Ji } 14388bdfc5daSXin Ji 14398bdfc5daSXin Ji static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 14408bdfc5daSXin Ji const struct drm_display_mode *mode, 14418bdfc5daSXin Ji struct drm_display_mode *adj) 14428bdfc5daSXin Ji { 14438bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 14448bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14458bdfc5daSXin Ji u32 hsync, hfp, hbp, hblanking; 14468bdfc5daSXin Ji u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 14478bdfc5daSXin Ji u32 vref, adj_clock; 14488bdfc5daSXin Ji 14498bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 14508bdfc5daSXin Ji 14518bdfc5daSXin Ji hsync = mode->hsync_end - mode->hsync_start; 14528bdfc5daSXin Ji hfp = mode->hsync_start - mode->hdisplay; 14538bdfc5daSXin Ji hbp = mode->htotal - mode->hsync_end; 14548bdfc5daSXin Ji hblanking = mode->htotal - mode->hdisplay; 14558bdfc5daSXin Ji 14568bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 14578bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 14588bdfc5daSXin Ji hsync, hfp, hbp, adj->clock); 14598bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 14608bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 14618bdfc5daSXin Ji 14628bdfc5daSXin Ji adj_hfp = hfp; 14638bdfc5daSXin Ji adj_hsync = hsync; 14648bdfc5daSXin Ji adj_hbp = hbp; 14658bdfc5daSXin Ji adj_hblanking = hblanking; 14668bdfc5daSXin Ji 14678bdfc5daSXin Ji /* HFP needs to be even */ 14688bdfc5daSXin Ji if (hfp & 0x1) { 14698bdfc5daSXin Ji adj_hfp += 1; 14708bdfc5daSXin Ji adj_hblanking += 1; 14718bdfc5daSXin Ji } 14728bdfc5daSXin Ji 14738bdfc5daSXin Ji /* HBP needs to be even */ 14748bdfc5daSXin Ji if (hbp & 0x1) { 14758bdfc5daSXin Ji adj_hbp -= 1; 14768bdfc5daSXin Ji adj_hblanking -= 1; 14778bdfc5daSXin Ji } 14788bdfc5daSXin Ji 14798bdfc5daSXin Ji /* HSYNC needs to be even */ 14808bdfc5daSXin Ji if (hsync & 0x1) { 14818bdfc5daSXin Ji if (adj_hblanking < hblanking) 14828bdfc5daSXin Ji adj_hsync += 1; 14838bdfc5daSXin Ji else 14848bdfc5daSXin Ji adj_hsync -= 1; 14858bdfc5daSXin Ji } 14868bdfc5daSXin Ji 14878bdfc5daSXin Ji /* 14888bdfc5daSXin Ji * Once illegal timing detected, use default HFP, HSYNC, HBP 14898bdfc5daSXin Ji * This adjusting made for built-in eDP panel, for the externel 14908bdfc5daSXin Ji * DP monitor, may need return false. 14918bdfc5daSXin Ji */ 14928bdfc5daSXin Ji if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 14938bdfc5daSXin Ji adj_hsync = SYNC_LEN_DEF; 14948bdfc5daSXin Ji adj_hfp = HFP_HBP_DEF; 14958bdfc5daSXin Ji adj_hbp = HFP_HBP_DEF; 14968bdfc5daSXin Ji vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 14978bdfc5daSXin Ji if (hblanking < HBLANKING_MIN) { 14988bdfc5daSXin Ji delta_adj = HBLANKING_MIN - hblanking; 14998bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 15008bdfc5daSXin Ji adj->clock += DIV_ROUND_UP(adj_clock, 1000); 15018bdfc5daSXin Ji } else { 15028bdfc5daSXin Ji delta_adj = hblanking - HBLANKING_MIN; 15038bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 15048bdfc5daSXin Ji adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 15058bdfc5daSXin Ji } 15068bdfc5daSXin Ji 15078bdfc5daSXin Ji DRM_WARN("illegal hblanking timing, use default.\n"); 15088bdfc5daSXin Ji DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 15098bdfc5daSXin Ji } else if (adj_hfp < HP_MIN) { 15108bdfc5daSXin Ji /* Adjust hfp if hfp less than HP_MIN */ 15118bdfc5daSXin Ji delta_adj = HP_MIN - adj_hfp; 15128bdfc5daSXin Ji adj_hfp = HP_MIN; 15138bdfc5daSXin Ji 15148bdfc5daSXin Ji /* 15158bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP does not have enough 15168bdfc5daSXin Ji * space, adjust HSYNC length, otherwise adjust HBP 15178bdfc5daSXin Ji */ 15188bdfc5daSXin Ji if ((adj_hbp - delta_adj) < HP_MIN) 15198bdfc5daSXin Ji /* HBP not enough space */ 15208bdfc5daSXin Ji adj_hsync -= delta_adj; 15218bdfc5daSXin Ji else 15228bdfc5daSXin Ji adj_hbp -= delta_adj; 15238bdfc5daSXin Ji } else if (adj_hbp < HP_MIN) { 15248bdfc5daSXin Ji delta_adj = HP_MIN - adj_hbp; 15258bdfc5daSXin Ji adj_hbp = HP_MIN; 15268bdfc5daSXin Ji 15278bdfc5daSXin Ji /* 15288bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP hasn't enough space, 15298bdfc5daSXin Ji * adjust HSYNC length, otherwize adjust HBP 15308bdfc5daSXin Ji */ 15318bdfc5daSXin Ji if ((adj_hfp - delta_adj) < HP_MIN) 15328bdfc5daSXin Ji /* HFP not enough space */ 15338bdfc5daSXin Ji adj_hsync -= delta_adj; 15348bdfc5daSXin Ji else 15358bdfc5daSXin Ji adj_hfp -= delta_adj; 15368bdfc5daSXin Ji } 15378bdfc5daSXin Ji 15388bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 15398bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 15408bdfc5daSXin Ji adj_hsync, adj_hfp, adj_hbp, adj->clock); 15418bdfc5daSXin Ji 15428bdfc5daSXin Ji /* Reconstruct timing */ 15438bdfc5daSXin Ji adj->hsync_start = adj->hdisplay + adj_hfp; 15448bdfc5daSXin Ji adj->hsync_end = adj->hsync_start + adj_hsync; 15458bdfc5daSXin Ji adj->htotal = adj->hsync_end + adj_hbp; 15468bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 15478bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 15488bdfc5daSXin Ji 15498bdfc5daSXin Ji return true; 15508bdfc5daSXin Ji } 15518bdfc5daSXin Ji 15528bdfc5daSXin Ji static void anx7625_bridge_enable(struct drm_bridge *bridge) 15538bdfc5daSXin Ji { 15548bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 15558bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15568bdfc5daSXin Ji 15578bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 15588bdfc5daSXin Ji 155960487584SPi-Hsun Shih pm_runtime_get_sync(dev); 15608bdfc5daSXin Ji 15618bdfc5daSXin Ji anx7625_dp_start(ctx); 15628bdfc5daSXin Ji } 15638bdfc5daSXin Ji 15648bdfc5daSXin Ji static void anx7625_bridge_disable(struct drm_bridge *bridge) 15658bdfc5daSXin Ji { 15668bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 15678bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15688bdfc5daSXin Ji 15698bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 15708bdfc5daSXin Ji 15718bdfc5daSXin Ji anx7625_dp_stop(ctx); 15728bdfc5daSXin Ji 15733203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 15748bdfc5daSXin Ji } 15758bdfc5daSXin Ji 15768bdfc5daSXin Ji static enum drm_connector_status 15778bdfc5daSXin Ji anx7625_bridge_detect(struct drm_bridge *bridge) 15788bdfc5daSXin Ji { 15798bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 15808bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15818bdfc5daSXin Ji 15828bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 15838bdfc5daSXin Ji 15848bdfc5daSXin Ji return anx7625_sink_detect(ctx); 15858bdfc5daSXin Ji } 15868bdfc5daSXin Ji 15878bdfc5daSXin Ji static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 15888bdfc5daSXin Ji struct drm_connector *connector) 15898bdfc5daSXin Ji { 15908bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 15918bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15928bdfc5daSXin Ji 15938bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 15948bdfc5daSXin Ji 15958bdfc5daSXin Ji return anx7625_get_edid(ctx); 15968bdfc5daSXin Ji } 15978bdfc5daSXin Ji 15988bdfc5daSXin Ji static const struct drm_bridge_funcs anx7625_bridge_funcs = { 15998bdfc5daSXin Ji .attach = anx7625_bridge_attach, 16008bdfc5daSXin Ji .detach = anx7625_bridge_detach, 16018bdfc5daSXin Ji .disable = anx7625_bridge_disable, 16028bdfc5daSXin Ji .mode_valid = anx7625_bridge_mode_valid, 16038bdfc5daSXin Ji .mode_set = anx7625_bridge_mode_set, 16048bdfc5daSXin Ji .mode_fixup = anx7625_bridge_mode_fixup, 16058bdfc5daSXin Ji .enable = anx7625_bridge_enable, 16068bdfc5daSXin Ji .detect = anx7625_bridge_detect, 16078bdfc5daSXin Ji .get_edid = anx7625_bridge_get_edid, 16088bdfc5daSXin Ji }; 16098bdfc5daSXin Ji 16108bdfc5daSXin Ji static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 16118bdfc5daSXin Ji struct i2c_client *client) 16128bdfc5daSXin Ji { 16138bdfc5daSXin Ji ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 16148bdfc5daSXin Ji TX_P0_ADDR >> 1); 16158bdfc5daSXin Ji if (!ctx->i2c.tx_p0_client) 16168bdfc5daSXin Ji return -ENOMEM; 16178bdfc5daSXin Ji 16188bdfc5daSXin Ji ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 16198bdfc5daSXin Ji TX_P1_ADDR >> 1); 16208bdfc5daSXin Ji if (!ctx->i2c.tx_p1_client) 16218bdfc5daSXin Ji goto free_tx_p0; 16228bdfc5daSXin Ji 16238bdfc5daSXin Ji ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 16248bdfc5daSXin Ji TX_P2_ADDR >> 1); 16258bdfc5daSXin Ji if (!ctx->i2c.tx_p2_client) 16268bdfc5daSXin Ji goto free_tx_p1; 16278bdfc5daSXin Ji 16288bdfc5daSXin Ji ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 16298bdfc5daSXin Ji RX_P0_ADDR >> 1); 16308bdfc5daSXin Ji if (!ctx->i2c.rx_p0_client) 16318bdfc5daSXin Ji goto free_tx_p2; 16328bdfc5daSXin Ji 16338bdfc5daSXin Ji ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 16348bdfc5daSXin Ji RX_P1_ADDR >> 1); 16358bdfc5daSXin Ji if (!ctx->i2c.rx_p1_client) 16368bdfc5daSXin Ji goto free_rx_p0; 16378bdfc5daSXin Ji 16388bdfc5daSXin Ji ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 16398bdfc5daSXin Ji RX_P2_ADDR >> 1); 16408bdfc5daSXin Ji if (!ctx->i2c.rx_p2_client) 16418bdfc5daSXin Ji goto free_rx_p1; 16428bdfc5daSXin Ji 16438bdfc5daSXin Ji ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 16448bdfc5daSXin Ji TCPC_INTERFACE_ADDR >> 1); 16458bdfc5daSXin Ji if (!ctx->i2c.tcpc_client) 16468bdfc5daSXin Ji goto free_rx_p2; 16478bdfc5daSXin Ji 16488bdfc5daSXin Ji return 0; 16498bdfc5daSXin Ji 16508bdfc5daSXin Ji free_rx_p2: 16518bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 16528bdfc5daSXin Ji free_rx_p1: 16538bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 16548bdfc5daSXin Ji free_rx_p0: 16558bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 16568bdfc5daSXin Ji free_tx_p2: 16578bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 16588bdfc5daSXin Ji free_tx_p1: 16598bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 16608bdfc5daSXin Ji free_tx_p0: 16618bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 16628bdfc5daSXin Ji 16638bdfc5daSXin Ji return -ENOMEM; 16648bdfc5daSXin Ji } 16658bdfc5daSXin Ji 16668bdfc5daSXin Ji static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 16678bdfc5daSXin Ji { 16688bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 16698bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 16708bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 16718bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 16728bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 16738bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 16748bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tcpc_client); 16758bdfc5daSXin Ji } 16768bdfc5daSXin Ji 167760487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 167860487584SPi-Hsun Shih { 167960487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 168060487584SPi-Hsun Shih 168160487584SPi-Hsun Shih mutex_lock(&ctx->lock); 168260487584SPi-Hsun Shih 168360487584SPi-Hsun Shih anx7625_stop_dp_work(ctx); 168460487584SPi-Hsun Shih anx7625_power_standby(ctx); 168560487584SPi-Hsun Shih 168660487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 168760487584SPi-Hsun Shih 168860487584SPi-Hsun Shih return 0; 168960487584SPi-Hsun Shih } 169060487584SPi-Hsun Shih 169160487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 169260487584SPi-Hsun Shih { 169360487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 169460487584SPi-Hsun Shih 169560487584SPi-Hsun Shih mutex_lock(&ctx->lock); 169660487584SPi-Hsun Shih 169760487584SPi-Hsun Shih anx7625_power_on_init(ctx); 169860487584SPi-Hsun Shih anx7625_hpd_polling(ctx); 169960487584SPi-Hsun Shih 170060487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 170160487584SPi-Hsun Shih 170260487584SPi-Hsun Shih return 0; 170360487584SPi-Hsun Shih } 170460487584SPi-Hsun Shih 1705409776faSPi-Hsun Shih static int __maybe_unused anx7625_resume(struct device *dev) 1706409776faSPi-Hsun Shih { 1707409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 1708409776faSPi-Hsun Shih 1709409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 1710409776faSPi-Hsun Shih return 0; 1711409776faSPi-Hsun Shih 1712409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1713409776faSPi-Hsun Shih enable_irq(ctx->pdata.intp_irq); 1714409776faSPi-Hsun Shih anx7625_runtime_pm_resume(dev); 1715409776faSPi-Hsun Shih } 1716409776faSPi-Hsun Shih 1717409776faSPi-Hsun Shih return 0; 1718409776faSPi-Hsun Shih } 1719409776faSPi-Hsun Shih 1720409776faSPi-Hsun Shih static int __maybe_unused anx7625_suspend(struct device *dev) 1721409776faSPi-Hsun Shih { 1722409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 1723409776faSPi-Hsun Shih 1724409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 1725409776faSPi-Hsun Shih return 0; 1726409776faSPi-Hsun Shih 1727409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 1728409776faSPi-Hsun Shih anx7625_runtime_pm_suspend(dev); 1729409776faSPi-Hsun Shih disable_irq(ctx->pdata.intp_irq); 1730409776faSPi-Hsun Shih } 1731409776faSPi-Hsun Shih 1732409776faSPi-Hsun Shih return 0; 1733409776faSPi-Hsun Shih } 1734409776faSPi-Hsun Shih 173560487584SPi-Hsun Shih static const struct dev_pm_ops anx7625_pm_ops = { 1736409776faSPi-Hsun Shih SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 173760487584SPi-Hsun Shih SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 173860487584SPi-Hsun Shih anx7625_runtime_pm_resume, NULL) 173960487584SPi-Hsun Shih }; 174060487584SPi-Hsun Shih 17418bdfc5daSXin Ji static int anx7625_i2c_probe(struct i2c_client *client, 17428bdfc5daSXin Ji const struct i2c_device_id *id) 17438bdfc5daSXin Ji { 17448bdfc5daSXin Ji struct anx7625_data *platform; 17458bdfc5daSXin Ji struct anx7625_platform_data *pdata; 17468bdfc5daSXin Ji int ret = 0; 17478bdfc5daSXin Ji struct device *dev = &client->dev; 17488bdfc5daSXin Ji 17498bdfc5daSXin Ji if (!i2c_check_functionality(client->adapter, 17508bdfc5daSXin Ji I2C_FUNC_SMBUS_I2C_BLOCK)) { 17518bdfc5daSXin Ji DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 17528bdfc5daSXin Ji return -ENODEV; 17538bdfc5daSXin Ji } 17548bdfc5daSXin Ji 17558bdfc5daSXin Ji platform = kzalloc(sizeof(*platform), GFP_KERNEL); 17568bdfc5daSXin Ji if (!platform) { 17578bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 17588bdfc5daSXin Ji return -ENOMEM; 17598bdfc5daSXin Ji } 17608bdfc5daSXin Ji 17618bdfc5daSXin Ji pdata = &platform->pdata; 17628bdfc5daSXin Ji 17638bdfc5daSXin Ji ret = anx7625_parse_dt(dev, pdata); 17648bdfc5daSXin Ji if (ret) { 17658bdfc5daSXin Ji if (ret != -EPROBE_DEFER) 17668bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 17678bdfc5daSXin Ji goto free_platform; 17688bdfc5daSXin Ji } 17698bdfc5daSXin Ji 17708bdfc5daSXin Ji platform->client = client; 17718bdfc5daSXin Ji i2c_set_clientdata(client, platform); 17728bdfc5daSXin Ji 17736c744983SHsin-Yi Wang pdata->supplies[0].supply = "vdd10"; 17746c744983SHsin-Yi Wang pdata->supplies[1].supply = "vdd18"; 17756c744983SHsin-Yi Wang pdata->supplies[2].supply = "vdd33"; 17766c744983SHsin-Yi Wang ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 17776c744983SHsin-Yi Wang pdata->supplies); 17786c744983SHsin-Yi Wang if (ret) { 17796c744983SHsin-Yi Wang DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 17806c744983SHsin-Yi Wang return ret; 17816c744983SHsin-Yi Wang } 17828bdfc5daSXin Ji anx7625_init_gpio(platform); 17838bdfc5daSXin Ji 17848bdfc5daSXin Ji mutex_init(&platform->lock); 17858bdfc5daSXin Ji 17868bdfc5daSXin Ji platform->pdata.intp_irq = client->irq; 17878bdfc5daSXin Ji if (platform->pdata.intp_irq) { 17888bdfc5daSXin Ji INIT_WORK(&platform->work, anx7625_work_func); 1789f03ab662SPi-Hsun Shih platform->workqueue = alloc_workqueue("anx7625_work", 1790f03ab662SPi-Hsun Shih WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 17918bdfc5daSXin Ji if (!platform->workqueue) { 17928bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create work queue\n"); 17938bdfc5daSXin Ji ret = -ENOMEM; 17948bdfc5daSXin Ji goto free_platform; 17958bdfc5daSXin Ji } 17968bdfc5daSXin Ji 17978bdfc5daSXin Ji ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 17988bdfc5daSXin Ji NULL, anx7625_intr_hpd_isr, 17998bdfc5daSXin Ji IRQF_TRIGGER_FALLING | 18008bdfc5daSXin Ji IRQF_ONESHOT, 18018bdfc5daSXin Ji "anx7625-intp", platform); 18028bdfc5daSXin Ji if (ret) { 18038bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to request irq\n"); 18048bdfc5daSXin Ji goto free_wq; 18058bdfc5daSXin Ji } 18068bdfc5daSXin Ji } 18078bdfc5daSXin Ji 18088bdfc5daSXin Ji if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 18098bdfc5daSXin Ji ret = -ENOMEM; 18108bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 18118bdfc5daSXin Ji goto free_wq; 18128bdfc5daSXin Ji } 18138bdfc5daSXin Ji 181460487584SPi-Hsun Shih pm_runtime_enable(dev); 181560487584SPi-Hsun Shih 181660487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) { 18178bdfc5daSXin Ji anx7625_disable_pd_protocol(platform); 181860487584SPi-Hsun Shih pm_runtime_get_sync(dev); 18198bdfc5daSXin Ji } 18208bdfc5daSXin Ji 18218bdfc5daSXin Ji /* Add work function */ 18228bdfc5daSXin Ji if (platform->pdata.intp_irq) 18238bdfc5daSXin Ji queue_work(platform->workqueue, &platform->work); 18248bdfc5daSXin Ji 18258bdfc5daSXin Ji platform->bridge.funcs = &anx7625_bridge_funcs; 18268bdfc5daSXin Ji platform->bridge.of_node = client->dev.of_node; 18278bdfc5daSXin Ji platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 18288bdfc5daSXin Ji platform->bridge.type = DRM_MODE_CONNECTOR_eDP; 18298bdfc5daSXin Ji drm_bridge_add(&platform->bridge); 18308bdfc5daSXin Ji 18318bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 18328bdfc5daSXin Ji 18338bdfc5daSXin Ji return 0; 18348bdfc5daSXin Ji 18358bdfc5daSXin Ji free_wq: 18368bdfc5daSXin Ji if (platform->workqueue) 18378bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 18388bdfc5daSXin Ji 18398bdfc5daSXin Ji free_platform: 18408bdfc5daSXin Ji kfree(platform); 18418bdfc5daSXin Ji 18428bdfc5daSXin Ji return ret; 18438bdfc5daSXin Ji } 18448bdfc5daSXin Ji 18458bdfc5daSXin Ji static int anx7625_i2c_remove(struct i2c_client *client) 18468bdfc5daSXin Ji { 18478bdfc5daSXin Ji struct anx7625_data *platform = i2c_get_clientdata(client); 18488bdfc5daSXin Ji 18498bdfc5daSXin Ji drm_bridge_remove(&platform->bridge); 18508bdfc5daSXin Ji 18518bdfc5daSXin Ji if (platform->pdata.intp_irq) 18528bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 18538bdfc5daSXin Ji 185460487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) 185560487584SPi-Hsun Shih pm_runtime_put_sync_suspend(&client->dev); 185660487584SPi-Hsun Shih 18578bdfc5daSXin Ji anx7625_unregister_i2c_dummy_clients(platform); 18588bdfc5daSXin Ji 18598bdfc5daSXin Ji kfree(platform); 18608bdfc5daSXin Ji return 0; 18618bdfc5daSXin Ji } 18628bdfc5daSXin Ji 18638bdfc5daSXin Ji static const struct i2c_device_id anx7625_id[] = { 18648bdfc5daSXin Ji {"anx7625", 0}, 18658bdfc5daSXin Ji {} 18668bdfc5daSXin Ji }; 18678bdfc5daSXin Ji 18688bdfc5daSXin Ji MODULE_DEVICE_TABLE(i2c, anx7625_id); 18698bdfc5daSXin Ji 18708bdfc5daSXin Ji static const struct of_device_id anx_match_table[] = { 18718bdfc5daSXin Ji {.compatible = "analogix,anx7625",}, 18728bdfc5daSXin Ji {}, 18738bdfc5daSXin Ji }; 1874ad5fd900SYu Jiahua MODULE_DEVICE_TABLE(of, anx_match_table); 18758bdfc5daSXin Ji 18768bdfc5daSXin Ji static struct i2c_driver anx7625_driver = { 18778bdfc5daSXin Ji .driver = { 18788bdfc5daSXin Ji .name = "anx7625", 18798bdfc5daSXin Ji .of_match_table = anx_match_table, 188060487584SPi-Hsun Shih .pm = &anx7625_pm_ops, 18818bdfc5daSXin Ji }, 18828bdfc5daSXin Ji .probe = anx7625_i2c_probe, 18838bdfc5daSXin Ji .remove = anx7625_i2c_remove, 18848bdfc5daSXin Ji 18858bdfc5daSXin Ji .id_table = anx7625_id, 18868bdfc5daSXin Ji }; 18878bdfc5daSXin Ji 18888bdfc5daSXin Ji module_i2c_driver(anx7625_driver); 18898bdfc5daSXin Ji 18908bdfc5daSXin Ji MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 18918bdfc5daSXin Ji MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 18928bdfc5daSXin Ji MODULE_LICENSE("GPL v2"); 18938bdfc5daSXin Ji MODULE_VERSION(ANX7625_DRV_VERSION); 1894