18bdfc5daSXin Ji // SPDX-License-Identifier: GPL-2.0-only 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji #include <linux/gcd.h> 78bdfc5daSXin Ji #include <linux/gpio/consumer.h> 88bdfc5daSXin Ji #include <linux/i2c.h> 98bdfc5daSXin Ji #include <linux/interrupt.h> 108bdfc5daSXin Ji #include <linux/iopoll.h> 118bdfc5daSXin Ji #include <linux/kernel.h> 128bdfc5daSXin Ji #include <linux/module.h> 138bdfc5daSXin Ji #include <linux/mutex.h> 1460487584SPi-Hsun Shih #include <linux/pm_runtime.h> 156c744983SHsin-Yi Wang #include <linux/regulator/consumer.h> 168bdfc5daSXin Ji #include <linux/slab.h> 178bdfc5daSXin Ji #include <linux/types.h> 188bdfc5daSXin Ji #include <linux/workqueue.h> 198bdfc5daSXin Ji 208bdfc5daSXin Ji #include <linux/of_gpio.h> 218bdfc5daSXin Ji #include <linux/of_graph.h> 228bdfc5daSXin Ji #include <linux/of_platform.h> 238bdfc5daSXin Ji 248bdfc5daSXin Ji #include <drm/drm_atomic_helper.h> 258bdfc5daSXin Ji #include <drm/drm_bridge.h> 268bdfc5daSXin Ji #include <drm/drm_crtc_helper.h> 27adca62ecSHsin-Yi Wang #include <drm/dp/drm_dp_aux_bus.h> 285b529e8dSThomas Zimmermann #include <drm/dp/drm_dp_helper.h> 298bdfc5daSXin Ji #include <drm/drm_edid.h> 30cd1637c7SXin Ji #include <drm/drm_hdcp.h> 318bdfc5daSXin Ji #include <drm/drm_mipi_dsi.h> 328bdfc5daSXin Ji #include <drm/drm_of.h> 338bdfc5daSXin Ji #include <drm/drm_panel.h> 348bdfc5daSXin Ji #include <drm/drm_print.h> 358bdfc5daSXin Ji #include <drm/drm_probe_helper.h> 368bdfc5daSXin Ji 37fd0310b6SXin Ji #include <media/v4l2-fwnode.h> 38566fef12SXin Ji #include <sound/hdmi-codec.h> 398bdfc5daSXin Ji #include <video/display_timing.h> 408bdfc5daSXin Ji 418bdfc5daSXin Ji #include "anx7625.h" 428bdfc5daSXin Ji 438bdfc5daSXin Ji /* 448bdfc5daSXin Ji * There is a sync issue while access I2C register between AP(CPU) and 458bdfc5daSXin Ji * internal firmware(OCM), to avoid the race condition, AP should access 468bdfc5daSXin Ji * the reserved slave address before slave address occurs changes. 478bdfc5daSXin Ji */ 488bdfc5daSXin Ji static int i2c_access_workaround(struct anx7625_data *ctx, 498bdfc5daSXin Ji struct i2c_client *client) 508bdfc5daSXin Ji { 518bdfc5daSXin Ji u8 offset; 528bdfc5daSXin Ji struct device *dev = &client->dev; 538bdfc5daSXin Ji int ret; 548bdfc5daSXin Ji 558bdfc5daSXin Ji if (client == ctx->last_client) 568bdfc5daSXin Ji return 0; 578bdfc5daSXin Ji 588bdfc5daSXin Ji ctx->last_client = client; 598bdfc5daSXin Ji 608bdfc5daSXin Ji if (client == ctx->i2c.tcpc_client) 618bdfc5daSXin Ji offset = RSVD_00_ADDR; 628bdfc5daSXin Ji else if (client == ctx->i2c.tx_p0_client) 638bdfc5daSXin Ji offset = RSVD_D1_ADDR; 648bdfc5daSXin Ji else if (client == ctx->i2c.tx_p1_client) 658bdfc5daSXin Ji offset = RSVD_60_ADDR; 668bdfc5daSXin Ji else if (client == ctx->i2c.rx_p0_client) 678bdfc5daSXin Ji offset = RSVD_39_ADDR; 688bdfc5daSXin Ji else if (client == ctx->i2c.rx_p1_client) 698bdfc5daSXin Ji offset = RSVD_7F_ADDR; 708bdfc5daSXin Ji else 718bdfc5daSXin Ji offset = RSVD_00_ADDR; 728bdfc5daSXin Ji 738bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, offset, 0x00); 748bdfc5daSXin Ji if (ret < 0) 758bdfc5daSXin Ji DRM_DEV_ERROR(dev, 768bdfc5daSXin Ji "fail to access i2c id=%x\n:%x", 778bdfc5daSXin Ji client->addr, offset); 788bdfc5daSXin Ji 798bdfc5daSXin Ji return ret; 808bdfc5daSXin Ji } 818bdfc5daSXin Ji 828bdfc5daSXin Ji static int anx7625_reg_read(struct anx7625_data *ctx, 838bdfc5daSXin Ji struct i2c_client *client, u8 reg_addr) 848bdfc5daSXin Ji { 858bdfc5daSXin Ji int ret; 868bdfc5daSXin Ji struct device *dev = &client->dev; 878bdfc5daSXin Ji 888bdfc5daSXin Ji i2c_access_workaround(ctx, client); 898bdfc5daSXin Ji 908bdfc5daSXin Ji ret = i2c_smbus_read_byte_data(client, reg_addr); 918bdfc5daSXin Ji if (ret < 0) 928bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 938bdfc5daSXin Ji client->addr, reg_addr); 948bdfc5daSXin Ji 958bdfc5daSXin Ji return ret; 968bdfc5daSXin Ji } 978bdfc5daSXin Ji 988bdfc5daSXin Ji static int anx7625_reg_block_read(struct anx7625_data *ctx, 998bdfc5daSXin Ji struct i2c_client *client, 1008bdfc5daSXin Ji u8 reg_addr, u8 len, u8 *buf) 1018bdfc5daSXin Ji { 1028bdfc5daSXin Ji int ret; 1038bdfc5daSXin Ji struct device *dev = &client->dev; 1048bdfc5daSXin Ji 1058bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1068bdfc5daSXin Ji 1078bdfc5daSXin Ji ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 1088bdfc5daSXin Ji if (ret < 0) 1098bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 1108bdfc5daSXin Ji client->addr, reg_addr); 1118bdfc5daSXin Ji 1128bdfc5daSXin Ji return ret; 1138bdfc5daSXin Ji } 1148bdfc5daSXin Ji 1158bdfc5daSXin Ji static int anx7625_reg_write(struct anx7625_data *ctx, 1168bdfc5daSXin Ji struct i2c_client *client, 1178bdfc5daSXin Ji u8 reg_addr, u8 reg_val) 1188bdfc5daSXin Ji { 1198bdfc5daSXin Ji int ret; 1208bdfc5daSXin Ji struct device *dev = &client->dev; 1218bdfc5daSXin Ji 1228bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1238bdfc5daSXin Ji 1248bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 1258bdfc5daSXin Ji 1268bdfc5daSXin Ji if (ret < 0) 1278bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 1288bdfc5daSXin Ji client->addr, reg_addr); 1298bdfc5daSXin Ji 1308bdfc5daSXin Ji return ret; 1318bdfc5daSXin Ji } 1328bdfc5daSXin Ji 133548b512eSXin Ji static int anx7625_reg_block_write(struct anx7625_data *ctx, 134548b512eSXin Ji struct i2c_client *client, 135548b512eSXin Ji u8 reg_addr, u8 len, u8 *buf) 136548b512eSXin Ji { 137548b512eSXin Ji int ret; 138548b512eSXin Ji struct device *dev = &client->dev; 139548b512eSXin Ji 140548b512eSXin Ji i2c_access_workaround(ctx, client); 141548b512eSXin Ji 142548b512eSXin Ji ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 143548b512eSXin Ji if (ret < 0) 144548b512eSXin Ji dev_err(dev, "write i2c block failed id=%x\n:%x", 145548b512eSXin Ji client->addr, reg_addr); 146548b512eSXin Ji 147548b512eSXin Ji return ret; 148548b512eSXin Ji } 149548b512eSXin Ji 1508bdfc5daSXin Ji static int anx7625_write_or(struct anx7625_data *ctx, 1518bdfc5daSXin Ji struct i2c_client *client, 1528bdfc5daSXin Ji u8 offset, u8 mask) 1538bdfc5daSXin Ji { 1548bdfc5daSXin Ji int val; 1558bdfc5daSXin Ji 1568bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1578bdfc5daSXin Ji if (val < 0) 1588bdfc5daSXin Ji return val; 1598bdfc5daSXin Ji 1608bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val | (mask))); 1618bdfc5daSXin Ji } 1628bdfc5daSXin Ji 1638bdfc5daSXin Ji static int anx7625_write_and(struct anx7625_data *ctx, 1648bdfc5daSXin Ji struct i2c_client *client, 1658bdfc5daSXin Ji u8 offset, u8 mask) 1668bdfc5daSXin Ji { 1678bdfc5daSXin Ji int val; 1688bdfc5daSXin Ji 1698bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1708bdfc5daSXin Ji if (val < 0) 1718bdfc5daSXin Ji return val; 1728bdfc5daSXin Ji 1738bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val & (mask))); 1748bdfc5daSXin Ji } 1758bdfc5daSXin Ji 176566fef12SXin Ji static int anx7625_write_and_or(struct anx7625_data *ctx, 177566fef12SXin Ji struct i2c_client *client, 178566fef12SXin Ji u8 offset, u8 and_mask, u8 or_mask) 179566fef12SXin Ji { 180566fef12SXin Ji int val; 181566fef12SXin Ji 182566fef12SXin Ji val = anx7625_reg_read(ctx, client, offset); 183566fef12SXin Ji if (val < 0) 184566fef12SXin Ji return val; 185566fef12SXin Ji 186566fef12SXin Ji return anx7625_reg_write(ctx, client, 187566fef12SXin Ji offset, (val & and_mask) | (or_mask)); 188566fef12SXin Ji } 189566fef12SXin Ji 190fd0310b6SXin Ji static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 1918bdfc5daSXin Ji { 192fd0310b6SXin Ji int i, ret; 1938bdfc5daSXin Ji 194fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 195fd0310b6SXin Ji AUDIO_CONTROL_REGISTER, 0x80); 196fd0310b6SXin Ji for (i = 0; i < 13; i++) 197fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 198fd0310b6SXin Ji VIDEO_BIT_MATRIX_12 + i, 199fd0310b6SXin Ji 0x18 + i); 2008bdfc5daSXin Ji 201fd0310b6SXin Ji return ret; 2028bdfc5daSXin Ji } 2038bdfc5daSXin Ji 2048bdfc5daSXin Ji static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 2058bdfc5daSXin Ji { 2068bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 2078bdfc5daSXin Ji } 2088bdfc5daSXin Ji 2098bdfc5daSXin Ji static int wait_aux_op_finish(struct anx7625_data *ctx) 2108bdfc5daSXin Ji { 2118bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 2128bdfc5daSXin Ji int val; 2138bdfc5daSXin Ji int ret; 2148bdfc5daSXin Ji 2158bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 2168bdfc5daSXin Ji ctx, val, 2178bdfc5daSXin Ji (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 2188bdfc5daSXin Ji 2000, 2198bdfc5daSXin Ji 2000 * 150); 2208bdfc5daSXin Ji if (ret) { 2218bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux operation fail!\n"); 2228bdfc5daSXin Ji return -EIO; 2238bdfc5daSXin Ji } 2248bdfc5daSXin Ji 2258bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 2268bdfc5daSXin Ji AP_AUX_CTRL_STATUS); 2278bdfc5daSXin Ji if (val < 0 || (val & 0x0F)) { 2288bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux status %02x\n", val); 2299a7e49bdSXin Ji return -EIO; 2308bdfc5daSXin Ji } 2318bdfc5daSXin Ji 2329a7e49bdSXin Ji return 0; 2338bdfc5daSXin Ji } 2348bdfc5daSXin Ji 235adca62ecSHsin-Yi Wang static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 236adca62ecSHsin-Yi Wang u8 len, u8 *buf) 237cd1637c7SXin Ji { 238cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 239cd1637c7SXin Ji int ret; 240cd1637c7SXin Ji u8 addrh, addrm, addrl; 241cd1637c7SXin Ji u8 cmd; 242adca62ecSHsin-Yi Wang bool is_write = !(op & DP_AUX_I2C_READ); 243cd1637c7SXin Ji 244adca62ecSHsin-Yi Wang if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 245cd1637c7SXin Ji dev_err(dev, "exceed aux buffer len.\n"); 246cd1637c7SXin Ji return -EINVAL; 247cd1637c7SXin Ji } 248cd1637c7SXin Ji 249adca62ecSHsin-Yi Wang if (!len) 250adca62ecSHsin-Yi Wang return len; 251adca62ecSHsin-Yi Wang 252cd1637c7SXin Ji addrl = address & 0xFF; 253cd1637c7SXin Ji addrm = (address >> 8) & 0xFF; 254cd1637c7SXin Ji addrh = (address >> 16) & 0xFF; 255cd1637c7SXin Ji 256548b512eSXin Ji cmd = DPCD_CMD(len, op); 257cd1637c7SXin Ji 258cd1637c7SXin Ji /* Set command and length */ 259cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 260cd1637c7SXin Ji AP_AUX_COMMAND, cmd); 261cd1637c7SXin Ji 262cd1637c7SXin Ji /* Set aux access address */ 263cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 264cd1637c7SXin Ji AP_AUX_ADDR_7_0, addrl); 265cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 266cd1637c7SXin Ji AP_AUX_ADDR_15_8, addrm); 267cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 268cd1637c7SXin Ji AP_AUX_ADDR_19_16, addrh); 269cd1637c7SXin Ji 270adca62ecSHsin-Yi Wang if (is_write) 271548b512eSXin Ji ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 272548b512eSXin Ji AP_AUX_BUFF_START, len, buf); 273cd1637c7SXin Ji /* Enable aux access */ 274cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 275cd1637c7SXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 276cd1637c7SXin Ji 277cd1637c7SXin Ji if (ret < 0) { 278cd1637c7SXin Ji dev_err(dev, "cannot access aux related register.\n"); 279cd1637c7SXin Ji return -EIO; 280cd1637c7SXin Ji } 281cd1637c7SXin Ji 282cd1637c7SXin Ji ret = wait_aux_op_finish(ctx); 283adca62ecSHsin-Yi Wang if (ret < 0) { 284cd1637c7SXin Ji dev_err(dev, "aux IO error: wait aux op finish.\n"); 285cd1637c7SXin Ji return ret; 286cd1637c7SXin Ji } 287cd1637c7SXin Ji 288548b512eSXin Ji /* Write done */ 289adca62ecSHsin-Yi Wang if (is_write) 290adca62ecSHsin-Yi Wang return len; 291548b512eSXin Ji 292548b512eSXin Ji /* Read done, read out dpcd data */ 293cd1637c7SXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 294cd1637c7SXin Ji AP_AUX_BUFF_START, len, buf); 295cd1637c7SXin Ji if (ret < 0) { 296cd1637c7SXin Ji dev_err(dev, "read dpcd register failed\n"); 297cd1637c7SXin Ji return -EIO; 298cd1637c7SXin Ji } 299cd1637c7SXin Ji 300adca62ecSHsin-Yi Wang return len; 301cd1637c7SXin Ji } 302cd1637c7SXin Ji 3038bdfc5daSXin Ji static int anx7625_video_mute_control(struct anx7625_data *ctx, 3048bdfc5daSXin Ji u8 status) 3058bdfc5daSXin Ji { 3068bdfc5daSXin Ji int ret; 3078bdfc5daSXin Ji 3088bdfc5daSXin Ji if (status) { 3098bdfc5daSXin Ji /* Set mute on flag */ 3108bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 3118bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_MUTE); 3128bdfc5daSXin Ji /* Clear mipi RX en */ 3138bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 3148bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 3158bdfc5daSXin Ji } else { 3168bdfc5daSXin Ji /* Mute off flag */ 3178bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 3188bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 3198bdfc5daSXin Ji /* Set MIPI RX EN */ 3208bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 3218bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 3228bdfc5daSXin Ji } 3238bdfc5daSXin Ji 3248bdfc5daSXin Ji return ret; 3258bdfc5daSXin Ji } 3268bdfc5daSXin Ji 3278bdfc5daSXin Ji /* Reduction of fraction a/b */ 3288bdfc5daSXin Ji static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 3298bdfc5daSXin Ji { 3308bdfc5daSXin Ji unsigned long gcd_num; 3318bdfc5daSXin Ji unsigned long tmp_a, tmp_b; 3328bdfc5daSXin Ji u32 i = 1; 3338bdfc5daSXin Ji 3348bdfc5daSXin Ji gcd_num = gcd(*a, *b); 3358bdfc5daSXin Ji *a /= gcd_num; 3368bdfc5daSXin Ji *b /= gcd_num; 3378bdfc5daSXin Ji 3388bdfc5daSXin Ji tmp_a = *a; 3398bdfc5daSXin Ji tmp_b = *b; 3408bdfc5daSXin Ji 3418bdfc5daSXin Ji while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 3428bdfc5daSXin Ji i++; 3438bdfc5daSXin Ji *a = tmp_a / i; 3448bdfc5daSXin Ji *b = tmp_b / i; 3458bdfc5daSXin Ji } 3468bdfc5daSXin Ji 3478bdfc5daSXin Ji /* 3488bdfc5daSXin Ji * In the end, make a, b larger to have higher ODFC PLL 3498bdfc5daSXin Ji * output frequency accuracy 3508bdfc5daSXin Ji */ 3518bdfc5daSXin Ji while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 3528bdfc5daSXin Ji *a <<= 1; 3538bdfc5daSXin Ji *b <<= 1; 3548bdfc5daSXin Ji } 3558bdfc5daSXin Ji 3568bdfc5daSXin Ji *a >>= 1; 3578bdfc5daSXin Ji *b >>= 1; 3588bdfc5daSXin Ji } 3598bdfc5daSXin Ji 3608bdfc5daSXin Ji static int anx7625_calculate_m_n(u32 pixelclock, 3618bdfc5daSXin Ji unsigned long *m, 3628bdfc5daSXin Ji unsigned long *n, 3638bdfc5daSXin Ji u8 *post_divider) 3648bdfc5daSXin Ji { 3658bdfc5daSXin Ji if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 3668bdfc5daSXin Ji /* Pixel clock frequency is too high */ 3678bdfc5daSXin Ji DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 3688bdfc5daSXin Ji pixelclock, 3698bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 3708bdfc5daSXin Ji return -EINVAL; 3718bdfc5daSXin Ji } 3728bdfc5daSXin Ji 3738bdfc5daSXin Ji if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 3748bdfc5daSXin Ji /* Pixel clock frequency is too low */ 3758bdfc5daSXin Ji DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 3768bdfc5daSXin Ji pixelclock, 3778bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 3788bdfc5daSXin Ji return -EINVAL; 3798bdfc5daSXin Ji } 3808bdfc5daSXin Ji 3818bdfc5daSXin Ji for (*post_divider = 1; 3828bdfc5daSXin Ji pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 3838bdfc5daSXin Ji *post_divider += 1; 3848bdfc5daSXin Ji 3858bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3868bdfc5daSXin Ji for (*post_divider = 1; 3878bdfc5daSXin Ji (pixelclock < 3888bdfc5daSXin Ji (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 3898bdfc5daSXin Ji *post_divider += 1; 3908bdfc5daSXin Ji 3918bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3928bdfc5daSXin Ji DRM_ERROR("cannot find property post_divider(%d)\n", 3938bdfc5daSXin Ji *post_divider); 3948bdfc5daSXin Ji return -EDOM; 3958bdfc5daSXin Ji } 3968bdfc5daSXin Ji } 3978bdfc5daSXin Ji 3988bdfc5daSXin Ji /* Patch to improve the accuracy */ 3998bdfc5daSXin Ji if (*post_divider == 7) { 4008bdfc5daSXin Ji /* 27,000,000 is not divisible by 7 */ 4018bdfc5daSXin Ji *post_divider = 8; 4028bdfc5daSXin Ji } else if (*post_divider == 11) { 4038bdfc5daSXin Ji /* 27,000,000 is not divisible by 11 */ 4048bdfc5daSXin Ji *post_divider = 12; 4058bdfc5daSXin Ji } else if ((*post_divider == 13) || (*post_divider == 14)) { 4068bdfc5daSXin Ji /* 27,000,000 is not divisible by 13 or 14 */ 4078bdfc5daSXin Ji *post_divider = 15; 4088bdfc5daSXin Ji } 4098bdfc5daSXin Ji 4108bdfc5daSXin Ji if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 4118bdfc5daSXin Ji DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 4128bdfc5daSXin Ji pixelclock * (*post_divider), 4138bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX); 4148bdfc5daSXin Ji return -EDOM; 4158bdfc5daSXin Ji } 4168bdfc5daSXin Ji 4178bdfc5daSXin Ji *m = pixelclock; 4188bdfc5daSXin Ji *n = XTAL_FRQ / (*post_divider); 4198bdfc5daSXin Ji 4208bdfc5daSXin Ji anx7625_reduction_of_a_fraction(m, n); 4218bdfc5daSXin Ji 4228bdfc5daSXin Ji return 0; 4238bdfc5daSXin Ji } 4248bdfc5daSXin Ji 4258bdfc5daSXin Ji static int anx7625_odfc_config(struct anx7625_data *ctx, 4268bdfc5daSXin Ji u8 post_divider) 4278bdfc5daSXin Ji { 4288bdfc5daSXin Ji int ret; 4298bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4308bdfc5daSXin Ji 4318bdfc5daSXin Ji /* Config input reference clock frequency 27MHz/19.2MHz */ 4328bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 4338bdfc5daSXin Ji ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 4348bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 4358bdfc5daSXin Ji (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 4368bdfc5daSXin Ji /* Post divider */ 4378bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4388bdfc5daSXin Ji MIPI_DIGITAL_PLL_8, 0x0f); 4398bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 4408bdfc5daSXin Ji post_divider << 4); 4418bdfc5daSXin Ji 4428bdfc5daSXin Ji /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 4438bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4448bdfc5daSXin Ji ~MIPI_PLL_VCO_TUNE_REG_VAL); 4458bdfc5daSXin Ji 4468bdfc5daSXin Ji /* Reset ODFC PLL */ 4478bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4488bdfc5daSXin Ji ~MIPI_PLL_RESET_N); 4498bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4508bdfc5daSXin Ji MIPI_PLL_RESET_N); 4518bdfc5daSXin Ji 4528bdfc5daSXin Ji if (ret < 0) 4538bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error.\n"); 4548bdfc5daSXin Ji 4558bdfc5daSXin Ji return ret; 4568bdfc5daSXin Ji } 4578bdfc5daSXin Ji 4587d066dc7SXin Ji /* 4597d066dc7SXin Ji * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 4607d066dc7SXin Ji * anx7625 defined K ratio for matching MIPI input video clock and 4617d066dc7SXin Ji * DP output video clock. Increase K value can match bigger video data 4627d066dc7SXin Ji * variation. IVO panel has small variation than DP CTS spec, need 4637d066dc7SXin Ji * decrease the K value. 4647d066dc7SXin Ji */ 4657d066dc7SXin Ji static int anx7625_set_k_value(struct anx7625_data *ctx) 4667d066dc7SXin Ji { 4677d066dc7SXin Ji struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 4687d066dc7SXin Ji 4697d066dc7SXin Ji if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 4707d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4717d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3B); 4727d066dc7SXin Ji 4737d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4747d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3D); 4757d066dc7SXin Ji } 4767d066dc7SXin Ji 4778bdfc5daSXin Ji static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 4788bdfc5daSXin Ji { 4798bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4808bdfc5daSXin Ji unsigned long m, n; 4818bdfc5daSXin Ji u16 htotal; 4828bdfc5daSXin Ji int ret; 4838bdfc5daSXin Ji u8 post_divider = 0; 4848bdfc5daSXin Ji 4858bdfc5daSXin Ji ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 4868bdfc5daSXin Ji &m, &n, &post_divider); 4878bdfc5daSXin Ji 4888bdfc5daSXin Ji if (ret) { 4898bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 4908bdfc5daSXin Ji return ret; 4918bdfc5daSXin Ji } 4928bdfc5daSXin Ji 4938bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 4948bdfc5daSXin Ji m, n, post_divider); 4958bdfc5daSXin Ji 4968bdfc5daSXin Ji /* Configure pixel clock */ 4978bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 4988bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) & 0xFF); 4998bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 5008bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) >> 8); 5018bdfc5daSXin Ji /* Lane count */ 5028bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 5038bdfc5daSXin Ji MIPI_LANE_CTRL_0, 0xfc); 5048bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 505fd0310b6SXin Ji MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 5068bdfc5daSXin Ji 5078bdfc5daSXin Ji /* Htotal */ 5088bdfc5daSXin Ji htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 5098bdfc5daSXin Ji ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 5108bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5118bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 5128bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5138bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 5148bdfc5daSXin Ji /* Hactive */ 5158bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5168bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 5178bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5188bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 5198bdfc5daSXin Ji /* HFP */ 5208bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5218bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 5228bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5238bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_H, 5248bdfc5daSXin Ji ctx->dt.hfront_porch.min >> 8); 5258bdfc5daSXin Ji /* HWS */ 5268bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5278bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 5288bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5298bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 5308bdfc5daSXin Ji /* HBP */ 5318bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5328bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 5338bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5348bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 5358bdfc5daSXin Ji /* Vactive */ 5368bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 5378bdfc5daSXin Ji ctx->dt.vactive.min); 5388bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 5398bdfc5daSXin Ji ctx->dt.vactive.min >> 8); 5408bdfc5daSXin Ji /* VFP */ 5418bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5428bdfc5daSXin Ji VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 5438bdfc5daSXin Ji /* VWS */ 5448bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5458bdfc5daSXin Ji VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 5468bdfc5daSXin Ji /* VBP */ 5478bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5488bdfc5daSXin Ji VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 5498bdfc5daSXin Ji /* M value */ 5508bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5518bdfc5daSXin Ji MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 5528bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5538bdfc5daSXin Ji MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 5548bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5558bdfc5daSXin Ji MIPI_PLL_M_NUM_7_0, (m & 0xff)); 5568bdfc5daSXin Ji /* N value */ 5578bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5588bdfc5daSXin Ji MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 5598bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5608bdfc5daSXin Ji MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 5618bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 5628bdfc5daSXin Ji (n & 0xff)); 5637d066dc7SXin Ji 5647d066dc7SXin Ji anx7625_set_k_value(ctx); 5658bdfc5daSXin Ji 5668bdfc5daSXin Ji ret |= anx7625_odfc_config(ctx, post_divider - 1); 5678bdfc5daSXin Ji 5688bdfc5daSXin Ji if (ret < 0) 5698bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 5708bdfc5daSXin Ji 5718bdfc5daSXin Ji return ret; 5728bdfc5daSXin Ji } 5738bdfc5daSXin Ji 5748bdfc5daSXin Ji static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 5758bdfc5daSXin Ji { 5768bdfc5daSXin Ji int val; 5778bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5788bdfc5daSXin Ji 5798bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5808bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 5818bdfc5daSXin Ji if (val < 0) { 5828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 5838bdfc5daSXin Ji return -EIO; 5848bdfc5daSXin Ji } 5858bdfc5daSXin Ji 5868bdfc5daSXin Ji val |= (1 << MIPI_SWAP_CH3); 5878bdfc5daSXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 5888bdfc5daSXin Ji } 5898bdfc5daSXin Ji 5908bdfc5daSXin Ji static int anx7625_api_dsi_config(struct anx7625_data *ctx) 5918bdfc5daSXin Ji 5928bdfc5daSXin Ji { 5938bdfc5daSXin Ji int val, ret; 5948bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5958bdfc5daSXin Ji 5968bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5978bdfc5daSXin Ji ret = anx7625_swap_dsi_lane3(ctx); 5988bdfc5daSXin Ji if (ret < 0) { 5998bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 6008bdfc5daSXin Ji return ret; 6018bdfc5daSXin Ji } 6028bdfc5daSXin Ji 6038bdfc5daSXin Ji /* DSI clock settings */ 6048bdfc5daSXin Ji val = (0 << MIPI_HS_PWD_CLK) | 6058bdfc5daSXin Ji (0 << MIPI_HS_RT_CLK) | 6068bdfc5daSXin Ji (0 << MIPI_PD_CLK) | 6078bdfc5daSXin Ji (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 6088bdfc5daSXin Ji (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 6098bdfc5daSXin Ji (0 << MIPI_CLK_DET_DET_BYPASS) | 6108bdfc5daSXin Ji (0 << MIPI_CLK_MISS_CTRL) | 6118bdfc5daSXin Ji (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 6128bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6138bdfc5daSXin Ji MIPI_PHY_CONTROL_3, val); 6148bdfc5daSXin Ji 6158bdfc5daSXin Ji /* 6168bdfc5daSXin Ji * Decreased HS prepare timing delay from 160ns to 80ns work with 6178bdfc5daSXin Ji * a) Dragon board 810 series (Qualcomm AP) 6188bdfc5daSXin Ji * b) Moving Pixel DSI source (PG3A pattern generator + 6198bdfc5daSXin Ji * P332 D-PHY Probe) default D-PHY timing 6208bdfc5daSXin Ji * 5ns/step 6218bdfc5daSXin Ji */ 6228bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6238bdfc5daSXin Ji MIPI_TIME_HS_PRPR, 0x10); 6248bdfc5daSXin Ji 6258bdfc5daSXin Ji /* Enable DSI mode*/ 6268bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 6278bdfc5daSXin Ji SELECT_DSI << MIPI_DPI_SELECT); 6288bdfc5daSXin Ji 6298bdfc5daSXin Ji ret |= anx7625_dsi_video_timing_config(ctx); 6308bdfc5daSXin Ji if (ret < 0) { 6318bdfc5daSXin Ji DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 6328bdfc5daSXin Ji return ret; 6338bdfc5daSXin Ji } 6348bdfc5daSXin Ji 6358bdfc5daSXin Ji /* Toggle m, n ready */ 6368bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 6378bdfc5daSXin Ji ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 6388bdfc5daSXin Ji usleep_range(1000, 1100); 6398bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 6408bdfc5daSXin Ji MIPI_M_NUM_READY | MIPI_N_NUM_READY); 6418bdfc5daSXin Ji 6428bdfc5daSXin Ji /* Configure integer stable register */ 6438bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6448bdfc5daSXin Ji MIPI_VIDEO_STABLE_CNT, 0x02); 6458bdfc5daSXin Ji /* Power on MIPI RX */ 6468bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6478bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x00); 6488bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6498bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x80); 6508bdfc5daSXin Ji 6518bdfc5daSXin Ji if (ret < 0) 6528bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 6538bdfc5daSXin Ji 6548bdfc5daSXin Ji return ret; 6558bdfc5daSXin Ji } 6568bdfc5daSXin Ji 6578bdfc5daSXin Ji static int anx7625_dsi_config(struct anx7625_data *ctx) 6588bdfc5daSXin Ji { 6598bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6608bdfc5daSXin Ji int ret; 6618bdfc5daSXin Ji 6628bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 6638bdfc5daSXin Ji 6648bdfc5daSXin Ji /* DSC disable */ 6658bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 6668bdfc5daSXin Ji R_DSC_CTRL_0, ~DSC_EN); 6678bdfc5daSXin Ji 6688bdfc5daSXin Ji ret |= anx7625_api_dsi_config(ctx); 6698bdfc5daSXin Ji 6708bdfc5daSXin Ji if (ret < 0) { 6718bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 6728bdfc5daSXin Ji return ret; 6738bdfc5daSXin Ji } 6748bdfc5daSXin Ji 6758bdfc5daSXin Ji /* Set MIPI RX EN */ 6768bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 6778bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 6788bdfc5daSXin Ji /* Clear mute flag */ 6798bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 6808bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 6818bdfc5daSXin Ji if (ret < 0) 6828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 6838bdfc5daSXin Ji else 6848bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 6858bdfc5daSXin Ji 6868bdfc5daSXin Ji return ret; 6878bdfc5daSXin Ji } 6888bdfc5daSXin Ji 689fd0310b6SXin Ji static int anx7625_api_dpi_config(struct anx7625_data *ctx) 690fd0310b6SXin Ji { 691fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 692fd0310b6SXin Ji u16 freq = ctx->dt.pixelclock.min / 1000; 693fd0310b6SXin Ji int ret; 694fd0310b6SXin Ji 695fd0310b6SXin Ji /* configure pixel clock */ 696fd0310b6SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 697fd0310b6SXin Ji PIXEL_CLOCK_L, freq & 0xFF); 698fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 699fd0310b6SXin Ji PIXEL_CLOCK_H, (freq >> 8)); 700fd0310b6SXin Ji 701fd0310b6SXin Ji /* set DPI mode */ 702fd0310b6SXin Ji /* set to DPI PLL module sel */ 703fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 704fd0310b6SXin Ji MIPI_DIGITAL_PLL_9, 0x20); 705fd0310b6SXin Ji /* power down MIPI */ 706fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 707fd0310b6SXin Ji MIPI_LANE_CTRL_10, 0x08); 708fd0310b6SXin Ji /* enable DPI mode */ 709fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 710fd0310b6SXin Ji MIPI_DIGITAL_PLL_18, 0x1C); 711fd0310b6SXin Ji /* set first edge */ 712fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 713fd0310b6SXin Ji VIDEO_CONTROL_0, 0x06); 714fd0310b6SXin Ji if (ret < 0) 715fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 716fd0310b6SXin Ji 717fd0310b6SXin Ji return ret; 718fd0310b6SXin Ji } 719fd0310b6SXin Ji 720fd0310b6SXin Ji static int anx7625_dpi_config(struct anx7625_data *ctx) 721fd0310b6SXin Ji { 722fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 723fd0310b6SXin Ji int ret; 724fd0310b6SXin Ji 725fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 726fd0310b6SXin Ji 727fd0310b6SXin Ji /* DSC disable */ 728fd0310b6SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 729fd0310b6SXin Ji R_DSC_CTRL_0, ~DSC_EN); 730fd0310b6SXin Ji if (ret < 0) { 731fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 732fd0310b6SXin Ji return ret; 733fd0310b6SXin Ji } 734fd0310b6SXin Ji 735fd0310b6SXin Ji ret = anx7625_config_bit_matrix(ctx); 736fd0310b6SXin Ji if (ret < 0) { 737fd0310b6SXin Ji DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 738fd0310b6SXin Ji return ret; 739fd0310b6SXin Ji } 740fd0310b6SXin Ji 741fd0310b6SXin Ji ret = anx7625_api_dpi_config(ctx); 742fd0310b6SXin Ji if (ret < 0) { 743fd0310b6SXin Ji DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 744fd0310b6SXin Ji return ret; 745fd0310b6SXin Ji } 746fd0310b6SXin Ji 747fd0310b6SXin Ji /* set MIPI RX EN */ 748fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 749fd0310b6SXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 750fd0310b6SXin Ji /* clear mute flag */ 751fd0310b6SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 752fd0310b6SXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 753fd0310b6SXin Ji if (ret < 0) 754fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 755fd0310b6SXin Ji 756fd0310b6SXin Ji return ret; 757fd0310b6SXin Ji } 758fd0310b6SXin Ji 759cd1637c7SXin Ji static int anx7625_read_flash_status(struct anx7625_data *ctx) 760cd1637c7SXin Ji { 761cd1637c7SXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 762cd1637c7SXin Ji } 763cd1637c7SXin Ji 764cd1637c7SXin Ji static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 765cd1637c7SXin Ji { 766cd1637c7SXin Ji int ret, val; 767cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 768cd1637c7SXin Ji u8 ident[FLASH_BUF_LEN]; 769cd1637c7SXin Ji 770cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 771cd1637c7SXin Ji FLASH_ADDR_HIGH, 0x91); 772cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 773cd1637c7SXin Ji FLASH_ADDR_LOW, 0xA0); 774cd1637c7SXin Ji if (ret < 0) { 775cd1637c7SXin Ji dev_err(dev, "IO error : set key flash address.\n"); 776cd1637c7SXin Ji return ret; 777cd1637c7SXin Ji } 778cd1637c7SXin Ji 779cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 780cd1637c7SXin Ji FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 781cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 782cd1637c7SXin Ji FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 783cd1637c7SXin Ji if (ret < 0) { 784cd1637c7SXin Ji dev_err(dev, "IO error : set key flash len.\n"); 785cd1637c7SXin Ji return ret; 786cd1637c7SXin Ji } 787cd1637c7SXin Ji 788cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 789cd1637c7SXin Ji R_FLASH_RW_CTRL, FLASH_READ); 790cd1637c7SXin Ji ret |= readx_poll_timeout(anx7625_read_flash_status, 791cd1637c7SXin Ji ctx, val, 792cd1637c7SXin Ji ((val & FLASH_DONE) || (val < 0)), 793cd1637c7SXin Ji 2000, 794cd1637c7SXin Ji 2000 * 150); 795cd1637c7SXin Ji if (ret) { 796cd1637c7SXin Ji dev_err(dev, "flash read access fail!\n"); 797cd1637c7SXin Ji return -EIO; 798cd1637c7SXin Ji } 799cd1637c7SXin Ji 800cd1637c7SXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 801cd1637c7SXin Ji FLASH_BUF_BASE_ADDR, 802cd1637c7SXin Ji FLASH_BUF_LEN, ident); 803cd1637c7SXin Ji if (ret < 0) { 804cd1637c7SXin Ji dev_err(dev, "read flash data fail!\n"); 805cd1637c7SXin Ji return -EIO; 806cd1637c7SXin Ji } 807cd1637c7SXin Ji 808cd1637c7SXin Ji if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 809cd1637c7SXin Ji return -EINVAL; 810cd1637c7SXin Ji 811cd1637c7SXin Ji return 0; 812cd1637c7SXin Ji } 813cd1637c7SXin Ji 814cd1637c7SXin Ji static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 815cd1637c7SXin Ji { 816cd1637c7SXin Ji int ret; 817cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 818cd1637c7SXin Ji 819cd1637c7SXin Ji /* Select HDCP 1.4 KEY */ 820cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 821cd1637c7SXin Ji R_BOOT_RETRY, 0x12); 822cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 823cd1637c7SXin Ji FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 824cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 825cd1637c7SXin Ji FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 826cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827cd1637c7SXin Ji R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 828cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829cd1637c7SXin Ji R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 830cd1637c7SXin Ji 831cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 832cd1637c7SXin Ji R_RAM_ADDR_H, 0); 833cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 834cd1637c7SXin Ji R_RAM_ADDR_L, 0); 835cd1637c7SXin Ji /* Enable HDCP 1.4 KEY load */ 836cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 837cd1637c7SXin Ji R_RAM_CTRL, DECRYPT_EN | LOAD_START); 838cd1637c7SXin Ji dev_dbg(dev, "load HDCP 1.4 key done\n"); 839cd1637c7SXin Ji return ret; 840cd1637c7SXin Ji } 841cd1637c7SXin Ji 842cd1637c7SXin Ji static int anx7625_hdcp_disable(struct anx7625_data *ctx) 843cd1637c7SXin Ji { 844cd1637c7SXin Ji int ret; 845cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 846cd1637c7SXin Ji 847cd1637c7SXin Ji dev_dbg(dev, "disable HDCP 1.4\n"); 848cd1637c7SXin Ji 849cd1637c7SXin Ji /* Disable HDCP */ 850cd1637c7SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 851cd1637c7SXin Ji /* Try auth flag */ 852cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 853cd1637c7SXin Ji /* Interrupt for DRM */ 854cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 855cd1637c7SXin Ji if (ret < 0) 856cd1637c7SXin Ji dev_err(dev, "fail to disable HDCP\n"); 857cd1637c7SXin Ji 858cd1637c7SXin Ji return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 859cd1637c7SXin Ji TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 860cd1637c7SXin Ji } 861cd1637c7SXin Ji 862cd1637c7SXin Ji static int anx7625_hdcp_enable(struct anx7625_data *ctx) 863cd1637c7SXin Ji { 864cd1637c7SXin Ji u8 bcap; 865cd1637c7SXin Ji int ret; 866cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 867cd1637c7SXin Ji 868cd1637c7SXin Ji ret = anx7625_hdcp_key_probe(ctx); 869cd1637c7SXin Ji if (ret) { 870cd1637c7SXin Ji dev_dbg(dev, "no key found, not to do hdcp\n"); 871cd1637c7SXin Ji return ret; 872cd1637c7SXin Ji } 873cd1637c7SXin Ji 874cd1637c7SXin Ji /* Read downstream capability */ 875adca62ecSHsin-Yi Wang anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap); 876cd1637c7SXin Ji if (!(bcap & 0x01)) { 877cd1637c7SXin Ji pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 878cd1637c7SXin Ji return 0; 879cd1637c7SXin Ji } 880cd1637c7SXin Ji 881cd1637c7SXin Ji dev_dbg(dev, "enable HDCP 1.4\n"); 882cd1637c7SXin Ji 883cd1637c7SXin Ji /* First clear HDCP state */ 884cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 885cd1637c7SXin Ji TX_HDCP_CTRL0, 886cd1637c7SXin Ji KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 887cd1637c7SXin Ji usleep_range(1000, 1100); 888cd1637c7SXin Ji /* Second clear HDCP state */ 889cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 890cd1637c7SXin Ji TX_HDCP_CTRL0, 891cd1637c7SXin Ji KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 892cd1637c7SXin Ji 893cd1637c7SXin Ji /* Set time for waiting KSVR */ 894cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 895cd1637c7SXin Ji SP_TX_WAIT_KSVR_TIME, 0xc8); 896cd1637c7SXin Ji /* Set time for waiting R0 */ 897cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 898cd1637c7SXin Ji SP_TX_WAIT_R0_TIME, 0xb0); 899cd1637c7SXin Ji ret |= anx7625_hdcp_key_load(ctx); 900cd1637c7SXin Ji if (ret) { 901cd1637c7SXin Ji pr_warn("prepare HDCP key failed.\n"); 902cd1637c7SXin Ji return ret; 903cd1637c7SXin Ji } 904cd1637c7SXin Ji 905cd1637c7SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 906cd1637c7SXin Ji 907cd1637c7SXin Ji /* Try auth flag */ 908cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 909cd1637c7SXin Ji /* Interrupt for DRM */ 910cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 911cd1637c7SXin Ji if (ret < 0) 912cd1637c7SXin Ji dev_err(dev, "fail to enable HDCP\n"); 913cd1637c7SXin Ji 914cd1637c7SXin Ji return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 915cd1637c7SXin Ji TX_HDCP_CTRL0, HARD_AUTH_EN); 916cd1637c7SXin Ji } 917cd1637c7SXin Ji 9188bdfc5daSXin Ji static void anx7625_dp_start(struct anx7625_data *ctx) 9198bdfc5daSXin Ji { 9208bdfc5daSXin Ji int ret; 9218bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9228bdfc5daSXin Ji 9238bdfc5daSXin Ji if (!ctx->display_timing_valid) { 9248bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 9258bdfc5daSXin Ji return; 9268bdfc5daSXin Ji } 9278bdfc5daSXin Ji 928cd1637c7SXin Ji /* Disable HDCP */ 929cd1637c7SXin Ji anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 930cd1637c7SXin Ji 931fd0310b6SXin Ji if (ctx->pdata.is_dpi) 932fd0310b6SXin Ji ret = anx7625_dpi_config(ctx); 933fd0310b6SXin Ji else 9348bdfc5daSXin Ji ret = anx7625_dsi_config(ctx); 9358bdfc5daSXin Ji 9368bdfc5daSXin Ji if (ret < 0) 9378bdfc5daSXin Ji DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 938cd1637c7SXin Ji 939cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 940cd1637c7SXin Ji 941cd1637c7SXin Ji ctx->dp_en = 1; 9428bdfc5daSXin Ji } 9438bdfc5daSXin Ji 9448bdfc5daSXin Ji static void anx7625_dp_stop(struct anx7625_data *ctx) 9458bdfc5daSXin Ji { 9468bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9478bdfc5daSXin Ji int ret; 948548b512eSXin Ji u8 data; 9498bdfc5daSXin Ji 9508bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 9518bdfc5daSXin Ji 9528bdfc5daSXin Ji /* 9538bdfc5daSXin Ji * Video disable: 0x72:08 bit 7 = 0; 9548bdfc5daSXin Ji * Audio disable: 0x70:87 bit 0 = 0; 9558bdfc5daSXin Ji */ 9568bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 9578bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 9588bdfc5daSXin Ji 9598bdfc5daSXin Ji ret |= anx7625_video_mute_control(ctx, 1); 960548b512eSXin Ji 961548b512eSXin Ji dev_dbg(dev, "notify downstream enter into standby\n"); 962548b512eSXin Ji /* Downstream monitor enter into standby mode */ 963548b512eSXin Ji data = 2; 964adca62ecSHsin-Yi Wang ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data); 9658bdfc5daSXin Ji if (ret < 0) 9668bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 967cd1637c7SXin Ji 968cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 969cd1637c7SXin Ji 970cd1637c7SXin Ji ctx->dp_en = 0; 9718bdfc5daSXin Ji } 9728bdfc5daSXin Ji 9738bdfc5daSXin Ji static int sp_tx_rst_aux(struct anx7625_data *ctx) 9748bdfc5daSXin Ji { 9758bdfc5daSXin Ji int ret; 9768bdfc5daSXin Ji 9778bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 9788bdfc5daSXin Ji AUX_RST); 9798bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 9808bdfc5daSXin Ji ~AUX_RST); 9818bdfc5daSXin Ji return ret; 9828bdfc5daSXin Ji } 9838bdfc5daSXin Ji 9848bdfc5daSXin Ji static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 9858bdfc5daSXin Ji { 9868bdfc5daSXin Ji int ret; 9878bdfc5daSXin Ji 9888bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9898bdfc5daSXin Ji AP_AUX_BUFF_START, offset); 9908bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9918bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 9928bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 9938bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 9948bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 9958bdfc5daSXin Ji } 9968bdfc5daSXin Ji 9978bdfc5daSXin Ji static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 9988bdfc5daSXin Ji { 9998bdfc5daSXin Ji int ret; 10008bdfc5daSXin Ji 10018bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10028bdfc5daSXin Ji AP_AUX_COMMAND, len_cmd); 10038bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 10048bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 10058bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 10068bdfc5daSXin Ji } 10078bdfc5daSXin Ji 10088bdfc5daSXin Ji static int sp_tx_get_edid_block(struct anx7625_data *ctx) 10098bdfc5daSXin Ji { 10108bdfc5daSXin Ji int c = 0; 10118bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10128bdfc5daSXin Ji 10138bdfc5daSXin Ji sp_tx_aux_wr(ctx, 0x7e); 10148bdfc5daSXin Ji sp_tx_aux_rd(ctx, 0x01); 10158bdfc5daSXin Ji c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 10168bdfc5daSXin Ji if (c < 0) { 10178bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 10188bdfc5daSXin Ji return -EIO; 10198bdfc5daSXin Ji } 10208bdfc5daSXin Ji 10218bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 10228bdfc5daSXin Ji 10238bdfc5daSXin Ji if (c > MAX_EDID_BLOCK) 10248bdfc5daSXin Ji c = 1; 10258bdfc5daSXin Ji 10268bdfc5daSXin Ji return c; 10278bdfc5daSXin Ji } 10288bdfc5daSXin Ji 10298bdfc5daSXin Ji static int edid_read(struct anx7625_data *ctx, 10308bdfc5daSXin Ji u8 offset, u8 *pblock_buf) 10318bdfc5daSXin Ji { 10328bdfc5daSXin Ji int ret, cnt; 10338bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10348bdfc5daSXin Ji 10358bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 10368bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 10378bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 10388bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 10398bdfc5daSXin Ji 10408bdfc5daSXin Ji if (ret) { 10417f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 10428bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 10438bdfc5daSXin Ji } else { 10448bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 10458bdfc5daSXin Ji AP_AUX_BUFF_START, 10468bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, 10478bdfc5daSXin Ji pblock_buf); 10488bdfc5daSXin Ji if (ret > 0) 10498bdfc5daSXin Ji break; 10508bdfc5daSXin Ji } 10518bdfc5daSXin Ji } 10528bdfc5daSXin Ji 10538bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 10548bdfc5daSXin Ji return -EIO; 10558bdfc5daSXin Ji 10567f16d0f3SRobert Foss return ret; 10578bdfc5daSXin Ji } 10588bdfc5daSXin Ji 10598bdfc5daSXin Ji static int segments_edid_read(struct anx7625_data *ctx, 10608bdfc5daSXin Ji u8 segment, u8 *buf, u8 offset) 10618bdfc5daSXin Ji { 10628bdfc5daSXin Ji u8 cnt; 10638bdfc5daSXin Ji int ret; 10648bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10658bdfc5daSXin Ji 10668bdfc5daSXin Ji /* Write address only */ 10678bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10688bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x30); 10698bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10708bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 10718bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10728bdfc5daSXin Ji AP_AUX_CTRL_STATUS, 10738bdfc5daSXin Ji AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 10748bdfc5daSXin Ji 10758bdfc5daSXin Ji ret |= wait_aux_op_finish(ctx); 10768bdfc5daSXin Ji /* Write segment address */ 10778bdfc5daSXin Ji ret |= sp_tx_aux_wr(ctx, segment); 10788bdfc5daSXin Ji /* Data read */ 10798bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10808bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 10818bdfc5daSXin Ji if (ret) { 10828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 10838bdfc5daSXin Ji return ret; 10848bdfc5daSXin Ji } 10858bdfc5daSXin Ji 10868bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 10878bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 10888bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 10898bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 10908bdfc5daSXin Ji 10918bdfc5daSXin Ji if (ret) { 10928bdfc5daSXin Ji ret = sp_tx_rst_aux(ctx); 10938bdfc5daSXin Ji DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 10948bdfc5daSXin Ji } else { 10958bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 10968bdfc5daSXin Ji AP_AUX_BUFF_START, 10978bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, buf); 10988bdfc5daSXin Ji if (ret > 0) 10998bdfc5daSXin Ji break; 11008bdfc5daSXin Ji } 11018bdfc5daSXin Ji } 11028bdfc5daSXin Ji 11038bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 11048bdfc5daSXin Ji return -EIO; 11058bdfc5daSXin Ji 11067f16d0f3SRobert Foss return ret; 11078bdfc5daSXin Ji } 11088bdfc5daSXin Ji 11098bdfc5daSXin Ji static int sp_tx_edid_read(struct anx7625_data *ctx, 11108bdfc5daSXin Ji u8 *pedid_blocks_buf) 11118bdfc5daSXin Ji { 1112*d5c6f647SPin-Yen Lin u8 offset; 1113*d5c6f647SPin-Yen Lin int edid_pos; 11148bdfc5daSXin Ji int count, blocks_num; 11158bdfc5daSXin Ji u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 11168bdfc5daSXin Ji u8 i, j; 11170bae5687SHsin-Yi Wang int g_edid_break = 0; 11188bdfc5daSXin Ji int ret; 11198bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11208bdfc5daSXin Ji 11218bdfc5daSXin Ji /* Address initial */ 11228bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11238bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 11248bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11258bdfc5daSXin Ji AP_AUX_ADDR_15_8, 0); 11268bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 11278bdfc5daSXin Ji AP_AUX_ADDR_19_16, 0xf0); 11288bdfc5daSXin Ji if (ret < 0) { 11298bdfc5daSXin Ji DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 11308bdfc5daSXin Ji return -EIO; 11318bdfc5daSXin Ji } 11328bdfc5daSXin Ji 11338bdfc5daSXin Ji blocks_num = sp_tx_get_edid_block(ctx); 11348bdfc5daSXin Ji if (blocks_num < 0) 11358bdfc5daSXin Ji return blocks_num; 11368bdfc5daSXin Ji 11378bdfc5daSXin Ji count = 0; 11388bdfc5daSXin Ji 11398bdfc5daSXin Ji do { 11408bdfc5daSXin Ji switch (count) { 11418bdfc5daSXin Ji case 0: 11428bdfc5daSXin Ji case 1: 11438bdfc5daSXin Ji for (i = 0; i < 8; i++) { 11448bdfc5daSXin Ji offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 11458bdfc5daSXin Ji g_edid_break = edid_read(ctx, offset, 11468bdfc5daSXin Ji pblock_buf); 11478bdfc5daSXin Ji 11480bae5687SHsin-Yi Wang if (g_edid_break < 0) 11498bdfc5daSXin Ji break; 11508bdfc5daSXin Ji 11518bdfc5daSXin Ji memcpy(&pedid_blocks_buf[offset], 11528bdfc5daSXin Ji pblock_buf, 11538bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11548bdfc5daSXin Ji } 11558bdfc5daSXin Ji 11568bdfc5daSXin Ji break; 11578bdfc5daSXin Ji case 2: 11588bdfc5daSXin Ji offset = 0x00; 11598bdfc5daSXin Ji 11608bdfc5daSXin Ji for (j = 0; j < 8; j++) { 11618bdfc5daSXin Ji edid_pos = (j + count * 8) * 11628bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 11638bdfc5daSXin Ji 11648bdfc5daSXin Ji if (g_edid_break == 1) 11658bdfc5daSXin Ji break; 11668bdfc5daSXin Ji 1167a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 11688bdfc5daSXin Ji pblock_buf, offset); 1169a23e0a2aSRobert Foss if (ret < 0) 1170a23e0a2aSRobert Foss return ret; 1171a23e0a2aSRobert Foss 11728bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 11738bdfc5daSXin Ji pblock_buf, 11748bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11758bdfc5daSXin Ji offset = offset + 0x10; 11768bdfc5daSXin Ji } 11778bdfc5daSXin Ji 11788bdfc5daSXin Ji break; 11798bdfc5daSXin Ji case 3: 11808bdfc5daSXin Ji offset = 0x80; 11818bdfc5daSXin Ji 11828bdfc5daSXin Ji for (j = 0; j < 8; j++) { 11838bdfc5daSXin Ji edid_pos = (j + count * 8) * 11848bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 11858bdfc5daSXin Ji if (g_edid_break == 1) 11868bdfc5daSXin Ji break; 11878bdfc5daSXin Ji 1188a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 11898bdfc5daSXin Ji pblock_buf, offset); 1190a23e0a2aSRobert Foss if (ret < 0) 1191a23e0a2aSRobert Foss return ret; 1192a23e0a2aSRobert Foss 11938bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 11948bdfc5daSXin Ji pblock_buf, 11958bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11968bdfc5daSXin Ji offset = offset + 0x10; 11978bdfc5daSXin Ji } 11988bdfc5daSXin Ji 11998bdfc5daSXin Ji break; 12008bdfc5daSXin Ji default: 12018bdfc5daSXin Ji break; 12028bdfc5daSXin Ji } 12038bdfc5daSXin Ji 12048bdfc5daSXin Ji count++; 12058bdfc5daSXin Ji 12068bdfc5daSXin Ji } while (blocks_num >= count); 12078bdfc5daSXin Ji 12088bdfc5daSXin Ji /* Check edid data */ 12098bdfc5daSXin Ji if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 12108bdfc5daSXin Ji DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 12118bdfc5daSXin Ji return -EINVAL; 12128bdfc5daSXin Ji } 12138bdfc5daSXin Ji 12148bdfc5daSXin Ji /* Reset aux channel */ 12157f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 12167f16d0f3SRobert Foss if (ret < 0) { 12177f16d0f3SRobert Foss DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 12187f16d0f3SRobert Foss return ret; 12197f16d0f3SRobert Foss } 12208bdfc5daSXin Ji 12218bdfc5daSXin Ji return (blocks_num + 1); 12228bdfc5daSXin Ji } 12238bdfc5daSXin Ji 12248bdfc5daSXin Ji static void anx7625_power_on(struct anx7625_data *ctx) 12258bdfc5daSXin Ji { 12268bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12276c744983SHsin-Yi Wang int ret, i; 12288bdfc5daSXin Ji 12298bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 12308bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 12318bdfc5daSXin Ji return; 12328bdfc5daSXin Ji } 12338bdfc5daSXin Ji 12346c744983SHsin-Yi Wang for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 12356c744983SHsin-Yi Wang ret = regulator_enable(ctx->pdata.supplies[i].consumer); 12366c744983SHsin-Yi Wang if (ret < 0) { 12376c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 12386c744983SHsin-Yi Wang i, ret); 12396c744983SHsin-Yi Wang goto reg_err; 12406c744983SHsin-Yi Wang } 12416c744983SHsin-Yi Wang usleep_range(2000, 2100); 12426c744983SHsin-Yi Wang } 12436c744983SHsin-Yi Wang 12441fcf24fbSHsin-Yi Wang usleep_range(11000, 12000); 12456c744983SHsin-Yi Wang 12468bdfc5daSXin Ji /* Power on pin enable */ 12478bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 1); 12488bdfc5daSXin Ji usleep_range(10000, 11000); 12498bdfc5daSXin Ji /* Power reset pin enable */ 12508bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 1); 12518bdfc5daSXin Ji usleep_range(10000, 11000); 12528bdfc5daSXin Ji 12538bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 12546c744983SHsin-Yi Wang return; 12556c744983SHsin-Yi Wang reg_err: 12566c744983SHsin-Yi Wang for (--i; i >= 0; i--) 12576c744983SHsin-Yi Wang regulator_disable(ctx->pdata.supplies[i].consumer); 12588bdfc5daSXin Ji } 12598bdfc5daSXin Ji 12608bdfc5daSXin Ji static void anx7625_power_standby(struct anx7625_data *ctx) 12618bdfc5daSXin Ji { 12628bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12636c744983SHsin-Yi Wang int ret; 12648bdfc5daSXin Ji 12658bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 12668bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 12678bdfc5daSXin Ji return; 12688bdfc5daSXin Ji } 12698bdfc5daSXin Ji 12708bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 0); 12718bdfc5daSXin Ji usleep_range(1000, 1100); 12728bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 0); 12738bdfc5daSXin Ji usleep_range(1000, 1100); 12746c744983SHsin-Yi Wang 12756c744983SHsin-Yi Wang ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 12766c744983SHsin-Yi Wang ctx->pdata.supplies); 12776c744983SHsin-Yi Wang if (ret < 0) 12786c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 12796c744983SHsin-Yi Wang 12808bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 12818bdfc5daSXin Ji } 12828bdfc5daSXin Ji 12838bdfc5daSXin Ji /* Basic configurations of ANX7625 */ 12848bdfc5daSXin Ji static void anx7625_config(struct anx7625_data *ctx) 12858bdfc5daSXin Ji { 12868bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12878bdfc5daSXin Ji XTAL_FRQ_SEL, XTAL_FRQ_27M); 12888bdfc5daSXin Ji } 12898bdfc5daSXin Ji 12908bdfc5daSXin Ji static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 12918bdfc5daSXin Ji { 12928bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12938bdfc5daSXin Ji int ret; 12948bdfc5daSXin Ji 12958bdfc5daSXin Ji /* Reset main ocm */ 12968bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 12978bdfc5daSXin Ji /* Disable PD */ 12988bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12998bdfc5daSXin Ji AP_AV_STATUS, AP_DISABLE_PD); 13008bdfc5daSXin Ji /* Release main ocm */ 13018bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 13028bdfc5daSXin Ji 13038bdfc5daSXin Ji if (ret < 0) 13048bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 13058bdfc5daSXin Ji else 13068bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 13078bdfc5daSXin Ji } 13088bdfc5daSXin Ji 13098bdfc5daSXin Ji static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 13108bdfc5daSXin Ji { 13118bdfc5daSXin Ji int ret; 13128bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13138bdfc5daSXin Ji 13148bdfc5daSXin Ji /* Check interface workable */ 13158bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 13168bdfc5daSXin Ji FLASH_LOAD_STA); 13178bdfc5daSXin Ji if (ret < 0) { 13188bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 13198bdfc5daSXin Ji return ret; 13208bdfc5daSXin Ji } 13218bdfc5daSXin Ji if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 13228bdfc5daSXin Ji return -ENODEV; 13238bdfc5daSXin Ji 13248bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 13258bdfc5daSXin Ji 13268bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 13278bdfc5daSXin Ji anx7625_reg_read(ctx, 13288bdfc5daSXin Ji ctx->i2c.rx_p0_client, 13298bdfc5daSXin Ji OCM_FW_VERSION), 13308bdfc5daSXin Ji anx7625_reg_read(ctx, 13318bdfc5daSXin Ji ctx->i2c.rx_p0_client, 13328bdfc5daSXin Ji OCM_FW_REVERSION)); 13338bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 13348bdfc5daSXin Ji ANX7625_DRV_VERSION); 13358bdfc5daSXin Ji 13368bdfc5daSXin Ji return 0; 13378bdfc5daSXin Ji } 13388bdfc5daSXin Ji 13398bdfc5daSXin Ji static void anx7625_power_on_init(struct anx7625_data *ctx) 13408bdfc5daSXin Ji { 13418bdfc5daSXin Ji int retry_count, i; 13428bdfc5daSXin Ji 13438bdfc5daSXin Ji for (retry_count = 0; retry_count < 3; retry_count++) { 13448bdfc5daSXin Ji anx7625_power_on(ctx); 13458bdfc5daSXin Ji anx7625_config(ctx); 13468bdfc5daSXin Ji 13478bdfc5daSXin Ji for (i = 0; i < OCM_LOADING_TIME; i++) { 13488bdfc5daSXin Ji if (!anx7625_ocm_loading_check(ctx)) 13498bdfc5daSXin Ji return; 13508bdfc5daSXin Ji usleep_range(1000, 1100); 13518bdfc5daSXin Ji } 13528bdfc5daSXin Ji anx7625_power_standby(ctx); 13538bdfc5daSXin Ji } 13548bdfc5daSXin Ji } 13558bdfc5daSXin Ji 13568bdfc5daSXin Ji static void anx7625_init_gpio(struct anx7625_data *platform) 13578bdfc5daSXin Ji { 13588bdfc5daSXin Ji struct device *dev = &platform->client->dev; 13598bdfc5daSXin Ji 13608bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 13618bdfc5daSXin Ji 13628bdfc5daSXin Ji /* Gpio for chip power enable */ 13638bdfc5daSXin Ji platform->pdata.gpio_p_on = 13648bdfc5daSXin Ji devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 13657020449bSXin Ji if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 13667020449bSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 13677020449bSXin Ji platform->pdata.gpio_p_on = NULL; 13687020449bSXin Ji } 13697020449bSXin Ji 13708bdfc5daSXin Ji /* Gpio for chip reset */ 13718bdfc5daSXin Ji platform->pdata.gpio_reset = 13728bdfc5daSXin Ji devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 13737020449bSXin Ji if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 13747020449bSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 13757020449bSXin Ji platform->pdata.gpio_reset = NULL; 13767020449bSXin Ji } 13778bdfc5daSXin Ji 13788bdfc5daSXin Ji if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 13798bdfc5daSXin Ji platform->pdata.low_power_mode = 1; 13808bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 13818bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_p_on), 13828bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_reset)); 13838bdfc5daSXin Ji } else { 13848bdfc5daSXin Ji platform->pdata.low_power_mode = 0; 13858bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 13868bdfc5daSXin Ji } 13878bdfc5daSXin Ji } 13888bdfc5daSXin Ji 13898bdfc5daSXin Ji static void anx7625_stop_dp_work(struct anx7625_data *ctx) 13908bdfc5daSXin Ji { 13918bdfc5daSXin Ji ctx->hpd_status = 0; 13928bdfc5daSXin Ji ctx->hpd_high_cnt = 0; 13938bdfc5daSXin Ji ctx->display_timing_valid = 0; 13948bdfc5daSXin Ji } 13958bdfc5daSXin Ji 13968bdfc5daSXin Ji static void anx7625_start_dp_work(struct anx7625_data *ctx) 13978bdfc5daSXin Ji { 13988bdfc5daSXin Ji int ret; 13998bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14008bdfc5daSXin Ji 14018bdfc5daSXin Ji if (ctx->hpd_high_cnt >= 2) { 14028bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 14038bdfc5daSXin Ji return; 14048bdfc5daSXin Ji } 14058bdfc5daSXin Ji 1406fd0310b6SXin Ji ctx->hpd_status = 1; 14078bdfc5daSXin Ji ctx->hpd_high_cnt++; 14088bdfc5daSXin Ji 14098bdfc5daSXin Ji /* Not support HDCP */ 14108bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 14118bdfc5daSXin Ji 14128bdfc5daSXin Ji /* Try auth flag */ 14138bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 14148bdfc5daSXin Ji /* Interrupt for DRM */ 14158bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1416fd0310b6SXin Ji if (ret < 0) { 1417fd0310b6SXin Ji DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 14188bdfc5daSXin Ji return; 1419fd0310b6SXin Ji } 14208bdfc5daSXin Ji 14218bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 14228bdfc5daSXin Ji if (ret < 0) 14238bdfc5daSXin Ji return; 14248bdfc5daSXin Ji 14258bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 14268bdfc5daSXin Ji } 14278bdfc5daSXin Ji 14288bdfc5daSXin Ji static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 14298bdfc5daSXin Ji { 14308bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 14318bdfc5daSXin Ji } 14328bdfc5daSXin Ji 14338bdfc5daSXin Ji static void anx7625_hpd_polling(struct anx7625_data *ctx) 14348bdfc5daSXin Ji { 14358bdfc5daSXin Ji int ret, val; 14368bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14378bdfc5daSXin Ji 1438fd0310b6SXin Ji /* Interrupt mode, no need poll HPD status, just return */ 1439fd0310b6SXin Ji if (ctx->pdata.intp_irq) 1440fd0310b6SXin Ji return; 1441fd0310b6SXin Ji 14428bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 14438bdfc5daSXin Ji ctx, val, 14448bdfc5daSXin Ji ((val & HPD_STATUS) || (val < 0)), 14458bdfc5daSXin Ji 5000, 14468bdfc5daSXin Ji 5000 * 100); 14478bdfc5daSXin Ji if (ret) { 144860487584SPi-Hsun Shih DRM_DEV_ERROR(dev, "no hpd.\n"); 144960487584SPi-Hsun Shih return; 145060487584SPi-Hsun Shih } 145160487584SPi-Hsun Shih 145260487584SPi-Hsun Shih DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 14538bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 14548bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 14558bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 14568bdfc5daSXin Ji INTERFACE_CHANGE_INT, 0); 14578bdfc5daSXin Ji 14588bdfc5daSXin Ji anx7625_start_dp_work(ctx); 14598bdfc5daSXin Ji 146060487584SPi-Hsun Shih if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 146160487584SPi-Hsun Shih drm_helper_hpd_irq_event(ctx->bridge.dev); 14628bdfc5daSXin Ji } 14638bdfc5daSXin Ji 14648bdfc5daSXin Ji static void anx7625_remove_edid(struct anx7625_data *ctx) 14658bdfc5daSXin Ji { 14668bdfc5daSXin Ji ctx->slimport_edid_p.edid_block_num = -1; 14678bdfc5daSXin Ji } 14688bdfc5daSXin Ji 1469fd0310b6SXin Ji static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1470fd0310b6SXin Ji { 1471fd0310b6SXin Ji int i; 1472fd0310b6SXin Ji 1473fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1474fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1475fd0310b6SXin Ji DP_TX_LANE0_SWING_REG0 + i, 1476fd0310b6SXin Ji ctx->pdata.lane0_reg_data[i] & 0xFF); 1477fd0310b6SXin Ji 1478fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1479fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1480fd0310b6SXin Ji DP_TX_LANE1_SWING_REG0 + i, 1481fd0310b6SXin Ji ctx->pdata.lane1_reg_data[i] & 0xFF); 1482fd0310b6SXin Ji } 1483fd0310b6SXin Ji 14848bdfc5daSXin Ji static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 14858bdfc5daSXin Ji { 14868bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14878bdfc5daSXin Ji 14888bdfc5daSXin Ji /* HPD changed */ 14898bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 14908bdfc5daSXin Ji (u32)on); 14918bdfc5daSXin Ji 14928bdfc5daSXin Ji if (on == 0) { 14938bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 14948bdfc5daSXin Ji anx7625_remove_edid(ctx); 14958bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 14968bdfc5daSXin Ji } else { 14978bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 14988bdfc5daSXin Ji anx7625_start_dp_work(ctx); 1499fd0310b6SXin Ji anx7625_dp_adjust_swing(ctx); 15008bdfc5daSXin Ji } 15018bdfc5daSXin Ji } 15028bdfc5daSXin Ji 15038bdfc5daSXin Ji static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 15048bdfc5daSXin Ji { 15058bdfc5daSXin Ji int intr_vector, status; 15068bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15078bdfc5daSXin Ji 15088bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 15098bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 15108bdfc5daSXin Ji if (status < 0) { 15118bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 15128bdfc5daSXin Ji return status; 15138bdfc5daSXin Ji } 15148bdfc5daSXin Ji 15158bdfc5daSXin Ji intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 15168bdfc5daSXin Ji INTERFACE_CHANGE_INT); 15178bdfc5daSXin Ji if (intr_vector < 0) { 15188bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 15198bdfc5daSXin Ji return intr_vector; 15208bdfc5daSXin Ji } 15218bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 15228bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 15238bdfc5daSXin Ji INTERFACE_CHANGE_INT, 15248bdfc5daSXin Ji intr_vector & (~intr_vector)); 15258bdfc5daSXin Ji if (status < 0) { 15268bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 15278bdfc5daSXin Ji return status; 15288bdfc5daSXin Ji } 15298bdfc5daSXin Ji 15308bdfc5daSXin Ji if (!(intr_vector & HPD_STATUS_CHANGE)) 15318bdfc5daSXin Ji return -ENOENT; 15328bdfc5daSXin Ji 15338bdfc5daSXin Ji status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 15348bdfc5daSXin Ji SYSTEM_STSTUS); 15358bdfc5daSXin Ji if (status < 0) { 15368bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 15378bdfc5daSXin Ji return status; 15388bdfc5daSXin Ji } 15398bdfc5daSXin Ji 15408bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 15418bdfc5daSXin Ji dp_hpd_change_handler(ctx, status & HPD_STATUS); 15428bdfc5daSXin Ji 15438bdfc5daSXin Ji return 0; 15448bdfc5daSXin Ji } 15458bdfc5daSXin Ji 15468bdfc5daSXin Ji static void anx7625_work_func(struct work_struct *work) 15478bdfc5daSXin Ji { 15488bdfc5daSXin Ji int event; 15498bdfc5daSXin Ji struct anx7625_data *ctx = container_of(work, 15508bdfc5daSXin Ji struct anx7625_data, work); 15518bdfc5daSXin Ji 15528bdfc5daSXin Ji mutex_lock(&ctx->lock); 155360487584SPi-Hsun Shih 155460487584SPi-Hsun Shih if (pm_runtime_suspended(&ctx->client->dev)) 155560487584SPi-Hsun Shih goto unlock; 155660487584SPi-Hsun Shih 15578bdfc5daSXin Ji event = anx7625_hpd_change_detect(ctx); 15588bdfc5daSXin Ji if (event < 0) 155960487584SPi-Hsun Shih goto unlock; 15608bdfc5daSXin Ji 15618bdfc5daSXin Ji if (ctx->bridge_attached) 15628bdfc5daSXin Ji drm_helper_hpd_irq_event(ctx->bridge.dev); 156360487584SPi-Hsun Shih 156460487584SPi-Hsun Shih unlock: 156560487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 15668bdfc5daSXin Ji } 15678bdfc5daSXin Ji 15688bdfc5daSXin Ji static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 15698bdfc5daSXin Ji { 15708bdfc5daSXin Ji struct anx7625_data *ctx = (struct anx7625_data *)data; 15718bdfc5daSXin Ji 15728bdfc5daSXin Ji queue_work(ctx->workqueue, &ctx->work); 15738bdfc5daSXin Ji 15748bdfc5daSXin Ji return IRQ_HANDLED; 15758bdfc5daSXin Ji } 15768bdfc5daSXin Ji 1577fd0310b6SXin Ji static int anx7625_get_swing_setting(struct device *dev, 1578fd0310b6SXin Ji struct anx7625_platform_data *pdata) 1579fd0310b6SXin Ji { 1580fd0310b6SXin Ji int num_regs; 1581fd0310b6SXin Ji 1582fd0310b6SXin Ji if (of_get_property(dev->of_node, 1583fd0310b6SXin Ji "analogix,lane0-swing", &num_regs)) { 1584fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1585fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1586fd0310b6SXin Ji 1587fd0310b6SXin Ji pdata->dp_lane0_swing_reg_cnt = num_regs; 1588fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1589fd0310b6SXin Ji pdata->lane0_reg_data, num_regs); 1590fd0310b6SXin Ji } 1591fd0310b6SXin Ji 1592fd0310b6SXin Ji if (of_get_property(dev->of_node, 1593fd0310b6SXin Ji "analogix,lane1-swing", &num_regs)) { 1594fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1595fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1596fd0310b6SXin Ji 1597fd0310b6SXin Ji pdata->dp_lane1_swing_reg_cnt = num_regs; 1598fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1599fd0310b6SXin Ji pdata->lane1_reg_data, num_regs); 1600fd0310b6SXin Ji } 1601fd0310b6SXin Ji 1602fd0310b6SXin Ji return 0; 1603fd0310b6SXin Ji } 1604fd0310b6SXin Ji 16058bdfc5daSXin Ji static int anx7625_parse_dt(struct device *dev, 16068bdfc5daSXin Ji struct anx7625_platform_data *pdata) 16078bdfc5daSXin Ji { 1608fd0310b6SXin Ji struct device_node *np = dev->of_node, *ep0; 16098bdfc5daSXin Ji struct drm_panel *panel; 16108bdfc5daSXin Ji int ret; 1611fd0310b6SXin Ji int bus_type, mipi_lanes; 16128bdfc5daSXin Ji 1613fd0310b6SXin Ji anx7625_get_swing_setting(dev, pdata); 1614fd0310b6SXin Ji 1615fd0310b6SXin Ji pdata->is_dpi = 1; /* default dpi mode */ 16168bdfc5daSXin Ji pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 16178bdfc5daSXin Ji if (!pdata->mipi_host_node) { 16188bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 16198bdfc5daSXin Ji return -ENODEV; 16208bdfc5daSXin Ji } 16218bdfc5daSXin Ji 1622fd0310b6SXin Ji bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1623fd0310b6SXin Ji mipi_lanes = MAX_LANES_SUPPORT; 1624fd0310b6SXin Ji ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1625fd0310b6SXin Ji if (ep0) { 1626fd0310b6SXin Ji if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1627fd0310b6SXin Ji bus_type = 0; 1628fd0310b6SXin Ji 1629fd0310b6SXin Ji mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1630fd0310b6SXin Ji } 1631fd0310b6SXin Ji 1632fd0310b6SXin Ji if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1633fd0310b6SXin Ji pdata->is_dpi = 0; 1634fd0310b6SXin Ji 1635fd0310b6SXin Ji pdata->mipi_lanes = mipi_lanes; 1636fd0310b6SXin Ji if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1637fd0310b6SXin Ji pdata->mipi_lanes = MAX_LANES_SUPPORT; 1638fd0310b6SXin Ji 1639fd0310b6SXin Ji if (pdata->is_dpi) 1640fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1641fd0310b6SXin Ji else 1642fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 16438bdfc5daSXin Ji 1644566fef12SXin Ji if (of_property_read_bool(np, "analogix,audio-enable")) 1645566fef12SXin Ji pdata->audio_en = 1; 1646566fef12SXin Ji 16478bdfc5daSXin Ji ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 16488bdfc5daSXin Ji if (ret < 0) { 16498bdfc5daSXin Ji if (ret == -ENODEV) 16508bdfc5daSXin Ji return 0; 16518bdfc5daSXin Ji return ret; 16528bdfc5daSXin Ji } 16538bdfc5daSXin Ji if (!panel) 16548bdfc5daSXin Ji return -ENODEV; 16558bdfc5daSXin Ji 16568bdfc5daSXin Ji pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 16578bdfc5daSXin Ji if (IS_ERR(pdata->panel_bridge)) 16588bdfc5daSXin Ji return PTR_ERR(pdata->panel_bridge); 16598bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 16608bdfc5daSXin Ji 16618bdfc5daSXin Ji return 0; 16628bdfc5daSXin Ji } 16638bdfc5daSXin Ji 1664adca62ecSHsin-Yi Wang static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1665adca62ecSHsin-Yi Wang { 1666adca62ecSHsin-Yi Wang struct device_node *bus, *panel; 1667adca62ecSHsin-Yi Wang 1668adca62ecSHsin-Yi Wang bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1669adca62ecSHsin-Yi Wang if (!bus) 1670adca62ecSHsin-Yi Wang return false; 1671adca62ecSHsin-Yi Wang 1672adca62ecSHsin-Yi Wang panel = of_get_child_by_name(bus, "panel"); 1673adca62ecSHsin-Yi Wang of_node_put(bus); 1674adca62ecSHsin-Yi Wang if (!panel) 1675adca62ecSHsin-Yi Wang return false; 1676adca62ecSHsin-Yi Wang of_node_put(panel); 1677adca62ecSHsin-Yi Wang 1678adca62ecSHsin-Yi Wang return true; 1679adca62ecSHsin-Yi Wang } 1680adca62ecSHsin-Yi Wang 16818bdfc5daSXin Ji static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 16828bdfc5daSXin Ji { 16838bdfc5daSXin Ji return container_of(bridge, struct anx7625_data, bridge); 16848bdfc5daSXin Ji } 16858bdfc5daSXin Ji 1686adca62ecSHsin-Yi Wang static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1687adca62ecSHsin-Yi Wang struct drm_dp_aux_msg *msg) 1688adca62ecSHsin-Yi Wang { 1689adca62ecSHsin-Yi Wang struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1690adca62ecSHsin-Yi Wang struct device *dev = &ctx->client->dev; 1691adca62ecSHsin-Yi Wang u8 request = msg->request & ~DP_AUX_I2C_MOT; 1692adca62ecSHsin-Yi Wang int ret = 0; 1693adca62ecSHsin-Yi Wang 1694adca62ecSHsin-Yi Wang pm_runtime_get_sync(dev); 1695adca62ecSHsin-Yi Wang msg->reply = 0; 1696adca62ecSHsin-Yi Wang switch (request) { 1697adca62ecSHsin-Yi Wang case DP_AUX_NATIVE_WRITE: 1698adca62ecSHsin-Yi Wang case DP_AUX_I2C_WRITE: 1699adca62ecSHsin-Yi Wang case DP_AUX_NATIVE_READ: 1700adca62ecSHsin-Yi Wang case DP_AUX_I2C_READ: 1701adca62ecSHsin-Yi Wang break; 1702adca62ecSHsin-Yi Wang default: 1703adca62ecSHsin-Yi Wang ret = -EINVAL; 1704adca62ecSHsin-Yi Wang } 1705adca62ecSHsin-Yi Wang if (!ret) 1706adca62ecSHsin-Yi Wang ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1707adca62ecSHsin-Yi Wang msg->size, msg->buffer); 1708adca62ecSHsin-Yi Wang pm_runtime_mark_last_busy(dev); 1709adca62ecSHsin-Yi Wang pm_runtime_put_autosuspend(dev); 1710adca62ecSHsin-Yi Wang 1711adca62ecSHsin-Yi Wang return ret; 1712adca62ecSHsin-Yi Wang } 1713adca62ecSHsin-Yi Wang 17148bdfc5daSXin Ji static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 17158bdfc5daSXin Ji { 17168bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17178bdfc5daSXin Ji struct s_edid_data *p_edid = &ctx->slimport_edid_p; 17188bdfc5daSXin Ji int edid_num; 17198bdfc5daSXin Ji u8 *edid; 17208bdfc5daSXin Ji 17218bdfc5daSXin Ji edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 17228bdfc5daSXin Ji if (!edid) { 17238bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 17248bdfc5daSXin Ji return NULL; 17258bdfc5daSXin Ji } 17268bdfc5daSXin Ji 17278bdfc5daSXin Ji if (ctx->slimport_edid_p.edid_block_num > 0) { 17288bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 17298bdfc5daSXin Ji FOUR_BLOCK_SIZE); 17308bdfc5daSXin Ji return (struct edid *)edid; 17318bdfc5daSXin Ji } 17328bdfc5daSXin Ji 173360487584SPi-Hsun Shih pm_runtime_get_sync(dev); 17348bdfc5daSXin Ji edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 17353203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 17368bdfc5daSXin Ji 17378bdfc5daSXin Ji if (edid_num < 1) { 17388bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 17398bdfc5daSXin Ji kfree(edid); 17408bdfc5daSXin Ji return NULL; 17418bdfc5daSXin Ji } 17428bdfc5daSXin Ji 17438bdfc5daSXin Ji p_edid->edid_block_num = edid_num; 17448bdfc5daSXin Ji 17458bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 17468bdfc5daSXin Ji return (struct edid *)edid; 17478bdfc5daSXin Ji } 17488bdfc5daSXin Ji 17498bdfc5daSXin Ji static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 17508bdfc5daSXin Ji { 17518bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17528bdfc5daSXin Ji 1753fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 17548bdfc5daSXin Ji 1755fd0310b6SXin Ji if (ctx->pdata.panel_bridge) 17568bdfc5daSXin Ji return connector_status_connected; 1757fd0310b6SXin Ji 1758fd0310b6SXin Ji return ctx->hpd_status ? connector_status_connected : 1759fd0310b6SXin Ji connector_status_disconnected; 17608bdfc5daSXin Ji } 17618bdfc5daSXin Ji 1762566fef12SXin Ji static int anx7625_audio_hw_params(struct device *dev, void *data, 1763566fef12SXin Ji struct hdmi_codec_daifmt *fmt, 1764566fef12SXin Ji struct hdmi_codec_params *params) 1765566fef12SXin Ji { 1766566fef12SXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 1767566fef12SXin Ji int wl, ch, rate; 1768566fef12SXin Ji int ret = 0; 1769566fef12SXin Ji 1770566fef12SXin Ji if (fmt->fmt != HDMI_DSP_A) { 1771566fef12SXin Ji DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1772566fef12SXin Ji return -EINVAL; 1773566fef12SXin Ji } 1774566fef12SXin Ji 1775566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1776566fef12SXin Ji params->sample_rate, params->sample_width, 1777566fef12SXin Ji params->cea.channels); 1778566fef12SXin Ji 1779566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1780566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 1781566fef12SXin Ji ~I2S_SLAVE_MODE, 1782566fef12SXin Ji TDM_SLAVE_MODE); 1783566fef12SXin Ji 1784566fef12SXin Ji /* Word length */ 1785566fef12SXin Ji switch (params->sample_width) { 1786566fef12SXin Ji case 16: 1787566fef12SXin Ji wl = AUDIO_W_LEN_16_20MAX; 1788566fef12SXin Ji break; 1789566fef12SXin Ji case 18: 1790566fef12SXin Ji wl = AUDIO_W_LEN_18_20MAX; 1791566fef12SXin Ji break; 1792566fef12SXin Ji case 20: 1793566fef12SXin Ji wl = AUDIO_W_LEN_20_20MAX; 1794566fef12SXin Ji break; 1795566fef12SXin Ji case 24: 1796566fef12SXin Ji wl = AUDIO_W_LEN_24_24MAX; 1797566fef12SXin Ji break; 1798566fef12SXin Ji default: 1799566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1800566fef12SXin Ji params->sample_width); 1801566fef12SXin Ji return -EINVAL; 1802566fef12SXin Ji } 1803566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1804566fef12SXin Ji AUDIO_CHANNEL_STATUS_5, 1805566fef12SXin Ji 0xf0, wl); 1806566fef12SXin Ji 1807566fef12SXin Ji /* Channel num */ 1808566fef12SXin Ji switch (params->cea.channels) { 1809566fef12SXin Ji case 2: 1810566fef12SXin Ji ch = I2S_CH_2; 1811566fef12SXin Ji break; 1812566fef12SXin Ji case 4: 1813566fef12SXin Ji ch = TDM_CH_4; 1814566fef12SXin Ji break; 1815566fef12SXin Ji case 6: 1816566fef12SXin Ji ch = TDM_CH_6; 1817566fef12SXin Ji break; 1818566fef12SXin Ji case 8: 1819566fef12SXin Ji ch = TDM_CH_8; 1820566fef12SXin Ji break; 1821566fef12SXin Ji default: 1822566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1823566fef12SXin Ji params->cea.channels); 1824566fef12SXin Ji return -EINVAL; 1825566fef12SXin Ji } 1826566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1827566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1828566fef12SXin Ji if (ch > I2S_CH_2) 1829566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1830566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1831566fef12SXin Ji else 1832566fef12SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1833566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1834566fef12SXin Ji 1835566fef12SXin Ji /* FS */ 1836566fef12SXin Ji switch (params->sample_rate) { 1837566fef12SXin Ji case 32000: 1838566fef12SXin Ji rate = AUDIO_FS_32K; 1839566fef12SXin Ji break; 1840566fef12SXin Ji case 44100: 1841566fef12SXin Ji rate = AUDIO_FS_441K; 1842566fef12SXin Ji break; 1843566fef12SXin Ji case 48000: 1844566fef12SXin Ji rate = AUDIO_FS_48K; 1845566fef12SXin Ji break; 1846566fef12SXin Ji case 88200: 1847566fef12SXin Ji rate = AUDIO_FS_882K; 1848566fef12SXin Ji break; 1849566fef12SXin Ji case 96000: 1850566fef12SXin Ji rate = AUDIO_FS_96K; 1851566fef12SXin Ji break; 1852566fef12SXin Ji case 176400: 1853566fef12SXin Ji rate = AUDIO_FS_1764K; 1854566fef12SXin Ji break; 1855566fef12SXin Ji case 192000: 1856566fef12SXin Ji rate = AUDIO_FS_192K; 1857566fef12SXin Ji break; 1858566fef12SXin Ji default: 1859566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1860566fef12SXin Ji params->sample_rate); 1861566fef12SXin Ji return -EINVAL; 1862566fef12SXin Ji } 1863566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1864566fef12SXin Ji AUDIO_CHANNEL_STATUS_4, 1865566fef12SXin Ji 0xf0, rate); 1866566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1867566fef12SXin Ji AP_AV_STATUS, AP_AUDIO_CHG); 1868566fef12SXin Ji if (ret < 0) { 1869566fef12SXin Ji DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1870566fef12SXin Ji return -EIO; 1871566fef12SXin Ji } 1872566fef12SXin Ji 1873566fef12SXin Ji return 0; 1874566fef12SXin Ji } 1875566fef12SXin Ji 1876566fef12SXin Ji static void anx7625_audio_shutdown(struct device *dev, void *data) 1877566fef12SXin Ji { 1878566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1879566fef12SXin Ji } 1880566fef12SXin Ji 1881566fef12SXin Ji static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1882566fef12SXin Ji struct device_node *endpoint) 1883566fef12SXin Ji { 1884566fef12SXin Ji struct of_endpoint of_ep; 1885566fef12SXin Ji int ret; 1886566fef12SXin Ji 1887566fef12SXin Ji ret = of_graph_parse_endpoint(endpoint, &of_ep); 1888566fef12SXin Ji if (ret < 0) 1889566fef12SXin Ji return ret; 1890566fef12SXin Ji 1891566fef12SXin Ji /* 1892566fef12SXin Ji * HDMI sound should be located at external DPI port 1893566fef12SXin Ji * Didn't have good way to check where is internal(DSI) 1894566fef12SXin Ji * or external(DPI) bridge 1895566fef12SXin Ji */ 1896566fef12SXin Ji return 0; 1897566fef12SXin Ji } 1898566fef12SXin Ji 1899566fef12SXin Ji static void 1900566fef12SXin Ji anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1901566fef12SXin Ji enum drm_connector_status status) 1902566fef12SXin Ji { 1903566fef12SXin Ji if (ctx->plugged_cb && ctx->codec_dev) { 1904566fef12SXin Ji ctx->plugged_cb(ctx->codec_dev, 1905566fef12SXin Ji status == connector_status_connected); 1906566fef12SXin Ji } 1907566fef12SXin Ji } 1908566fef12SXin Ji 1909566fef12SXin Ji static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1910566fef12SXin Ji hdmi_codec_plugged_cb fn, 1911566fef12SXin Ji struct device *codec_dev) 1912566fef12SXin Ji { 1913566fef12SXin Ji struct anx7625_data *ctx = data; 1914566fef12SXin Ji 1915566fef12SXin Ji ctx->plugged_cb = fn; 1916566fef12SXin Ji ctx->codec_dev = codec_dev; 1917566fef12SXin Ji anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1918566fef12SXin Ji 1919566fef12SXin Ji return 0; 1920566fef12SXin Ji } 1921566fef12SXin Ji 1922607a264eSXin Ji static int anx7625_audio_get_eld(struct device *dev, void *data, 1923607a264eSXin Ji u8 *buf, size_t len) 1924607a264eSXin Ji { 1925607a264eSXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 1926607a264eSXin Ji 1927607a264eSXin Ji if (!ctx->connector) { 1928607a264eSXin Ji dev_err(dev, "connector not initial\n"); 1929607a264eSXin Ji return -EINVAL; 1930607a264eSXin Ji } 1931607a264eSXin Ji 1932607a264eSXin Ji dev_dbg(dev, "audio copy eld\n"); 1933607a264eSXin Ji memcpy(buf, ctx->connector->eld, 1934607a264eSXin Ji min(sizeof(ctx->connector->eld), len)); 1935607a264eSXin Ji 1936607a264eSXin Ji return 0; 1937607a264eSXin Ji } 1938607a264eSXin Ji 1939566fef12SXin Ji static const struct hdmi_codec_ops anx7625_codec_ops = { 1940566fef12SXin Ji .hw_params = anx7625_audio_hw_params, 1941566fef12SXin Ji .audio_shutdown = anx7625_audio_shutdown, 1942607a264eSXin Ji .get_eld = anx7625_audio_get_eld, 1943566fef12SXin Ji .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1944566fef12SXin Ji .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1945566fef12SXin Ji }; 1946566fef12SXin Ji 1947566fef12SXin Ji static void anx7625_unregister_audio(struct anx7625_data *ctx) 1948566fef12SXin Ji { 1949566fef12SXin Ji struct device *dev = &ctx->client->dev; 1950566fef12SXin Ji 1951566fef12SXin Ji if (ctx->audio_pdev) { 1952566fef12SXin Ji platform_device_unregister(ctx->audio_pdev); 1953566fef12SXin Ji ctx->audio_pdev = NULL; 1954566fef12SXin Ji } 1955566fef12SXin Ji 1956566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1957566fef12SXin Ji } 1958566fef12SXin Ji 1959566fef12SXin Ji static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1960566fef12SXin Ji { 1961566fef12SXin Ji struct hdmi_codec_pdata codec_data = { 1962566fef12SXin Ji .ops = &anx7625_codec_ops, 1963566fef12SXin Ji .max_i2s_channels = 8, 1964566fef12SXin Ji .i2s = 1, 1965566fef12SXin Ji .data = ctx, 1966566fef12SXin Ji }; 1967566fef12SXin Ji 1968566fef12SXin Ji ctx->audio_pdev = platform_device_register_data(dev, 1969566fef12SXin Ji HDMI_CODEC_DRV_NAME, 1970566fef12SXin Ji PLATFORM_DEVID_AUTO, 1971566fef12SXin Ji &codec_data, 1972566fef12SXin Ji sizeof(codec_data)); 1973566fef12SXin Ji 1974566fef12SXin Ji if (IS_ERR(ctx->audio_pdev)) 197583ddd806SDan Carpenter return PTR_ERR(ctx->audio_pdev); 1976566fef12SXin Ji 1977566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1978566fef12SXin Ji 1979566fef12SXin Ji return 0; 1980566fef12SXin Ji } 1981566fef12SXin Ji 19828bdfc5daSXin Ji static int anx7625_attach_dsi(struct anx7625_data *ctx) 19838bdfc5daSXin Ji { 19848bdfc5daSXin Ji struct mipi_dsi_device *dsi; 19858bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 19868bdfc5daSXin Ji struct mipi_dsi_host *host; 19878bdfc5daSXin Ji const struct mipi_dsi_device_info info = { 19888bdfc5daSXin Ji .type = "anx7625", 19898bdfc5daSXin Ji .channel = 0, 19908bdfc5daSXin Ji .node = NULL, 19918bdfc5daSXin Ji }; 199225a390a9SMaxime Ripard int ret; 19938bdfc5daSXin Ji 19948bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 19958bdfc5daSXin Ji 19968bdfc5daSXin Ji host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 19978bdfc5daSXin Ji if (!host) { 19988bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 199926933299Sowen return -EPROBE_DEFER; 20008bdfc5daSXin Ji } 20018bdfc5daSXin Ji 200225a390a9SMaxime Ripard dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 20038bdfc5daSXin Ji if (IS_ERR(dsi)) { 20048bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 20058bdfc5daSXin Ji return -EINVAL; 20068bdfc5daSXin Ji } 20078bdfc5daSXin Ji 2008fd0310b6SXin Ji dsi->lanes = ctx->pdata.mipi_lanes; 20098bdfc5daSXin Ji dsi->format = MIPI_DSI_FMT_RGB888; 20108bdfc5daSXin Ji dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 20118bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 20128bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_HSE; 20138bdfc5daSXin Ji 201425a390a9SMaxime Ripard ret = devm_mipi_dsi_attach(dev, dsi); 201525a390a9SMaxime Ripard if (ret) { 20168bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 201725a390a9SMaxime Ripard return ret; 20188bdfc5daSXin Ji } 20198bdfc5daSXin Ji 20208bdfc5daSXin Ji ctx->dsi = dsi; 20218bdfc5daSXin Ji 20228bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 20238bdfc5daSXin Ji 20248bdfc5daSXin Ji return 0; 20258bdfc5daSXin Ji } 20268bdfc5daSXin Ji 2027cd1637c7SXin Ji static void hdcp_check_work_func(struct work_struct *work) 2028cd1637c7SXin Ji { 2029cd1637c7SXin Ji u8 status; 2030cd1637c7SXin Ji struct delayed_work *dwork; 2031cd1637c7SXin Ji struct anx7625_data *ctx; 2032cd1637c7SXin Ji struct device *dev; 2033cd1637c7SXin Ji struct drm_device *drm_dev; 2034cd1637c7SXin Ji 2035cd1637c7SXin Ji dwork = to_delayed_work(work); 2036cd1637c7SXin Ji ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2037cd1637c7SXin Ji dev = &ctx->client->dev; 2038cd1637c7SXin Ji 2039cd1637c7SXin Ji if (!ctx->connector) { 2040cd1637c7SXin Ji dev_err(dev, "HDCP connector is null!"); 2041cd1637c7SXin Ji return; 2042cd1637c7SXin Ji } 2043cd1637c7SXin Ji 2044cd1637c7SXin Ji drm_dev = ctx->connector->dev; 2045cd1637c7SXin Ji drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2046cd1637c7SXin Ji mutex_lock(&ctx->hdcp_wq_lock); 2047cd1637c7SXin Ji 2048cd1637c7SXin Ji status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2049cd1637c7SXin Ji dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2050cd1637c7SXin Ji if (status & BIT(1)) { 2051cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2052cd1637c7SXin Ji drm_hdcp_update_content_protection(ctx->connector, 2053cd1637c7SXin Ji ctx->hdcp_cp); 2054cd1637c7SXin Ji dev_dbg(dev, "update CP to ENABLE\n"); 2055cd1637c7SXin Ji } 2056cd1637c7SXin Ji 2057cd1637c7SXin Ji mutex_unlock(&ctx->hdcp_wq_lock); 2058cd1637c7SXin Ji drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2059cd1637c7SXin Ji } 2060cd1637c7SXin Ji 2061cd1637c7SXin Ji static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2062cd1637c7SXin Ji struct drm_connector_state *state) 2063cd1637c7SXin Ji { 2064cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 2065cd1637c7SXin Ji int cp; 2066cd1637c7SXin Ji 2067cd1637c7SXin Ji dev_dbg(dev, "hdcp state check\n"); 2068cd1637c7SXin Ji cp = state->content_protection; 2069cd1637c7SXin Ji 2070cd1637c7SXin Ji if (cp == ctx->hdcp_cp) 2071cd1637c7SXin Ji return 0; 2072cd1637c7SXin Ji 2073cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2074cd1637c7SXin Ji if (ctx->dp_en) { 2075cd1637c7SXin Ji dev_dbg(dev, "enable HDCP\n"); 2076cd1637c7SXin Ji anx7625_hdcp_enable(ctx); 2077cd1637c7SXin Ji 2078cd1637c7SXin Ji queue_delayed_work(ctx->hdcp_workqueue, 2079cd1637c7SXin Ji &ctx->hdcp_work, 2080cd1637c7SXin Ji msecs_to_jiffies(2000)); 2081cd1637c7SXin Ji } 2082cd1637c7SXin Ji } 2083cd1637c7SXin Ji 2084cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2085cd1637c7SXin Ji if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2086cd1637c7SXin Ji dev_err(dev, "current CP is not ENABLED\n"); 2087cd1637c7SXin Ji return -EINVAL; 2088cd1637c7SXin Ji } 2089cd1637c7SXin Ji anx7625_hdcp_disable(ctx); 2090cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2091cd1637c7SXin Ji drm_hdcp_update_content_protection(ctx->connector, 2092cd1637c7SXin Ji ctx->hdcp_cp); 2093cd1637c7SXin Ji dev_dbg(dev, "update CP to UNDESIRE\n"); 2094cd1637c7SXin Ji } 2095cd1637c7SXin Ji 2096cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2097cd1637c7SXin Ji dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2098cd1637c7SXin Ji return -EINVAL; 2099cd1637c7SXin Ji } 2100cd1637c7SXin Ji 2101cd1637c7SXin Ji return 0; 2102cd1637c7SXin Ji } 2103cd1637c7SXin Ji 21048bdfc5daSXin Ji static int anx7625_bridge_attach(struct drm_bridge *bridge, 21058bdfc5daSXin Ji enum drm_bridge_attach_flags flags) 21068bdfc5daSXin Ji { 21078bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 21088bdfc5daSXin Ji int err; 21098bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 21108bdfc5daSXin Ji 21118bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 21128bdfc5daSXin Ji if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 21138bdfc5daSXin Ji return -EINVAL; 21148bdfc5daSXin Ji 21158bdfc5daSXin Ji if (!bridge->encoder) { 21168bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Parent encoder object not found"); 21178bdfc5daSXin Ji return -ENODEV; 21188bdfc5daSXin Ji } 21198bdfc5daSXin Ji 2120adca62ecSHsin-Yi Wang ctx->aux.drm_dev = bridge->dev; 2121adca62ecSHsin-Yi Wang err = drm_dp_aux_register(&ctx->aux); 2122adca62ecSHsin-Yi Wang if (err) { 2123adca62ecSHsin-Yi Wang dev_err(dev, "failed to register aux channel: %d\n", err); 2124adca62ecSHsin-Yi Wang return err; 2125adca62ecSHsin-Yi Wang } 2126adca62ecSHsin-Yi Wang 21278bdfc5daSXin Ji if (ctx->pdata.panel_bridge) { 21288bdfc5daSXin Ji err = drm_bridge_attach(bridge->encoder, 21298bdfc5daSXin Ji ctx->pdata.panel_bridge, 21308bdfc5daSXin Ji &ctx->bridge, flags); 2131fb8d617fSLaurent Pinchart if (err) 21328bdfc5daSXin Ji return err; 21338bdfc5daSXin Ji } 21348bdfc5daSXin Ji 21358bdfc5daSXin Ji ctx->bridge_attached = 1; 21368bdfc5daSXin Ji 21378bdfc5daSXin Ji return 0; 21388bdfc5daSXin Ji } 21398bdfc5daSXin Ji 2140adca62ecSHsin-Yi Wang static void anx7625_bridge_detach(struct drm_bridge *bridge) 2141adca62ecSHsin-Yi Wang { 2142adca62ecSHsin-Yi Wang struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2143adca62ecSHsin-Yi Wang 2144adca62ecSHsin-Yi Wang drm_dp_aux_unregister(&ctx->aux); 2145adca62ecSHsin-Yi Wang } 2146adca62ecSHsin-Yi Wang 21478bdfc5daSXin Ji static enum drm_mode_status 21488bdfc5daSXin Ji anx7625_bridge_mode_valid(struct drm_bridge *bridge, 21498bdfc5daSXin Ji const struct drm_display_info *info, 21508bdfc5daSXin Ji const struct drm_display_mode *mode) 21518bdfc5daSXin Ji { 21528bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 21538bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 21548bdfc5daSXin Ji 21558bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 21568bdfc5daSXin Ji 21578bdfc5daSXin Ji /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 21588bdfc5daSXin Ji if (mode->clock > SUPPORT_PIXEL_CLOCK) { 21598bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, 21608bdfc5daSXin Ji "drm mode invalid, pixelclock too high.\n"); 21618bdfc5daSXin Ji return MODE_CLOCK_HIGH; 21628bdfc5daSXin Ji } 21638bdfc5daSXin Ji 21648bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 21658bdfc5daSXin Ji 21668bdfc5daSXin Ji return MODE_OK; 21678bdfc5daSXin Ji } 21688bdfc5daSXin Ji 21698bdfc5daSXin Ji static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 21708bdfc5daSXin Ji const struct drm_display_mode *old_mode, 21718bdfc5daSXin Ji const struct drm_display_mode *mode) 21728bdfc5daSXin Ji { 21738bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 21748bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 21758bdfc5daSXin Ji 21768bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 21778bdfc5daSXin Ji 21788bdfc5daSXin Ji ctx->dt.pixelclock.min = mode->clock; 21798bdfc5daSXin Ji ctx->dt.hactive.min = mode->hdisplay; 21808bdfc5daSXin Ji ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 21818bdfc5daSXin Ji ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 21828bdfc5daSXin Ji ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 21838bdfc5daSXin Ji ctx->dt.vactive.min = mode->vdisplay; 21848bdfc5daSXin Ji ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 21858bdfc5daSXin Ji ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 21868bdfc5daSXin Ji ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 21878bdfc5daSXin Ji 21888bdfc5daSXin Ji ctx->display_timing_valid = 1; 21898bdfc5daSXin Ji 21908bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 21918bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 21928bdfc5daSXin Ji ctx->dt.hactive.min, 21938bdfc5daSXin Ji ctx->dt.hsync_len.min, 21948bdfc5daSXin Ji ctx->dt.hfront_porch.min, 21958bdfc5daSXin Ji ctx->dt.hback_porch.min); 21968bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 21978bdfc5daSXin Ji ctx->dt.vactive.min, 21988bdfc5daSXin Ji ctx->dt.vsync_len.min, 21998bdfc5daSXin Ji ctx->dt.vfront_porch.min, 22008bdfc5daSXin Ji ctx->dt.vback_porch.min); 22018bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 22028bdfc5daSXin Ji mode->hdisplay, 22038bdfc5daSXin Ji mode->hsync_start); 22048bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 22058bdfc5daSXin Ji mode->hsync_end, 22068bdfc5daSXin Ji mode->htotal); 22078bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 22088bdfc5daSXin Ji mode->vdisplay, 22098bdfc5daSXin Ji mode->vsync_start); 22108bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 22118bdfc5daSXin Ji mode->vsync_end, 22128bdfc5daSXin Ji mode->vtotal); 22138bdfc5daSXin Ji } 22148bdfc5daSXin Ji 22158bdfc5daSXin Ji static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 22168bdfc5daSXin Ji const struct drm_display_mode *mode, 22178bdfc5daSXin Ji struct drm_display_mode *adj) 22188bdfc5daSXin Ji { 22198bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 22208bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 22218bdfc5daSXin Ji u32 hsync, hfp, hbp, hblanking; 22228bdfc5daSXin Ji u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 22238bdfc5daSXin Ji u32 vref, adj_clock; 22248bdfc5daSXin Ji 22258bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 22268bdfc5daSXin Ji 2227fd0310b6SXin Ji /* No need fixup for external monitor */ 2228fd0310b6SXin Ji if (!ctx->pdata.panel_bridge) 2229fd0310b6SXin Ji return true; 2230fd0310b6SXin Ji 22318bdfc5daSXin Ji hsync = mode->hsync_end - mode->hsync_start; 22328bdfc5daSXin Ji hfp = mode->hsync_start - mode->hdisplay; 22338bdfc5daSXin Ji hbp = mode->htotal - mode->hsync_end; 22348bdfc5daSXin Ji hblanking = mode->htotal - mode->hdisplay; 22358bdfc5daSXin Ji 22368bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 22378bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 22388bdfc5daSXin Ji hsync, hfp, hbp, adj->clock); 22398bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 22408bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 22418bdfc5daSXin Ji 22428bdfc5daSXin Ji adj_hfp = hfp; 22438bdfc5daSXin Ji adj_hsync = hsync; 22448bdfc5daSXin Ji adj_hbp = hbp; 22458bdfc5daSXin Ji adj_hblanking = hblanking; 22468bdfc5daSXin Ji 22478bdfc5daSXin Ji /* HFP needs to be even */ 22488bdfc5daSXin Ji if (hfp & 0x1) { 22498bdfc5daSXin Ji adj_hfp += 1; 22508bdfc5daSXin Ji adj_hblanking += 1; 22518bdfc5daSXin Ji } 22528bdfc5daSXin Ji 22538bdfc5daSXin Ji /* HBP needs to be even */ 22548bdfc5daSXin Ji if (hbp & 0x1) { 22558bdfc5daSXin Ji adj_hbp -= 1; 22568bdfc5daSXin Ji adj_hblanking -= 1; 22578bdfc5daSXin Ji } 22588bdfc5daSXin Ji 22598bdfc5daSXin Ji /* HSYNC needs to be even */ 22608bdfc5daSXin Ji if (hsync & 0x1) { 22618bdfc5daSXin Ji if (adj_hblanking < hblanking) 22628bdfc5daSXin Ji adj_hsync += 1; 22638bdfc5daSXin Ji else 22648bdfc5daSXin Ji adj_hsync -= 1; 22658bdfc5daSXin Ji } 22668bdfc5daSXin Ji 22678bdfc5daSXin Ji /* 22688bdfc5daSXin Ji * Once illegal timing detected, use default HFP, HSYNC, HBP 22698bdfc5daSXin Ji * This adjusting made for built-in eDP panel, for the externel 22708bdfc5daSXin Ji * DP monitor, may need return false. 22718bdfc5daSXin Ji */ 22728bdfc5daSXin Ji if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 22738bdfc5daSXin Ji adj_hsync = SYNC_LEN_DEF; 22748bdfc5daSXin Ji adj_hfp = HFP_HBP_DEF; 22758bdfc5daSXin Ji adj_hbp = HFP_HBP_DEF; 22768bdfc5daSXin Ji vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 22778bdfc5daSXin Ji if (hblanking < HBLANKING_MIN) { 22788bdfc5daSXin Ji delta_adj = HBLANKING_MIN - hblanking; 22798bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 22808bdfc5daSXin Ji adj->clock += DIV_ROUND_UP(adj_clock, 1000); 22818bdfc5daSXin Ji } else { 22828bdfc5daSXin Ji delta_adj = hblanking - HBLANKING_MIN; 22838bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 22848bdfc5daSXin Ji adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 22858bdfc5daSXin Ji } 22868bdfc5daSXin Ji 22878bdfc5daSXin Ji DRM_WARN("illegal hblanking timing, use default.\n"); 22888bdfc5daSXin Ji DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 22898bdfc5daSXin Ji } else if (adj_hfp < HP_MIN) { 22908bdfc5daSXin Ji /* Adjust hfp if hfp less than HP_MIN */ 22918bdfc5daSXin Ji delta_adj = HP_MIN - adj_hfp; 22928bdfc5daSXin Ji adj_hfp = HP_MIN; 22938bdfc5daSXin Ji 22948bdfc5daSXin Ji /* 22958bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP does not have enough 22968bdfc5daSXin Ji * space, adjust HSYNC length, otherwise adjust HBP 22978bdfc5daSXin Ji */ 22988bdfc5daSXin Ji if ((adj_hbp - delta_adj) < HP_MIN) 22998bdfc5daSXin Ji /* HBP not enough space */ 23008bdfc5daSXin Ji adj_hsync -= delta_adj; 23018bdfc5daSXin Ji else 23028bdfc5daSXin Ji adj_hbp -= delta_adj; 23038bdfc5daSXin Ji } else if (adj_hbp < HP_MIN) { 23048bdfc5daSXin Ji delta_adj = HP_MIN - adj_hbp; 23058bdfc5daSXin Ji adj_hbp = HP_MIN; 23068bdfc5daSXin Ji 23078bdfc5daSXin Ji /* 23088bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP hasn't enough space, 23098bdfc5daSXin Ji * adjust HSYNC length, otherwize adjust HBP 23108bdfc5daSXin Ji */ 23118bdfc5daSXin Ji if ((adj_hfp - delta_adj) < HP_MIN) 23128bdfc5daSXin Ji /* HFP not enough space */ 23138bdfc5daSXin Ji adj_hsync -= delta_adj; 23148bdfc5daSXin Ji else 23158bdfc5daSXin Ji adj_hfp -= delta_adj; 23168bdfc5daSXin Ji } 23178bdfc5daSXin Ji 23188bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 23198bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 23208bdfc5daSXin Ji adj_hsync, adj_hfp, adj_hbp, adj->clock); 23218bdfc5daSXin Ji 23228bdfc5daSXin Ji /* Reconstruct timing */ 23238bdfc5daSXin Ji adj->hsync_start = adj->hdisplay + adj_hfp; 23248bdfc5daSXin Ji adj->hsync_end = adj->hsync_start + adj_hsync; 23258bdfc5daSXin Ji adj->htotal = adj->hsync_end + adj_hbp; 23268bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 23278bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 23288bdfc5daSXin Ji 23298bdfc5daSXin Ji return true; 23308bdfc5daSXin Ji } 23318bdfc5daSXin Ji 2332191be002SXin Ji static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2333191be002SXin Ji struct drm_bridge_state *bridge_state, 2334191be002SXin Ji struct drm_crtc_state *crtc_state, 2335191be002SXin Ji struct drm_connector_state *conn_state) 23368bdfc5daSXin Ji { 23378bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 23388bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 23398bdfc5daSXin Ji 2340191be002SXin Ji dev_dbg(dev, "drm bridge atomic check\n"); 2341cd1637c7SXin Ji 2342cd1637c7SXin Ji anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2343191be002SXin Ji &crtc_state->adjusted_mode); 2344cd1637c7SXin Ji 2345cd1637c7SXin Ji return anx7625_connector_atomic_check(ctx, conn_state); 2346191be002SXin Ji } 2347191be002SXin Ji 2348191be002SXin Ji static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2349191be002SXin Ji struct drm_bridge_state *state) 2350191be002SXin Ji { 2351191be002SXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2352191be002SXin Ji struct device *dev = &ctx->client->dev; 2353191be002SXin Ji struct drm_connector *connector; 2354191be002SXin Ji 2355191be002SXin Ji dev_dbg(dev, "drm atomic enable\n"); 2356191be002SXin Ji 2357191be002SXin Ji if (!bridge->encoder) { 2358191be002SXin Ji dev_err(dev, "Parent encoder object not found"); 2359191be002SXin Ji return; 2360191be002SXin Ji } 2361191be002SXin Ji 2362191be002SXin Ji connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2363191be002SXin Ji bridge->encoder); 2364191be002SXin Ji if (!connector) 2365191be002SXin Ji return; 2366191be002SXin Ji 2367191be002SXin Ji ctx->connector = connector; 23688bdfc5daSXin Ji 236960487584SPi-Hsun Shih pm_runtime_get_sync(dev); 23708bdfc5daSXin Ji 23718bdfc5daSXin Ji anx7625_dp_start(ctx); 23728bdfc5daSXin Ji } 23738bdfc5daSXin Ji 2374191be002SXin Ji static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2375191be002SXin Ji struct drm_bridge_state *old) 23768bdfc5daSXin Ji { 23778bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 23788bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 23798bdfc5daSXin Ji 2380191be002SXin Ji dev_dbg(dev, "drm atomic disable\n"); 23818bdfc5daSXin Ji 2382191be002SXin Ji ctx->connector = NULL; 23838bdfc5daSXin Ji anx7625_dp_stop(ctx); 23848bdfc5daSXin Ji 23853203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 23868bdfc5daSXin Ji } 23878bdfc5daSXin Ji 23888bdfc5daSXin Ji static enum drm_connector_status 23898bdfc5daSXin Ji anx7625_bridge_detect(struct drm_bridge *bridge) 23908bdfc5daSXin Ji { 23918bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 23928bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 23938bdfc5daSXin Ji 23948bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 23958bdfc5daSXin Ji 23968bdfc5daSXin Ji return anx7625_sink_detect(ctx); 23978bdfc5daSXin Ji } 23988bdfc5daSXin Ji 23998bdfc5daSXin Ji static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 24008bdfc5daSXin Ji struct drm_connector *connector) 24018bdfc5daSXin Ji { 24028bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 24038bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 24048bdfc5daSXin Ji 24058bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 24068bdfc5daSXin Ji 24078bdfc5daSXin Ji return anx7625_get_edid(ctx); 24088bdfc5daSXin Ji } 24098bdfc5daSXin Ji 24108bdfc5daSXin Ji static const struct drm_bridge_funcs anx7625_bridge_funcs = { 24118bdfc5daSXin Ji .attach = anx7625_bridge_attach, 2412adca62ecSHsin-Yi Wang .detach = anx7625_bridge_detach, 24138bdfc5daSXin Ji .mode_valid = anx7625_bridge_mode_valid, 24148bdfc5daSXin Ji .mode_set = anx7625_bridge_mode_set, 2415191be002SXin Ji .atomic_check = anx7625_bridge_atomic_check, 2416191be002SXin Ji .atomic_enable = anx7625_bridge_atomic_enable, 2417191be002SXin Ji .atomic_disable = anx7625_bridge_atomic_disable, 2418191be002SXin Ji .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2419191be002SXin Ji .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2420191be002SXin Ji .atomic_reset = drm_atomic_helper_bridge_reset, 24218bdfc5daSXin Ji .detect = anx7625_bridge_detect, 24228bdfc5daSXin Ji .get_edid = anx7625_bridge_get_edid, 24238bdfc5daSXin Ji }; 24248bdfc5daSXin Ji 24258bdfc5daSXin Ji static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 24268bdfc5daSXin Ji struct i2c_client *client) 24278bdfc5daSXin Ji { 2428f5f05ddcSMiaoqian Lin int err = 0; 2429f5f05ddcSMiaoqian Lin 24308bdfc5daSXin Ji ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 24318bdfc5daSXin Ji TX_P0_ADDR >> 1); 2432f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p0_client)) 2433f5f05ddcSMiaoqian Lin return PTR_ERR(ctx->i2c.tx_p0_client); 24348bdfc5daSXin Ji 24358bdfc5daSXin Ji ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 24368bdfc5daSXin Ji TX_P1_ADDR >> 1); 2437f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p1_client)) { 2438f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tx_p1_client); 24398bdfc5daSXin Ji goto free_tx_p0; 2440f5f05ddcSMiaoqian Lin } 24418bdfc5daSXin Ji 24428bdfc5daSXin Ji ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 24438bdfc5daSXin Ji TX_P2_ADDR >> 1); 2444f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p2_client)) { 2445f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tx_p2_client); 24468bdfc5daSXin Ji goto free_tx_p1; 2447f5f05ddcSMiaoqian Lin } 24488bdfc5daSXin Ji 24498bdfc5daSXin Ji ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 24508bdfc5daSXin Ji RX_P0_ADDR >> 1); 2451f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p0_client)) { 2452f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p0_client); 24538bdfc5daSXin Ji goto free_tx_p2; 2454f5f05ddcSMiaoqian Lin } 24558bdfc5daSXin Ji 24568bdfc5daSXin Ji ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 24578bdfc5daSXin Ji RX_P1_ADDR >> 1); 2458f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p1_client)) { 2459f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p1_client); 24608bdfc5daSXin Ji goto free_rx_p0; 2461f5f05ddcSMiaoqian Lin } 24628bdfc5daSXin Ji 24638bdfc5daSXin Ji ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 24648bdfc5daSXin Ji RX_P2_ADDR >> 1); 2465f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p2_client)) { 2466f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p2_client); 24678bdfc5daSXin Ji goto free_rx_p1; 2468f5f05ddcSMiaoqian Lin } 24698bdfc5daSXin Ji 24708bdfc5daSXin Ji ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 24718bdfc5daSXin Ji TCPC_INTERFACE_ADDR >> 1); 2472f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tcpc_client)) { 2473f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tcpc_client); 24748bdfc5daSXin Ji goto free_rx_p2; 2475f5f05ddcSMiaoqian Lin } 24768bdfc5daSXin Ji 24778bdfc5daSXin Ji return 0; 24788bdfc5daSXin Ji 24798bdfc5daSXin Ji free_rx_p2: 24808bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 24818bdfc5daSXin Ji free_rx_p1: 24828bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 24838bdfc5daSXin Ji free_rx_p0: 24848bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 24858bdfc5daSXin Ji free_tx_p2: 24868bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 24878bdfc5daSXin Ji free_tx_p1: 24888bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 24898bdfc5daSXin Ji free_tx_p0: 24908bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 24918bdfc5daSXin Ji 2492f5f05ddcSMiaoqian Lin return err; 24938bdfc5daSXin Ji } 24948bdfc5daSXin Ji 24958bdfc5daSXin Ji static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 24968bdfc5daSXin Ji { 24978bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 24988bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 24998bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 25008bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 25018bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 25028bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 25038bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tcpc_client); 25048bdfc5daSXin Ji } 25058bdfc5daSXin Ji 250660487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 250760487584SPi-Hsun Shih { 250860487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 250960487584SPi-Hsun Shih 251060487584SPi-Hsun Shih mutex_lock(&ctx->lock); 251160487584SPi-Hsun Shih 251260487584SPi-Hsun Shih anx7625_stop_dp_work(ctx); 251360487584SPi-Hsun Shih anx7625_power_standby(ctx); 251460487584SPi-Hsun Shih 251560487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 251660487584SPi-Hsun Shih 251760487584SPi-Hsun Shih return 0; 251860487584SPi-Hsun Shih } 251960487584SPi-Hsun Shih 252060487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 252160487584SPi-Hsun Shih { 252260487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 252360487584SPi-Hsun Shih 252460487584SPi-Hsun Shih mutex_lock(&ctx->lock); 252560487584SPi-Hsun Shih 252660487584SPi-Hsun Shih anx7625_power_on_init(ctx); 252760487584SPi-Hsun Shih anx7625_hpd_polling(ctx); 252860487584SPi-Hsun Shih 252960487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 253060487584SPi-Hsun Shih 253160487584SPi-Hsun Shih return 0; 253260487584SPi-Hsun Shih } 253360487584SPi-Hsun Shih 2534409776faSPi-Hsun Shih static int __maybe_unused anx7625_resume(struct device *dev) 2535409776faSPi-Hsun Shih { 2536409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 2537409776faSPi-Hsun Shih 2538409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 2539409776faSPi-Hsun Shih return 0; 2540409776faSPi-Hsun Shih 2541409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2542409776faSPi-Hsun Shih enable_irq(ctx->pdata.intp_irq); 2543409776faSPi-Hsun Shih anx7625_runtime_pm_resume(dev); 2544409776faSPi-Hsun Shih } 2545409776faSPi-Hsun Shih 2546409776faSPi-Hsun Shih return 0; 2547409776faSPi-Hsun Shih } 2548409776faSPi-Hsun Shih 2549409776faSPi-Hsun Shih static int __maybe_unused anx7625_suspend(struct device *dev) 2550409776faSPi-Hsun Shih { 2551409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 2552409776faSPi-Hsun Shih 2553409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 2554409776faSPi-Hsun Shih return 0; 2555409776faSPi-Hsun Shih 2556409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2557409776faSPi-Hsun Shih anx7625_runtime_pm_suspend(dev); 2558409776faSPi-Hsun Shih disable_irq(ctx->pdata.intp_irq); 2559409776faSPi-Hsun Shih } 2560409776faSPi-Hsun Shih 2561409776faSPi-Hsun Shih return 0; 2562409776faSPi-Hsun Shih } 2563409776faSPi-Hsun Shih 256460487584SPi-Hsun Shih static const struct dev_pm_ops anx7625_pm_ops = { 2565409776faSPi-Hsun Shih SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 256660487584SPi-Hsun Shih SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 256760487584SPi-Hsun Shih anx7625_runtime_pm_resume, NULL) 256860487584SPi-Hsun Shih }; 256960487584SPi-Hsun Shih 2570adca62ecSHsin-Yi Wang static void anx7625_runtime_disable(void *data) 2571adca62ecSHsin-Yi Wang { 2572adca62ecSHsin-Yi Wang pm_runtime_dont_use_autosuspend(data); 2573adca62ecSHsin-Yi Wang pm_runtime_disable(data); 2574adca62ecSHsin-Yi Wang } 2575adca62ecSHsin-Yi Wang 25768bdfc5daSXin Ji static int anx7625_i2c_probe(struct i2c_client *client, 25778bdfc5daSXin Ji const struct i2c_device_id *id) 25788bdfc5daSXin Ji { 25798bdfc5daSXin Ji struct anx7625_data *platform; 25808bdfc5daSXin Ji struct anx7625_platform_data *pdata; 25818bdfc5daSXin Ji int ret = 0; 25828bdfc5daSXin Ji struct device *dev = &client->dev; 25838bdfc5daSXin Ji 25848bdfc5daSXin Ji if (!i2c_check_functionality(client->adapter, 25858bdfc5daSXin Ji I2C_FUNC_SMBUS_I2C_BLOCK)) { 25868bdfc5daSXin Ji DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 25878bdfc5daSXin Ji return -ENODEV; 25888bdfc5daSXin Ji } 25898bdfc5daSXin Ji 259057bfb34aSHsin-Yi Wang platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL); 25918bdfc5daSXin Ji if (!platform) { 25928bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 25938bdfc5daSXin Ji return -ENOMEM; 25948bdfc5daSXin Ji } 25958bdfc5daSXin Ji 25968bdfc5daSXin Ji pdata = &platform->pdata; 25978bdfc5daSXin Ji 25988bdfc5daSXin Ji platform->client = client; 25998bdfc5daSXin Ji i2c_set_clientdata(client, platform); 26008bdfc5daSXin Ji 26016c744983SHsin-Yi Wang pdata->supplies[0].supply = "vdd10"; 26026c744983SHsin-Yi Wang pdata->supplies[1].supply = "vdd18"; 26036c744983SHsin-Yi Wang pdata->supplies[2].supply = "vdd33"; 26046c744983SHsin-Yi Wang ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 26056c744983SHsin-Yi Wang pdata->supplies); 26066c744983SHsin-Yi Wang if (ret) { 26076c744983SHsin-Yi Wang DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 26086c744983SHsin-Yi Wang return ret; 26096c744983SHsin-Yi Wang } 26108bdfc5daSXin Ji anx7625_init_gpio(platform); 26118bdfc5daSXin Ji 26128bdfc5daSXin Ji mutex_init(&platform->lock); 2613cd1637c7SXin Ji mutex_init(&platform->hdcp_wq_lock); 2614cd1637c7SXin Ji 2615cd1637c7SXin Ji INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2616cd1637c7SXin Ji platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2617cd1637c7SXin Ji if (!platform->hdcp_workqueue) { 2618cd1637c7SXin Ji dev_err(dev, "fail to create work queue\n"); 2619cd1637c7SXin Ji ret = -ENOMEM; 262057bfb34aSHsin-Yi Wang return ret; 2621cd1637c7SXin Ji } 26228bdfc5daSXin Ji 26238bdfc5daSXin Ji platform->pdata.intp_irq = client->irq; 26248bdfc5daSXin Ji if (platform->pdata.intp_irq) { 26258bdfc5daSXin Ji INIT_WORK(&platform->work, anx7625_work_func); 2626f03ab662SPi-Hsun Shih platform->workqueue = alloc_workqueue("anx7625_work", 2627f03ab662SPi-Hsun Shih WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 26288bdfc5daSXin Ji if (!platform->workqueue) { 26298bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create work queue\n"); 26308bdfc5daSXin Ji ret = -ENOMEM; 2631cd1637c7SXin Ji goto free_hdcp_wq; 26328bdfc5daSXin Ji } 26338bdfc5daSXin Ji 26348bdfc5daSXin Ji ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 26358bdfc5daSXin Ji NULL, anx7625_intr_hpd_isr, 26368bdfc5daSXin Ji IRQF_TRIGGER_FALLING | 26378bdfc5daSXin Ji IRQF_ONESHOT, 26388bdfc5daSXin Ji "anx7625-intp", platform); 26398bdfc5daSXin Ji if (ret) { 26408bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to request irq\n"); 26418bdfc5daSXin Ji goto free_wq; 26428bdfc5daSXin Ji } 26438bdfc5daSXin Ji } 26448bdfc5daSXin Ji 2645adca62ecSHsin-Yi Wang platform->aux.name = "anx7625-aux"; 2646adca62ecSHsin-Yi Wang platform->aux.dev = dev; 2647adca62ecSHsin-Yi Wang platform->aux.transfer = anx7625_aux_transfer; 2648adca62ecSHsin-Yi Wang drm_dp_aux_init(&platform->aux); 2649adca62ecSHsin-Yi Wang devm_of_dp_aux_populate_ep_devices(&platform->aux); 2650adca62ecSHsin-Yi Wang 2651adca62ecSHsin-Yi Wang ret = anx7625_parse_dt(dev, pdata); 2652adca62ecSHsin-Yi Wang if (ret) { 2653adca62ecSHsin-Yi Wang if (ret != -EPROBE_DEFER) 2654adca62ecSHsin-Yi Wang DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2655adca62ecSHsin-Yi Wang return ret; 2656adca62ecSHsin-Yi Wang } 2657adca62ecSHsin-Yi Wang 26588bdfc5daSXin Ji if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 26598bdfc5daSXin Ji ret = -ENOMEM; 26608bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 26618bdfc5daSXin Ji goto free_wq; 26628bdfc5daSXin Ji } 26638bdfc5daSXin Ji 266460487584SPi-Hsun Shih pm_runtime_enable(dev); 2665adca62ecSHsin-Yi Wang pm_runtime_set_autosuspend_delay(dev, 1000); 2666adca62ecSHsin-Yi Wang pm_runtime_use_autosuspend(dev); 2667adca62ecSHsin-Yi Wang pm_suspend_ignore_children(dev, true); 2668adca62ecSHsin-Yi Wang ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev); 2669adca62ecSHsin-Yi Wang if (ret) 2670adca62ecSHsin-Yi Wang return ret; 267160487584SPi-Hsun Shih 267260487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) { 26738bdfc5daSXin Ji anx7625_disable_pd_protocol(platform); 267460487584SPi-Hsun Shih pm_runtime_get_sync(dev); 26758bdfc5daSXin Ji } 26768bdfc5daSXin Ji 26778bdfc5daSXin Ji /* Add work function */ 26788bdfc5daSXin Ji if (platform->pdata.intp_irq) 26798bdfc5daSXin Ji queue_work(platform->workqueue, &platform->work); 26808bdfc5daSXin Ji 26818bdfc5daSXin Ji platform->bridge.funcs = &anx7625_bridge_funcs; 26828bdfc5daSXin Ji platform->bridge.of_node = client->dev.of_node; 2683adca62ecSHsin-Yi Wang if (!anx7625_of_panel_on_aux_bus(&client->dev)) 2684adca62ecSHsin-Yi Wang platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 2685fd0310b6SXin Ji if (!platform->pdata.panel_bridge) 2686fd0310b6SXin Ji platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2687fd0310b6SXin Ji DRM_BRIDGE_OP_DETECT; 2688fd0310b6SXin Ji platform->bridge.type = platform->pdata.panel_bridge ? 2689fd0310b6SXin Ji DRM_MODE_CONNECTOR_eDP : 2690fd0310b6SXin Ji DRM_MODE_CONNECTOR_DisplayPort; 2691fd0310b6SXin Ji 26928bdfc5daSXin Ji drm_bridge_add(&platform->bridge); 26938bdfc5daSXin Ji 2694fd0310b6SXin Ji if (!platform->pdata.is_dpi) { 269549e61beeSMaxime Ripard ret = anx7625_attach_dsi(platform); 269649e61beeSMaxime Ripard if (ret) { 269749e61beeSMaxime Ripard DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 269849e61beeSMaxime Ripard goto unregister_bridge; 269949e61beeSMaxime Ripard } 2700fd0310b6SXin Ji } 270149e61beeSMaxime Ripard 2702566fef12SXin Ji if (platform->pdata.audio_en) 2703566fef12SXin Ji anx7625_register_audio(dev, platform); 2704566fef12SXin Ji 27058bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 27068bdfc5daSXin Ji 27078bdfc5daSXin Ji return 0; 27088bdfc5daSXin Ji 270949e61beeSMaxime Ripard unregister_bridge: 271049e61beeSMaxime Ripard drm_bridge_remove(&platform->bridge); 271149e61beeSMaxime Ripard 271249e61beeSMaxime Ripard if (!platform->pdata.low_power_mode) 271349e61beeSMaxime Ripard pm_runtime_put_sync_suspend(&client->dev); 271449e61beeSMaxime Ripard 271549e61beeSMaxime Ripard anx7625_unregister_i2c_dummy_clients(platform); 271649e61beeSMaxime Ripard 27178bdfc5daSXin Ji free_wq: 27188bdfc5daSXin Ji if (platform->workqueue) 27198bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 27208bdfc5daSXin Ji 2721cd1637c7SXin Ji free_hdcp_wq: 2722cd1637c7SXin Ji if (platform->hdcp_workqueue) 2723cd1637c7SXin Ji destroy_workqueue(platform->hdcp_workqueue); 2724cd1637c7SXin Ji 27258bdfc5daSXin Ji return ret; 27268bdfc5daSXin Ji } 27278bdfc5daSXin Ji 27288bdfc5daSXin Ji static int anx7625_i2c_remove(struct i2c_client *client) 27298bdfc5daSXin Ji { 27308bdfc5daSXin Ji struct anx7625_data *platform = i2c_get_clientdata(client); 27318bdfc5daSXin Ji 27328bdfc5daSXin Ji drm_bridge_remove(&platform->bridge); 27338bdfc5daSXin Ji 27348bdfc5daSXin Ji if (platform->pdata.intp_irq) 27358bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 27368bdfc5daSXin Ji 2737cd1637c7SXin Ji if (platform->hdcp_workqueue) { 2738cd1637c7SXin Ji cancel_delayed_work(&platform->hdcp_work); 2739cd1637c7SXin Ji flush_workqueue(platform->workqueue); 2740cd1637c7SXin Ji destroy_workqueue(platform->workqueue); 2741cd1637c7SXin Ji } 2742cd1637c7SXin Ji 274360487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) 274460487584SPi-Hsun Shih pm_runtime_put_sync_suspend(&client->dev); 274560487584SPi-Hsun Shih 27468bdfc5daSXin Ji anx7625_unregister_i2c_dummy_clients(platform); 27478bdfc5daSXin Ji 2748566fef12SXin Ji if (platform->pdata.audio_en) 2749566fef12SXin Ji anx7625_unregister_audio(platform); 2750566fef12SXin Ji 27518bdfc5daSXin Ji return 0; 27528bdfc5daSXin Ji } 27538bdfc5daSXin Ji 27548bdfc5daSXin Ji static const struct i2c_device_id anx7625_id[] = { 27558bdfc5daSXin Ji {"anx7625", 0}, 27568bdfc5daSXin Ji {} 27578bdfc5daSXin Ji }; 27588bdfc5daSXin Ji 27598bdfc5daSXin Ji MODULE_DEVICE_TABLE(i2c, anx7625_id); 27608bdfc5daSXin Ji 27618bdfc5daSXin Ji static const struct of_device_id anx_match_table[] = { 27628bdfc5daSXin Ji {.compatible = "analogix,anx7625",}, 27638bdfc5daSXin Ji {}, 27648bdfc5daSXin Ji }; 2765ad5fd900SYu Jiahua MODULE_DEVICE_TABLE(of, anx_match_table); 27668bdfc5daSXin Ji 27678bdfc5daSXin Ji static struct i2c_driver anx7625_driver = { 27688bdfc5daSXin Ji .driver = { 27698bdfc5daSXin Ji .name = "anx7625", 27708bdfc5daSXin Ji .of_match_table = anx_match_table, 277160487584SPi-Hsun Shih .pm = &anx7625_pm_ops, 27728bdfc5daSXin Ji }, 27738bdfc5daSXin Ji .probe = anx7625_i2c_probe, 27748bdfc5daSXin Ji .remove = anx7625_i2c_remove, 27758bdfc5daSXin Ji 27768bdfc5daSXin Ji .id_table = anx7625_id, 27778bdfc5daSXin Ji }; 27788bdfc5daSXin Ji 27798bdfc5daSXin Ji module_i2c_driver(anx7625_driver); 27808bdfc5daSXin Ji 27818bdfc5daSXin Ji MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 27828bdfc5daSXin Ji MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 27838bdfc5daSXin Ji MODULE_LICENSE("GPL v2"); 27848bdfc5daSXin Ji MODULE_VERSION(ANX7625_DRV_VERSION); 2785