1*8bdfc5daSXin Ji // SPDX-License-Identifier: GPL-2.0-only 2*8bdfc5daSXin Ji /* 3*8bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4*8bdfc5daSXin Ji * 5*8bdfc5daSXin Ji */ 6*8bdfc5daSXin Ji #include <linux/gcd.h> 7*8bdfc5daSXin Ji #include <linux/gpio/consumer.h> 8*8bdfc5daSXin Ji #include <linux/i2c.h> 9*8bdfc5daSXin Ji #include <linux/interrupt.h> 10*8bdfc5daSXin Ji #include <linux/iopoll.h> 11*8bdfc5daSXin Ji #include <linux/kernel.h> 12*8bdfc5daSXin Ji #include <linux/module.h> 13*8bdfc5daSXin Ji #include <linux/mutex.h> 14*8bdfc5daSXin Ji #include <linux/slab.h> 15*8bdfc5daSXin Ji #include <linux/types.h> 16*8bdfc5daSXin Ji #include <linux/workqueue.h> 17*8bdfc5daSXin Ji 18*8bdfc5daSXin Ji #include <linux/of_gpio.h> 19*8bdfc5daSXin Ji #include <linux/of_graph.h> 20*8bdfc5daSXin Ji #include <linux/of_platform.h> 21*8bdfc5daSXin Ji 22*8bdfc5daSXin Ji #include <drm/drm_atomic_helper.h> 23*8bdfc5daSXin Ji #include <drm/drm_bridge.h> 24*8bdfc5daSXin Ji #include <drm/drm_crtc_helper.h> 25*8bdfc5daSXin Ji #include <drm/drm_dp_helper.h> 26*8bdfc5daSXin Ji #include <drm/drm_edid.h> 27*8bdfc5daSXin Ji #include <drm/drm_mipi_dsi.h> 28*8bdfc5daSXin Ji #include <drm/drm_of.h> 29*8bdfc5daSXin Ji #include <drm/drm_panel.h> 30*8bdfc5daSXin Ji #include <drm/drm_print.h> 31*8bdfc5daSXin Ji #include <drm/drm_probe_helper.h> 32*8bdfc5daSXin Ji 33*8bdfc5daSXin Ji #include <video/display_timing.h> 34*8bdfc5daSXin Ji 35*8bdfc5daSXin Ji #include "anx7625.h" 36*8bdfc5daSXin Ji 37*8bdfc5daSXin Ji /* 38*8bdfc5daSXin Ji * There is a sync issue while access I2C register between AP(CPU) and 39*8bdfc5daSXin Ji * internal firmware(OCM), to avoid the race condition, AP should access 40*8bdfc5daSXin Ji * the reserved slave address before slave address occurs changes. 41*8bdfc5daSXin Ji */ 42*8bdfc5daSXin Ji static int i2c_access_workaround(struct anx7625_data *ctx, 43*8bdfc5daSXin Ji struct i2c_client *client) 44*8bdfc5daSXin Ji { 45*8bdfc5daSXin Ji u8 offset; 46*8bdfc5daSXin Ji struct device *dev = &client->dev; 47*8bdfc5daSXin Ji int ret; 48*8bdfc5daSXin Ji 49*8bdfc5daSXin Ji if (client == ctx->last_client) 50*8bdfc5daSXin Ji return 0; 51*8bdfc5daSXin Ji 52*8bdfc5daSXin Ji ctx->last_client = client; 53*8bdfc5daSXin Ji 54*8bdfc5daSXin Ji if (client == ctx->i2c.tcpc_client) 55*8bdfc5daSXin Ji offset = RSVD_00_ADDR; 56*8bdfc5daSXin Ji else if (client == ctx->i2c.tx_p0_client) 57*8bdfc5daSXin Ji offset = RSVD_D1_ADDR; 58*8bdfc5daSXin Ji else if (client == ctx->i2c.tx_p1_client) 59*8bdfc5daSXin Ji offset = RSVD_60_ADDR; 60*8bdfc5daSXin Ji else if (client == ctx->i2c.rx_p0_client) 61*8bdfc5daSXin Ji offset = RSVD_39_ADDR; 62*8bdfc5daSXin Ji else if (client == ctx->i2c.rx_p1_client) 63*8bdfc5daSXin Ji offset = RSVD_7F_ADDR; 64*8bdfc5daSXin Ji else 65*8bdfc5daSXin Ji offset = RSVD_00_ADDR; 66*8bdfc5daSXin Ji 67*8bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, offset, 0x00); 68*8bdfc5daSXin Ji if (ret < 0) 69*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, 70*8bdfc5daSXin Ji "fail to access i2c id=%x\n:%x", 71*8bdfc5daSXin Ji client->addr, offset); 72*8bdfc5daSXin Ji 73*8bdfc5daSXin Ji return ret; 74*8bdfc5daSXin Ji } 75*8bdfc5daSXin Ji 76*8bdfc5daSXin Ji static int anx7625_reg_read(struct anx7625_data *ctx, 77*8bdfc5daSXin Ji struct i2c_client *client, u8 reg_addr) 78*8bdfc5daSXin Ji { 79*8bdfc5daSXin Ji int ret; 80*8bdfc5daSXin Ji struct device *dev = &client->dev; 81*8bdfc5daSXin Ji 82*8bdfc5daSXin Ji i2c_access_workaround(ctx, client); 83*8bdfc5daSXin Ji 84*8bdfc5daSXin Ji ret = i2c_smbus_read_byte_data(client, reg_addr); 85*8bdfc5daSXin Ji if (ret < 0) 86*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 87*8bdfc5daSXin Ji client->addr, reg_addr); 88*8bdfc5daSXin Ji 89*8bdfc5daSXin Ji return ret; 90*8bdfc5daSXin Ji } 91*8bdfc5daSXin Ji 92*8bdfc5daSXin Ji static int anx7625_reg_block_read(struct anx7625_data *ctx, 93*8bdfc5daSXin Ji struct i2c_client *client, 94*8bdfc5daSXin Ji u8 reg_addr, u8 len, u8 *buf) 95*8bdfc5daSXin Ji { 96*8bdfc5daSXin Ji int ret; 97*8bdfc5daSXin Ji struct device *dev = &client->dev; 98*8bdfc5daSXin Ji 99*8bdfc5daSXin Ji i2c_access_workaround(ctx, client); 100*8bdfc5daSXin Ji 101*8bdfc5daSXin Ji ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 102*8bdfc5daSXin Ji if (ret < 0) 103*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 104*8bdfc5daSXin Ji client->addr, reg_addr); 105*8bdfc5daSXin Ji 106*8bdfc5daSXin Ji return ret; 107*8bdfc5daSXin Ji } 108*8bdfc5daSXin Ji 109*8bdfc5daSXin Ji static int anx7625_reg_write(struct anx7625_data *ctx, 110*8bdfc5daSXin Ji struct i2c_client *client, 111*8bdfc5daSXin Ji u8 reg_addr, u8 reg_val) 112*8bdfc5daSXin Ji { 113*8bdfc5daSXin Ji int ret; 114*8bdfc5daSXin Ji struct device *dev = &client->dev; 115*8bdfc5daSXin Ji 116*8bdfc5daSXin Ji i2c_access_workaround(ctx, client); 117*8bdfc5daSXin Ji 118*8bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 119*8bdfc5daSXin Ji 120*8bdfc5daSXin Ji if (ret < 0) 121*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 122*8bdfc5daSXin Ji client->addr, reg_addr); 123*8bdfc5daSXin Ji 124*8bdfc5daSXin Ji return ret; 125*8bdfc5daSXin Ji } 126*8bdfc5daSXin Ji 127*8bdfc5daSXin Ji static int anx7625_write_or(struct anx7625_data *ctx, 128*8bdfc5daSXin Ji struct i2c_client *client, 129*8bdfc5daSXin Ji u8 offset, u8 mask) 130*8bdfc5daSXin Ji { 131*8bdfc5daSXin Ji int val; 132*8bdfc5daSXin Ji 133*8bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 134*8bdfc5daSXin Ji if (val < 0) 135*8bdfc5daSXin Ji return val; 136*8bdfc5daSXin Ji 137*8bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val | (mask))); 138*8bdfc5daSXin Ji } 139*8bdfc5daSXin Ji 140*8bdfc5daSXin Ji static int anx7625_write_and(struct anx7625_data *ctx, 141*8bdfc5daSXin Ji struct i2c_client *client, 142*8bdfc5daSXin Ji u8 offset, u8 mask) 143*8bdfc5daSXin Ji { 144*8bdfc5daSXin Ji int val; 145*8bdfc5daSXin Ji 146*8bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 147*8bdfc5daSXin Ji if (val < 0) 148*8bdfc5daSXin Ji return val; 149*8bdfc5daSXin Ji 150*8bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val & (mask))); 151*8bdfc5daSXin Ji } 152*8bdfc5daSXin Ji 153*8bdfc5daSXin Ji static int anx7625_write_and_or(struct anx7625_data *ctx, 154*8bdfc5daSXin Ji struct i2c_client *client, 155*8bdfc5daSXin Ji u8 offset, u8 and_mask, u8 or_mask) 156*8bdfc5daSXin Ji { 157*8bdfc5daSXin Ji int val; 158*8bdfc5daSXin Ji 159*8bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 160*8bdfc5daSXin Ji if (val < 0) 161*8bdfc5daSXin Ji return val; 162*8bdfc5daSXin Ji 163*8bdfc5daSXin Ji return anx7625_reg_write(ctx, client, 164*8bdfc5daSXin Ji offset, (val & and_mask) | (or_mask)); 165*8bdfc5daSXin Ji } 166*8bdfc5daSXin Ji 167*8bdfc5daSXin Ji static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 168*8bdfc5daSXin Ji { 169*8bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 170*8bdfc5daSXin Ji } 171*8bdfc5daSXin Ji 172*8bdfc5daSXin Ji static int wait_aux_op_finish(struct anx7625_data *ctx) 173*8bdfc5daSXin Ji { 174*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 175*8bdfc5daSXin Ji int val; 176*8bdfc5daSXin Ji int ret; 177*8bdfc5daSXin Ji 178*8bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 179*8bdfc5daSXin Ji ctx, val, 180*8bdfc5daSXin Ji (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 181*8bdfc5daSXin Ji 2000, 182*8bdfc5daSXin Ji 2000 * 150); 183*8bdfc5daSXin Ji if (ret) { 184*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux operation fail!\n"); 185*8bdfc5daSXin Ji return -EIO; 186*8bdfc5daSXin Ji } 187*8bdfc5daSXin Ji 188*8bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 189*8bdfc5daSXin Ji AP_AUX_CTRL_STATUS); 190*8bdfc5daSXin Ji if (val < 0 || (val & 0x0F)) { 191*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux status %02x\n", val); 192*8bdfc5daSXin Ji val = -EIO; 193*8bdfc5daSXin Ji } 194*8bdfc5daSXin Ji 195*8bdfc5daSXin Ji return val; 196*8bdfc5daSXin Ji } 197*8bdfc5daSXin Ji 198*8bdfc5daSXin Ji static int anx7625_video_mute_control(struct anx7625_data *ctx, 199*8bdfc5daSXin Ji u8 status) 200*8bdfc5daSXin Ji { 201*8bdfc5daSXin Ji int ret; 202*8bdfc5daSXin Ji 203*8bdfc5daSXin Ji if (status) { 204*8bdfc5daSXin Ji /* Set mute on flag */ 205*8bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 206*8bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_MUTE); 207*8bdfc5daSXin Ji /* Clear mipi RX en */ 208*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 209*8bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 210*8bdfc5daSXin Ji } else { 211*8bdfc5daSXin Ji /* Mute off flag */ 212*8bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 213*8bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 214*8bdfc5daSXin Ji /* Set MIPI RX EN */ 215*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 216*8bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 217*8bdfc5daSXin Ji } 218*8bdfc5daSXin Ji 219*8bdfc5daSXin Ji return ret; 220*8bdfc5daSXin Ji } 221*8bdfc5daSXin Ji 222*8bdfc5daSXin Ji static int anx7625_config_audio_input(struct anx7625_data *ctx) 223*8bdfc5daSXin Ji { 224*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 225*8bdfc5daSXin Ji int ret; 226*8bdfc5daSXin Ji 227*8bdfc5daSXin Ji /* Channel num */ 228*8bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 229*8bdfc5daSXin Ji AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5); 230*8bdfc5daSXin Ji 231*8bdfc5daSXin Ji /* FS */ 232*8bdfc5daSXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 233*8bdfc5daSXin Ji AUDIO_CHANNEL_STATUS_4, 234*8bdfc5daSXin Ji 0xf0, AUDIO_FS_48K); 235*8bdfc5daSXin Ji /* Word length */ 236*8bdfc5daSXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 237*8bdfc5daSXin Ji AUDIO_CHANNEL_STATUS_5, 238*8bdfc5daSXin Ji 0xf0, AUDIO_W_LEN_24_24MAX); 239*8bdfc5daSXin Ji /* I2S */ 240*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 241*8bdfc5daSXin Ji AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE); 242*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 243*8bdfc5daSXin Ji AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE); 244*8bdfc5daSXin Ji /* Audio change flag */ 245*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 246*8bdfc5daSXin Ji AP_AV_STATUS, AP_AUDIO_CHG); 247*8bdfc5daSXin Ji 248*8bdfc5daSXin Ji if (ret < 0) 249*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to config audio.\n"); 250*8bdfc5daSXin Ji 251*8bdfc5daSXin Ji return ret; 252*8bdfc5daSXin Ji } 253*8bdfc5daSXin Ji 254*8bdfc5daSXin Ji /* Reduction of fraction a/b */ 255*8bdfc5daSXin Ji static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 256*8bdfc5daSXin Ji { 257*8bdfc5daSXin Ji unsigned long gcd_num; 258*8bdfc5daSXin Ji unsigned long tmp_a, tmp_b; 259*8bdfc5daSXin Ji u32 i = 1; 260*8bdfc5daSXin Ji 261*8bdfc5daSXin Ji gcd_num = gcd(*a, *b); 262*8bdfc5daSXin Ji *a /= gcd_num; 263*8bdfc5daSXin Ji *b /= gcd_num; 264*8bdfc5daSXin Ji 265*8bdfc5daSXin Ji tmp_a = *a; 266*8bdfc5daSXin Ji tmp_b = *b; 267*8bdfc5daSXin Ji 268*8bdfc5daSXin Ji while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 269*8bdfc5daSXin Ji i++; 270*8bdfc5daSXin Ji *a = tmp_a / i; 271*8bdfc5daSXin Ji *b = tmp_b / i; 272*8bdfc5daSXin Ji } 273*8bdfc5daSXin Ji 274*8bdfc5daSXin Ji /* 275*8bdfc5daSXin Ji * In the end, make a, b larger to have higher ODFC PLL 276*8bdfc5daSXin Ji * output frequency accuracy 277*8bdfc5daSXin Ji */ 278*8bdfc5daSXin Ji while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 279*8bdfc5daSXin Ji *a <<= 1; 280*8bdfc5daSXin Ji *b <<= 1; 281*8bdfc5daSXin Ji } 282*8bdfc5daSXin Ji 283*8bdfc5daSXin Ji *a >>= 1; 284*8bdfc5daSXin Ji *b >>= 1; 285*8bdfc5daSXin Ji } 286*8bdfc5daSXin Ji 287*8bdfc5daSXin Ji static int anx7625_calculate_m_n(u32 pixelclock, 288*8bdfc5daSXin Ji unsigned long *m, 289*8bdfc5daSXin Ji unsigned long *n, 290*8bdfc5daSXin Ji u8 *post_divider) 291*8bdfc5daSXin Ji { 292*8bdfc5daSXin Ji if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 293*8bdfc5daSXin Ji /* Pixel clock frequency is too high */ 294*8bdfc5daSXin Ji DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 295*8bdfc5daSXin Ji pixelclock, 296*8bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 297*8bdfc5daSXin Ji return -EINVAL; 298*8bdfc5daSXin Ji } 299*8bdfc5daSXin Ji 300*8bdfc5daSXin Ji if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 301*8bdfc5daSXin Ji /* Pixel clock frequency is too low */ 302*8bdfc5daSXin Ji DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 303*8bdfc5daSXin Ji pixelclock, 304*8bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 305*8bdfc5daSXin Ji return -EINVAL; 306*8bdfc5daSXin Ji } 307*8bdfc5daSXin Ji 308*8bdfc5daSXin Ji for (*post_divider = 1; 309*8bdfc5daSXin Ji pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 310*8bdfc5daSXin Ji *post_divider += 1; 311*8bdfc5daSXin Ji 312*8bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 313*8bdfc5daSXin Ji for (*post_divider = 1; 314*8bdfc5daSXin Ji (pixelclock < 315*8bdfc5daSXin Ji (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 316*8bdfc5daSXin Ji *post_divider += 1; 317*8bdfc5daSXin Ji 318*8bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 319*8bdfc5daSXin Ji DRM_ERROR("cannot find property post_divider(%d)\n", 320*8bdfc5daSXin Ji *post_divider); 321*8bdfc5daSXin Ji return -EDOM; 322*8bdfc5daSXin Ji } 323*8bdfc5daSXin Ji } 324*8bdfc5daSXin Ji 325*8bdfc5daSXin Ji /* Patch to improve the accuracy */ 326*8bdfc5daSXin Ji if (*post_divider == 7) { 327*8bdfc5daSXin Ji /* 27,000,000 is not divisible by 7 */ 328*8bdfc5daSXin Ji *post_divider = 8; 329*8bdfc5daSXin Ji } else if (*post_divider == 11) { 330*8bdfc5daSXin Ji /* 27,000,000 is not divisible by 11 */ 331*8bdfc5daSXin Ji *post_divider = 12; 332*8bdfc5daSXin Ji } else if ((*post_divider == 13) || (*post_divider == 14)) { 333*8bdfc5daSXin Ji /* 27,000,000 is not divisible by 13 or 14 */ 334*8bdfc5daSXin Ji *post_divider = 15; 335*8bdfc5daSXin Ji } 336*8bdfc5daSXin Ji 337*8bdfc5daSXin Ji if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 338*8bdfc5daSXin Ji DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 339*8bdfc5daSXin Ji pixelclock * (*post_divider), 340*8bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX); 341*8bdfc5daSXin Ji return -EDOM; 342*8bdfc5daSXin Ji } 343*8bdfc5daSXin Ji 344*8bdfc5daSXin Ji *m = pixelclock; 345*8bdfc5daSXin Ji *n = XTAL_FRQ / (*post_divider); 346*8bdfc5daSXin Ji 347*8bdfc5daSXin Ji anx7625_reduction_of_a_fraction(m, n); 348*8bdfc5daSXin Ji 349*8bdfc5daSXin Ji return 0; 350*8bdfc5daSXin Ji } 351*8bdfc5daSXin Ji 352*8bdfc5daSXin Ji static int anx7625_odfc_config(struct anx7625_data *ctx, 353*8bdfc5daSXin Ji u8 post_divider) 354*8bdfc5daSXin Ji { 355*8bdfc5daSXin Ji int ret; 356*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 357*8bdfc5daSXin Ji 358*8bdfc5daSXin Ji /* Config input reference clock frequency 27MHz/19.2MHz */ 359*8bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 360*8bdfc5daSXin Ji ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 361*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 362*8bdfc5daSXin Ji (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 363*8bdfc5daSXin Ji /* Post divider */ 364*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 365*8bdfc5daSXin Ji MIPI_DIGITAL_PLL_8, 0x0f); 366*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 367*8bdfc5daSXin Ji post_divider << 4); 368*8bdfc5daSXin Ji 369*8bdfc5daSXin Ji /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 370*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 371*8bdfc5daSXin Ji ~MIPI_PLL_VCO_TUNE_REG_VAL); 372*8bdfc5daSXin Ji 373*8bdfc5daSXin Ji /* Reset ODFC PLL */ 374*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 375*8bdfc5daSXin Ji ~MIPI_PLL_RESET_N); 376*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 377*8bdfc5daSXin Ji MIPI_PLL_RESET_N); 378*8bdfc5daSXin Ji 379*8bdfc5daSXin Ji if (ret < 0) 380*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error.\n"); 381*8bdfc5daSXin Ji 382*8bdfc5daSXin Ji return ret; 383*8bdfc5daSXin Ji } 384*8bdfc5daSXin Ji 385*8bdfc5daSXin Ji static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 386*8bdfc5daSXin Ji { 387*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 388*8bdfc5daSXin Ji unsigned long m, n; 389*8bdfc5daSXin Ji u16 htotal; 390*8bdfc5daSXin Ji int ret; 391*8bdfc5daSXin Ji u8 post_divider = 0; 392*8bdfc5daSXin Ji 393*8bdfc5daSXin Ji ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 394*8bdfc5daSXin Ji &m, &n, &post_divider); 395*8bdfc5daSXin Ji 396*8bdfc5daSXin Ji if (ret) { 397*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 398*8bdfc5daSXin Ji return ret; 399*8bdfc5daSXin Ji } 400*8bdfc5daSXin Ji 401*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 402*8bdfc5daSXin Ji m, n, post_divider); 403*8bdfc5daSXin Ji 404*8bdfc5daSXin Ji /* Configure pixel clock */ 405*8bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 406*8bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) & 0xFF); 407*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 408*8bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) >> 8); 409*8bdfc5daSXin Ji /* Lane count */ 410*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 411*8bdfc5daSXin Ji MIPI_LANE_CTRL_0, 0xfc); 412*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 413*8bdfc5daSXin Ji MIPI_LANE_CTRL_0, 3); 414*8bdfc5daSXin Ji 415*8bdfc5daSXin Ji /* Htotal */ 416*8bdfc5daSXin Ji htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 417*8bdfc5daSXin Ji ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 418*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 419*8bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 420*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 421*8bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 422*8bdfc5daSXin Ji /* Hactive */ 423*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 424*8bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 425*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 426*8bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 427*8bdfc5daSXin Ji /* HFP */ 428*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 429*8bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 430*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 431*8bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_H, 432*8bdfc5daSXin Ji ctx->dt.hfront_porch.min >> 8); 433*8bdfc5daSXin Ji /* HWS */ 434*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 435*8bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 436*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 437*8bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 438*8bdfc5daSXin Ji /* HBP */ 439*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 440*8bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 441*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 442*8bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 443*8bdfc5daSXin Ji /* Vactive */ 444*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 445*8bdfc5daSXin Ji ctx->dt.vactive.min); 446*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 447*8bdfc5daSXin Ji ctx->dt.vactive.min >> 8); 448*8bdfc5daSXin Ji /* VFP */ 449*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 450*8bdfc5daSXin Ji VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 451*8bdfc5daSXin Ji /* VWS */ 452*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 453*8bdfc5daSXin Ji VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 454*8bdfc5daSXin Ji /* VBP */ 455*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 456*8bdfc5daSXin Ji VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 457*8bdfc5daSXin Ji /* M value */ 458*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 459*8bdfc5daSXin Ji MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 460*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 461*8bdfc5daSXin Ji MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 462*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 463*8bdfc5daSXin Ji MIPI_PLL_M_NUM_7_0, (m & 0xff)); 464*8bdfc5daSXin Ji /* N value */ 465*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 466*8bdfc5daSXin Ji MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 467*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 468*8bdfc5daSXin Ji MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 469*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 470*8bdfc5daSXin Ji (n & 0xff)); 471*8bdfc5daSXin Ji /* Diff */ 472*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 473*8bdfc5daSXin Ji MIPI_DIGITAL_ADJ_1, 0x3D); 474*8bdfc5daSXin Ji 475*8bdfc5daSXin Ji ret |= anx7625_odfc_config(ctx, post_divider - 1); 476*8bdfc5daSXin Ji 477*8bdfc5daSXin Ji if (ret < 0) 478*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 479*8bdfc5daSXin Ji 480*8bdfc5daSXin Ji return ret; 481*8bdfc5daSXin Ji } 482*8bdfc5daSXin Ji 483*8bdfc5daSXin Ji static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 484*8bdfc5daSXin Ji { 485*8bdfc5daSXin Ji int val; 486*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 487*8bdfc5daSXin Ji 488*8bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 489*8bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 490*8bdfc5daSXin Ji if (val < 0) { 491*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 492*8bdfc5daSXin Ji return -EIO; 493*8bdfc5daSXin Ji } 494*8bdfc5daSXin Ji 495*8bdfc5daSXin Ji val |= (1 << MIPI_SWAP_CH3); 496*8bdfc5daSXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 497*8bdfc5daSXin Ji } 498*8bdfc5daSXin Ji 499*8bdfc5daSXin Ji static int anx7625_api_dsi_config(struct anx7625_data *ctx) 500*8bdfc5daSXin Ji 501*8bdfc5daSXin Ji { 502*8bdfc5daSXin Ji int val, ret; 503*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 504*8bdfc5daSXin Ji 505*8bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 506*8bdfc5daSXin Ji ret = anx7625_swap_dsi_lane3(ctx); 507*8bdfc5daSXin Ji if (ret < 0) { 508*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 509*8bdfc5daSXin Ji return ret; 510*8bdfc5daSXin Ji } 511*8bdfc5daSXin Ji 512*8bdfc5daSXin Ji /* DSI clock settings */ 513*8bdfc5daSXin Ji val = (0 << MIPI_HS_PWD_CLK) | 514*8bdfc5daSXin Ji (0 << MIPI_HS_RT_CLK) | 515*8bdfc5daSXin Ji (0 << MIPI_PD_CLK) | 516*8bdfc5daSXin Ji (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 517*8bdfc5daSXin Ji (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 518*8bdfc5daSXin Ji (0 << MIPI_CLK_DET_DET_BYPASS) | 519*8bdfc5daSXin Ji (0 << MIPI_CLK_MISS_CTRL) | 520*8bdfc5daSXin Ji (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 521*8bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 522*8bdfc5daSXin Ji MIPI_PHY_CONTROL_3, val); 523*8bdfc5daSXin Ji 524*8bdfc5daSXin Ji /* 525*8bdfc5daSXin Ji * Decreased HS prepare timing delay from 160ns to 80ns work with 526*8bdfc5daSXin Ji * a) Dragon board 810 series (Qualcomm AP) 527*8bdfc5daSXin Ji * b) Moving Pixel DSI source (PG3A pattern generator + 528*8bdfc5daSXin Ji * P332 D-PHY Probe) default D-PHY timing 529*8bdfc5daSXin Ji * 5ns/step 530*8bdfc5daSXin Ji */ 531*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 532*8bdfc5daSXin Ji MIPI_TIME_HS_PRPR, 0x10); 533*8bdfc5daSXin Ji 534*8bdfc5daSXin Ji /* Enable DSI mode*/ 535*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 536*8bdfc5daSXin Ji SELECT_DSI << MIPI_DPI_SELECT); 537*8bdfc5daSXin Ji 538*8bdfc5daSXin Ji ret |= anx7625_dsi_video_timing_config(ctx); 539*8bdfc5daSXin Ji if (ret < 0) { 540*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 541*8bdfc5daSXin Ji return ret; 542*8bdfc5daSXin Ji } 543*8bdfc5daSXin Ji 544*8bdfc5daSXin Ji /* Toggle m, n ready */ 545*8bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 546*8bdfc5daSXin Ji ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 547*8bdfc5daSXin Ji usleep_range(1000, 1100); 548*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 549*8bdfc5daSXin Ji MIPI_M_NUM_READY | MIPI_N_NUM_READY); 550*8bdfc5daSXin Ji 551*8bdfc5daSXin Ji /* Configure integer stable register */ 552*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 553*8bdfc5daSXin Ji MIPI_VIDEO_STABLE_CNT, 0x02); 554*8bdfc5daSXin Ji /* Power on MIPI RX */ 555*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 556*8bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x00); 557*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 558*8bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x80); 559*8bdfc5daSXin Ji 560*8bdfc5daSXin Ji if (ret < 0) 561*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 562*8bdfc5daSXin Ji 563*8bdfc5daSXin Ji return ret; 564*8bdfc5daSXin Ji } 565*8bdfc5daSXin Ji 566*8bdfc5daSXin Ji static int anx7625_dsi_config(struct anx7625_data *ctx) 567*8bdfc5daSXin Ji { 568*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 569*8bdfc5daSXin Ji int ret; 570*8bdfc5daSXin Ji 571*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 572*8bdfc5daSXin Ji 573*8bdfc5daSXin Ji /* DSC disable */ 574*8bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 575*8bdfc5daSXin Ji R_DSC_CTRL_0, ~DSC_EN); 576*8bdfc5daSXin Ji 577*8bdfc5daSXin Ji ret |= anx7625_api_dsi_config(ctx); 578*8bdfc5daSXin Ji 579*8bdfc5daSXin Ji if (ret < 0) { 580*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 581*8bdfc5daSXin Ji return ret; 582*8bdfc5daSXin Ji } 583*8bdfc5daSXin Ji 584*8bdfc5daSXin Ji /* Set MIPI RX EN */ 585*8bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 586*8bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 587*8bdfc5daSXin Ji /* Clear mute flag */ 588*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 589*8bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 590*8bdfc5daSXin Ji if (ret < 0) 591*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 592*8bdfc5daSXin Ji else 593*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 594*8bdfc5daSXin Ji 595*8bdfc5daSXin Ji return ret; 596*8bdfc5daSXin Ji } 597*8bdfc5daSXin Ji 598*8bdfc5daSXin Ji static void anx7625_dp_start(struct anx7625_data *ctx) 599*8bdfc5daSXin Ji { 600*8bdfc5daSXin Ji int ret; 601*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 602*8bdfc5daSXin Ji 603*8bdfc5daSXin Ji if (!ctx->display_timing_valid) { 604*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 605*8bdfc5daSXin Ji return; 606*8bdfc5daSXin Ji } 607*8bdfc5daSXin Ji 608*8bdfc5daSXin Ji anx7625_config_audio_input(ctx); 609*8bdfc5daSXin Ji 610*8bdfc5daSXin Ji ret = anx7625_dsi_config(ctx); 611*8bdfc5daSXin Ji 612*8bdfc5daSXin Ji if (ret < 0) 613*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 614*8bdfc5daSXin Ji } 615*8bdfc5daSXin Ji 616*8bdfc5daSXin Ji static void anx7625_dp_stop(struct anx7625_data *ctx) 617*8bdfc5daSXin Ji { 618*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 619*8bdfc5daSXin Ji int ret; 620*8bdfc5daSXin Ji 621*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 622*8bdfc5daSXin Ji 623*8bdfc5daSXin Ji /* 624*8bdfc5daSXin Ji * Video disable: 0x72:08 bit 7 = 0; 625*8bdfc5daSXin Ji * Audio disable: 0x70:87 bit 0 = 0; 626*8bdfc5daSXin Ji */ 627*8bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 628*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 629*8bdfc5daSXin Ji 630*8bdfc5daSXin Ji ret |= anx7625_video_mute_control(ctx, 1); 631*8bdfc5daSXin Ji if (ret < 0) 632*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 633*8bdfc5daSXin Ji } 634*8bdfc5daSXin Ji 635*8bdfc5daSXin Ji static int sp_tx_rst_aux(struct anx7625_data *ctx) 636*8bdfc5daSXin Ji { 637*8bdfc5daSXin Ji int ret; 638*8bdfc5daSXin Ji 639*8bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 640*8bdfc5daSXin Ji AUX_RST); 641*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 642*8bdfc5daSXin Ji ~AUX_RST); 643*8bdfc5daSXin Ji return ret; 644*8bdfc5daSXin Ji } 645*8bdfc5daSXin Ji 646*8bdfc5daSXin Ji static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 647*8bdfc5daSXin Ji { 648*8bdfc5daSXin Ji int ret; 649*8bdfc5daSXin Ji 650*8bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 651*8bdfc5daSXin Ji AP_AUX_BUFF_START, offset); 652*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 653*8bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 654*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 655*8bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 656*8bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 657*8bdfc5daSXin Ji } 658*8bdfc5daSXin Ji 659*8bdfc5daSXin Ji static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 660*8bdfc5daSXin Ji { 661*8bdfc5daSXin Ji int ret; 662*8bdfc5daSXin Ji 663*8bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 664*8bdfc5daSXin Ji AP_AUX_COMMAND, len_cmd); 665*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 666*8bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 667*8bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 668*8bdfc5daSXin Ji } 669*8bdfc5daSXin Ji 670*8bdfc5daSXin Ji static int sp_tx_get_edid_block(struct anx7625_data *ctx) 671*8bdfc5daSXin Ji { 672*8bdfc5daSXin Ji int c = 0; 673*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 674*8bdfc5daSXin Ji 675*8bdfc5daSXin Ji sp_tx_aux_wr(ctx, 0x7e); 676*8bdfc5daSXin Ji sp_tx_aux_rd(ctx, 0x01); 677*8bdfc5daSXin Ji c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 678*8bdfc5daSXin Ji if (c < 0) { 679*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 680*8bdfc5daSXin Ji return -EIO; 681*8bdfc5daSXin Ji } 682*8bdfc5daSXin Ji 683*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 684*8bdfc5daSXin Ji 685*8bdfc5daSXin Ji if (c > MAX_EDID_BLOCK) 686*8bdfc5daSXin Ji c = 1; 687*8bdfc5daSXin Ji 688*8bdfc5daSXin Ji return c; 689*8bdfc5daSXin Ji } 690*8bdfc5daSXin Ji 691*8bdfc5daSXin Ji static int edid_read(struct anx7625_data *ctx, 692*8bdfc5daSXin Ji u8 offset, u8 *pblock_buf) 693*8bdfc5daSXin Ji { 694*8bdfc5daSXin Ji int ret, cnt; 695*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 696*8bdfc5daSXin Ji 697*8bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 698*8bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 699*8bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 700*8bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 701*8bdfc5daSXin Ji 702*8bdfc5daSXin Ji if (ret) { 703*8bdfc5daSXin Ji sp_tx_rst_aux(ctx); 704*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 705*8bdfc5daSXin Ji } else { 706*8bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 707*8bdfc5daSXin Ji AP_AUX_BUFF_START, 708*8bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, 709*8bdfc5daSXin Ji pblock_buf); 710*8bdfc5daSXin Ji if (ret > 0) 711*8bdfc5daSXin Ji break; 712*8bdfc5daSXin Ji } 713*8bdfc5daSXin Ji } 714*8bdfc5daSXin Ji 715*8bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 716*8bdfc5daSXin Ji return -EIO; 717*8bdfc5daSXin Ji 718*8bdfc5daSXin Ji return 0; 719*8bdfc5daSXin Ji } 720*8bdfc5daSXin Ji 721*8bdfc5daSXin Ji static int segments_edid_read(struct anx7625_data *ctx, 722*8bdfc5daSXin Ji u8 segment, u8 *buf, u8 offset) 723*8bdfc5daSXin Ji { 724*8bdfc5daSXin Ji u8 cnt; 725*8bdfc5daSXin Ji int ret; 726*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 727*8bdfc5daSXin Ji 728*8bdfc5daSXin Ji /* Write address only */ 729*8bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 730*8bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x30); 731*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 732*8bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 733*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 734*8bdfc5daSXin Ji AP_AUX_CTRL_STATUS, 735*8bdfc5daSXin Ji AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 736*8bdfc5daSXin Ji 737*8bdfc5daSXin Ji ret |= wait_aux_op_finish(ctx); 738*8bdfc5daSXin Ji /* Write segment address */ 739*8bdfc5daSXin Ji ret |= sp_tx_aux_wr(ctx, segment); 740*8bdfc5daSXin Ji /* Data read */ 741*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 742*8bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 743*8bdfc5daSXin Ji if (ret) { 744*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 745*8bdfc5daSXin Ji return ret; 746*8bdfc5daSXin Ji } 747*8bdfc5daSXin Ji 748*8bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 749*8bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 750*8bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 751*8bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 752*8bdfc5daSXin Ji 753*8bdfc5daSXin Ji if (ret) { 754*8bdfc5daSXin Ji ret = sp_tx_rst_aux(ctx); 755*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 756*8bdfc5daSXin Ji } else { 757*8bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 758*8bdfc5daSXin Ji AP_AUX_BUFF_START, 759*8bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, buf); 760*8bdfc5daSXin Ji if (ret > 0) 761*8bdfc5daSXin Ji break; 762*8bdfc5daSXin Ji } 763*8bdfc5daSXin Ji } 764*8bdfc5daSXin Ji 765*8bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 766*8bdfc5daSXin Ji return -EIO; 767*8bdfc5daSXin Ji 768*8bdfc5daSXin Ji return 0; 769*8bdfc5daSXin Ji } 770*8bdfc5daSXin Ji 771*8bdfc5daSXin Ji static int sp_tx_edid_read(struct anx7625_data *ctx, 772*8bdfc5daSXin Ji u8 *pedid_blocks_buf) 773*8bdfc5daSXin Ji { 774*8bdfc5daSXin Ji u8 offset, edid_pos; 775*8bdfc5daSXin Ji int count, blocks_num; 776*8bdfc5daSXin Ji u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 777*8bdfc5daSXin Ji u8 i, j; 778*8bdfc5daSXin Ji u8 g_edid_break = 0; 779*8bdfc5daSXin Ji int ret; 780*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 781*8bdfc5daSXin Ji 782*8bdfc5daSXin Ji /* Address initial */ 783*8bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 784*8bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 785*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 786*8bdfc5daSXin Ji AP_AUX_ADDR_15_8, 0); 787*8bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 788*8bdfc5daSXin Ji AP_AUX_ADDR_19_16, 0xf0); 789*8bdfc5daSXin Ji if (ret < 0) { 790*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 791*8bdfc5daSXin Ji return -EIO; 792*8bdfc5daSXin Ji } 793*8bdfc5daSXin Ji 794*8bdfc5daSXin Ji blocks_num = sp_tx_get_edid_block(ctx); 795*8bdfc5daSXin Ji if (blocks_num < 0) 796*8bdfc5daSXin Ji return blocks_num; 797*8bdfc5daSXin Ji 798*8bdfc5daSXin Ji count = 0; 799*8bdfc5daSXin Ji 800*8bdfc5daSXin Ji do { 801*8bdfc5daSXin Ji switch (count) { 802*8bdfc5daSXin Ji case 0: 803*8bdfc5daSXin Ji case 1: 804*8bdfc5daSXin Ji for (i = 0; i < 8; i++) { 805*8bdfc5daSXin Ji offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 806*8bdfc5daSXin Ji g_edid_break = edid_read(ctx, offset, 807*8bdfc5daSXin Ji pblock_buf); 808*8bdfc5daSXin Ji 809*8bdfc5daSXin Ji if (g_edid_break) 810*8bdfc5daSXin Ji break; 811*8bdfc5daSXin Ji 812*8bdfc5daSXin Ji memcpy(&pedid_blocks_buf[offset], 813*8bdfc5daSXin Ji pblock_buf, 814*8bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 815*8bdfc5daSXin Ji } 816*8bdfc5daSXin Ji 817*8bdfc5daSXin Ji break; 818*8bdfc5daSXin Ji case 2: 819*8bdfc5daSXin Ji offset = 0x00; 820*8bdfc5daSXin Ji 821*8bdfc5daSXin Ji for (j = 0; j < 8; j++) { 822*8bdfc5daSXin Ji edid_pos = (j + count * 8) * 823*8bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 824*8bdfc5daSXin Ji 825*8bdfc5daSXin Ji if (g_edid_break == 1) 826*8bdfc5daSXin Ji break; 827*8bdfc5daSXin Ji 828*8bdfc5daSXin Ji segments_edid_read(ctx, count / 2, 829*8bdfc5daSXin Ji pblock_buf, offset); 830*8bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 831*8bdfc5daSXin Ji pblock_buf, 832*8bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 833*8bdfc5daSXin Ji offset = offset + 0x10; 834*8bdfc5daSXin Ji } 835*8bdfc5daSXin Ji 836*8bdfc5daSXin Ji break; 837*8bdfc5daSXin Ji case 3: 838*8bdfc5daSXin Ji offset = 0x80; 839*8bdfc5daSXin Ji 840*8bdfc5daSXin Ji for (j = 0; j < 8; j++) { 841*8bdfc5daSXin Ji edid_pos = (j + count * 8) * 842*8bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 843*8bdfc5daSXin Ji if (g_edid_break == 1) 844*8bdfc5daSXin Ji break; 845*8bdfc5daSXin Ji 846*8bdfc5daSXin Ji segments_edid_read(ctx, count / 2, 847*8bdfc5daSXin Ji pblock_buf, offset); 848*8bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 849*8bdfc5daSXin Ji pblock_buf, 850*8bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 851*8bdfc5daSXin Ji offset = offset + 0x10; 852*8bdfc5daSXin Ji } 853*8bdfc5daSXin Ji 854*8bdfc5daSXin Ji break; 855*8bdfc5daSXin Ji default: 856*8bdfc5daSXin Ji break; 857*8bdfc5daSXin Ji } 858*8bdfc5daSXin Ji 859*8bdfc5daSXin Ji count++; 860*8bdfc5daSXin Ji 861*8bdfc5daSXin Ji } while (blocks_num >= count); 862*8bdfc5daSXin Ji 863*8bdfc5daSXin Ji /* Check edid data */ 864*8bdfc5daSXin Ji if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 865*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 866*8bdfc5daSXin Ji return -EINVAL; 867*8bdfc5daSXin Ji } 868*8bdfc5daSXin Ji 869*8bdfc5daSXin Ji /* Reset aux channel */ 870*8bdfc5daSXin Ji sp_tx_rst_aux(ctx); 871*8bdfc5daSXin Ji 872*8bdfc5daSXin Ji return (blocks_num + 1); 873*8bdfc5daSXin Ji } 874*8bdfc5daSXin Ji 875*8bdfc5daSXin Ji static void anx7625_power_on(struct anx7625_data *ctx) 876*8bdfc5daSXin Ji { 877*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 878*8bdfc5daSXin Ji 879*8bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 880*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 881*8bdfc5daSXin Ji return; 882*8bdfc5daSXin Ji } 883*8bdfc5daSXin Ji 884*8bdfc5daSXin Ji /* Power on pin enable */ 885*8bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 1); 886*8bdfc5daSXin Ji usleep_range(10000, 11000); 887*8bdfc5daSXin Ji /* Power reset pin enable */ 888*8bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 1); 889*8bdfc5daSXin Ji usleep_range(10000, 11000); 890*8bdfc5daSXin Ji 891*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 892*8bdfc5daSXin Ji } 893*8bdfc5daSXin Ji 894*8bdfc5daSXin Ji static void anx7625_power_standby(struct anx7625_data *ctx) 895*8bdfc5daSXin Ji { 896*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 897*8bdfc5daSXin Ji 898*8bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 899*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 900*8bdfc5daSXin Ji return; 901*8bdfc5daSXin Ji } 902*8bdfc5daSXin Ji 903*8bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 0); 904*8bdfc5daSXin Ji usleep_range(1000, 1100); 905*8bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 0); 906*8bdfc5daSXin Ji usleep_range(1000, 1100); 907*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 908*8bdfc5daSXin Ji } 909*8bdfc5daSXin Ji 910*8bdfc5daSXin Ji /* Basic configurations of ANX7625 */ 911*8bdfc5daSXin Ji static void anx7625_config(struct anx7625_data *ctx) 912*8bdfc5daSXin Ji { 913*8bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 914*8bdfc5daSXin Ji XTAL_FRQ_SEL, XTAL_FRQ_27M); 915*8bdfc5daSXin Ji } 916*8bdfc5daSXin Ji 917*8bdfc5daSXin Ji static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 918*8bdfc5daSXin Ji { 919*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 920*8bdfc5daSXin Ji int ret; 921*8bdfc5daSXin Ji 922*8bdfc5daSXin Ji /* Reset main ocm */ 923*8bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 924*8bdfc5daSXin Ji /* Disable PD */ 925*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 926*8bdfc5daSXin Ji AP_AV_STATUS, AP_DISABLE_PD); 927*8bdfc5daSXin Ji /* Release main ocm */ 928*8bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 929*8bdfc5daSXin Ji 930*8bdfc5daSXin Ji if (ret < 0) 931*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 932*8bdfc5daSXin Ji else 933*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 934*8bdfc5daSXin Ji } 935*8bdfc5daSXin Ji 936*8bdfc5daSXin Ji static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 937*8bdfc5daSXin Ji { 938*8bdfc5daSXin Ji int ret; 939*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 940*8bdfc5daSXin Ji 941*8bdfc5daSXin Ji /* Check interface workable */ 942*8bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 943*8bdfc5daSXin Ji FLASH_LOAD_STA); 944*8bdfc5daSXin Ji if (ret < 0) { 945*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 946*8bdfc5daSXin Ji return ret; 947*8bdfc5daSXin Ji } 948*8bdfc5daSXin Ji if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 949*8bdfc5daSXin Ji return -ENODEV; 950*8bdfc5daSXin Ji 951*8bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 952*8bdfc5daSXin Ji 953*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 954*8bdfc5daSXin Ji anx7625_reg_read(ctx, 955*8bdfc5daSXin Ji ctx->i2c.rx_p0_client, 956*8bdfc5daSXin Ji OCM_FW_VERSION), 957*8bdfc5daSXin Ji anx7625_reg_read(ctx, 958*8bdfc5daSXin Ji ctx->i2c.rx_p0_client, 959*8bdfc5daSXin Ji OCM_FW_REVERSION)); 960*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 961*8bdfc5daSXin Ji ANX7625_DRV_VERSION); 962*8bdfc5daSXin Ji 963*8bdfc5daSXin Ji return 0; 964*8bdfc5daSXin Ji } 965*8bdfc5daSXin Ji 966*8bdfc5daSXin Ji static void anx7625_power_on_init(struct anx7625_data *ctx) 967*8bdfc5daSXin Ji { 968*8bdfc5daSXin Ji int retry_count, i; 969*8bdfc5daSXin Ji 970*8bdfc5daSXin Ji for (retry_count = 0; retry_count < 3; retry_count++) { 971*8bdfc5daSXin Ji anx7625_power_on(ctx); 972*8bdfc5daSXin Ji anx7625_config(ctx); 973*8bdfc5daSXin Ji 974*8bdfc5daSXin Ji for (i = 0; i < OCM_LOADING_TIME; i++) { 975*8bdfc5daSXin Ji if (!anx7625_ocm_loading_check(ctx)) 976*8bdfc5daSXin Ji return; 977*8bdfc5daSXin Ji usleep_range(1000, 1100); 978*8bdfc5daSXin Ji } 979*8bdfc5daSXin Ji anx7625_power_standby(ctx); 980*8bdfc5daSXin Ji } 981*8bdfc5daSXin Ji } 982*8bdfc5daSXin Ji 983*8bdfc5daSXin Ji static void anx7625_chip_control(struct anx7625_data *ctx, int state) 984*8bdfc5daSXin Ji { 985*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 986*8bdfc5daSXin Ji 987*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before set, power_state(%d).\n", 988*8bdfc5daSXin Ji atomic_read(&ctx->power_status)); 989*8bdfc5daSXin Ji 990*8bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) 991*8bdfc5daSXin Ji return; 992*8bdfc5daSXin Ji 993*8bdfc5daSXin Ji if (state) { 994*8bdfc5daSXin Ji atomic_inc(&ctx->power_status); 995*8bdfc5daSXin Ji if (atomic_read(&ctx->power_status) == 1) 996*8bdfc5daSXin Ji anx7625_power_on_init(ctx); 997*8bdfc5daSXin Ji } else { 998*8bdfc5daSXin Ji if (atomic_read(&ctx->power_status)) { 999*8bdfc5daSXin Ji atomic_dec(&ctx->power_status); 1000*8bdfc5daSXin Ji 1001*8bdfc5daSXin Ji if (atomic_read(&ctx->power_status) == 0) 1002*8bdfc5daSXin Ji anx7625_power_standby(ctx); 1003*8bdfc5daSXin Ji } 1004*8bdfc5daSXin Ji } 1005*8bdfc5daSXin Ji 1006*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after set, power_state(%d).\n", 1007*8bdfc5daSXin Ji atomic_read(&ctx->power_status)); 1008*8bdfc5daSXin Ji } 1009*8bdfc5daSXin Ji 1010*8bdfc5daSXin Ji static void anx7625_init_gpio(struct anx7625_data *platform) 1011*8bdfc5daSXin Ji { 1012*8bdfc5daSXin Ji struct device *dev = &platform->client->dev; 1013*8bdfc5daSXin Ji 1014*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1015*8bdfc5daSXin Ji 1016*8bdfc5daSXin Ji /* Gpio for chip power enable */ 1017*8bdfc5daSXin Ji platform->pdata.gpio_p_on = 1018*8bdfc5daSXin Ji devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1019*8bdfc5daSXin Ji /* Gpio for chip reset */ 1020*8bdfc5daSXin Ji platform->pdata.gpio_reset = 1021*8bdfc5daSXin Ji devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1022*8bdfc5daSXin Ji 1023*8bdfc5daSXin Ji if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1024*8bdfc5daSXin Ji platform->pdata.low_power_mode = 1; 1025*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1026*8bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_p_on), 1027*8bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_reset)); 1028*8bdfc5daSXin Ji } else { 1029*8bdfc5daSXin Ji platform->pdata.low_power_mode = 0; 1030*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1031*8bdfc5daSXin Ji } 1032*8bdfc5daSXin Ji } 1033*8bdfc5daSXin Ji 1034*8bdfc5daSXin Ji static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1035*8bdfc5daSXin Ji { 1036*8bdfc5daSXin Ji ctx->hpd_status = 0; 1037*8bdfc5daSXin Ji ctx->hpd_high_cnt = 0; 1038*8bdfc5daSXin Ji ctx->display_timing_valid = 0; 1039*8bdfc5daSXin Ji 1040*8bdfc5daSXin Ji if (ctx->pdata.low_power_mode == 0) 1041*8bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 1042*8bdfc5daSXin Ji } 1043*8bdfc5daSXin Ji 1044*8bdfc5daSXin Ji static void anx7625_start_dp_work(struct anx7625_data *ctx) 1045*8bdfc5daSXin Ji { 1046*8bdfc5daSXin Ji int ret; 1047*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1048*8bdfc5daSXin Ji 1049*8bdfc5daSXin Ji if (ctx->hpd_high_cnt >= 2) { 1050*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1051*8bdfc5daSXin Ji return; 1052*8bdfc5daSXin Ji } 1053*8bdfc5daSXin Ji 1054*8bdfc5daSXin Ji ctx->hpd_high_cnt++; 1055*8bdfc5daSXin Ji 1056*8bdfc5daSXin Ji /* Not support HDCP */ 1057*8bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1058*8bdfc5daSXin Ji 1059*8bdfc5daSXin Ji /* Try auth flag */ 1060*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1061*8bdfc5daSXin Ji /* Interrupt for DRM */ 1062*8bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1063*8bdfc5daSXin Ji if (ret < 0) 1064*8bdfc5daSXin Ji return; 1065*8bdfc5daSXin Ji 1066*8bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1067*8bdfc5daSXin Ji if (ret < 0) 1068*8bdfc5daSXin Ji return; 1069*8bdfc5daSXin Ji 1070*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1071*8bdfc5daSXin Ji } 1072*8bdfc5daSXin Ji 1073*8bdfc5daSXin Ji static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1074*8bdfc5daSXin Ji { 1075*8bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1076*8bdfc5daSXin Ji } 1077*8bdfc5daSXin Ji 1078*8bdfc5daSXin Ji static void anx7625_hpd_polling(struct anx7625_data *ctx) 1079*8bdfc5daSXin Ji { 1080*8bdfc5daSXin Ji int ret, val; 1081*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1082*8bdfc5daSXin Ji 1083*8bdfc5daSXin Ji if (atomic_read(&ctx->power_status) != 1) { 1084*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "No need to poling HPD status.\n"); 1085*8bdfc5daSXin Ji return; 1086*8bdfc5daSXin Ji } 1087*8bdfc5daSXin Ji 1088*8bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1089*8bdfc5daSXin Ji ctx, val, 1090*8bdfc5daSXin Ji ((val & HPD_STATUS) || (val < 0)), 1091*8bdfc5daSXin Ji 5000, 1092*8bdfc5daSXin Ji 5000 * 100); 1093*8bdfc5daSXin Ji if (ret) { 1094*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "HPD polling timeout!\n"); 1095*8bdfc5daSXin Ji } else { 1096*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "HPD raise up.\n"); 1097*8bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1098*8bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 1099*8bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1100*8bdfc5daSXin Ji INTERFACE_CHANGE_INT, 0); 1101*8bdfc5daSXin Ji } 1102*8bdfc5daSXin Ji 1103*8bdfc5daSXin Ji anx7625_start_dp_work(ctx); 1104*8bdfc5daSXin Ji } 1105*8bdfc5daSXin Ji 1106*8bdfc5daSXin Ji static void anx7625_disconnect_check(struct anx7625_data *ctx) 1107*8bdfc5daSXin Ji { 1108*8bdfc5daSXin Ji if (atomic_read(&ctx->power_status) == 0) 1109*8bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 1110*8bdfc5daSXin Ji } 1111*8bdfc5daSXin Ji 1112*8bdfc5daSXin Ji static void anx7625_low_power_mode_check(struct anx7625_data *ctx, 1113*8bdfc5daSXin Ji int state) 1114*8bdfc5daSXin Ji { 1115*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1116*8bdfc5daSXin Ji 1117*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode check, state(%d).\n", state); 1118*8bdfc5daSXin Ji 1119*8bdfc5daSXin Ji if (ctx->pdata.low_power_mode) { 1120*8bdfc5daSXin Ji anx7625_chip_control(ctx, state); 1121*8bdfc5daSXin Ji if (state) 1122*8bdfc5daSXin Ji anx7625_hpd_polling(ctx); 1123*8bdfc5daSXin Ji else 1124*8bdfc5daSXin Ji anx7625_disconnect_check(ctx); 1125*8bdfc5daSXin Ji } 1126*8bdfc5daSXin Ji } 1127*8bdfc5daSXin Ji 1128*8bdfc5daSXin Ji static void anx7625_remove_edid(struct anx7625_data *ctx) 1129*8bdfc5daSXin Ji { 1130*8bdfc5daSXin Ji ctx->slimport_edid_p.edid_block_num = -1; 1131*8bdfc5daSXin Ji } 1132*8bdfc5daSXin Ji 1133*8bdfc5daSXin Ji static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1134*8bdfc5daSXin Ji { 1135*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1136*8bdfc5daSXin Ji 1137*8bdfc5daSXin Ji /* HPD changed */ 1138*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1139*8bdfc5daSXin Ji (u32)on); 1140*8bdfc5daSXin Ji 1141*8bdfc5daSXin Ji if (on == 0) { 1142*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1143*8bdfc5daSXin Ji anx7625_remove_edid(ctx); 1144*8bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 1145*8bdfc5daSXin Ji } else { 1146*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1147*8bdfc5daSXin Ji anx7625_start_dp_work(ctx); 1148*8bdfc5daSXin Ji } 1149*8bdfc5daSXin Ji 1150*8bdfc5daSXin Ji ctx->hpd_status = 1; 1151*8bdfc5daSXin Ji } 1152*8bdfc5daSXin Ji 1153*8bdfc5daSXin Ji static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 1154*8bdfc5daSXin Ji { 1155*8bdfc5daSXin Ji int intr_vector, status; 1156*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1157*8bdfc5daSXin Ji 1158*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power_status=%d\n", 1159*8bdfc5daSXin Ji (u32)atomic_read(&ctx->power_status)); 1160*8bdfc5daSXin Ji 1161*8bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1162*8bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 1163*8bdfc5daSXin Ji if (status < 0) { 1164*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1165*8bdfc5daSXin Ji return status; 1166*8bdfc5daSXin Ji } 1167*8bdfc5daSXin Ji 1168*8bdfc5daSXin Ji intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1169*8bdfc5daSXin Ji INTERFACE_CHANGE_INT); 1170*8bdfc5daSXin Ji if (intr_vector < 0) { 1171*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1172*8bdfc5daSXin Ji return intr_vector; 1173*8bdfc5daSXin Ji } 1174*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1175*8bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1176*8bdfc5daSXin Ji INTERFACE_CHANGE_INT, 1177*8bdfc5daSXin Ji intr_vector & (~intr_vector)); 1178*8bdfc5daSXin Ji if (status < 0) { 1179*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1180*8bdfc5daSXin Ji return status; 1181*8bdfc5daSXin Ji } 1182*8bdfc5daSXin Ji 1183*8bdfc5daSXin Ji if (!(intr_vector & HPD_STATUS_CHANGE)) 1184*8bdfc5daSXin Ji return -ENOENT; 1185*8bdfc5daSXin Ji 1186*8bdfc5daSXin Ji status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1187*8bdfc5daSXin Ji SYSTEM_STSTUS); 1188*8bdfc5daSXin Ji if (status < 0) { 1189*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1190*8bdfc5daSXin Ji return status; 1191*8bdfc5daSXin Ji } 1192*8bdfc5daSXin Ji 1193*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1194*8bdfc5daSXin Ji dp_hpd_change_handler(ctx, status & HPD_STATUS); 1195*8bdfc5daSXin Ji 1196*8bdfc5daSXin Ji return 0; 1197*8bdfc5daSXin Ji } 1198*8bdfc5daSXin Ji 1199*8bdfc5daSXin Ji static void anx7625_work_func(struct work_struct *work) 1200*8bdfc5daSXin Ji { 1201*8bdfc5daSXin Ji int event; 1202*8bdfc5daSXin Ji struct anx7625_data *ctx = container_of(work, 1203*8bdfc5daSXin Ji struct anx7625_data, work); 1204*8bdfc5daSXin Ji 1205*8bdfc5daSXin Ji mutex_lock(&ctx->lock); 1206*8bdfc5daSXin Ji event = anx7625_hpd_change_detect(ctx); 1207*8bdfc5daSXin Ji mutex_unlock(&ctx->lock); 1208*8bdfc5daSXin Ji if (event < 0) 1209*8bdfc5daSXin Ji return; 1210*8bdfc5daSXin Ji 1211*8bdfc5daSXin Ji if (ctx->bridge_attached) 1212*8bdfc5daSXin Ji drm_helper_hpd_irq_event(ctx->bridge.dev); 1213*8bdfc5daSXin Ji } 1214*8bdfc5daSXin Ji 1215*8bdfc5daSXin Ji static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1216*8bdfc5daSXin Ji { 1217*8bdfc5daSXin Ji struct anx7625_data *ctx = (struct anx7625_data *)data; 1218*8bdfc5daSXin Ji 1219*8bdfc5daSXin Ji if (atomic_read(&ctx->power_status) != 1) 1220*8bdfc5daSXin Ji return IRQ_NONE; 1221*8bdfc5daSXin Ji 1222*8bdfc5daSXin Ji queue_work(ctx->workqueue, &ctx->work); 1223*8bdfc5daSXin Ji 1224*8bdfc5daSXin Ji return IRQ_HANDLED; 1225*8bdfc5daSXin Ji } 1226*8bdfc5daSXin Ji 1227*8bdfc5daSXin Ji static int anx7625_parse_dt(struct device *dev, 1228*8bdfc5daSXin Ji struct anx7625_platform_data *pdata) 1229*8bdfc5daSXin Ji { 1230*8bdfc5daSXin Ji struct device_node *np = dev->of_node; 1231*8bdfc5daSXin Ji struct drm_panel *panel; 1232*8bdfc5daSXin Ji int ret; 1233*8bdfc5daSXin Ji 1234*8bdfc5daSXin Ji pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1235*8bdfc5daSXin Ji if (!pdata->mipi_host_node) { 1236*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1237*8bdfc5daSXin Ji return -ENODEV; 1238*8bdfc5daSXin Ji } 1239*8bdfc5daSXin Ji 1240*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n"); 1241*8bdfc5daSXin Ji 1242*8bdfc5daSXin Ji ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 1243*8bdfc5daSXin Ji if (ret < 0) { 1244*8bdfc5daSXin Ji if (ret == -ENODEV) 1245*8bdfc5daSXin Ji return 0; 1246*8bdfc5daSXin Ji return ret; 1247*8bdfc5daSXin Ji } 1248*8bdfc5daSXin Ji if (!panel) 1249*8bdfc5daSXin Ji return -ENODEV; 1250*8bdfc5daSXin Ji 1251*8bdfc5daSXin Ji pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 1252*8bdfc5daSXin Ji if (IS_ERR(pdata->panel_bridge)) 1253*8bdfc5daSXin Ji return PTR_ERR(pdata->panel_bridge); 1254*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1255*8bdfc5daSXin Ji 1256*8bdfc5daSXin Ji return 0; 1257*8bdfc5daSXin Ji } 1258*8bdfc5daSXin Ji 1259*8bdfc5daSXin Ji static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1260*8bdfc5daSXin Ji { 1261*8bdfc5daSXin Ji return container_of(bridge, struct anx7625_data, bridge); 1262*8bdfc5daSXin Ji } 1263*8bdfc5daSXin Ji 1264*8bdfc5daSXin Ji static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 1265*8bdfc5daSXin Ji { 1266*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1267*8bdfc5daSXin Ji struct s_edid_data *p_edid = &ctx->slimport_edid_p; 1268*8bdfc5daSXin Ji int edid_num; 1269*8bdfc5daSXin Ji u8 *edid; 1270*8bdfc5daSXin Ji 1271*8bdfc5daSXin Ji edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1272*8bdfc5daSXin Ji if (!edid) { 1273*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 1274*8bdfc5daSXin Ji return NULL; 1275*8bdfc5daSXin Ji } 1276*8bdfc5daSXin Ji 1277*8bdfc5daSXin Ji if (ctx->slimport_edid_p.edid_block_num > 0) { 1278*8bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 1279*8bdfc5daSXin Ji FOUR_BLOCK_SIZE); 1280*8bdfc5daSXin Ji return (struct edid *)edid; 1281*8bdfc5daSXin Ji } 1282*8bdfc5daSXin Ji 1283*8bdfc5daSXin Ji anx7625_low_power_mode_check(ctx, 1); 1284*8bdfc5daSXin Ji edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 1285*8bdfc5daSXin Ji anx7625_low_power_mode_check(ctx, 0); 1286*8bdfc5daSXin Ji 1287*8bdfc5daSXin Ji if (edid_num < 1) { 1288*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1289*8bdfc5daSXin Ji kfree(edid); 1290*8bdfc5daSXin Ji return NULL; 1291*8bdfc5daSXin Ji } 1292*8bdfc5daSXin Ji 1293*8bdfc5daSXin Ji p_edid->edid_block_num = edid_num; 1294*8bdfc5daSXin Ji 1295*8bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 1296*8bdfc5daSXin Ji return (struct edid *)edid; 1297*8bdfc5daSXin Ji } 1298*8bdfc5daSXin Ji 1299*8bdfc5daSXin Ji static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1300*8bdfc5daSXin Ji { 1301*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1302*8bdfc5daSXin Ji 1303*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n"); 1304*8bdfc5daSXin Ji 1305*8bdfc5daSXin Ji return connector_status_connected; 1306*8bdfc5daSXin Ji } 1307*8bdfc5daSXin Ji 1308*8bdfc5daSXin Ji static int anx7625_attach_dsi(struct anx7625_data *ctx) 1309*8bdfc5daSXin Ji { 1310*8bdfc5daSXin Ji struct mipi_dsi_device *dsi; 1311*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1312*8bdfc5daSXin Ji struct mipi_dsi_host *host; 1313*8bdfc5daSXin Ji const struct mipi_dsi_device_info info = { 1314*8bdfc5daSXin Ji .type = "anx7625", 1315*8bdfc5daSXin Ji .channel = 0, 1316*8bdfc5daSXin Ji .node = NULL, 1317*8bdfc5daSXin Ji }; 1318*8bdfc5daSXin Ji 1319*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 1320*8bdfc5daSXin Ji 1321*8bdfc5daSXin Ji host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 1322*8bdfc5daSXin Ji if (!host) { 1323*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 1324*8bdfc5daSXin Ji return -EINVAL; 1325*8bdfc5daSXin Ji } 1326*8bdfc5daSXin Ji 1327*8bdfc5daSXin Ji dsi = mipi_dsi_device_register_full(host, &info); 1328*8bdfc5daSXin Ji if (IS_ERR(dsi)) { 1329*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 1330*8bdfc5daSXin Ji return -EINVAL; 1331*8bdfc5daSXin Ji } 1332*8bdfc5daSXin Ji 1333*8bdfc5daSXin Ji dsi->lanes = 4; 1334*8bdfc5daSXin Ji dsi->format = MIPI_DSI_FMT_RGB888; 1335*8bdfc5daSXin Ji dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1336*8bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1337*8bdfc5daSXin Ji MIPI_DSI_MODE_EOT_PACKET | 1338*8bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_HSE; 1339*8bdfc5daSXin Ji 1340*8bdfc5daSXin Ji if (mipi_dsi_attach(dsi) < 0) { 1341*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 1342*8bdfc5daSXin Ji mipi_dsi_device_unregister(dsi); 1343*8bdfc5daSXin Ji return -EINVAL; 1344*8bdfc5daSXin Ji } 1345*8bdfc5daSXin Ji 1346*8bdfc5daSXin Ji ctx->dsi = dsi; 1347*8bdfc5daSXin Ji 1348*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 1349*8bdfc5daSXin Ji 1350*8bdfc5daSXin Ji return 0; 1351*8bdfc5daSXin Ji } 1352*8bdfc5daSXin Ji 1353*8bdfc5daSXin Ji static void anx7625_bridge_detach(struct drm_bridge *bridge) 1354*8bdfc5daSXin Ji { 1355*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1356*8bdfc5daSXin Ji 1357*8bdfc5daSXin Ji if (ctx->dsi) { 1358*8bdfc5daSXin Ji mipi_dsi_detach(ctx->dsi); 1359*8bdfc5daSXin Ji mipi_dsi_device_unregister(ctx->dsi); 1360*8bdfc5daSXin Ji } 1361*8bdfc5daSXin Ji } 1362*8bdfc5daSXin Ji 1363*8bdfc5daSXin Ji static int anx7625_bridge_attach(struct drm_bridge *bridge, 1364*8bdfc5daSXin Ji enum drm_bridge_attach_flags flags) 1365*8bdfc5daSXin Ji { 1366*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1367*8bdfc5daSXin Ji int err; 1368*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1369*8bdfc5daSXin Ji 1370*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 1371*8bdfc5daSXin Ji if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 1372*8bdfc5daSXin Ji return -EINVAL; 1373*8bdfc5daSXin Ji 1374*8bdfc5daSXin Ji if (!bridge->encoder) { 1375*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Parent encoder object not found"); 1376*8bdfc5daSXin Ji return -ENODEV; 1377*8bdfc5daSXin Ji } 1378*8bdfc5daSXin Ji 1379*8bdfc5daSXin Ji err = anx7625_attach_dsi(ctx); 1380*8bdfc5daSXin Ji if (err) { 1381*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err); 1382*8bdfc5daSXin Ji return err; 1383*8bdfc5daSXin Ji } 1384*8bdfc5daSXin Ji 1385*8bdfc5daSXin Ji if (ctx->pdata.panel_bridge) { 1386*8bdfc5daSXin Ji err = drm_bridge_attach(bridge->encoder, 1387*8bdfc5daSXin Ji ctx->pdata.panel_bridge, 1388*8bdfc5daSXin Ji &ctx->bridge, flags); 1389*8bdfc5daSXin Ji if (err) { 1390*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, 1391*8bdfc5daSXin Ji "Fail to attach panel bridge: %d\n", err); 1392*8bdfc5daSXin Ji return err; 1393*8bdfc5daSXin Ji } 1394*8bdfc5daSXin Ji } 1395*8bdfc5daSXin Ji 1396*8bdfc5daSXin Ji ctx->bridge_attached = 1; 1397*8bdfc5daSXin Ji 1398*8bdfc5daSXin Ji return 0; 1399*8bdfc5daSXin Ji } 1400*8bdfc5daSXin Ji 1401*8bdfc5daSXin Ji static enum drm_mode_status 1402*8bdfc5daSXin Ji anx7625_bridge_mode_valid(struct drm_bridge *bridge, 1403*8bdfc5daSXin Ji const struct drm_display_info *info, 1404*8bdfc5daSXin Ji const struct drm_display_mode *mode) 1405*8bdfc5daSXin Ji { 1406*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1407*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1408*8bdfc5daSXin Ji 1409*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 1410*8bdfc5daSXin Ji 1411*8bdfc5daSXin Ji /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 1412*8bdfc5daSXin Ji if (mode->clock > SUPPORT_PIXEL_CLOCK) { 1413*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, 1414*8bdfc5daSXin Ji "drm mode invalid, pixelclock too high.\n"); 1415*8bdfc5daSXin Ji return MODE_CLOCK_HIGH; 1416*8bdfc5daSXin Ji } 1417*8bdfc5daSXin Ji 1418*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 1419*8bdfc5daSXin Ji 1420*8bdfc5daSXin Ji return MODE_OK; 1421*8bdfc5daSXin Ji } 1422*8bdfc5daSXin Ji 1423*8bdfc5daSXin Ji static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 1424*8bdfc5daSXin Ji const struct drm_display_mode *old_mode, 1425*8bdfc5daSXin Ji const struct drm_display_mode *mode) 1426*8bdfc5daSXin Ji { 1427*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1428*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1429*8bdfc5daSXin Ji 1430*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 1431*8bdfc5daSXin Ji 1432*8bdfc5daSXin Ji ctx->dt.pixelclock.min = mode->clock; 1433*8bdfc5daSXin Ji ctx->dt.hactive.min = mode->hdisplay; 1434*8bdfc5daSXin Ji ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 1435*8bdfc5daSXin Ji ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 1436*8bdfc5daSXin Ji ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 1437*8bdfc5daSXin Ji ctx->dt.vactive.min = mode->vdisplay; 1438*8bdfc5daSXin Ji ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 1439*8bdfc5daSXin Ji ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 1440*8bdfc5daSXin Ji ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 1441*8bdfc5daSXin Ji 1442*8bdfc5daSXin Ji ctx->display_timing_valid = 1; 1443*8bdfc5daSXin Ji 1444*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 1445*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 1446*8bdfc5daSXin Ji ctx->dt.hactive.min, 1447*8bdfc5daSXin Ji ctx->dt.hsync_len.min, 1448*8bdfc5daSXin Ji ctx->dt.hfront_porch.min, 1449*8bdfc5daSXin Ji ctx->dt.hback_porch.min); 1450*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 1451*8bdfc5daSXin Ji ctx->dt.vactive.min, 1452*8bdfc5daSXin Ji ctx->dt.vsync_len.min, 1453*8bdfc5daSXin Ji ctx->dt.vfront_porch.min, 1454*8bdfc5daSXin Ji ctx->dt.vback_porch.min); 1455*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 1456*8bdfc5daSXin Ji mode->hdisplay, 1457*8bdfc5daSXin Ji mode->hsync_start); 1458*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 1459*8bdfc5daSXin Ji mode->hsync_end, 1460*8bdfc5daSXin Ji mode->htotal); 1461*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 1462*8bdfc5daSXin Ji mode->vdisplay, 1463*8bdfc5daSXin Ji mode->vsync_start); 1464*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 1465*8bdfc5daSXin Ji mode->vsync_end, 1466*8bdfc5daSXin Ji mode->vtotal); 1467*8bdfc5daSXin Ji } 1468*8bdfc5daSXin Ji 1469*8bdfc5daSXin Ji static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 1470*8bdfc5daSXin Ji const struct drm_display_mode *mode, 1471*8bdfc5daSXin Ji struct drm_display_mode *adj) 1472*8bdfc5daSXin Ji { 1473*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1474*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1475*8bdfc5daSXin Ji u32 hsync, hfp, hbp, hblanking; 1476*8bdfc5daSXin Ji u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 1477*8bdfc5daSXin Ji u32 vref, adj_clock; 1478*8bdfc5daSXin Ji 1479*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 1480*8bdfc5daSXin Ji 1481*8bdfc5daSXin Ji hsync = mode->hsync_end - mode->hsync_start; 1482*8bdfc5daSXin Ji hfp = mode->hsync_start - mode->hdisplay; 1483*8bdfc5daSXin Ji hbp = mode->htotal - mode->hsync_end; 1484*8bdfc5daSXin Ji hblanking = mode->htotal - mode->hdisplay; 1485*8bdfc5daSXin Ji 1486*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 1487*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1488*8bdfc5daSXin Ji hsync, hfp, hbp, adj->clock); 1489*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1490*8bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 1491*8bdfc5daSXin Ji 1492*8bdfc5daSXin Ji adj_hfp = hfp; 1493*8bdfc5daSXin Ji adj_hsync = hsync; 1494*8bdfc5daSXin Ji adj_hbp = hbp; 1495*8bdfc5daSXin Ji adj_hblanking = hblanking; 1496*8bdfc5daSXin Ji 1497*8bdfc5daSXin Ji /* HFP needs to be even */ 1498*8bdfc5daSXin Ji if (hfp & 0x1) { 1499*8bdfc5daSXin Ji adj_hfp += 1; 1500*8bdfc5daSXin Ji adj_hblanking += 1; 1501*8bdfc5daSXin Ji } 1502*8bdfc5daSXin Ji 1503*8bdfc5daSXin Ji /* HBP needs to be even */ 1504*8bdfc5daSXin Ji if (hbp & 0x1) { 1505*8bdfc5daSXin Ji adj_hbp -= 1; 1506*8bdfc5daSXin Ji adj_hblanking -= 1; 1507*8bdfc5daSXin Ji } 1508*8bdfc5daSXin Ji 1509*8bdfc5daSXin Ji /* HSYNC needs to be even */ 1510*8bdfc5daSXin Ji if (hsync & 0x1) { 1511*8bdfc5daSXin Ji if (adj_hblanking < hblanking) 1512*8bdfc5daSXin Ji adj_hsync += 1; 1513*8bdfc5daSXin Ji else 1514*8bdfc5daSXin Ji adj_hsync -= 1; 1515*8bdfc5daSXin Ji } 1516*8bdfc5daSXin Ji 1517*8bdfc5daSXin Ji /* 1518*8bdfc5daSXin Ji * Once illegal timing detected, use default HFP, HSYNC, HBP 1519*8bdfc5daSXin Ji * This adjusting made for built-in eDP panel, for the externel 1520*8bdfc5daSXin Ji * DP monitor, may need return false. 1521*8bdfc5daSXin Ji */ 1522*8bdfc5daSXin Ji if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 1523*8bdfc5daSXin Ji adj_hsync = SYNC_LEN_DEF; 1524*8bdfc5daSXin Ji adj_hfp = HFP_HBP_DEF; 1525*8bdfc5daSXin Ji adj_hbp = HFP_HBP_DEF; 1526*8bdfc5daSXin Ji vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 1527*8bdfc5daSXin Ji if (hblanking < HBLANKING_MIN) { 1528*8bdfc5daSXin Ji delta_adj = HBLANKING_MIN - hblanking; 1529*8bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 1530*8bdfc5daSXin Ji adj->clock += DIV_ROUND_UP(adj_clock, 1000); 1531*8bdfc5daSXin Ji } else { 1532*8bdfc5daSXin Ji delta_adj = hblanking - HBLANKING_MIN; 1533*8bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 1534*8bdfc5daSXin Ji adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 1535*8bdfc5daSXin Ji } 1536*8bdfc5daSXin Ji 1537*8bdfc5daSXin Ji DRM_WARN("illegal hblanking timing, use default.\n"); 1538*8bdfc5daSXin Ji DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 1539*8bdfc5daSXin Ji } else if (adj_hfp < HP_MIN) { 1540*8bdfc5daSXin Ji /* Adjust hfp if hfp less than HP_MIN */ 1541*8bdfc5daSXin Ji delta_adj = HP_MIN - adj_hfp; 1542*8bdfc5daSXin Ji adj_hfp = HP_MIN; 1543*8bdfc5daSXin Ji 1544*8bdfc5daSXin Ji /* 1545*8bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP does not have enough 1546*8bdfc5daSXin Ji * space, adjust HSYNC length, otherwise adjust HBP 1547*8bdfc5daSXin Ji */ 1548*8bdfc5daSXin Ji if ((adj_hbp - delta_adj) < HP_MIN) 1549*8bdfc5daSXin Ji /* HBP not enough space */ 1550*8bdfc5daSXin Ji adj_hsync -= delta_adj; 1551*8bdfc5daSXin Ji else 1552*8bdfc5daSXin Ji adj_hbp -= delta_adj; 1553*8bdfc5daSXin Ji } else if (adj_hbp < HP_MIN) { 1554*8bdfc5daSXin Ji delta_adj = HP_MIN - adj_hbp; 1555*8bdfc5daSXin Ji adj_hbp = HP_MIN; 1556*8bdfc5daSXin Ji 1557*8bdfc5daSXin Ji /* 1558*8bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP hasn't enough space, 1559*8bdfc5daSXin Ji * adjust HSYNC length, otherwize adjust HBP 1560*8bdfc5daSXin Ji */ 1561*8bdfc5daSXin Ji if ((adj_hfp - delta_adj) < HP_MIN) 1562*8bdfc5daSXin Ji /* HFP not enough space */ 1563*8bdfc5daSXin Ji adj_hsync -= delta_adj; 1564*8bdfc5daSXin Ji else 1565*8bdfc5daSXin Ji adj_hfp -= delta_adj; 1566*8bdfc5daSXin Ji } 1567*8bdfc5daSXin Ji 1568*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 1569*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 1570*8bdfc5daSXin Ji adj_hsync, adj_hfp, adj_hbp, adj->clock); 1571*8bdfc5daSXin Ji 1572*8bdfc5daSXin Ji /* Reconstruct timing */ 1573*8bdfc5daSXin Ji adj->hsync_start = adj->hdisplay + adj_hfp; 1574*8bdfc5daSXin Ji adj->hsync_end = adj->hsync_start + adj_hsync; 1575*8bdfc5daSXin Ji adj->htotal = adj->hsync_end + adj_hbp; 1576*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 1577*8bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 1578*8bdfc5daSXin Ji 1579*8bdfc5daSXin Ji return true; 1580*8bdfc5daSXin Ji } 1581*8bdfc5daSXin Ji 1582*8bdfc5daSXin Ji static void anx7625_bridge_enable(struct drm_bridge *bridge) 1583*8bdfc5daSXin Ji { 1584*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1585*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1586*8bdfc5daSXin Ji 1587*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 1588*8bdfc5daSXin Ji 1589*8bdfc5daSXin Ji anx7625_low_power_mode_check(ctx, 1); 1590*8bdfc5daSXin Ji 1591*8bdfc5daSXin Ji if (WARN_ON(!atomic_read(&ctx->power_status))) 1592*8bdfc5daSXin Ji return; 1593*8bdfc5daSXin Ji 1594*8bdfc5daSXin Ji anx7625_dp_start(ctx); 1595*8bdfc5daSXin Ji } 1596*8bdfc5daSXin Ji 1597*8bdfc5daSXin Ji static void anx7625_bridge_disable(struct drm_bridge *bridge) 1598*8bdfc5daSXin Ji { 1599*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1600*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1601*8bdfc5daSXin Ji 1602*8bdfc5daSXin Ji if (WARN_ON(!atomic_read(&ctx->power_status))) 1603*8bdfc5daSXin Ji return; 1604*8bdfc5daSXin Ji 1605*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 1606*8bdfc5daSXin Ji 1607*8bdfc5daSXin Ji anx7625_dp_stop(ctx); 1608*8bdfc5daSXin Ji 1609*8bdfc5daSXin Ji anx7625_low_power_mode_check(ctx, 0); 1610*8bdfc5daSXin Ji } 1611*8bdfc5daSXin Ji 1612*8bdfc5daSXin Ji static enum drm_connector_status 1613*8bdfc5daSXin Ji anx7625_bridge_detect(struct drm_bridge *bridge) 1614*8bdfc5daSXin Ji { 1615*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1616*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1617*8bdfc5daSXin Ji 1618*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 1619*8bdfc5daSXin Ji 1620*8bdfc5daSXin Ji return anx7625_sink_detect(ctx); 1621*8bdfc5daSXin Ji } 1622*8bdfc5daSXin Ji 1623*8bdfc5daSXin Ji static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 1624*8bdfc5daSXin Ji struct drm_connector *connector) 1625*8bdfc5daSXin Ji { 1626*8bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 1627*8bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1628*8bdfc5daSXin Ji 1629*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 1630*8bdfc5daSXin Ji 1631*8bdfc5daSXin Ji return anx7625_get_edid(ctx); 1632*8bdfc5daSXin Ji } 1633*8bdfc5daSXin Ji 1634*8bdfc5daSXin Ji static const struct drm_bridge_funcs anx7625_bridge_funcs = { 1635*8bdfc5daSXin Ji .attach = anx7625_bridge_attach, 1636*8bdfc5daSXin Ji .detach = anx7625_bridge_detach, 1637*8bdfc5daSXin Ji .disable = anx7625_bridge_disable, 1638*8bdfc5daSXin Ji .mode_valid = anx7625_bridge_mode_valid, 1639*8bdfc5daSXin Ji .mode_set = anx7625_bridge_mode_set, 1640*8bdfc5daSXin Ji .mode_fixup = anx7625_bridge_mode_fixup, 1641*8bdfc5daSXin Ji .enable = anx7625_bridge_enable, 1642*8bdfc5daSXin Ji .detect = anx7625_bridge_detect, 1643*8bdfc5daSXin Ji .get_edid = anx7625_bridge_get_edid, 1644*8bdfc5daSXin Ji }; 1645*8bdfc5daSXin Ji 1646*8bdfc5daSXin Ji static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 1647*8bdfc5daSXin Ji struct i2c_client *client) 1648*8bdfc5daSXin Ji { 1649*8bdfc5daSXin Ji ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 1650*8bdfc5daSXin Ji TX_P0_ADDR >> 1); 1651*8bdfc5daSXin Ji if (!ctx->i2c.tx_p0_client) 1652*8bdfc5daSXin Ji return -ENOMEM; 1653*8bdfc5daSXin Ji 1654*8bdfc5daSXin Ji ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 1655*8bdfc5daSXin Ji TX_P1_ADDR >> 1); 1656*8bdfc5daSXin Ji if (!ctx->i2c.tx_p1_client) 1657*8bdfc5daSXin Ji goto free_tx_p0; 1658*8bdfc5daSXin Ji 1659*8bdfc5daSXin Ji ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 1660*8bdfc5daSXin Ji TX_P2_ADDR >> 1); 1661*8bdfc5daSXin Ji if (!ctx->i2c.tx_p2_client) 1662*8bdfc5daSXin Ji goto free_tx_p1; 1663*8bdfc5daSXin Ji 1664*8bdfc5daSXin Ji ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 1665*8bdfc5daSXin Ji RX_P0_ADDR >> 1); 1666*8bdfc5daSXin Ji if (!ctx->i2c.rx_p0_client) 1667*8bdfc5daSXin Ji goto free_tx_p2; 1668*8bdfc5daSXin Ji 1669*8bdfc5daSXin Ji ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 1670*8bdfc5daSXin Ji RX_P1_ADDR >> 1); 1671*8bdfc5daSXin Ji if (!ctx->i2c.rx_p1_client) 1672*8bdfc5daSXin Ji goto free_rx_p0; 1673*8bdfc5daSXin Ji 1674*8bdfc5daSXin Ji ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 1675*8bdfc5daSXin Ji RX_P2_ADDR >> 1); 1676*8bdfc5daSXin Ji if (!ctx->i2c.rx_p2_client) 1677*8bdfc5daSXin Ji goto free_rx_p1; 1678*8bdfc5daSXin Ji 1679*8bdfc5daSXin Ji ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 1680*8bdfc5daSXin Ji TCPC_INTERFACE_ADDR >> 1); 1681*8bdfc5daSXin Ji if (!ctx->i2c.tcpc_client) 1682*8bdfc5daSXin Ji goto free_rx_p2; 1683*8bdfc5daSXin Ji 1684*8bdfc5daSXin Ji return 0; 1685*8bdfc5daSXin Ji 1686*8bdfc5daSXin Ji free_rx_p2: 1687*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 1688*8bdfc5daSXin Ji free_rx_p1: 1689*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 1690*8bdfc5daSXin Ji free_rx_p0: 1691*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 1692*8bdfc5daSXin Ji free_tx_p2: 1693*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 1694*8bdfc5daSXin Ji free_tx_p1: 1695*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 1696*8bdfc5daSXin Ji free_tx_p0: 1697*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 1698*8bdfc5daSXin Ji 1699*8bdfc5daSXin Ji return -ENOMEM; 1700*8bdfc5daSXin Ji } 1701*8bdfc5daSXin Ji 1702*8bdfc5daSXin Ji static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 1703*8bdfc5daSXin Ji { 1704*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 1705*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 1706*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 1707*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 1708*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 1709*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 1710*8bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tcpc_client); 1711*8bdfc5daSXin Ji } 1712*8bdfc5daSXin Ji 1713*8bdfc5daSXin Ji static int anx7625_i2c_probe(struct i2c_client *client, 1714*8bdfc5daSXin Ji const struct i2c_device_id *id) 1715*8bdfc5daSXin Ji { 1716*8bdfc5daSXin Ji struct anx7625_data *platform; 1717*8bdfc5daSXin Ji struct anx7625_platform_data *pdata; 1718*8bdfc5daSXin Ji int ret = 0; 1719*8bdfc5daSXin Ji struct device *dev = &client->dev; 1720*8bdfc5daSXin Ji 1721*8bdfc5daSXin Ji if (!i2c_check_functionality(client->adapter, 1722*8bdfc5daSXin Ji I2C_FUNC_SMBUS_I2C_BLOCK)) { 1723*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 1724*8bdfc5daSXin Ji return -ENODEV; 1725*8bdfc5daSXin Ji } 1726*8bdfc5daSXin Ji 1727*8bdfc5daSXin Ji platform = kzalloc(sizeof(*platform), GFP_KERNEL); 1728*8bdfc5daSXin Ji if (!platform) { 1729*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 1730*8bdfc5daSXin Ji return -ENOMEM; 1731*8bdfc5daSXin Ji } 1732*8bdfc5daSXin Ji 1733*8bdfc5daSXin Ji pdata = &platform->pdata; 1734*8bdfc5daSXin Ji 1735*8bdfc5daSXin Ji ret = anx7625_parse_dt(dev, pdata); 1736*8bdfc5daSXin Ji if (ret) { 1737*8bdfc5daSXin Ji if (ret != -EPROBE_DEFER) 1738*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 1739*8bdfc5daSXin Ji goto free_platform; 1740*8bdfc5daSXin Ji } 1741*8bdfc5daSXin Ji 1742*8bdfc5daSXin Ji platform->client = client; 1743*8bdfc5daSXin Ji i2c_set_clientdata(client, platform); 1744*8bdfc5daSXin Ji 1745*8bdfc5daSXin Ji anx7625_init_gpio(platform); 1746*8bdfc5daSXin Ji 1747*8bdfc5daSXin Ji atomic_set(&platform->power_status, 0); 1748*8bdfc5daSXin Ji 1749*8bdfc5daSXin Ji mutex_init(&platform->lock); 1750*8bdfc5daSXin Ji 1751*8bdfc5daSXin Ji platform->pdata.intp_irq = client->irq; 1752*8bdfc5daSXin Ji if (platform->pdata.intp_irq) { 1753*8bdfc5daSXin Ji INIT_WORK(&platform->work, anx7625_work_func); 1754*8bdfc5daSXin Ji platform->workqueue = create_workqueue("anx7625_work"); 1755*8bdfc5daSXin Ji if (!platform->workqueue) { 1756*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create work queue\n"); 1757*8bdfc5daSXin Ji ret = -ENOMEM; 1758*8bdfc5daSXin Ji goto free_platform; 1759*8bdfc5daSXin Ji } 1760*8bdfc5daSXin Ji 1761*8bdfc5daSXin Ji ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 1762*8bdfc5daSXin Ji NULL, anx7625_intr_hpd_isr, 1763*8bdfc5daSXin Ji IRQF_TRIGGER_FALLING | 1764*8bdfc5daSXin Ji IRQF_ONESHOT, 1765*8bdfc5daSXin Ji "anx7625-intp", platform); 1766*8bdfc5daSXin Ji if (ret) { 1767*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to request irq\n"); 1768*8bdfc5daSXin Ji goto free_wq; 1769*8bdfc5daSXin Ji } 1770*8bdfc5daSXin Ji } 1771*8bdfc5daSXin Ji 1772*8bdfc5daSXin Ji if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 1773*8bdfc5daSXin Ji ret = -ENOMEM; 1774*8bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 1775*8bdfc5daSXin Ji goto free_wq; 1776*8bdfc5daSXin Ji } 1777*8bdfc5daSXin Ji 1778*8bdfc5daSXin Ji if (platform->pdata.low_power_mode == 0) { 1779*8bdfc5daSXin Ji anx7625_disable_pd_protocol(platform); 1780*8bdfc5daSXin Ji atomic_set(&platform->power_status, 1); 1781*8bdfc5daSXin Ji } 1782*8bdfc5daSXin Ji 1783*8bdfc5daSXin Ji /* Add work function */ 1784*8bdfc5daSXin Ji if (platform->pdata.intp_irq) 1785*8bdfc5daSXin Ji queue_work(platform->workqueue, &platform->work); 1786*8bdfc5daSXin Ji 1787*8bdfc5daSXin Ji platform->bridge.funcs = &anx7625_bridge_funcs; 1788*8bdfc5daSXin Ji platform->bridge.of_node = client->dev.of_node; 1789*8bdfc5daSXin Ji platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 1790*8bdfc5daSXin Ji platform->bridge.type = DRM_MODE_CONNECTOR_eDP; 1791*8bdfc5daSXin Ji drm_bridge_add(&platform->bridge); 1792*8bdfc5daSXin Ji 1793*8bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 1794*8bdfc5daSXin Ji 1795*8bdfc5daSXin Ji return 0; 1796*8bdfc5daSXin Ji 1797*8bdfc5daSXin Ji free_wq: 1798*8bdfc5daSXin Ji if (platform->workqueue) 1799*8bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 1800*8bdfc5daSXin Ji 1801*8bdfc5daSXin Ji free_platform: 1802*8bdfc5daSXin Ji kfree(platform); 1803*8bdfc5daSXin Ji 1804*8bdfc5daSXin Ji return ret; 1805*8bdfc5daSXin Ji } 1806*8bdfc5daSXin Ji 1807*8bdfc5daSXin Ji static int anx7625_i2c_remove(struct i2c_client *client) 1808*8bdfc5daSXin Ji { 1809*8bdfc5daSXin Ji struct anx7625_data *platform = i2c_get_clientdata(client); 1810*8bdfc5daSXin Ji 1811*8bdfc5daSXin Ji drm_bridge_remove(&platform->bridge); 1812*8bdfc5daSXin Ji 1813*8bdfc5daSXin Ji if (platform->pdata.intp_irq) 1814*8bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 1815*8bdfc5daSXin Ji 1816*8bdfc5daSXin Ji anx7625_unregister_i2c_dummy_clients(platform); 1817*8bdfc5daSXin Ji 1818*8bdfc5daSXin Ji kfree(platform); 1819*8bdfc5daSXin Ji return 0; 1820*8bdfc5daSXin Ji } 1821*8bdfc5daSXin Ji 1822*8bdfc5daSXin Ji static const struct i2c_device_id anx7625_id[] = { 1823*8bdfc5daSXin Ji {"anx7625", 0}, 1824*8bdfc5daSXin Ji {} 1825*8bdfc5daSXin Ji }; 1826*8bdfc5daSXin Ji 1827*8bdfc5daSXin Ji MODULE_DEVICE_TABLE(i2c, anx7625_id); 1828*8bdfc5daSXin Ji 1829*8bdfc5daSXin Ji static const struct of_device_id anx_match_table[] = { 1830*8bdfc5daSXin Ji {.compatible = "analogix,anx7625",}, 1831*8bdfc5daSXin Ji {}, 1832*8bdfc5daSXin Ji }; 1833*8bdfc5daSXin Ji 1834*8bdfc5daSXin Ji static struct i2c_driver anx7625_driver = { 1835*8bdfc5daSXin Ji .driver = { 1836*8bdfc5daSXin Ji .name = "anx7625", 1837*8bdfc5daSXin Ji .of_match_table = anx_match_table, 1838*8bdfc5daSXin Ji }, 1839*8bdfc5daSXin Ji .probe = anx7625_i2c_probe, 1840*8bdfc5daSXin Ji .remove = anx7625_i2c_remove, 1841*8bdfc5daSXin Ji 1842*8bdfc5daSXin Ji .id_table = anx7625_id, 1843*8bdfc5daSXin Ji }; 1844*8bdfc5daSXin Ji 1845*8bdfc5daSXin Ji module_i2c_driver(anx7625_driver); 1846*8bdfc5daSXin Ji 1847*8bdfc5daSXin Ji MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 1848*8bdfc5daSXin Ji MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 1849*8bdfc5daSXin Ji MODULE_LICENSE("GPL v2"); 1850*8bdfc5daSXin Ji MODULE_VERSION(ANX7625_DRV_VERSION); 1851