18bdfc5daSXin Ji // SPDX-License-Identifier: GPL-2.0-only 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji #include <linux/gcd.h> 78bdfc5daSXin Ji #include <linux/gpio/consumer.h> 88bdfc5daSXin Ji #include <linux/i2c.h> 98bdfc5daSXin Ji #include <linux/interrupt.h> 108bdfc5daSXin Ji #include <linux/iopoll.h> 118bdfc5daSXin Ji #include <linux/kernel.h> 128bdfc5daSXin Ji #include <linux/module.h> 138bdfc5daSXin Ji #include <linux/mutex.h> 1460487584SPi-Hsun Shih #include <linux/pm_runtime.h> 156c744983SHsin-Yi Wang #include <linux/regulator/consumer.h> 168bdfc5daSXin Ji #include <linux/slab.h> 178bdfc5daSXin Ji #include <linux/types.h> 188bdfc5daSXin Ji #include <linux/workqueue.h> 198bdfc5daSXin Ji 208bdfc5daSXin Ji #include <linux/of_gpio.h> 218bdfc5daSXin Ji #include <linux/of_graph.h> 228bdfc5daSXin Ji #include <linux/of_platform.h> 238bdfc5daSXin Ji 248bdfc5daSXin Ji #include <drm/drm_atomic_helper.h> 258bdfc5daSXin Ji #include <drm/drm_bridge.h> 268bdfc5daSXin Ji #include <drm/drm_crtc_helper.h> 27*5b529e8dSThomas Zimmermann #include <drm/dp/drm_dp_helper.h> 288bdfc5daSXin Ji #include <drm/drm_edid.h> 29cd1637c7SXin Ji #include <drm/drm_hdcp.h> 308bdfc5daSXin Ji #include <drm/drm_mipi_dsi.h> 318bdfc5daSXin Ji #include <drm/drm_of.h> 328bdfc5daSXin Ji #include <drm/drm_panel.h> 338bdfc5daSXin Ji #include <drm/drm_print.h> 348bdfc5daSXin Ji #include <drm/drm_probe_helper.h> 358bdfc5daSXin Ji 36fd0310b6SXin Ji #include <media/v4l2-fwnode.h> 37566fef12SXin Ji #include <sound/hdmi-codec.h> 388bdfc5daSXin Ji #include <video/display_timing.h> 398bdfc5daSXin Ji 408bdfc5daSXin Ji #include "anx7625.h" 418bdfc5daSXin Ji 428bdfc5daSXin Ji /* 438bdfc5daSXin Ji * There is a sync issue while access I2C register between AP(CPU) and 448bdfc5daSXin Ji * internal firmware(OCM), to avoid the race condition, AP should access 458bdfc5daSXin Ji * the reserved slave address before slave address occurs changes. 468bdfc5daSXin Ji */ 478bdfc5daSXin Ji static int i2c_access_workaround(struct anx7625_data *ctx, 488bdfc5daSXin Ji struct i2c_client *client) 498bdfc5daSXin Ji { 508bdfc5daSXin Ji u8 offset; 518bdfc5daSXin Ji struct device *dev = &client->dev; 528bdfc5daSXin Ji int ret; 538bdfc5daSXin Ji 548bdfc5daSXin Ji if (client == ctx->last_client) 558bdfc5daSXin Ji return 0; 568bdfc5daSXin Ji 578bdfc5daSXin Ji ctx->last_client = client; 588bdfc5daSXin Ji 598bdfc5daSXin Ji if (client == ctx->i2c.tcpc_client) 608bdfc5daSXin Ji offset = RSVD_00_ADDR; 618bdfc5daSXin Ji else if (client == ctx->i2c.tx_p0_client) 628bdfc5daSXin Ji offset = RSVD_D1_ADDR; 638bdfc5daSXin Ji else if (client == ctx->i2c.tx_p1_client) 648bdfc5daSXin Ji offset = RSVD_60_ADDR; 658bdfc5daSXin Ji else if (client == ctx->i2c.rx_p0_client) 668bdfc5daSXin Ji offset = RSVD_39_ADDR; 678bdfc5daSXin Ji else if (client == ctx->i2c.rx_p1_client) 688bdfc5daSXin Ji offset = RSVD_7F_ADDR; 698bdfc5daSXin Ji else 708bdfc5daSXin Ji offset = RSVD_00_ADDR; 718bdfc5daSXin Ji 728bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, offset, 0x00); 738bdfc5daSXin Ji if (ret < 0) 748bdfc5daSXin Ji DRM_DEV_ERROR(dev, 758bdfc5daSXin Ji "fail to access i2c id=%x\n:%x", 768bdfc5daSXin Ji client->addr, offset); 778bdfc5daSXin Ji 788bdfc5daSXin Ji return ret; 798bdfc5daSXin Ji } 808bdfc5daSXin Ji 818bdfc5daSXin Ji static int anx7625_reg_read(struct anx7625_data *ctx, 828bdfc5daSXin Ji struct i2c_client *client, u8 reg_addr) 838bdfc5daSXin Ji { 848bdfc5daSXin Ji int ret; 858bdfc5daSXin Ji struct device *dev = &client->dev; 868bdfc5daSXin Ji 878bdfc5daSXin Ji i2c_access_workaround(ctx, client); 888bdfc5daSXin Ji 898bdfc5daSXin Ji ret = i2c_smbus_read_byte_data(client, reg_addr); 908bdfc5daSXin Ji if (ret < 0) 918bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 928bdfc5daSXin Ji client->addr, reg_addr); 938bdfc5daSXin Ji 948bdfc5daSXin Ji return ret; 958bdfc5daSXin Ji } 968bdfc5daSXin Ji 978bdfc5daSXin Ji static int anx7625_reg_block_read(struct anx7625_data *ctx, 988bdfc5daSXin Ji struct i2c_client *client, 998bdfc5daSXin Ji u8 reg_addr, u8 len, u8 *buf) 1008bdfc5daSXin Ji { 1018bdfc5daSXin Ji int ret; 1028bdfc5daSXin Ji struct device *dev = &client->dev; 1038bdfc5daSXin Ji 1048bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1058bdfc5daSXin Ji 1068bdfc5daSXin Ji ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 1078bdfc5daSXin Ji if (ret < 0) 1088bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 1098bdfc5daSXin Ji client->addr, reg_addr); 1108bdfc5daSXin Ji 1118bdfc5daSXin Ji return ret; 1128bdfc5daSXin Ji } 1138bdfc5daSXin Ji 1148bdfc5daSXin Ji static int anx7625_reg_write(struct anx7625_data *ctx, 1158bdfc5daSXin Ji struct i2c_client *client, 1168bdfc5daSXin Ji u8 reg_addr, u8 reg_val) 1178bdfc5daSXin Ji { 1188bdfc5daSXin Ji int ret; 1198bdfc5daSXin Ji struct device *dev = &client->dev; 1208bdfc5daSXin Ji 1218bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1228bdfc5daSXin Ji 1238bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 1248bdfc5daSXin Ji 1258bdfc5daSXin Ji if (ret < 0) 1268bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 1278bdfc5daSXin Ji client->addr, reg_addr); 1288bdfc5daSXin Ji 1298bdfc5daSXin Ji return ret; 1308bdfc5daSXin Ji } 1318bdfc5daSXin Ji 1328bdfc5daSXin Ji static int anx7625_write_or(struct anx7625_data *ctx, 1338bdfc5daSXin Ji struct i2c_client *client, 1348bdfc5daSXin Ji u8 offset, u8 mask) 1358bdfc5daSXin Ji { 1368bdfc5daSXin Ji int val; 1378bdfc5daSXin Ji 1388bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1398bdfc5daSXin Ji if (val < 0) 1408bdfc5daSXin Ji return val; 1418bdfc5daSXin Ji 1428bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val | (mask))); 1438bdfc5daSXin Ji } 1448bdfc5daSXin Ji 1458bdfc5daSXin Ji static int anx7625_write_and(struct anx7625_data *ctx, 1468bdfc5daSXin Ji struct i2c_client *client, 1478bdfc5daSXin Ji u8 offset, u8 mask) 1488bdfc5daSXin Ji { 1498bdfc5daSXin Ji int val; 1508bdfc5daSXin Ji 1518bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1528bdfc5daSXin Ji if (val < 0) 1538bdfc5daSXin Ji return val; 1548bdfc5daSXin Ji 1558bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val & (mask))); 1568bdfc5daSXin Ji } 1578bdfc5daSXin Ji 158566fef12SXin Ji static int anx7625_write_and_or(struct anx7625_data *ctx, 159566fef12SXin Ji struct i2c_client *client, 160566fef12SXin Ji u8 offset, u8 and_mask, u8 or_mask) 161566fef12SXin Ji { 162566fef12SXin Ji int val; 163566fef12SXin Ji 164566fef12SXin Ji val = anx7625_reg_read(ctx, client, offset); 165566fef12SXin Ji if (val < 0) 166566fef12SXin Ji return val; 167566fef12SXin Ji 168566fef12SXin Ji return anx7625_reg_write(ctx, client, 169566fef12SXin Ji offset, (val & and_mask) | (or_mask)); 170566fef12SXin Ji } 171566fef12SXin Ji 172fd0310b6SXin Ji static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 1738bdfc5daSXin Ji { 174fd0310b6SXin Ji int i, ret; 1758bdfc5daSXin Ji 176fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 177fd0310b6SXin Ji AUDIO_CONTROL_REGISTER, 0x80); 178fd0310b6SXin Ji for (i = 0; i < 13; i++) 179fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 180fd0310b6SXin Ji VIDEO_BIT_MATRIX_12 + i, 181fd0310b6SXin Ji 0x18 + i); 1828bdfc5daSXin Ji 183fd0310b6SXin Ji return ret; 1848bdfc5daSXin Ji } 1858bdfc5daSXin Ji 1868bdfc5daSXin Ji static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 1878bdfc5daSXin Ji { 1888bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 1898bdfc5daSXin Ji } 1908bdfc5daSXin Ji 1918bdfc5daSXin Ji static int wait_aux_op_finish(struct anx7625_data *ctx) 1928bdfc5daSXin Ji { 1938bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1948bdfc5daSXin Ji int val; 1958bdfc5daSXin Ji int ret; 1968bdfc5daSXin Ji 1978bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 1988bdfc5daSXin Ji ctx, val, 1998bdfc5daSXin Ji (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 2008bdfc5daSXin Ji 2000, 2018bdfc5daSXin Ji 2000 * 150); 2028bdfc5daSXin Ji if (ret) { 2038bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux operation fail!\n"); 2048bdfc5daSXin Ji return -EIO; 2058bdfc5daSXin Ji } 2068bdfc5daSXin Ji 2078bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 2088bdfc5daSXin Ji AP_AUX_CTRL_STATUS); 2098bdfc5daSXin Ji if (val < 0 || (val & 0x0F)) { 2108bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux status %02x\n", val); 2119a7e49bdSXin Ji return -EIO; 2128bdfc5daSXin Ji } 2138bdfc5daSXin Ji 2149a7e49bdSXin Ji return 0; 2158bdfc5daSXin Ji } 2168bdfc5daSXin Ji 217cd1637c7SXin Ji static int anx7625_aux_dpcd_read(struct anx7625_data *ctx, 218cd1637c7SXin Ji u32 address, u8 len, u8 *buf) 219cd1637c7SXin Ji { 220cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 221cd1637c7SXin Ji int ret; 222cd1637c7SXin Ji u8 addrh, addrm, addrl; 223cd1637c7SXin Ji u8 cmd; 224cd1637c7SXin Ji 225cd1637c7SXin Ji if (len > MAX_DPCD_BUFFER_SIZE) { 226cd1637c7SXin Ji dev_err(dev, "exceed aux buffer len.\n"); 227cd1637c7SXin Ji return -EINVAL; 228cd1637c7SXin Ji } 229cd1637c7SXin Ji 230cd1637c7SXin Ji addrl = address & 0xFF; 231cd1637c7SXin Ji addrm = (address >> 8) & 0xFF; 232cd1637c7SXin Ji addrh = (address >> 16) & 0xFF; 233cd1637c7SXin Ji 234cd1637c7SXin Ji cmd = DPCD_CMD(len, DPCD_READ); 235cd1637c7SXin Ji cmd = ((len - 1) << 4) | 0x09; 236cd1637c7SXin Ji 237cd1637c7SXin Ji /* Set command and length */ 238cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 239cd1637c7SXin Ji AP_AUX_COMMAND, cmd); 240cd1637c7SXin Ji 241cd1637c7SXin Ji /* Set aux access address */ 242cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 243cd1637c7SXin Ji AP_AUX_ADDR_7_0, addrl); 244cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 245cd1637c7SXin Ji AP_AUX_ADDR_15_8, addrm); 246cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 247cd1637c7SXin Ji AP_AUX_ADDR_19_16, addrh); 248cd1637c7SXin Ji 249cd1637c7SXin Ji /* Enable aux access */ 250cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 251cd1637c7SXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 252cd1637c7SXin Ji 253cd1637c7SXin Ji if (ret < 0) { 254cd1637c7SXin Ji dev_err(dev, "cannot access aux related register.\n"); 255cd1637c7SXin Ji return -EIO; 256cd1637c7SXin Ji } 257cd1637c7SXin Ji 258cd1637c7SXin Ji usleep_range(2000, 2100); 259cd1637c7SXin Ji 260cd1637c7SXin Ji ret = wait_aux_op_finish(ctx); 261cd1637c7SXin Ji if (ret) { 262cd1637c7SXin Ji dev_err(dev, "aux IO error: wait aux op finish.\n"); 263cd1637c7SXin Ji return ret; 264cd1637c7SXin Ji } 265cd1637c7SXin Ji 266cd1637c7SXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 267cd1637c7SXin Ji AP_AUX_BUFF_START, len, buf); 268cd1637c7SXin Ji if (ret < 0) { 269cd1637c7SXin Ji dev_err(dev, "read dpcd register failed\n"); 270cd1637c7SXin Ji return -EIO; 271cd1637c7SXin Ji } 272cd1637c7SXin Ji 273cd1637c7SXin Ji return 0; 274cd1637c7SXin Ji } 275cd1637c7SXin Ji 2768bdfc5daSXin Ji static int anx7625_video_mute_control(struct anx7625_data *ctx, 2778bdfc5daSXin Ji u8 status) 2788bdfc5daSXin Ji { 2798bdfc5daSXin Ji int ret; 2808bdfc5daSXin Ji 2818bdfc5daSXin Ji if (status) { 2828bdfc5daSXin Ji /* Set mute on flag */ 2838bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2848bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_MUTE); 2858bdfc5daSXin Ji /* Clear mipi RX en */ 2868bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 2878bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 2888bdfc5daSXin Ji } else { 2898bdfc5daSXin Ji /* Mute off flag */ 2908bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 2918bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 2928bdfc5daSXin Ji /* Set MIPI RX EN */ 2938bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2948bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 2958bdfc5daSXin Ji } 2968bdfc5daSXin Ji 2978bdfc5daSXin Ji return ret; 2988bdfc5daSXin Ji } 2998bdfc5daSXin Ji 3008bdfc5daSXin Ji /* Reduction of fraction a/b */ 3018bdfc5daSXin Ji static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 3028bdfc5daSXin Ji { 3038bdfc5daSXin Ji unsigned long gcd_num; 3048bdfc5daSXin Ji unsigned long tmp_a, tmp_b; 3058bdfc5daSXin Ji u32 i = 1; 3068bdfc5daSXin Ji 3078bdfc5daSXin Ji gcd_num = gcd(*a, *b); 3088bdfc5daSXin Ji *a /= gcd_num; 3098bdfc5daSXin Ji *b /= gcd_num; 3108bdfc5daSXin Ji 3118bdfc5daSXin Ji tmp_a = *a; 3128bdfc5daSXin Ji tmp_b = *b; 3138bdfc5daSXin Ji 3148bdfc5daSXin Ji while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 3158bdfc5daSXin Ji i++; 3168bdfc5daSXin Ji *a = tmp_a / i; 3178bdfc5daSXin Ji *b = tmp_b / i; 3188bdfc5daSXin Ji } 3198bdfc5daSXin Ji 3208bdfc5daSXin Ji /* 3218bdfc5daSXin Ji * In the end, make a, b larger to have higher ODFC PLL 3228bdfc5daSXin Ji * output frequency accuracy 3238bdfc5daSXin Ji */ 3248bdfc5daSXin Ji while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 3258bdfc5daSXin Ji *a <<= 1; 3268bdfc5daSXin Ji *b <<= 1; 3278bdfc5daSXin Ji } 3288bdfc5daSXin Ji 3298bdfc5daSXin Ji *a >>= 1; 3308bdfc5daSXin Ji *b >>= 1; 3318bdfc5daSXin Ji } 3328bdfc5daSXin Ji 3338bdfc5daSXin Ji static int anx7625_calculate_m_n(u32 pixelclock, 3348bdfc5daSXin Ji unsigned long *m, 3358bdfc5daSXin Ji unsigned long *n, 3368bdfc5daSXin Ji u8 *post_divider) 3378bdfc5daSXin Ji { 3388bdfc5daSXin Ji if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 3398bdfc5daSXin Ji /* Pixel clock frequency is too high */ 3408bdfc5daSXin Ji DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 3418bdfc5daSXin Ji pixelclock, 3428bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 3438bdfc5daSXin Ji return -EINVAL; 3448bdfc5daSXin Ji } 3458bdfc5daSXin Ji 3468bdfc5daSXin Ji if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 3478bdfc5daSXin Ji /* Pixel clock frequency is too low */ 3488bdfc5daSXin Ji DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 3498bdfc5daSXin Ji pixelclock, 3508bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 3518bdfc5daSXin Ji return -EINVAL; 3528bdfc5daSXin Ji } 3538bdfc5daSXin Ji 3548bdfc5daSXin Ji for (*post_divider = 1; 3558bdfc5daSXin Ji pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 3568bdfc5daSXin Ji *post_divider += 1; 3578bdfc5daSXin Ji 3588bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3598bdfc5daSXin Ji for (*post_divider = 1; 3608bdfc5daSXin Ji (pixelclock < 3618bdfc5daSXin Ji (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 3628bdfc5daSXin Ji *post_divider += 1; 3638bdfc5daSXin Ji 3648bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3658bdfc5daSXin Ji DRM_ERROR("cannot find property post_divider(%d)\n", 3668bdfc5daSXin Ji *post_divider); 3678bdfc5daSXin Ji return -EDOM; 3688bdfc5daSXin Ji } 3698bdfc5daSXin Ji } 3708bdfc5daSXin Ji 3718bdfc5daSXin Ji /* Patch to improve the accuracy */ 3728bdfc5daSXin Ji if (*post_divider == 7) { 3738bdfc5daSXin Ji /* 27,000,000 is not divisible by 7 */ 3748bdfc5daSXin Ji *post_divider = 8; 3758bdfc5daSXin Ji } else if (*post_divider == 11) { 3768bdfc5daSXin Ji /* 27,000,000 is not divisible by 11 */ 3778bdfc5daSXin Ji *post_divider = 12; 3788bdfc5daSXin Ji } else if ((*post_divider == 13) || (*post_divider == 14)) { 3798bdfc5daSXin Ji /* 27,000,000 is not divisible by 13 or 14 */ 3808bdfc5daSXin Ji *post_divider = 15; 3818bdfc5daSXin Ji } 3828bdfc5daSXin Ji 3838bdfc5daSXin Ji if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 3848bdfc5daSXin Ji DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 3858bdfc5daSXin Ji pixelclock * (*post_divider), 3868bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX); 3878bdfc5daSXin Ji return -EDOM; 3888bdfc5daSXin Ji } 3898bdfc5daSXin Ji 3908bdfc5daSXin Ji *m = pixelclock; 3918bdfc5daSXin Ji *n = XTAL_FRQ / (*post_divider); 3928bdfc5daSXin Ji 3938bdfc5daSXin Ji anx7625_reduction_of_a_fraction(m, n); 3948bdfc5daSXin Ji 3958bdfc5daSXin Ji return 0; 3968bdfc5daSXin Ji } 3978bdfc5daSXin Ji 3988bdfc5daSXin Ji static int anx7625_odfc_config(struct anx7625_data *ctx, 3998bdfc5daSXin Ji u8 post_divider) 4008bdfc5daSXin Ji { 4018bdfc5daSXin Ji int ret; 4028bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4038bdfc5daSXin Ji 4048bdfc5daSXin Ji /* Config input reference clock frequency 27MHz/19.2MHz */ 4058bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 4068bdfc5daSXin Ji ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 4078bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 4088bdfc5daSXin Ji (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 4098bdfc5daSXin Ji /* Post divider */ 4108bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4118bdfc5daSXin Ji MIPI_DIGITAL_PLL_8, 0x0f); 4128bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 4138bdfc5daSXin Ji post_divider << 4); 4148bdfc5daSXin Ji 4158bdfc5daSXin Ji /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 4168bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4178bdfc5daSXin Ji ~MIPI_PLL_VCO_TUNE_REG_VAL); 4188bdfc5daSXin Ji 4198bdfc5daSXin Ji /* Reset ODFC PLL */ 4208bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4218bdfc5daSXin Ji ~MIPI_PLL_RESET_N); 4228bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4238bdfc5daSXin Ji MIPI_PLL_RESET_N); 4248bdfc5daSXin Ji 4258bdfc5daSXin Ji if (ret < 0) 4268bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error.\n"); 4278bdfc5daSXin Ji 4288bdfc5daSXin Ji return ret; 4298bdfc5daSXin Ji } 4308bdfc5daSXin Ji 4317d066dc7SXin Ji /* 4327d066dc7SXin Ji * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 4337d066dc7SXin Ji * anx7625 defined K ratio for matching MIPI input video clock and 4347d066dc7SXin Ji * DP output video clock. Increase K value can match bigger video data 4357d066dc7SXin Ji * variation. IVO panel has small variation than DP CTS spec, need 4367d066dc7SXin Ji * decrease the K value. 4377d066dc7SXin Ji */ 4387d066dc7SXin Ji static int anx7625_set_k_value(struct anx7625_data *ctx) 4397d066dc7SXin Ji { 4407d066dc7SXin Ji struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 4417d066dc7SXin Ji 4427d066dc7SXin Ji if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 4437d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4447d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3B); 4457d066dc7SXin Ji 4467d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4477d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3D); 4487d066dc7SXin Ji } 4497d066dc7SXin Ji 4508bdfc5daSXin Ji static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 4518bdfc5daSXin Ji { 4528bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4538bdfc5daSXin Ji unsigned long m, n; 4548bdfc5daSXin Ji u16 htotal; 4558bdfc5daSXin Ji int ret; 4568bdfc5daSXin Ji u8 post_divider = 0; 4578bdfc5daSXin Ji 4588bdfc5daSXin Ji ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 4598bdfc5daSXin Ji &m, &n, &post_divider); 4608bdfc5daSXin Ji 4618bdfc5daSXin Ji if (ret) { 4628bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 4638bdfc5daSXin Ji return ret; 4648bdfc5daSXin Ji } 4658bdfc5daSXin Ji 4668bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 4678bdfc5daSXin Ji m, n, post_divider); 4688bdfc5daSXin Ji 4698bdfc5daSXin Ji /* Configure pixel clock */ 4708bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 4718bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) & 0xFF); 4728bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 4738bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) >> 8); 4748bdfc5daSXin Ji /* Lane count */ 4758bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4768bdfc5daSXin Ji MIPI_LANE_CTRL_0, 0xfc); 4778bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 478fd0310b6SXin Ji MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 4798bdfc5daSXin Ji 4808bdfc5daSXin Ji /* Htotal */ 4818bdfc5daSXin Ji htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 4828bdfc5daSXin Ji ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 4838bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4848bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 4858bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4868bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 4878bdfc5daSXin Ji /* Hactive */ 4888bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4898bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 4908bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4918bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 4928bdfc5daSXin Ji /* HFP */ 4938bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4948bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 4958bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4968bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_H, 4978bdfc5daSXin Ji ctx->dt.hfront_porch.min >> 8); 4988bdfc5daSXin Ji /* HWS */ 4998bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5008bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 5018bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5028bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 5038bdfc5daSXin Ji /* HBP */ 5048bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5058bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 5068bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5078bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 5088bdfc5daSXin Ji /* Vactive */ 5098bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 5108bdfc5daSXin Ji ctx->dt.vactive.min); 5118bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 5128bdfc5daSXin Ji ctx->dt.vactive.min >> 8); 5138bdfc5daSXin Ji /* VFP */ 5148bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5158bdfc5daSXin Ji VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 5168bdfc5daSXin Ji /* VWS */ 5178bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5188bdfc5daSXin Ji VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 5198bdfc5daSXin Ji /* VBP */ 5208bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5218bdfc5daSXin Ji VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 5228bdfc5daSXin Ji /* M value */ 5238bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5248bdfc5daSXin Ji MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 5258bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5268bdfc5daSXin Ji MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 5278bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5288bdfc5daSXin Ji MIPI_PLL_M_NUM_7_0, (m & 0xff)); 5298bdfc5daSXin Ji /* N value */ 5308bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5318bdfc5daSXin Ji MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 5328bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5338bdfc5daSXin Ji MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 5348bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 5358bdfc5daSXin Ji (n & 0xff)); 5367d066dc7SXin Ji 5377d066dc7SXin Ji anx7625_set_k_value(ctx); 5388bdfc5daSXin Ji 5398bdfc5daSXin Ji ret |= anx7625_odfc_config(ctx, post_divider - 1); 5408bdfc5daSXin Ji 5418bdfc5daSXin Ji if (ret < 0) 5428bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 5438bdfc5daSXin Ji 5448bdfc5daSXin Ji return ret; 5458bdfc5daSXin Ji } 5468bdfc5daSXin Ji 5478bdfc5daSXin Ji static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 5488bdfc5daSXin Ji { 5498bdfc5daSXin Ji int val; 5508bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5518bdfc5daSXin Ji 5528bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5538bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 5548bdfc5daSXin Ji if (val < 0) { 5558bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 5568bdfc5daSXin Ji return -EIO; 5578bdfc5daSXin Ji } 5588bdfc5daSXin Ji 5598bdfc5daSXin Ji val |= (1 << MIPI_SWAP_CH3); 5608bdfc5daSXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 5618bdfc5daSXin Ji } 5628bdfc5daSXin Ji 5638bdfc5daSXin Ji static int anx7625_api_dsi_config(struct anx7625_data *ctx) 5648bdfc5daSXin Ji 5658bdfc5daSXin Ji { 5668bdfc5daSXin Ji int val, ret; 5678bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5688bdfc5daSXin Ji 5698bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5708bdfc5daSXin Ji ret = anx7625_swap_dsi_lane3(ctx); 5718bdfc5daSXin Ji if (ret < 0) { 5728bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 5738bdfc5daSXin Ji return ret; 5748bdfc5daSXin Ji } 5758bdfc5daSXin Ji 5768bdfc5daSXin Ji /* DSI clock settings */ 5778bdfc5daSXin Ji val = (0 << MIPI_HS_PWD_CLK) | 5788bdfc5daSXin Ji (0 << MIPI_HS_RT_CLK) | 5798bdfc5daSXin Ji (0 << MIPI_PD_CLK) | 5808bdfc5daSXin Ji (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 5818bdfc5daSXin Ji (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 5828bdfc5daSXin Ji (0 << MIPI_CLK_DET_DET_BYPASS) | 5838bdfc5daSXin Ji (0 << MIPI_CLK_MISS_CTRL) | 5848bdfc5daSXin Ji (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 5858bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5868bdfc5daSXin Ji MIPI_PHY_CONTROL_3, val); 5878bdfc5daSXin Ji 5888bdfc5daSXin Ji /* 5898bdfc5daSXin Ji * Decreased HS prepare timing delay from 160ns to 80ns work with 5908bdfc5daSXin Ji * a) Dragon board 810 series (Qualcomm AP) 5918bdfc5daSXin Ji * b) Moving Pixel DSI source (PG3A pattern generator + 5928bdfc5daSXin Ji * P332 D-PHY Probe) default D-PHY timing 5938bdfc5daSXin Ji * 5ns/step 5948bdfc5daSXin Ji */ 5958bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5968bdfc5daSXin Ji MIPI_TIME_HS_PRPR, 0x10); 5978bdfc5daSXin Ji 5988bdfc5daSXin Ji /* Enable DSI mode*/ 5998bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 6008bdfc5daSXin Ji SELECT_DSI << MIPI_DPI_SELECT); 6018bdfc5daSXin Ji 6028bdfc5daSXin Ji ret |= anx7625_dsi_video_timing_config(ctx); 6038bdfc5daSXin Ji if (ret < 0) { 6048bdfc5daSXin Ji DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 6058bdfc5daSXin Ji return ret; 6068bdfc5daSXin Ji } 6078bdfc5daSXin Ji 6088bdfc5daSXin Ji /* Toggle m, n ready */ 6098bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 6108bdfc5daSXin Ji ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 6118bdfc5daSXin Ji usleep_range(1000, 1100); 6128bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 6138bdfc5daSXin Ji MIPI_M_NUM_READY | MIPI_N_NUM_READY); 6148bdfc5daSXin Ji 6158bdfc5daSXin Ji /* Configure integer stable register */ 6168bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6178bdfc5daSXin Ji MIPI_VIDEO_STABLE_CNT, 0x02); 6188bdfc5daSXin Ji /* Power on MIPI RX */ 6198bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6208bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x00); 6218bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6228bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x80); 6238bdfc5daSXin Ji 6248bdfc5daSXin Ji if (ret < 0) 6258bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 6268bdfc5daSXin Ji 6278bdfc5daSXin Ji return ret; 6288bdfc5daSXin Ji } 6298bdfc5daSXin Ji 6308bdfc5daSXin Ji static int anx7625_dsi_config(struct anx7625_data *ctx) 6318bdfc5daSXin Ji { 6328bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6338bdfc5daSXin Ji int ret; 6348bdfc5daSXin Ji 6358bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 6368bdfc5daSXin Ji 6378bdfc5daSXin Ji /* DSC disable */ 6388bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 6398bdfc5daSXin Ji R_DSC_CTRL_0, ~DSC_EN); 6408bdfc5daSXin Ji 6418bdfc5daSXin Ji ret |= anx7625_api_dsi_config(ctx); 6428bdfc5daSXin Ji 6438bdfc5daSXin Ji if (ret < 0) { 6448bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 6458bdfc5daSXin Ji return ret; 6468bdfc5daSXin Ji } 6478bdfc5daSXin Ji 6488bdfc5daSXin Ji /* Set MIPI RX EN */ 6498bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 6508bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 6518bdfc5daSXin Ji /* Clear mute flag */ 6528bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 6538bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 6548bdfc5daSXin Ji if (ret < 0) 6558bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 6568bdfc5daSXin Ji else 6578bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 6588bdfc5daSXin Ji 6598bdfc5daSXin Ji return ret; 6608bdfc5daSXin Ji } 6618bdfc5daSXin Ji 662fd0310b6SXin Ji static int anx7625_api_dpi_config(struct anx7625_data *ctx) 663fd0310b6SXin Ji { 664fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 665fd0310b6SXin Ji u16 freq = ctx->dt.pixelclock.min / 1000; 666fd0310b6SXin Ji int ret; 667fd0310b6SXin Ji 668fd0310b6SXin Ji /* configure pixel clock */ 669fd0310b6SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 670fd0310b6SXin Ji PIXEL_CLOCK_L, freq & 0xFF); 671fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 672fd0310b6SXin Ji PIXEL_CLOCK_H, (freq >> 8)); 673fd0310b6SXin Ji 674fd0310b6SXin Ji /* set DPI mode */ 675fd0310b6SXin Ji /* set to DPI PLL module sel */ 676fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 677fd0310b6SXin Ji MIPI_DIGITAL_PLL_9, 0x20); 678fd0310b6SXin Ji /* power down MIPI */ 679fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 680fd0310b6SXin Ji MIPI_LANE_CTRL_10, 0x08); 681fd0310b6SXin Ji /* enable DPI mode */ 682fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 683fd0310b6SXin Ji MIPI_DIGITAL_PLL_18, 0x1C); 684fd0310b6SXin Ji /* set first edge */ 685fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 686fd0310b6SXin Ji VIDEO_CONTROL_0, 0x06); 687fd0310b6SXin Ji if (ret < 0) 688fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 689fd0310b6SXin Ji 690fd0310b6SXin Ji return ret; 691fd0310b6SXin Ji } 692fd0310b6SXin Ji 693fd0310b6SXin Ji static int anx7625_dpi_config(struct anx7625_data *ctx) 694fd0310b6SXin Ji { 695fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 696fd0310b6SXin Ji int ret; 697fd0310b6SXin Ji 698fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 699fd0310b6SXin Ji 700fd0310b6SXin Ji /* DSC disable */ 701fd0310b6SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 702fd0310b6SXin Ji R_DSC_CTRL_0, ~DSC_EN); 703fd0310b6SXin Ji if (ret < 0) { 704fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 705fd0310b6SXin Ji return ret; 706fd0310b6SXin Ji } 707fd0310b6SXin Ji 708fd0310b6SXin Ji ret = anx7625_config_bit_matrix(ctx); 709fd0310b6SXin Ji if (ret < 0) { 710fd0310b6SXin Ji DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 711fd0310b6SXin Ji return ret; 712fd0310b6SXin Ji } 713fd0310b6SXin Ji 714fd0310b6SXin Ji ret = anx7625_api_dpi_config(ctx); 715fd0310b6SXin Ji if (ret < 0) { 716fd0310b6SXin Ji DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 717fd0310b6SXin Ji return ret; 718fd0310b6SXin Ji } 719fd0310b6SXin Ji 720fd0310b6SXin Ji /* set MIPI RX EN */ 721fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 722fd0310b6SXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 723fd0310b6SXin Ji /* clear mute flag */ 724fd0310b6SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 725fd0310b6SXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 726fd0310b6SXin Ji if (ret < 0) 727fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 728fd0310b6SXin Ji 729fd0310b6SXin Ji return ret; 730fd0310b6SXin Ji } 731fd0310b6SXin Ji 732cd1637c7SXin Ji static int anx7625_read_flash_status(struct anx7625_data *ctx) 733cd1637c7SXin Ji { 734cd1637c7SXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 735cd1637c7SXin Ji } 736cd1637c7SXin Ji 737cd1637c7SXin Ji static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 738cd1637c7SXin Ji { 739cd1637c7SXin Ji int ret, val; 740cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 741cd1637c7SXin Ji u8 ident[FLASH_BUF_LEN]; 742cd1637c7SXin Ji 743cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 744cd1637c7SXin Ji FLASH_ADDR_HIGH, 0x91); 745cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 746cd1637c7SXin Ji FLASH_ADDR_LOW, 0xA0); 747cd1637c7SXin Ji if (ret < 0) { 748cd1637c7SXin Ji dev_err(dev, "IO error : set key flash address.\n"); 749cd1637c7SXin Ji return ret; 750cd1637c7SXin Ji } 751cd1637c7SXin Ji 752cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 753cd1637c7SXin Ji FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 754cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 755cd1637c7SXin Ji FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 756cd1637c7SXin Ji if (ret < 0) { 757cd1637c7SXin Ji dev_err(dev, "IO error : set key flash len.\n"); 758cd1637c7SXin Ji return ret; 759cd1637c7SXin Ji } 760cd1637c7SXin Ji 761cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 762cd1637c7SXin Ji R_FLASH_RW_CTRL, FLASH_READ); 763cd1637c7SXin Ji ret |= readx_poll_timeout(anx7625_read_flash_status, 764cd1637c7SXin Ji ctx, val, 765cd1637c7SXin Ji ((val & FLASH_DONE) || (val < 0)), 766cd1637c7SXin Ji 2000, 767cd1637c7SXin Ji 2000 * 150); 768cd1637c7SXin Ji if (ret) { 769cd1637c7SXin Ji dev_err(dev, "flash read access fail!\n"); 770cd1637c7SXin Ji return -EIO; 771cd1637c7SXin Ji } 772cd1637c7SXin Ji 773cd1637c7SXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 774cd1637c7SXin Ji FLASH_BUF_BASE_ADDR, 775cd1637c7SXin Ji FLASH_BUF_LEN, ident); 776cd1637c7SXin Ji if (ret < 0) { 777cd1637c7SXin Ji dev_err(dev, "read flash data fail!\n"); 778cd1637c7SXin Ji return -EIO; 779cd1637c7SXin Ji } 780cd1637c7SXin Ji 781cd1637c7SXin Ji if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 782cd1637c7SXin Ji return -EINVAL; 783cd1637c7SXin Ji 784cd1637c7SXin Ji return 0; 785cd1637c7SXin Ji } 786cd1637c7SXin Ji 787cd1637c7SXin Ji static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 788cd1637c7SXin Ji { 789cd1637c7SXin Ji int ret; 790cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 791cd1637c7SXin Ji 792cd1637c7SXin Ji /* Select HDCP 1.4 KEY */ 793cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 794cd1637c7SXin Ji R_BOOT_RETRY, 0x12); 795cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 796cd1637c7SXin Ji FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 797cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 798cd1637c7SXin Ji FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 799cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 800cd1637c7SXin Ji R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 801cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 802cd1637c7SXin Ji R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 803cd1637c7SXin Ji 804cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 805cd1637c7SXin Ji R_RAM_ADDR_H, 0); 806cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 807cd1637c7SXin Ji R_RAM_ADDR_L, 0); 808cd1637c7SXin Ji /* Enable HDCP 1.4 KEY load */ 809cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 810cd1637c7SXin Ji R_RAM_CTRL, DECRYPT_EN | LOAD_START); 811cd1637c7SXin Ji dev_dbg(dev, "load HDCP 1.4 key done\n"); 812cd1637c7SXin Ji return ret; 813cd1637c7SXin Ji } 814cd1637c7SXin Ji 815cd1637c7SXin Ji static int anx7625_hdcp_disable(struct anx7625_data *ctx) 816cd1637c7SXin Ji { 817cd1637c7SXin Ji int ret; 818cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 819cd1637c7SXin Ji 820cd1637c7SXin Ji dev_dbg(dev, "disable HDCP 1.4\n"); 821cd1637c7SXin Ji 822cd1637c7SXin Ji /* Disable HDCP */ 823cd1637c7SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 824cd1637c7SXin Ji /* Try auth flag */ 825cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 826cd1637c7SXin Ji /* Interrupt for DRM */ 827cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 828cd1637c7SXin Ji if (ret < 0) 829cd1637c7SXin Ji dev_err(dev, "fail to disable HDCP\n"); 830cd1637c7SXin Ji 831cd1637c7SXin Ji return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 832cd1637c7SXin Ji TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 833cd1637c7SXin Ji } 834cd1637c7SXin Ji 835cd1637c7SXin Ji static int anx7625_hdcp_enable(struct anx7625_data *ctx) 836cd1637c7SXin Ji { 837cd1637c7SXin Ji u8 bcap; 838cd1637c7SXin Ji int ret; 839cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 840cd1637c7SXin Ji 841cd1637c7SXin Ji ret = anx7625_hdcp_key_probe(ctx); 842cd1637c7SXin Ji if (ret) { 843cd1637c7SXin Ji dev_dbg(dev, "no key found, not to do hdcp\n"); 844cd1637c7SXin Ji return ret; 845cd1637c7SXin Ji } 846cd1637c7SXin Ji 847cd1637c7SXin Ji /* Read downstream capability */ 848cd1637c7SXin Ji anx7625_aux_dpcd_read(ctx, 0x68028, 1, &bcap); 849cd1637c7SXin Ji if (!(bcap & 0x01)) { 850cd1637c7SXin Ji pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 851cd1637c7SXin Ji return 0; 852cd1637c7SXin Ji } 853cd1637c7SXin Ji 854cd1637c7SXin Ji dev_dbg(dev, "enable HDCP 1.4\n"); 855cd1637c7SXin Ji 856cd1637c7SXin Ji /* First clear HDCP state */ 857cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 858cd1637c7SXin Ji TX_HDCP_CTRL0, 859cd1637c7SXin Ji KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 860cd1637c7SXin Ji usleep_range(1000, 1100); 861cd1637c7SXin Ji /* Second clear HDCP state */ 862cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 863cd1637c7SXin Ji TX_HDCP_CTRL0, 864cd1637c7SXin Ji KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 865cd1637c7SXin Ji 866cd1637c7SXin Ji /* Set time for waiting KSVR */ 867cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 868cd1637c7SXin Ji SP_TX_WAIT_KSVR_TIME, 0xc8); 869cd1637c7SXin Ji /* Set time for waiting R0 */ 870cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 871cd1637c7SXin Ji SP_TX_WAIT_R0_TIME, 0xb0); 872cd1637c7SXin Ji ret |= anx7625_hdcp_key_load(ctx); 873cd1637c7SXin Ji if (ret) { 874cd1637c7SXin Ji pr_warn("prepare HDCP key failed.\n"); 875cd1637c7SXin Ji return ret; 876cd1637c7SXin Ji } 877cd1637c7SXin Ji 878cd1637c7SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 879cd1637c7SXin Ji 880cd1637c7SXin Ji /* Try auth flag */ 881cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 882cd1637c7SXin Ji /* Interrupt for DRM */ 883cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 884cd1637c7SXin Ji if (ret < 0) 885cd1637c7SXin Ji dev_err(dev, "fail to enable HDCP\n"); 886cd1637c7SXin Ji 887cd1637c7SXin Ji return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 888cd1637c7SXin Ji TX_HDCP_CTRL0, HARD_AUTH_EN); 889cd1637c7SXin Ji } 890cd1637c7SXin Ji 8918bdfc5daSXin Ji static void anx7625_dp_start(struct anx7625_data *ctx) 8928bdfc5daSXin Ji { 8938bdfc5daSXin Ji int ret; 8948bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 8958bdfc5daSXin Ji 8968bdfc5daSXin Ji if (!ctx->display_timing_valid) { 8978bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 8988bdfc5daSXin Ji return; 8998bdfc5daSXin Ji } 9008bdfc5daSXin Ji 901cd1637c7SXin Ji /* Disable HDCP */ 902cd1637c7SXin Ji anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 903cd1637c7SXin Ji 904fd0310b6SXin Ji if (ctx->pdata.is_dpi) 905fd0310b6SXin Ji ret = anx7625_dpi_config(ctx); 906fd0310b6SXin Ji else 9078bdfc5daSXin Ji ret = anx7625_dsi_config(ctx); 9088bdfc5daSXin Ji 9098bdfc5daSXin Ji if (ret < 0) 9108bdfc5daSXin Ji DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 911cd1637c7SXin Ji 912cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 913cd1637c7SXin Ji 914cd1637c7SXin Ji ctx->dp_en = 1; 9158bdfc5daSXin Ji } 9168bdfc5daSXin Ji 9178bdfc5daSXin Ji static void anx7625_dp_stop(struct anx7625_data *ctx) 9188bdfc5daSXin Ji { 9198bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9208bdfc5daSXin Ji int ret; 9218bdfc5daSXin Ji 9228bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 9238bdfc5daSXin Ji 9248bdfc5daSXin Ji /* 9258bdfc5daSXin Ji * Video disable: 0x72:08 bit 7 = 0; 9268bdfc5daSXin Ji * Audio disable: 0x70:87 bit 0 = 0; 9278bdfc5daSXin Ji */ 9288bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 9298bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 9308bdfc5daSXin Ji 9318bdfc5daSXin Ji ret |= anx7625_video_mute_control(ctx, 1); 9328bdfc5daSXin Ji if (ret < 0) 9338bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 934cd1637c7SXin Ji 935cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 936cd1637c7SXin Ji 937cd1637c7SXin Ji ctx->dp_en = 0; 9388bdfc5daSXin Ji } 9398bdfc5daSXin Ji 9408bdfc5daSXin Ji static int sp_tx_rst_aux(struct anx7625_data *ctx) 9418bdfc5daSXin Ji { 9428bdfc5daSXin Ji int ret; 9438bdfc5daSXin Ji 9448bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 9458bdfc5daSXin Ji AUX_RST); 9468bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 9478bdfc5daSXin Ji ~AUX_RST); 9488bdfc5daSXin Ji return ret; 9498bdfc5daSXin Ji } 9508bdfc5daSXin Ji 9518bdfc5daSXin Ji static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 9528bdfc5daSXin Ji { 9538bdfc5daSXin Ji int ret; 9548bdfc5daSXin Ji 9558bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9568bdfc5daSXin Ji AP_AUX_BUFF_START, offset); 9578bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9588bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 9598bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 9608bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 9618bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 9628bdfc5daSXin Ji } 9638bdfc5daSXin Ji 9648bdfc5daSXin Ji static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 9658bdfc5daSXin Ji { 9668bdfc5daSXin Ji int ret; 9678bdfc5daSXin Ji 9688bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9698bdfc5daSXin Ji AP_AUX_COMMAND, len_cmd); 9708bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 9718bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 9728bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 9738bdfc5daSXin Ji } 9748bdfc5daSXin Ji 9758bdfc5daSXin Ji static int sp_tx_get_edid_block(struct anx7625_data *ctx) 9768bdfc5daSXin Ji { 9778bdfc5daSXin Ji int c = 0; 9788bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9798bdfc5daSXin Ji 9808bdfc5daSXin Ji sp_tx_aux_wr(ctx, 0x7e); 9818bdfc5daSXin Ji sp_tx_aux_rd(ctx, 0x01); 9828bdfc5daSXin Ji c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 9838bdfc5daSXin Ji if (c < 0) { 9848bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 9858bdfc5daSXin Ji return -EIO; 9868bdfc5daSXin Ji } 9878bdfc5daSXin Ji 9888bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 9898bdfc5daSXin Ji 9908bdfc5daSXin Ji if (c > MAX_EDID_BLOCK) 9918bdfc5daSXin Ji c = 1; 9928bdfc5daSXin Ji 9938bdfc5daSXin Ji return c; 9948bdfc5daSXin Ji } 9958bdfc5daSXin Ji 9968bdfc5daSXin Ji static int edid_read(struct anx7625_data *ctx, 9978bdfc5daSXin Ji u8 offset, u8 *pblock_buf) 9988bdfc5daSXin Ji { 9998bdfc5daSXin Ji int ret, cnt; 10008bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10018bdfc5daSXin Ji 10028bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 10038bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 10048bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 10058bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 10068bdfc5daSXin Ji 10078bdfc5daSXin Ji if (ret) { 10087f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 10098bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 10108bdfc5daSXin Ji } else { 10118bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 10128bdfc5daSXin Ji AP_AUX_BUFF_START, 10138bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, 10148bdfc5daSXin Ji pblock_buf); 10158bdfc5daSXin Ji if (ret > 0) 10168bdfc5daSXin Ji break; 10178bdfc5daSXin Ji } 10188bdfc5daSXin Ji } 10198bdfc5daSXin Ji 10208bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 10218bdfc5daSXin Ji return -EIO; 10228bdfc5daSXin Ji 10237f16d0f3SRobert Foss return ret; 10248bdfc5daSXin Ji } 10258bdfc5daSXin Ji 10268bdfc5daSXin Ji static int segments_edid_read(struct anx7625_data *ctx, 10278bdfc5daSXin Ji u8 segment, u8 *buf, u8 offset) 10288bdfc5daSXin Ji { 10298bdfc5daSXin Ji u8 cnt; 10308bdfc5daSXin Ji int ret; 10318bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10328bdfc5daSXin Ji 10338bdfc5daSXin Ji /* Write address only */ 10348bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10358bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x30); 10368bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10378bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 10388bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10398bdfc5daSXin Ji AP_AUX_CTRL_STATUS, 10408bdfc5daSXin Ji AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 10418bdfc5daSXin Ji 10428bdfc5daSXin Ji ret |= wait_aux_op_finish(ctx); 10438bdfc5daSXin Ji /* Write segment address */ 10448bdfc5daSXin Ji ret |= sp_tx_aux_wr(ctx, segment); 10458bdfc5daSXin Ji /* Data read */ 10468bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10478bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 10488bdfc5daSXin Ji if (ret) { 10498bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 10508bdfc5daSXin Ji return ret; 10518bdfc5daSXin Ji } 10528bdfc5daSXin Ji 10538bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 10548bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 10558bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 10568bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 10578bdfc5daSXin Ji 10588bdfc5daSXin Ji if (ret) { 10598bdfc5daSXin Ji ret = sp_tx_rst_aux(ctx); 10608bdfc5daSXin Ji DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 10618bdfc5daSXin Ji } else { 10628bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 10638bdfc5daSXin Ji AP_AUX_BUFF_START, 10648bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, buf); 10658bdfc5daSXin Ji if (ret > 0) 10668bdfc5daSXin Ji break; 10678bdfc5daSXin Ji } 10688bdfc5daSXin Ji } 10698bdfc5daSXin Ji 10708bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 10718bdfc5daSXin Ji return -EIO; 10728bdfc5daSXin Ji 10737f16d0f3SRobert Foss return ret; 10748bdfc5daSXin Ji } 10758bdfc5daSXin Ji 10768bdfc5daSXin Ji static int sp_tx_edid_read(struct anx7625_data *ctx, 10778bdfc5daSXin Ji u8 *pedid_blocks_buf) 10788bdfc5daSXin Ji { 10798bdfc5daSXin Ji u8 offset, edid_pos; 10808bdfc5daSXin Ji int count, blocks_num; 10818bdfc5daSXin Ji u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 10828bdfc5daSXin Ji u8 i, j; 10830bae5687SHsin-Yi Wang int g_edid_break = 0; 10848bdfc5daSXin Ji int ret; 10858bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10868bdfc5daSXin Ji 10878bdfc5daSXin Ji /* Address initial */ 10888bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10898bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 10908bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10918bdfc5daSXin Ji AP_AUX_ADDR_15_8, 0); 10928bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 10938bdfc5daSXin Ji AP_AUX_ADDR_19_16, 0xf0); 10948bdfc5daSXin Ji if (ret < 0) { 10958bdfc5daSXin Ji DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 10968bdfc5daSXin Ji return -EIO; 10978bdfc5daSXin Ji } 10988bdfc5daSXin Ji 10998bdfc5daSXin Ji blocks_num = sp_tx_get_edid_block(ctx); 11008bdfc5daSXin Ji if (blocks_num < 0) 11018bdfc5daSXin Ji return blocks_num; 11028bdfc5daSXin Ji 11038bdfc5daSXin Ji count = 0; 11048bdfc5daSXin Ji 11058bdfc5daSXin Ji do { 11068bdfc5daSXin Ji switch (count) { 11078bdfc5daSXin Ji case 0: 11088bdfc5daSXin Ji case 1: 11098bdfc5daSXin Ji for (i = 0; i < 8; i++) { 11108bdfc5daSXin Ji offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 11118bdfc5daSXin Ji g_edid_break = edid_read(ctx, offset, 11128bdfc5daSXin Ji pblock_buf); 11138bdfc5daSXin Ji 11140bae5687SHsin-Yi Wang if (g_edid_break < 0) 11158bdfc5daSXin Ji break; 11168bdfc5daSXin Ji 11178bdfc5daSXin Ji memcpy(&pedid_blocks_buf[offset], 11188bdfc5daSXin Ji pblock_buf, 11198bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11208bdfc5daSXin Ji } 11218bdfc5daSXin Ji 11228bdfc5daSXin Ji break; 11238bdfc5daSXin Ji case 2: 11248bdfc5daSXin Ji offset = 0x00; 11258bdfc5daSXin Ji 11268bdfc5daSXin Ji for (j = 0; j < 8; j++) { 11278bdfc5daSXin Ji edid_pos = (j + count * 8) * 11288bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 11298bdfc5daSXin Ji 11308bdfc5daSXin Ji if (g_edid_break == 1) 11318bdfc5daSXin Ji break; 11328bdfc5daSXin Ji 1133a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 11348bdfc5daSXin Ji pblock_buf, offset); 1135a23e0a2aSRobert Foss if (ret < 0) 1136a23e0a2aSRobert Foss return ret; 1137a23e0a2aSRobert Foss 11388bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 11398bdfc5daSXin Ji pblock_buf, 11408bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11418bdfc5daSXin Ji offset = offset + 0x10; 11428bdfc5daSXin Ji } 11438bdfc5daSXin Ji 11448bdfc5daSXin Ji break; 11458bdfc5daSXin Ji case 3: 11468bdfc5daSXin Ji offset = 0x80; 11478bdfc5daSXin Ji 11488bdfc5daSXin Ji for (j = 0; j < 8; j++) { 11498bdfc5daSXin Ji edid_pos = (j + count * 8) * 11508bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 11518bdfc5daSXin Ji if (g_edid_break == 1) 11528bdfc5daSXin Ji break; 11538bdfc5daSXin Ji 1154a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 11558bdfc5daSXin Ji pblock_buf, offset); 1156a23e0a2aSRobert Foss if (ret < 0) 1157a23e0a2aSRobert Foss return ret; 1158a23e0a2aSRobert Foss 11598bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 11608bdfc5daSXin Ji pblock_buf, 11618bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11628bdfc5daSXin Ji offset = offset + 0x10; 11638bdfc5daSXin Ji } 11648bdfc5daSXin Ji 11658bdfc5daSXin Ji break; 11668bdfc5daSXin Ji default: 11678bdfc5daSXin Ji break; 11688bdfc5daSXin Ji } 11698bdfc5daSXin Ji 11708bdfc5daSXin Ji count++; 11718bdfc5daSXin Ji 11728bdfc5daSXin Ji } while (blocks_num >= count); 11738bdfc5daSXin Ji 11748bdfc5daSXin Ji /* Check edid data */ 11758bdfc5daSXin Ji if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 11768bdfc5daSXin Ji DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 11778bdfc5daSXin Ji return -EINVAL; 11788bdfc5daSXin Ji } 11798bdfc5daSXin Ji 11808bdfc5daSXin Ji /* Reset aux channel */ 11817f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 11827f16d0f3SRobert Foss if (ret < 0) { 11837f16d0f3SRobert Foss DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 11847f16d0f3SRobert Foss return ret; 11857f16d0f3SRobert Foss } 11868bdfc5daSXin Ji 11878bdfc5daSXin Ji return (blocks_num + 1); 11888bdfc5daSXin Ji } 11898bdfc5daSXin Ji 11908bdfc5daSXin Ji static void anx7625_power_on(struct anx7625_data *ctx) 11918bdfc5daSXin Ji { 11928bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11936c744983SHsin-Yi Wang int ret, i; 11948bdfc5daSXin Ji 11958bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 11968bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 11978bdfc5daSXin Ji return; 11988bdfc5daSXin Ji } 11998bdfc5daSXin Ji 12006c744983SHsin-Yi Wang for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 12016c744983SHsin-Yi Wang ret = regulator_enable(ctx->pdata.supplies[i].consumer); 12026c744983SHsin-Yi Wang if (ret < 0) { 12036c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 12046c744983SHsin-Yi Wang i, ret); 12056c744983SHsin-Yi Wang goto reg_err; 12066c744983SHsin-Yi Wang } 12076c744983SHsin-Yi Wang usleep_range(2000, 2100); 12086c744983SHsin-Yi Wang } 12096c744983SHsin-Yi Wang 12101fcf24fbSHsin-Yi Wang usleep_range(11000, 12000); 12116c744983SHsin-Yi Wang 12128bdfc5daSXin Ji /* Power on pin enable */ 12138bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 1); 12148bdfc5daSXin Ji usleep_range(10000, 11000); 12158bdfc5daSXin Ji /* Power reset pin enable */ 12168bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 1); 12178bdfc5daSXin Ji usleep_range(10000, 11000); 12188bdfc5daSXin Ji 12198bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 12206c744983SHsin-Yi Wang return; 12216c744983SHsin-Yi Wang reg_err: 12226c744983SHsin-Yi Wang for (--i; i >= 0; i--) 12236c744983SHsin-Yi Wang regulator_disable(ctx->pdata.supplies[i].consumer); 12248bdfc5daSXin Ji } 12258bdfc5daSXin Ji 12268bdfc5daSXin Ji static void anx7625_power_standby(struct anx7625_data *ctx) 12278bdfc5daSXin Ji { 12288bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12296c744983SHsin-Yi Wang int ret; 12308bdfc5daSXin Ji 12318bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 12328bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 12338bdfc5daSXin Ji return; 12348bdfc5daSXin Ji } 12358bdfc5daSXin Ji 12368bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 0); 12378bdfc5daSXin Ji usleep_range(1000, 1100); 12388bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 0); 12398bdfc5daSXin Ji usleep_range(1000, 1100); 12406c744983SHsin-Yi Wang 12416c744983SHsin-Yi Wang ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 12426c744983SHsin-Yi Wang ctx->pdata.supplies); 12436c744983SHsin-Yi Wang if (ret < 0) 12446c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 12456c744983SHsin-Yi Wang 12468bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 12478bdfc5daSXin Ji } 12488bdfc5daSXin Ji 12498bdfc5daSXin Ji /* Basic configurations of ANX7625 */ 12508bdfc5daSXin Ji static void anx7625_config(struct anx7625_data *ctx) 12518bdfc5daSXin Ji { 12528bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12538bdfc5daSXin Ji XTAL_FRQ_SEL, XTAL_FRQ_27M); 12548bdfc5daSXin Ji } 12558bdfc5daSXin Ji 12568bdfc5daSXin Ji static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 12578bdfc5daSXin Ji { 12588bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12598bdfc5daSXin Ji int ret; 12608bdfc5daSXin Ji 12618bdfc5daSXin Ji /* Reset main ocm */ 12628bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 12638bdfc5daSXin Ji /* Disable PD */ 12648bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12658bdfc5daSXin Ji AP_AV_STATUS, AP_DISABLE_PD); 12668bdfc5daSXin Ji /* Release main ocm */ 12678bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 12688bdfc5daSXin Ji 12698bdfc5daSXin Ji if (ret < 0) 12708bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 12718bdfc5daSXin Ji else 12728bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 12738bdfc5daSXin Ji } 12748bdfc5daSXin Ji 12758bdfc5daSXin Ji static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 12768bdfc5daSXin Ji { 12778bdfc5daSXin Ji int ret; 12788bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12798bdfc5daSXin Ji 12808bdfc5daSXin Ji /* Check interface workable */ 12818bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 12828bdfc5daSXin Ji FLASH_LOAD_STA); 12838bdfc5daSXin Ji if (ret < 0) { 12848bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 12858bdfc5daSXin Ji return ret; 12868bdfc5daSXin Ji } 12878bdfc5daSXin Ji if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 12888bdfc5daSXin Ji return -ENODEV; 12898bdfc5daSXin Ji 12908bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 12918bdfc5daSXin Ji 12928bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 12938bdfc5daSXin Ji anx7625_reg_read(ctx, 12948bdfc5daSXin Ji ctx->i2c.rx_p0_client, 12958bdfc5daSXin Ji OCM_FW_VERSION), 12968bdfc5daSXin Ji anx7625_reg_read(ctx, 12978bdfc5daSXin Ji ctx->i2c.rx_p0_client, 12988bdfc5daSXin Ji OCM_FW_REVERSION)); 12998bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 13008bdfc5daSXin Ji ANX7625_DRV_VERSION); 13018bdfc5daSXin Ji 13028bdfc5daSXin Ji return 0; 13038bdfc5daSXin Ji } 13048bdfc5daSXin Ji 13058bdfc5daSXin Ji static void anx7625_power_on_init(struct anx7625_data *ctx) 13068bdfc5daSXin Ji { 13078bdfc5daSXin Ji int retry_count, i; 13088bdfc5daSXin Ji 13098bdfc5daSXin Ji for (retry_count = 0; retry_count < 3; retry_count++) { 13108bdfc5daSXin Ji anx7625_power_on(ctx); 13118bdfc5daSXin Ji anx7625_config(ctx); 13128bdfc5daSXin Ji 13138bdfc5daSXin Ji for (i = 0; i < OCM_LOADING_TIME; i++) { 13148bdfc5daSXin Ji if (!anx7625_ocm_loading_check(ctx)) 13158bdfc5daSXin Ji return; 13168bdfc5daSXin Ji usleep_range(1000, 1100); 13178bdfc5daSXin Ji } 13188bdfc5daSXin Ji anx7625_power_standby(ctx); 13198bdfc5daSXin Ji } 13208bdfc5daSXin Ji } 13218bdfc5daSXin Ji 13228bdfc5daSXin Ji static void anx7625_init_gpio(struct anx7625_data *platform) 13238bdfc5daSXin Ji { 13248bdfc5daSXin Ji struct device *dev = &platform->client->dev; 13258bdfc5daSXin Ji 13268bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 13278bdfc5daSXin Ji 13288bdfc5daSXin Ji /* Gpio for chip power enable */ 13298bdfc5daSXin Ji platform->pdata.gpio_p_on = 13308bdfc5daSXin Ji devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 13317020449bSXin Ji if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 13327020449bSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 13337020449bSXin Ji platform->pdata.gpio_p_on = NULL; 13347020449bSXin Ji } 13357020449bSXin Ji 13368bdfc5daSXin Ji /* Gpio for chip reset */ 13378bdfc5daSXin Ji platform->pdata.gpio_reset = 13388bdfc5daSXin Ji devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 13397020449bSXin Ji if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 13407020449bSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 13417020449bSXin Ji platform->pdata.gpio_reset = NULL; 13427020449bSXin Ji } 13438bdfc5daSXin Ji 13448bdfc5daSXin Ji if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 13458bdfc5daSXin Ji platform->pdata.low_power_mode = 1; 13468bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 13478bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_p_on), 13488bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_reset)); 13498bdfc5daSXin Ji } else { 13508bdfc5daSXin Ji platform->pdata.low_power_mode = 0; 13518bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 13528bdfc5daSXin Ji } 13538bdfc5daSXin Ji } 13548bdfc5daSXin Ji 13558bdfc5daSXin Ji static void anx7625_stop_dp_work(struct anx7625_data *ctx) 13568bdfc5daSXin Ji { 13578bdfc5daSXin Ji ctx->hpd_status = 0; 13588bdfc5daSXin Ji ctx->hpd_high_cnt = 0; 13598bdfc5daSXin Ji ctx->display_timing_valid = 0; 13608bdfc5daSXin Ji } 13618bdfc5daSXin Ji 13628bdfc5daSXin Ji static void anx7625_start_dp_work(struct anx7625_data *ctx) 13638bdfc5daSXin Ji { 13648bdfc5daSXin Ji int ret; 13658bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13668bdfc5daSXin Ji 13678bdfc5daSXin Ji if (ctx->hpd_high_cnt >= 2) { 13688bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 13698bdfc5daSXin Ji return; 13708bdfc5daSXin Ji } 13718bdfc5daSXin Ji 1372fd0310b6SXin Ji ctx->hpd_status = 1; 13738bdfc5daSXin Ji ctx->hpd_high_cnt++; 13748bdfc5daSXin Ji 13758bdfc5daSXin Ji /* Not support HDCP */ 13768bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 13778bdfc5daSXin Ji 13788bdfc5daSXin Ji /* Try auth flag */ 13798bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 13808bdfc5daSXin Ji /* Interrupt for DRM */ 13818bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1382fd0310b6SXin Ji if (ret < 0) { 1383fd0310b6SXin Ji DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 13848bdfc5daSXin Ji return; 1385fd0310b6SXin Ji } 13868bdfc5daSXin Ji 13878bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 13888bdfc5daSXin Ji if (ret < 0) 13898bdfc5daSXin Ji return; 13908bdfc5daSXin Ji 13918bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 13928bdfc5daSXin Ji } 13938bdfc5daSXin Ji 13948bdfc5daSXin Ji static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 13958bdfc5daSXin Ji { 13968bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 13978bdfc5daSXin Ji } 13988bdfc5daSXin Ji 13998bdfc5daSXin Ji static void anx7625_hpd_polling(struct anx7625_data *ctx) 14008bdfc5daSXin Ji { 14018bdfc5daSXin Ji int ret, val; 14028bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14038bdfc5daSXin Ji 1404fd0310b6SXin Ji /* Interrupt mode, no need poll HPD status, just return */ 1405fd0310b6SXin Ji if (ctx->pdata.intp_irq) 1406fd0310b6SXin Ji return; 1407fd0310b6SXin Ji 14088bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 14098bdfc5daSXin Ji ctx, val, 14108bdfc5daSXin Ji ((val & HPD_STATUS) || (val < 0)), 14118bdfc5daSXin Ji 5000, 14128bdfc5daSXin Ji 5000 * 100); 14138bdfc5daSXin Ji if (ret) { 141460487584SPi-Hsun Shih DRM_DEV_ERROR(dev, "no hpd.\n"); 141560487584SPi-Hsun Shih return; 141660487584SPi-Hsun Shih } 141760487584SPi-Hsun Shih 141860487584SPi-Hsun Shih DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 14198bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 14208bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 14218bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 14228bdfc5daSXin Ji INTERFACE_CHANGE_INT, 0); 14238bdfc5daSXin Ji 14248bdfc5daSXin Ji anx7625_start_dp_work(ctx); 14258bdfc5daSXin Ji 142660487584SPi-Hsun Shih if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 142760487584SPi-Hsun Shih drm_helper_hpd_irq_event(ctx->bridge.dev); 14288bdfc5daSXin Ji } 14298bdfc5daSXin Ji 14308bdfc5daSXin Ji static void anx7625_remove_edid(struct anx7625_data *ctx) 14318bdfc5daSXin Ji { 14328bdfc5daSXin Ji ctx->slimport_edid_p.edid_block_num = -1; 14338bdfc5daSXin Ji } 14348bdfc5daSXin Ji 1435fd0310b6SXin Ji static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1436fd0310b6SXin Ji { 1437fd0310b6SXin Ji int i; 1438fd0310b6SXin Ji 1439fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1440fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1441fd0310b6SXin Ji DP_TX_LANE0_SWING_REG0 + i, 1442fd0310b6SXin Ji ctx->pdata.lane0_reg_data[i] & 0xFF); 1443fd0310b6SXin Ji 1444fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1445fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1446fd0310b6SXin Ji DP_TX_LANE1_SWING_REG0 + i, 1447fd0310b6SXin Ji ctx->pdata.lane1_reg_data[i] & 0xFF); 1448fd0310b6SXin Ji } 1449fd0310b6SXin Ji 14508bdfc5daSXin Ji static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 14518bdfc5daSXin Ji { 14528bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14538bdfc5daSXin Ji 14548bdfc5daSXin Ji /* HPD changed */ 14558bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 14568bdfc5daSXin Ji (u32)on); 14578bdfc5daSXin Ji 14588bdfc5daSXin Ji if (on == 0) { 14598bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 14608bdfc5daSXin Ji anx7625_remove_edid(ctx); 14618bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 14628bdfc5daSXin Ji } else { 14638bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 14648bdfc5daSXin Ji anx7625_start_dp_work(ctx); 1465fd0310b6SXin Ji anx7625_dp_adjust_swing(ctx); 14668bdfc5daSXin Ji } 14678bdfc5daSXin Ji } 14688bdfc5daSXin Ji 14698bdfc5daSXin Ji static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 14708bdfc5daSXin Ji { 14718bdfc5daSXin Ji int intr_vector, status; 14728bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14738bdfc5daSXin Ji 14748bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 14758bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 14768bdfc5daSXin Ji if (status < 0) { 14778bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 14788bdfc5daSXin Ji return status; 14798bdfc5daSXin Ji } 14808bdfc5daSXin Ji 14818bdfc5daSXin Ji intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 14828bdfc5daSXin Ji INTERFACE_CHANGE_INT); 14838bdfc5daSXin Ji if (intr_vector < 0) { 14848bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 14858bdfc5daSXin Ji return intr_vector; 14868bdfc5daSXin Ji } 14878bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 14888bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 14898bdfc5daSXin Ji INTERFACE_CHANGE_INT, 14908bdfc5daSXin Ji intr_vector & (~intr_vector)); 14918bdfc5daSXin Ji if (status < 0) { 14928bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 14938bdfc5daSXin Ji return status; 14948bdfc5daSXin Ji } 14958bdfc5daSXin Ji 14968bdfc5daSXin Ji if (!(intr_vector & HPD_STATUS_CHANGE)) 14978bdfc5daSXin Ji return -ENOENT; 14988bdfc5daSXin Ji 14998bdfc5daSXin Ji status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 15008bdfc5daSXin Ji SYSTEM_STSTUS); 15018bdfc5daSXin Ji if (status < 0) { 15028bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 15038bdfc5daSXin Ji return status; 15048bdfc5daSXin Ji } 15058bdfc5daSXin Ji 15068bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 15078bdfc5daSXin Ji dp_hpd_change_handler(ctx, status & HPD_STATUS); 15088bdfc5daSXin Ji 15098bdfc5daSXin Ji return 0; 15108bdfc5daSXin Ji } 15118bdfc5daSXin Ji 15128bdfc5daSXin Ji static void anx7625_work_func(struct work_struct *work) 15138bdfc5daSXin Ji { 15148bdfc5daSXin Ji int event; 15158bdfc5daSXin Ji struct anx7625_data *ctx = container_of(work, 15168bdfc5daSXin Ji struct anx7625_data, work); 15178bdfc5daSXin Ji 15188bdfc5daSXin Ji mutex_lock(&ctx->lock); 151960487584SPi-Hsun Shih 152060487584SPi-Hsun Shih if (pm_runtime_suspended(&ctx->client->dev)) 152160487584SPi-Hsun Shih goto unlock; 152260487584SPi-Hsun Shih 15238bdfc5daSXin Ji event = anx7625_hpd_change_detect(ctx); 15248bdfc5daSXin Ji if (event < 0) 152560487584SPi-Hsun Shih goto unlock; 15268bdfc5daSXin Ji 15278bdfc5daSXin Ji if (ctx->bridge_attached) 15288bdfc5daSXin Ji drm_helper_hpd_irq_event(ctx->bridge.dev); 152960487584SPi-Hsun Shih 153060487584SPi-Hsun Shih unlock: 153160487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 15328bdfc5daSXin Ji } 15338bdfc5daSXin Ji 15348bdfc5daSXin Ji static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 15358bdfc5daSXin Ji { 15368bdfc5daSXin Ji struct anx7625_data *ctx = (struct anx7625_data *)data; 15378bdfc5daSXin Ji 15388bdfc5daSXin Ji queue_work(ctx->workqueue, &ctx->work); 15398bdfc5daSXin Ji 15408bdfc5daSXin Ji return IRQ_HANDLED; 15418bdfc5daSXin Ji } 15428bdfc5daSXin Ji 1543fd0310b6SXin Ji static int anx7625_get_swing_setting(struct device *dev, 1544fd0310b6SXin Ji struct anx7625_platform_data *pdata) 1545fd0310b6SXin Ji { 1546fd0310b6SXin Ji int num_regs; 1547fd0310b6SXin Ji 1548fd0310b6SXin Ji if (of_get_property(dev->of_node, 1549fd0310b6SXin Ji "analogix,lane0-swing", &num_regs)) { 1550fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1551fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1552fd0310b6SXin Ji 1553fd0310b6SXin Ji pdata->dp_lane0_swing_reg_cnt = num_regs; 1554fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1555fd0310b6SXin Ji pdata->lane0_reg_data, num_regs); 1556fd0310b6SXin Ji } 1557fd0310b6SXin Ji 1558fd0310b6SXin Ji if (of_get_property(dev->of_node, 1559fd0310b6SXin Ji "analogix,lane1-swing", &num_regs)) { 1560fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1561fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1562fd0310b6SXin Ji 1563fd0310b6SXin Ji pdata->dp_lane1_swing_reg_cnt = num_regs; 1564fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1565fd0310b6SXin Ji pdata->lane1_reg_data, num_regs); 1566fd0310b6SXin Ji } 1567fd0310b6SXin Ji 1568fd0310b6SXin Ji return 0; 1569fd0310b6SXin Ji } 1570fd0310b6SXin Ji 15718bdfc5daSXin Ji static int anx7625_parse_dt(struct device *dev, 15728bdfc5daSXin Ji struct anx7625_platform_data *pdata) 15738bdfc5daSXin Ji { 1574fd0310b6SXin Ji struct device_node *np = dev->of_node, *ep0; 15758bdfc5daSXin Ji struct drm_panel *panel; 15768bdfc5daSXin Ji int ret; 1577fd0310b6SXin Ji int bus_type, mipi_lanes; 15788bdfc5daSXin Ji 1579fd0310b6SXin Ji anx7625_get_swing_setting(dev, pdata); 1580fd0310b6SXin Ji 1581fd0310b6SXin Ji pdata->is_dpi = 1; /* default dpi mode */ 15828bdfc5daSXin Ji pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 15838bdfc5daSXin Ji if (!pdata->mipi_host_node) { 15848bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 15858bdfc5daSXin Ji return -ENODEV; 15868bdfc5daSXin Ji } 15878bdfc5daSXin Ji 1588fd0310b6SXin Ji bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1589fd0310b6SXin Ji mipi_lanes = MAX_LANES_SUPPORT; 1590fd0310b6SXin Ji ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1591fd0310b6SXin Ji if (ep0) { 1592fd0310b6SXin Ji if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1593fd0310b6SXin Ji bus_type = 0; 1594fd0310b6SXin Ji 1595fd0310b6SXin Ji mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1596fd0310b6SXin Ji } 1597fd0310b6SXin Ji 1598fd0310b6SXin Ji if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1599fd0310b6SXin Ji pdata->is_dpi = 0; 1600fd0310b6SXin Ji 1601fd0310b6SXin Ji pdata->mipi_lanes = mipi_lanes; 1602fd0310b6SXin Ji if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1603fd0310b6SXin Ji pdata->mipi_lanes = MAX_LANES_SUPPORT; 1604fd0310b6SXin Ji 1605fd0310b6SXin Ji if (pdata->is_dpi) 1606fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1607fd0310b6SXin Ji else 1608fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 16098bdfc5daSXin Ji 1610566fef12SXin Ji if (of_property_read_bool(np, "analogix,audio-enable")) 1611566fef12SXin Ji pdata->audio_en = 1; 1612566fef12SXin Ji 16138bdfc5daSXin Ji ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 16148bdfc5daSXin Ji if (ret < 0) { 16158bdfc5daSXin Ji if (ret == -ENODEV) 16168bdfc5daSXin Ji return 0; 16178bdfc5daSXin Ji return ret; 16188bdfc5daSXin Ji } 16198bdfc5daSXin Ji if (!panel) 16208bdfc5daSXin Ji return -ENODEV; 16218bdfc5daSXin Ji 16228bdfc5daSXin Ji pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 16238bdfc5daSXin Ji if (IS_ERR(pdata->panel_bridge)) 16248bdfc5daSXin Ji return PTR_ERR(pdata->panel_bridge); 16258bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 16268bdfc5daSXin Ji 16278bdfc5daSXin Ji return 0; 16288bdfc5daSXin Ji } 16298bdfc5daSXin Ji 16308bdfc5daSXin Ji static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 16318bdfc5daSXin Ji { 16328bdfc5daSXin Ji return container_of(bridge, struct anx7625_data, bridge); 16338bdfc5daSXin Ji } 16348bdfc5daSXin Ji 16358bdfc5daSXin Ji static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 16368bdfc5daSXin Ji { 16378bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 16388bdfc5daSXin Ji struct s_edid_data *p_edid = &ctx->slimport_edid_p; 16398bdfc5daSXin Ji int edid_num; 16408bdfc5daSXin Ji u8 *edid; 16418bdfc5daSXin Ji 16428bdfc5daSXin Ji edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 16438bdfc5daSXin Ji if (!edid) { 16448bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 16458bdfc5daSXin Ji return NULL; 16468bdfc5daSXin Ji } 16478bdfc5daSXin Ji 16488bdfc5daSXin Ji if (ctx->slimport_edid_p.edid_block_num > 0) { 16498bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 16508bdfc5daSXin Ji FOUR_BLOCK_SIZE); 16518bdfc5daSXin Ji return (struct edid *)edid; 16528bdfc5daSXin Ji } 16538bdfc5daSXin Ji 165460487584SPi-Hsun Shih pm_runtime_get_sync(dev); 16558bdfc5daSXin Ji edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 16563203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 16578bdfc5daSXin Ji 16588bdfc5daSXin Ji if (edid_num < 1) { 16598bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 16608bdfc5daSXin Ji kfree(edid); 16618bdfc5daSXin Ji return NULL; 16628bdfc5daSXin Ji } 16638bdfc5daSXin Ji 16648bdfc5daSXin Ji p_edid->edid_block_num = edid_num; 16658bdfc5daSXin Ji 16668bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 16678bdfc5daSXin Ji return (struct edid *)edid; 16688bdfc5daSXin Ji } 16698bdfc5daSXin Ji 16708bdfc5daSXin Ji static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 16718bdfc5daSXin Ji { 16728bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 16738bdfc5daSXin Ji 1674fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 16758bdfc5daSXin Ji 1676fd0310b6SXin Ji if (ctx->pdata.panel_bridge) 16778bdfc5daSXin Ji return connector_status_connected; 1678fd0310b6SXin Ji 1679fd0310b6SXin Ji return ctx->hpd_status ? connector_status_connected : 1680fd0310b6SXin Ji connector_status_disconnected; 16818bdfc5daSXin Ji } 16828bdfc5daSXin Ji 1683566fef12SXin Ji static int anx7625_audio_hw_params(struct device *dev, void *data, 1684566fef12SXin Ji struct hdmi_codec_daifmt *fmt, 1685566fef12SXin Ji struct hdmi_codec_params *params) 1686566fef12SXin Ji { 1687566fef12SXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 1688566fef12SXin Ji int wl, ch, rate; 1689566fef12SXin Ji int ret = 0; 1690566fef12SXin Ji 1691566fef12SXin Ji if (fmt->fmt != HDMI_DSP_A) { 1692566fef12SXin Ji DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1693566fef12SXin Ji return -EINVAL; 1694566fef12SXin Ji } 1695566fef12SXin Ji 1696566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1697566fef12SXin Ji params->sample_rate, params->sample_width, 1698566fef12SXin Ji params->cea.channels); 1699566fef12SXin Ji 1700566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1701566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 1702566fef12SXin Ji ~I2S_SLAVE_MODE, 1703566fef12SXin Ji TDM_SLAVE_MODE); 1704566fef12SXin Ji 1705566fef12SXin Ji /* Word length */ 1706566fef12SXin Ji switch (params->sample_width) { 1707566fef12SXin Ji case 16: 1708566fef12SXin Ji wl = AUDIO_W_LEN_16_20MAX; 1709566fef12SXin Ji break; 1710566fef12SXin Ji case 18: 1711566fef12SXin Ji wl = AUDIO_W_LEN_18_20MAX; 1712566fef12SXin Ji break; 1713566fef12SXin Ji case 20: 1714566fef12SXin Ji wl = AUDIO_W_LEN_20_20MAX; 1715566fef12SXin Ji break; 1716566fef12SXin Ji case 24: 1717566fef12SXin Ji wl = AUDIO_W_LEN_24_24MAX; 1718566fef12SXin Ji break; 1719566fef12SXin Ji default: 1720566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1721566fef12SXin Ji params->sample_width); 1722566fef12SXin Ji return -EINVAL; 1723566fef12SXin Ji } 1724566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1725566fef12SXin Ji AUDIO_CHANNEL_STATUS_5, 1726566fef12SXin Ji 0xf0, wl); 1727566fef12SXin Ji 1728566fef12SXin Ji /* Channel num */ 1729566fef12SXin Ji switch (params->cea.channels) { 1730566fef12SXin Ji case 2: 1731566fef12SXin Ji ch = I2S_CH_2; 1732566fef12SXin Ji break; 1733566fef12SXin Ji case 4: 1734566fef12SXin Ji ch = TDM_CH_4; 1735566fef12SXin Ji break; 1736566fef12SXin Ji case 6: 1737566fef12SXin Ji ch = TDM_CH_6; 1738566fef12SXin Ji break; 1739566fef12SXin Ji case 8: 1740566fef12SXin Ji ch = TDM_CH_8; 1741566fef12SXin Ji break; 1742566fef12SXin Ji default: 1743566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1744566fef12SXin Ji params->cea.channels); 1745566fef12SXin Ji return -EINVAL; 1746566fef12SXin Ji } 1747566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1748566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1749566fef12SXin Ji if (ch > I2S_CH_2) 1750566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1751566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1752566fef12SXin Ji else 1753566fef12SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1754566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1755566fef12SXin Ji 1756566fef12SXin Ji /* FS */ 1757566fef12SXin Ji switch (params->sample_rate) { 1758566fef12SXin Ji case 32000: 1759566fef12SXin Ji rate = AUDIO_FS_32K; 1760566fef12SXin Ji break; 1761566fef12SXin Ji case 44100: 1762566fef12SXin Ji rate = AUDIO_FS_441K; 1763566fef12SXin Ji break; 1764566fef12SXin Ji case 48000: 1765566fef12SXin Ji rate = AUDIO_FS_48K; 1766566fef12SXin Ji break; 1767566fef12SXin Ji case 88200: 1768566fef12SXin Ji rate = AUDIO_FS_882K; 1769566fef12SXin Ji break; 1770566fef12SXin Ji case 96000: 1771566fef12SXin Ji rate = AUDIO_FS_96K; 1772566fef12SXin Ji break; 1773566fef12SXin Ji case 176400: 1774566fef12SXin Ji rate = AUDIO_FS_1764K; 1775566fef12SXin Ji break; 1776566fef12SXin Ji case 192000: 1777566fef12SXin Ji rate = AUDIO_FS_192K; 1778566fef12SXin Ji break; 1779566fef12SXin Ji default: 1780566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1781566fef12SXin Ji params->sample_rate); 1782566fef12SXin Ji return -EINVAL; 1783566fef12SXin Ji } 1784566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1785566fef12SXin Ji AUDIO_CHANNEL_STATUS_4, 1786566fef12SXin Ji 0xf0, rate); 1787566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1788566fef12SXin Ji AP_AV_STATUS, AP_AUDIO_CHG); 1789566fef12SXin Ji if (ret < 0) { 1790566fef12SXin Ji DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1791566fef12SXin Ji return -EIO; 1792566fef12SXin Ji } 1793566fef12SXin Ji 1794566fef12SXin Ji return 0; 1795566fef12SXin Ji } 1796566fef12SXin Ji 1797566fef12SXin Ji static void anx7625_audio_shutdown(struct device *dev, void *data) 1798566fef12SXin Ji { 1799566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1800566fef12SXin Ji } 1801566fef12SXin Ji 1802566fef12SXin Ji static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1803566fef12SXin Ji struct device_node *endpoint) 1804566fef12SXin Ji { 1805566fef12SXin Ji struct of_endpoint of_ep; 1806566fef12SXin Ji int ret; 1807566fef12SXin Ji 1808566fef12SXin Ji ret = of_graph_parse_endpoint(endpoint, &of_ep); 1809566fef12SXin Ji if (ret < 0) 1810566fef12SXin Ji return ret; 1811566fef12SXin Ji 1812566fef12SXin Ji /* 1813566fef12SXin Ji * HDMI sound should be located at external DPI port 1814566fef12SXin Ji * Didn't have good way to check where is internal(DSI) 1815566fef12SXin Ji * or external(DPI) bridge 1816566fef12SXin Ji */ 1817566fef12SXin Ji return 0; 1818566fef12SXin Ji } 1819566fef12SXin Ji 1820566fef12SXin Ji static void 1821566fef12SXin Ji anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1822566fef12SXin Ji enum drm_connector_status status) 1823566fef12SXin Ji { 1824566fef12SXin Ji if (ctx->plugged_cb && ctx->codec_dev) { 1825566fef12SXin Ji ctx->plugged_cb(ctx->codec_dev, 1826566fef12SXin Ji status == connector_status_connected); 1827566fef12SXin Ji } 1828566fef12SXin Ji } 1829566fef12SXin Ji 1830566fef12SXin Ji static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1831566fef12SXin Ji hdmi_codec_plugged_cb fn, 1832566fef12SXin Ji struct device *codec_dev) 1833566fef12SXin Ji { 1834566fef12SXin Ji struct anx7625_data *ctx = data; 1835566fef12SXin Ji 1836566fef12SXin Ji ctx->plugged_cb = fn; 1837566fef12SXin Ji ctx->codec_dev = codec_dev; 1838566fef12SXin Ji anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1839566fef12SXin Ji 1840566fef12SXin Ji return 0; 1841566fef12SXin Ji } 1842566fef12SXin Ji 1843607a264eSXin Ji static int anx7625_audio_get_eld(struct device *dev, void *data, 1844607a264eSXin Ji u8 *buf, size_t len) 1845607a264eSXin Ji { 1846607a264eSXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 1847607a264eSXin Ji 1848607a264eSXin Ji if (!ctx->connector) { 1849607a264eSXin Ji dev_err(dev, "connector not initial\n"); 1850607a264eSXin Ji return -EINVAL; 1851607a264eSXin Ji } 1852607a264eSXin Ji 1853607a264eSXin Ji dev_dbg(dev, "audio copy eld\n"); 1854607a264eSXin Ji memcpy(buf, ctx->connector->eld, 1855607a264eSXin Ji min(sizeof(ctx->connector->eld), len)); 1856607a264eSXin Ji 1857607a264eSXin Ji return 0; 1858607a264eSXin Ji } 1859607a264eSXin Ji 1860566fef12SXin Ji static const struct hdmi_codec_ops anx7625_codec_ops = { 1861566fef12SXin Ji .hw_params = anx7625_audio_hw_params, 1862566fef12SXin Ji .audio_shutdown = anx7625_audio_shutdown, 1863607a264eSXin Ji .get_eld = anx7625_audio_get_eld, 1864566fef12SXin Ji .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1865566fef12SXin Ji .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1866566fef12SXin Ji }; 1867566fef12SXin Ji 1868566fef12SXin Ji static void anx7625_unregister_audio(struct anx7625_data *ctx) 1869566fef12SXin Ji { 1870566fef12SXin Ji struct device *dev = &ctx->client->dev; 1871566fef12SXin Ji 1872566fef12SXin Ji if (ctx->audio_pdev) { 1873566fef12SXin Ji platform_device_unregister(ctx->audio_pdev); 1874566fef12SXin Ji ctx->audio_pdev = NULL; 1875566fef12SXin Ji } 1876566fef12SXin Ji 1877566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1878566fef12SXin Ji } 1879566fef12SXin Ji 1880566fef12SXin Ji static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1881566fef12SXin Ji { 1882566fef12SXin Ji struct hdmi_codec_pdata codec_data = { 1883566fef12SXin Ji .ops = &anx7625_codec_ops, 1884566fef12SXin Ji .max_i2s_channels = 8, 1885566fef12SXin Ji .i2s = 1, 1886566fef12SXin Ji .data = ctx, 1887566fef12SXin Ji }; 1888566fef12SXin Ji 1889566fef12SXin Ji ctx->audio_pdev = platform_device_register_data(dev, 1890566fef12SXin Ji HDMI_CODEC_DRV_NAME, 1891566fef12SXin Ji PLATFORM_DEVID_AUTO, 1892566fef12SXin Ji &codec_data, 1893566fef12SXin Ji sizeof(codec_data)); 1894566fef12SXin Ji 1895566fef12SXin Ji if (IS_ERR(ctx->audio_pdev)) 189683ddd806SDan Carpenter return PTR_ERR(ctx->audio_pdev); 1897566fef12SXin Ji 1898566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1899566fef12SXin Ji 1900566fef12SXin Ji return 0; 1901566fef12SXin Ji } 1902566fef12SXin Ji 19038bdfc5daSXin Ji static int anx7625_attach_dsi(struct anx7625_data *ctx) 19048bdfc5daSXin Ji { 19058bdfc5daSXin Ji struct mipi_dsi_device *dsi; 19068bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 19078bdfc5daSXin Ji struct mipi_dsi_host *host; 19088bdfc5daSXin Ji const struct mipi_dsi_device_info info = { 19098bdfc5daSXin Ji .type = "anx7625", 19108bdfc5daSXin Ji .channel = 0, 19118bdfc5daSXin Ji .node = NULL, 19128bdfc5daSXin Ji }; 191325a390a9SMaxime Ripard int ret; 19148bdfc5daSXin Ji 19158bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 19168bdfc5daSXin Ji 19178bdfc5daSXin Ji host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 19188bdfc5daSXin Ji if (!host) { 19198bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 19208bdfc5daSXin Ji return -EINVAL; 19218bdfc5daSXin Ji } 19228bdfc5daSXin Ji 192325a390a9SMaxime Ripard dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 19248bdfc5daSXin Ji if (IS_ERR(dsi)) { 19258bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 19268bdfc5daSXin Ji return -EINVAL; 19278bdfc5daSXin Ji } 19288bdfc5daSXin Ji 1929fd0310b6SXin Ji dsi->lanes = ctx->pdata.mipi_lanes; 19308bdfc5daSXin Ji dsi->format = MIPI_DSI_FMT_RGB888; 19318bdfc5daSXin Ji dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 19328bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 19338bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_HSE; 19348bdfc5daSXin Ji 193525a390a9SMaxime Ripard ret = devm_mipi_dsi_attach(dev, dsi); 193625a390a9SMaxime Ripard if (ret) { 19378bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 193825a390a9SMaxime Ripard return ret; 19398bdfc5daSXin Ji } 19408bdfc5daSXin Ji 19418bdfc5daSXin Ji ctx->dsi = dsi; 19428bdfc5daSXin Ji 19438bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 19448bdfc5daSXin Ji 19458bdfc5daSXin Ji return 0; 19468bdfc5daSXin Ji } 19478bdfc5daSXin Ji 1948cd1637c7SXin Ji static void hdcp_check_work_func(struct work_struct *work) 1949cd1637c7SXin Ji { 1950cd1637c7SXin Ji u8 status; 1951cd1637c7SXin Ji struct delayed_work *dwork; 1952cd1637c7SXin Ji struct anx7625_data *ctx; 1953cd1637c7SXin Ji struct device *dev; 1954cd1637c7SXin Ji struct drm_device *drm_dev; 1955cd1637c7SXin Ji 1956cd1637c7SXin Ji dwork = to_delayed_work(work); 1957cd1637c7SXin Ji ctx = container_of(dwork, struct anx7625_data, hdcp_work); 1958cd1637c7SXin Ji dev = &ctx->client->dev; 1959cd1637c7SXin Ji 1960cd1637c7SXin Ji if (!ctx->connector) { 1961cd1637c7SXin Ji dev_err(dev, "HDCP connector is null!"); 1962cd1637c7SXin Ji return; 1963cd1637c7SXin Ji } 1964cd1637c7SXin Ji 1965cd1637c7SXin Ji drm_dev = ctx->connector->dev; 1966cd1637c7SXin Ji drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1967cd1637c7SXin Ji mutex_lock(&ctx->hdcp_wq_lock); 1968cd1637c7SXin Ji 1969cd1637c7SXin Ji status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 1970cd1637c7SXin Ji dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 1971cd1637c7SXin Ji if (status & BIT(1)) { 1972cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 1973cd1637c7SXin Ji drm_hdcp_update_content_protection(ctx->connector, 1974cd1637c7SXin Ji ctx->hdcp_cp); 1975cd1637c7SXin Ji dev_dbg(dev, "update CP to ENABLE\n"); 1976cd1637c7SXin Ji } 1977cd1637c7SXin Ji 1978cd1637c7SXin Ji mutex_unlock(&ctx->hdcp_wq_lock); 1979cd1637c7SXin Ji drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1980cd1637c7SXin Ji } 1981cd1637c7SXin Ji 1982cd1637c7SXin Ji static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 1983cd1637c7SXin Ji struct drm_connector_state *state) 1984cd1637c7SXin Ji { 1985cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 1986cd1637c7SXin Ji int cp; 1987cd1637c7SXin Ji 1988cd1637c7SXin Ji dev_dbg(dev, "hdcp state check\n"); 1989cd1637c7SXin Ji cp = state->content_protection; 1990cd1637c7SXin Ji 1991cd1637c7SXin Ji if (cp == ctx->hdcp_cp) 1992cd1637c7SXin Ji return 0; 1993cd1637c7SXin Ji 1994cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 1995cd1637c7SXin Ji if (ctx->dp_en) { 1996cd1637c7SXin Ji dev_dbg(dev, "enable HDCP\n"); 1997cd1637c7SXin Ji anx7625_hdcp_enable(ctx); 1998cd1637c7SXin Ji 1999cd1637c7SXin Ji queue_delayed_work(ctx->hdcp_workqueue, 2000cd1637c7SXin Ji &ctx->hdcp_work, 2001cd1637c7SXin Ji msecs_to_jiffies(2000)); 2002cd1637c7SXin Ji } 2003cd1637c7SXin Ji } 2004cd1637c7SXin Ji 2005cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2006cd1637c7SXin Ji if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2007cd1637c7SXin Ji dev_err(dev, "current CP is not ENABLED\n"); 2008cd1637c7SXin Ji return -EINVAL; 2009cd1637c7SXin Ji } 2010cd1637c7SXin Ji anx7625_hdcp_disable(ctx); 2011cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2012cd1637c7SXin Ji drm_hdcp_update_content_protection(ctx->connector, 2013cd1637c7SXin Ji ctx->hdcp_cp); 2014cd1637c7SXin Ji dev_dbg(dev, "update CP to UNDESIRE\n"); 2015cd1637c7SXin Ji } 2016cd1637c7SXin Ji 2017cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2018cd1637c7SXin Ji dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2019cd1637c7SXin Ji return -EINVAL; 2020cd1637c7SXin Ji } 2021cd1637c7SXin Ji 2022cd1637c7SXin Ji return 0; 2023cd1637c7SXin Ji } 2024cd1637c7SXin Ji 20258bdfc5daSXin Ji static int anx7625_bridge_attach(struct drm_bridge *bridge, 20268bdfc5daSXin Ji enum drm_bridge_attach_flags flags) 20278bdfc5daSXin Ji { 20288bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 20298bdfc5daSXin Ji int err; 20308bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 20318bdfc5daSXin Ji 20328bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 20338bdfc5daSXin Ji if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 20348bdfc5daSXin Ji return -EINVAL; 20358bdfc5daSXin Ji 20368bdfc5daSXin Ji if (!bridge->encoder) { 20378bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Parent encoder object not found"); 20388bdfc5daSXin Ji return -ENODEV; 20398bdfc5daSXin Ji } 20408bdfc5daSXin Ji 20418bdfc5daSXin Ji if (ctx->pdata.panel_bridge) { 20428bdfc5daSXin Ji err = drm_bridge_attach(bridge->encoder, 20438bdfc5daSXin Ji ctx->pdata.panel_bridge, 20448bdfc5daSXin Ji &ctx->bridge, flags); 2045fb8d617fSLaurent Pinchart if (err) 20468bdfc5daSXin Ji return err; 20478bdfc5daSXin Ji } 20488bdfc5daSXin Ji 20498bdfc5daSXin Ji ctx->bridge_attached = 1; 20508bdfc5daSXin Ji 20518bdfc5daSXin Ji return 0; 20528bdfc5daSXin Ji } 20538bdfc5daSXin Ji 20548bdfc5daSXin Ji static enum drm_mode_status 20558bdfc5daSXin Ji anx7625_bridge_mode_valid(struct drm_bridge *bridge, 20568bdfc5daSXin Ji const struct drm_display_info *info, 20578bdfc5daSXin Ji const struct drm_display_mode *mode) 20588bdfc5daSXin Ji { 20598bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 20608bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 20618bdfc5daSXin Ji 20628bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 20638bdfc5daSXin Ji 20648bdfc5daSXin Ji /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 20658bdfc5daSXin Ji if (mode->clock > SUPPORT_PIXEL_CLOCK) { 20668bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, 20678bdfc5daSXin Ji "drm mode invalid, pixelclock too high.\n"); 20688bdfc5daSXin Ji return MODE_CLOCK_HIGH; 20698bdfc5daSXin Ji } 20708bdfc5daSXin Ji 20718bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 20728bdfc5daSXin Ji 20738bdfc5daSXin Ji return MODE_OK; 20748bdfc5daSXin Ji } 20758bdfc5daSXin Ji 20768bdfc5daSXin Ji static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 20778bdfc5daSXin Ji const struct drm_display_mode *old_mode, 20788bdfc5daSXin Ji const struct drm_display_mode *mode) 20798bdfc5daSXin Ji { 20808bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 20818bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 20828bdfc5daSXin Ji 20838bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 20848bdfc5daSXin Ji 20858bdfc5daSXin Ji ctx->dt.pixelclock.min = mode->clock; 20868bdfc5daSXin Ji ctx->dt.hactive.min = mode->hdisplay; 20878bdfc5daSXin Ji ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 20888bdfc5daSXin Ji ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 20898bdfc5daSXin Ji ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 20908bdfc5daSXin Ji ctx->dt.vactive.min = mode->vdisplay; 20918bdfc5daSXin Ji ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 20928bdfc5daSXin Ji ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 20938bdfc5daSXin Ji ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 20948bdfc5daSXin Ji 20958bdfc5daSXin Ji ctx->display_timing_valid = 1; 20968bdfc5daSXin Ji 20978bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 20988bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 20998bdfc5daSXin Ji ctx->dt.hactive.min, 21008bdfc5daSXin Ji ctx->dt.hsync_len.min, 21018bdfc5daSXin Ji ctx->dt.hfront_porch.min, 21028bdfc5daSXin Ji ctx->dt.hback_porch.min); 21038bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 21048bdfc5daSXin Ji ctx->dt.vactive.min, 21058bdfc5daSXin Ji ctx->dt.vsync_len.min, 21068bdfc5daSXin Ji ctx->dt.vfront_porch.min, 21078bdfc5daSXin Ji ctx->dt.vback_porch.min); 21088bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 21098bdfc5daSXin Ji mode->hdisplay, 21108bdfc5daSXin Ji mode->hsync_start); 21118bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 21128bdfc5daSXin Ji mode->hsync_end, 21138bdfc5daSXin Ji mode->htotal); 21148bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 21158bdfc5daSXin Ji mode->vdisplay, 21168bdfc5daSXin Ji mode->vsync_start); 21178bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 21188bdfc5daSXin Ji mode->vsync_end, 21198bdfc5daSXin Ji mode->vtotal); 21208bdfc5daSXin Ji } 21218bdfc5daSXin Ji 21228bdfc5daSXin Ji static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 21238bdfc5daSXin Ji const struct drm_display_mode *mode, 21248bdfc5daSXin Ji struct drm_display_mode *adj) 21258bdfc5daSXin Ji { 21268bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 21278bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 21288bdfc5daSXin Ji u32 hsync, hfp, hbp, hblanking; 21298bdfc5daSXin Ji u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 21308bdfc5daSXin Ji u32 vref, adj_clock; 21318bdfc5daSXin Ji 21328bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 21338bdfc5daSXin Ji 2134fd0310b6SXin Ji /* No need fixup for external monitor */ 2135fd0310b6SXin Ji if (!ctx->pdata.panel_bridge) 2136fd0310b6SXin Ji return true; 2137fd0310b6SXin Ji 21388bdfc5daSXin Ji hsync = mode->hsync_end - mode->hsync_start; 21398bdfc5daSXin Ji hfp = mode->hsync_start - mode->hdisplay; 21408bdfc5daSXin Ji hbp = mode->htotal - mode->hsync_end; 21418bdfc5daSXin Ji hblanking = mode->htotal - mode->hdisplay; 21428bdfc5daSXin Ji 21438bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 21448bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 21458bdfc5daSXin Ji hsync, hfp, hbp, adj->clock); 21468bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 21478bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 21488bdfc5daSXin Ji 21498bdfc5daSXin Ji adj_hfp = hfp; 21508bdfc5daSXin Ji adj_hsync = hsync; 21518bdfc5daSXin Ji adj_hbp = hbp; 21528bdfc5daSXin Ji adj_hblanking = hblanking; 21538bdfc5daSXin Ji 21548bdfc5daSXin Ji /* HFP needs to be even */ 21558bdfc5daSXin Ji if (hfp & 0x1) { 21568bdfc5daSXin Ji adj_hfp += 1; 21578bdfc5daSXin Ji adj_hblanking += 1; 21588bdfc5daSXin Ji } 21598bdfc5daSXin Ji 21608bdfc5daSXin Ji /* HBP needs to be even */ 21618bdfc5daSXin Ji if (hbp & 0x1) { 21628bdfc5daSXin Ji adj_hbp -= 1; 21638bdfc5daSXin Ji adj_hblanking -= 1; 21648bdfc5daSXin Ji } 21658bdfc5daSXin Ji 21668bdfc5daSXin Ji /* HSYNC needs to be even */ 21678bdfc5daSXin Ji if (hsync & 0x1) { 21688bdfc5daSXin Ji if (adj_hblanking < hblanking) 21698bdfc5daSXin Ji adj_hsync += 1; 21708bdfc5daSXin Ji else 21718bdfc5daSXin Ji adj_hsync -= 1; 21728bdfc5daSXin Ji } 21738bdfc5daSXin Ji 21748bdfc5daSXin Ji /* 21758bdfc5daSXin Ji * Once illegal timing detected, use default HFP, HSYNC, HBP 21768bdfc5daSXin Ji * This adjusting made for built-in eDP panel, for the externel 21778bdfc5daSXin Ji * DP monitor, may need return false. 21788bdfc5daSXin Ji */ 21798bdfc5daSXin Ji if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 21808bdfc5daSXin Ji adj_hsync = SYNC_LEN_DEF; 21818bdfc5daSXin Ji adj_hfp = HFP_HBP_DEF; 21828bdfc5daSXin Ji adj_hbp = HFP_HBP_DEF; 21838bdfc5daSXin Ji vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 21848bdfc5daSXin Ji if (hblanking < HBLANKING_MIN) { 21858bdfc5daSXin Ji delta_adj = HBLANKING_MIN - hblanking; 21868bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 21878bdfc5daSXin Ji adj->clock += DIV_ROUND_UP(adj_clock, 1000); 21888bdfc5daSXin Ji } else { 21898bdfc5daSXin Ji delta_adj = hblanking - HBLANKING_MIN; 21908bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 21918bdfc5daSXin Ji adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 21928bdfc5daSXin Ji } 21938bdfc5daSXin Ji 21948bdfc5daSXin Ji DRM_WARN("illegal hblanking timing, use default.\n"); 21958bdfc5daSXin Ji DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 21968bdfc5daSXin Ji } else if (adj_hfp < HP_MIN) { 21978bdfc5daSXin Ji /* Adjust hfp if hfp less than HP_MIN */ 21988bdfc5daSXin Ji delta_adj = HP_MIN - adj_hfp; 21998bdfc5daSXin Ji adj_hfp = HP_MIN; 22008bdfc5daSXin Ji 22018bdfc5daSXin Ji /* 22028bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP does not have enough 22038bdfc5daSXin Ji * space, adjust HSYNC length, otherwise adjust HBP 22048bdfc5daSXin Ji */ 22058bdfc5daSXin Ji if ((adj_hbp - delta_adj) < HP_MIN) 22068bdfc5daSXin Ji /* HBP not enough space */ 22078bdfc5daSXin Ji adj_hsync -= delta_adj; 22088bdfc5daSXin Ji else 22098bdfc5daSXin Ji adj_hbp -= delta_adj; 22108bdfc5daSXin Ji } else if (adj_hbp < HP_MIN) { 22118bdfc5daSXin Ji delta_adj = HP_MIN - adj_hbp; 22128bdfc5daSXin Ji adj_hbp = HP_MIN; 22138bdfc5daSXin Ji 22148bdfc5daSXin Ji /* 22158bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP hasn't enough space, 22168bdfc5daSXin Ji * adjust HSYNC length, otherwize adjust HBP 22178bdfc5daSXin Ji */ 22188bdfc5daSXin Ji if ((adj_hfp - delta_adj) < HP_MIN) 22198bdfc5daSXin Ji /* HFP not enough space */ 22208bdfc5daSXin Ji adj_hsync -= delta_adj; 22218bdfc5daSXin Ji else 22228bdfc5daSXin Ji adj_hfp -= delta_adj; 22238bdfc5daSXin Ji } 22248bdfc5daSXin Ji 22258bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 22268bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 22278bdfc5daSXin Ji adj_hsync, adj_hfp, adj_hbp, adj->clock); 22288bdfc5daSXin Ji 22298bdfc5daSXin Ji /* Reconstruct timing */ 22308bdfc5daSXin Ji adj->hsync_start = adj->hdisplay + adj_hfp; 22318bdfc5daSXin Ji adj->hsync_end = adj->hsync_start + adj_hsync; 22328bdfc5daSXin Ji adj->htotal = adj->hsync_end + adj_hbp; 22338bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 22348bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 22358bdfc5daSXin Ji 22368bdfc5daSXin Ji return true; 22378bdfc5daSXin Ji } 22388bdfc5daSXin Ji 2239191be002SXin Ji static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2240191be002SXin Ji struct drm_bridge_state *bridge_state, 2241191be002SXin Ji struct drm_crtc_state *crtc_state, 2242191be002SXin Ji struct drm_connector_state *conn_state) 22438bdfc5daSXin Ji { 22448bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 22458bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 22468bdfc5daSXin Ji 2247191be002SXin Ji dev_dbg(dev, "drm bridge atomic check\n"); 2248cd1637c7SXin Ji 2249cd1637c7SXin Ji anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2250191be002SXin Ji &crtc_state->adjusted_mode); 2251cd1637c7SXin Ji 2252cd1637c7SXin Ji return anx7625_connector_atomic_check(ctx, conn_state); 2253191be002SXin Ji } 2254191be002SXin Ji 2255191be002SXin Ji static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2256191be002SXin Ji struct drm_bridge_state *state) 2257191be002SXin Ji { 2258191be002SXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2259191be002SXin Ji struct device *dev = &ctx->client->dev; 2260191be002SXin Ji struct drm_connector *connector; 2261191be002SXin Ji 2262191be002SXin Ji dev_dbg(dev, "drm atomic enable\n"); 2263191be002SXin Ji 2264191be002SXin Ji if (!bridge->encoder) { 2265191be002SXin Ji dev_err(dev, "Parent encoder object not found"); 2266191be002SXin Ji return; 2267191be002SXin Ji } 2268191be002SXin Ji 2269191be002SXin Ji connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2270191be002SXin Ji bridge->encoder); 2271191be002SXin Ji if (!connector) 2272191be002SXin Ji return; 2273191be002SXin Ji 2274191be002SXin Ji ctx->connector = connector; 22758bdfc5daSXin Ji 227660487584SPi-Hsun Shih pm_runtime_get_sync(dev); 22778bdfc5daSXin Ji 22788bdfc5daSXin Ji anx7625_dp_start(ctx); 22798bdfc5daSXin Ji } 22808bdfc5daSXin Ji 2281191be002SXin Ji static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2282191be002SXin Ji struct drm_bridge_state *old) 22838bdfc5daSXin Ji { 22848bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 22858bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 22868bdfc5daSXin Ji 2287191be002SXin Ji dev_dbg(dev, "drm atomic disable\n"); 22888bdfc5daSXin Ji 2289191be002SXin Ji ctx->connector = NULL; 22908bdfc5daSXin Ji anx7625_dp_stop(ctx); 22918bdfc5daSXin Ji 22923203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 22938bdfc5daSXin Ji } 22948bdfc5daSXin Ji 22958bdfc5daSXin Ji static enum drm_connector_status 22968bdfc5daSXin Ji anx7625_bridge_detect(struct drm_bridge *bridge) 22978bdfc5daSXin Ji { 22988bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 22998bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 23008bdfc5daSXin Ji 23018bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 23028bdfc5daSXin Ji 23038bdfc5daSXin Ji return anx7625_sink_detect(ctx); 23048bdfc5daSXin Ji } 23058bdfc5daSXin Ji 23068bdfc5daSXin Ji static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 23078bdfc5daSXin Ji struct drm_connector *connector) 23088bdfc5daSXin Ji { 23098bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 23108bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 23118bdfc5daSXin Ji 23128bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 23138bdfc5daSXin Ji 23148bdfc5daSXin Ji return anx7625_get_edid(ctx); 23158bdfc5daSXin Ji } 23168bdfc5daSXin Ji 23178bdfc5daSXin Ji static const struct drm_bridge_funcs anx7625_bridge_funcs = { 23188bdfc5daSXin Ji .attach = anx7625_bridge_attach, 23198bdfc5daSXin Ji .mode_valid = anx7625_bridge_mode_valid, 23208bdfc5daSXin Ji .mode_set = anx7625_bridge_mode_set, 2321191be002SXin Ji .atomic_check = anx7625_bridge_atomic_check, 2322191be002SXin Ji .atomic_enable = anx7625_bridge_atomic_enable, 2323191be002SXin Ji .atomic_disable = anx7625_bridge_atomic_disable, 2324191be002SXin Ji .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2325191be002SXin Ji .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2326191be002SXin Ji .atomic_reset = drm_atomic_helper_bridge_reset, 23278bdfc5daSXin Ji .detect = anx7625_bridge_detect, 23288bdfc5daSXin Ji .get_edid = anx7625_bridge_get_edid, 23298bdfc5daSXin Ji }; 23308bdfc5daSXin Ji 23318bdfc5daSXin Ji static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 23328bdfc5daSXin Ji struct i2c_client *client) 23338bdfc5daSXin Ji { 2334f5f05ddcSMiaoqian Lin int err = 0; 2335f5f05ddcSMiaoqian Lin 23368bdfc5daSXin Ji ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 23378bdfc5daSXin Ji TX_P0_ADDR >> 1); 2338f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p0_client)) 2339f5f05ddcSMiaoqian Lin return PTR_ERR(ctx->i2c.tx_p0_client); 23408bdfc5daSXin Ji 23418bdfc5daSXin Ji ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 23428bdfc5daSXin Ji TX_P1_ADDR >> 1); 2343f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p1_client)) { 2344f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tx_p1_client); 23458bdfc5daSXin Ji goto free_tx_p0; 2346f5f05ddcSMiaoqian Lin } 23478bdfc5daSXin Ji 23488bdfc5daSXin Ji ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 23498bdfc5daSXin Ji TX_P2_ADDR >> 1); 2350f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p2_client)) { 2351f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tx_p2_client); 23528bdfc5daSXin Ji goto free_tx_p1; 2353f5f05ddcSMiaoqian Lin } 23548bdfc5daSXin Ji 23558bdfc5daSXin Ji ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 23568bdfc5daSXin Ji RX_P0_ADDR >> 1); 2357f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p0_client)) { 2358f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p0_client); 23598bdfc5daSXin Ji goto free_tx_p2; 2360f5f05ddcSMiaoqian Lin } 23618bdfc5daSXin Ji 23628bdfc5daSXin Ji ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 23638bdfc5daSXin Ji RX_P1_ADDR >> 1); 2364f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p1_client)) { 2365f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p1_client); 23668bdfc5daSXin Ji goto free_rx_p0; 2367f5f05ddcSMiaoqian Lin } 23688bdfc5daSXin Ji 23698bdfc5daSXin Ji ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 23708bdfc5daSXin Ji RX_P2_ADDR >> 1); 2371f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p2_client)) { 2372f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p2_client); 23738bdfc5daSXin Ji goto free_rx_p1; 2374f5f05ddcSMiaoqian Lin } 23758bdfc5daSXin Ji 23768bdfc5daSXin Ji ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 23778bdfc5daSXin Ji TCPC_INTERFACE_ADDR >> 1); 2378f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tcpc_client)) { 2379f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tcpc_client); 23808bdfc5daSXin Ji goto free_rx_p2; 2381f5f05ddcSMiaoqian Lin } 23828bdfc5daSXin Ji 23838bdfc5daSXin Ji return 0; 23848bdfc5daSXin Ji 23858bdfc5daSXin Ji free_rx_p2: 23868bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 23878bdfc5daSXin Ji free_rx_p1: 23888bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 23898bdfc5daSXin Ji free_rx_p0: 23908bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 23918bdfc5daSXin Ji free_tx_p2: 23928bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 23938bdfc5daSXin Ji free_tx_p1: 23948bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 23958bdfc5daSXin Ji free_tx_p0: 23968bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 23978bdfc5daSXin Ji 2398f5f05ddcSMiaoqian Lin return err; 23998bdfc5daSXin Ji } 24008bdfc5daSXin Ji 24018bdfc5daSXin Ji static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 24028bdfc5daSXin Ji { 24038bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 24048bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 24058bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 24068bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 24078bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 24088bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 24098bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tcpc_client); 24108bdfc5daSXin Ji } 24118bdfc5daSXin Ji 241260487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 241360487584SPi-Hsun Shih { 241460487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 241560487584SPi-Hsun Shih 241660487584SPi-Hsun Shih mutex_lock(&ctx->lock); 241760487584SPi-Hsun Shih 241860487584SPi-Hsun Shih anx7625_stop_dp_work(ctx); 241960487584SPi-Hsun Shih anx7625_power_standby(ctx); 242060487584SPi-Hsun Shih 242160487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 242260487584SPi-Hsun Shih 242360487584SPi-Hsun Shih return 0; 242460487584SPi-Hsun Shih } 242560487584SPi-Hsun Shih 242660487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 242760487584SPi-Hsun Shih { 242860487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 242960487584SPi-Hsun Shih 243060487584SPi-Hsun Shih mutex_lock(&ctx->lock); 243160487584SPi-Hsun Shih 243260487584SPi-Hsun Shih anx7625_power_on_init(ctx); 243360487584SPi-Hsun Shih anx7625_hpd_polling(ctx); 243460487584SPi-Hsun Shih 243560487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 243660487584SPi-Hsun Shih 243760487584SPi-Hsun Shih return 0; 243860487584SPi-Hsun Shih } 243960487584SPi-Hsun Shih 2440409776faSPi-Hsun Shih static int __maybe_unused anx7625_resume(struct device *dev) 2441409776faSPi-Hsun Shih { 2442409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 2443409776faSPi-Hsun Shih 2444409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 2445409776faSPi-Hsun Shih return 0; 2446409776faSPi-Hsun Shih 2447409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2448409776faSPi-Hsun Shih enable_irq(ctx->pdata.intp_irq); 2449409776faSPi-Hsun Shih anx7625_runtime_pm_resume(dev); 2450409776faSPi-Hsun Shih } 2451409776faSPi-Hsun Shih 2452409776faSPi-Hsun Shih return 0; 2453409776faSPi-Hsun Shih } 2454409776faSPi-Hsun Shih 2455409776faSPi-Hsun Shih static int __maybe_unused anx7625_suspend(struct device *dev) 2456409776faSPi-Hsun Shih { 2457409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 2458409776faSPi-Hsun Shih 2459409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 2460409776faSPi-Hsun Shih return 0; 2461409776faSPi-Hsun Shih 2462409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2463409776faSPi-Hsun Shih anx7625_runtime_pm_suspend(dev); 2464409776faSPi-Hsun Shih disable_irq(ctx->pdata.intp_irq); 2465409776faSPi-Hsun Shih } 2466409776faSPi-Hsun Shih 2467409776faSPi-Hsun Shih return 0; 2468409776faSPi-Hsun Shih } 2469409776faSPi-Hsun Shih 247060487584SPi-Hsun Shih static const struct dev_pm_ops anx7625_pm_ops = { 2471409776faSPi-Hsun Shih SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 247260487584SPi-Hsun Shih SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 247360487584SPi-Hsun Shih anx7625_runtime_pm_resume, NULL) 247460487584SPi-Hsun Shih }; 247560487584SPi-Hsun Shih 24768bdfc5daSXin Ji static int anx7625_i2c_probe(struct i2c_client *client, 24778bdfc5daSXin Ji const struct i2c_device_id *id) 24788bdfc5daSXin Ji { 24798bdfc5daSXin Ji struct anx7625_data *platform; 24808bdfc5daSXin Ji struct anx7625_platform_data *pdata; 24818bdfc5daSXin Ji int ret = 0; 24828bdfc5daSXin Ji struct device *dev = &client->dev; 24838bdfc5daSXin Ji 24848bdfc5daSXin Ji if (!i2c_check_functionality(client->adapter, 24858bdfc5daSXin Ji I2C_FUNC_SMBUS_I2C_BLOCK)) { 24868bdfc5daSXin Ji DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 24878bdfc5daSXin Ji return -ENODEV; 24888bdfc5daSXin Ji } 24898bdfc5daSXin Ji 24908bdfc5daSXin Ji platform = kzalloc(sizeof(*platform), GFP_KERNEL); 24918bdfc5daSXin Ji if (!platform) { 24928bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 24938bdfc5daSXin Ji return -ENOMEM; 24948bdfc5daSXin Ji } 24958bdfc5daSXin Ji 24968bdfc5daSXin Ji pdata = &platform->pdata; 24978bdfc5daSXin Ji 24988bdfc5daSXin Ji ret = anx7625_parse_dt(dev, pdata); 24998bdfc5daSXin Ji if (ret) { 25008bdfc5daSXin Ji if (ret != -EPROBE_DEFER) 25018bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 25028bdfc5daSXin Ji goto free_platform; 25038bdfc5daSXin Ji } 25048bdfc5daSXin Ji 25058bdfc5daSXin Ji platform->client = client; 25068bdfc5daSXin Ji i2c_set_clientdata(client, platform); 25078bdfc5daSXin Ji 25086c744983SHsin-Yi Wang pdata->supplies[0].supply = "vdd10"; 25096c744983SHsin-Yi Wang pdata->supplies[1].supply = "vdd18"; 25106c744983SHsin-Yi Wang pdata->supplies[2].supply = "vdd33"; 25116c744983SHsin-Yi Wang ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 25126c744983SHsin-Yi Wang pdata->supplies); 25136c744983SHsin-Yi Wang if (ret) { 25146c744983SHsin-Yi Wang DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 25156c744983SHsin-Yi Wang return ret; 25166c744983SHsin-Yi Wang } 25178bdfc5daSXin Ji anx7625_init_gpio(platform); 25188bdfc5daSXin Ji 25198bdfc5daSXin Ji mutex_init(&platform->lock); 2520cd1637c7SXin Ji mutex_init(&platform->hdcp_wq_lock); 2521cd1637c7SXin Ji 2522cd1637c7SXin Ji INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2523cd1637c7SXin Ji platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2524cd1637c7SXin Ji if (!platform->hdcp_workqueue) { 2525cd1637c7SXin Ji dev_err(dev, "fail to create work queue\n"); 2526cd1637c7SXin Ji ret = -ENOMEM; 2527cd1637c7SXin Ji goto free_platform; 2528cd1637c7SXin Ji } 25298bdfc5daSXin Ji 25308bdfc5daSXin Ji platform->pdata.intp_irq = client->irq; 25318bdfc5daSXin Ji if (platform->pdata.intp_irq) { 25328bdfc5daSXin Ji INIT_WORK(&platform->work, anx7625_work_func); 2533f03ab662SPi-Hsun Shih platform->workqueue = alloc_workqueue("anx7625_work", 2534f03ab662SPi-Hsun Shih WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 25358bdfc5daSXin Ji if (!platform->workqueue) { 25368bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create work queue\n"); 25378bdfc5daSXin Ji ret = -ENOMEM; 2538cd1637c7SXin Ji goto free_hdcp_wq; 25398bdfc5daSXin Ji } 25408bdfc5daSXin Ji 25418bdfc5daSXin Ji ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 25428bdfc5daSXin Ji NULL, anx7625_intr_hpd_isr, 25438bdfc5daSXin Ji IRQF_TRIGGER_FALLING | 25448bdfc5daSXin Ji IRQF_ONESHOT, 25458bdfc5daSXin Ji "anx7625-intp", platform); 25468bdfc5daSXin Ji if (ret) { 25478bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to request irq\n"); 25488bdfc5daSXin Ji goto free_wq; 25498bdfc5daSXin Ji } 25508bdfc5daSXin Ji } 25518bdfc5daSXin Ji 25528bdfc5daSXin Ji if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 25538bdfc5daSXin Ji ret = -ENOMEM; 25548bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 25558bdfc5daSXin Ji goto free_wq; 25568bdfc5daSXin Ji } 25578bdfc5daSXin Ji 255860487584SPi-Hsun Shih pm_runtime_enable(dev); 255960487584SPi-Hsun Shih 256060487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) { 25618bdfc5daSXin Ji anx7625_disable_pd_protocol(platform); 256260487584SPi-Hsun Shih pm_runtime_get_sync(dev); 25638bdfc5daSXin Ji } 25648bdfc5daSXin Ji 25658bdfc5daSXin Ji /* Add work function */ 25668bdfc5daSXin Ji if (platform->pdata.intp_irq) 25678bdfc5daSXin Ji queue_work(platform->workqueue, &platform->work); 25688bdfc5daSXin Ji 25698bdfc5daSXin Ji platform->bridge.funcs = &anx7625_bridge_funcs; 25708bdfc5daSXin Ji platform->bridge.of_node = client->dev.of_node; 2571fd0310b6SXin Ji platform->bridge.ops = DRM_BRIDGE_OP_EDID; 2572fd0310b6SXin Ji if (!platform->pdata.panel_bridge) 2573fd0310b6SXin Ji platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2574fd0310b6SXin Ji DRM_BRIDGE_OP_DETECT; 2575fd0310b6SXin Ji platform->bridge.type = platform->pdata.panel_bridge ? 2576fd0310b6SXin Ji DRM_MODE_CONNECTOR_eDP : 2577fd0310b6SXin Ji DRM_MODE_CONNECTOR_DisplayPort; 2578fd0310b6SXin Ji 25798bdfc5daSXin Ji drm_bridge_add(&platform->bridge); 25808bdfc5daSXin Ji 2581fd0310b6SXin Ji if (!platform->pdata.is_dpi) { 258249e61beeSMaxime Ripard ret = anx7625_attach_dsi(platform); 258349e61beeSMaxime Ripard if (ret) { 258449e61beeSMaxime Ripard DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 258549e61beeSMaxime Ripard goto unregister_bridge; 258649e61beeSMaxime Ripard } 2587fd0310b6SXin Ji } 258849e61beeSMaxime Ripard 2589566fef12SXin Ji if (platform->pdata.audio_en) 2590566fef12SXin Ji anx7625_register_audio(dev, platform); 2591566fef12SXin Ji 25928bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 25938bdfc5daSXin Ji 25948bdfc5daSXin Ji return 0; 25958bdfc5daSXin Ji 259649e61beeSMaxime Ripard unregister_bridge: 259749e61beeSMaxime Ripard drm_bridge_remove(&platform->bridge); 259849e61beeSMaxime Ripard 259949e61beeSMaxime Ripard if (!platform->pdata.low_power_mode) 260049e61beeSMaxime Ripard pm_runtime_put_sync_suspend(&client->dev); 260149e61beeSMaxime Ripard 260249e61beeSMaxime Ripard anx7625_unregister_i2c_dummy_clients(platform); 260349e61beeSMaxime Ripard 26048bdfc5daSXin Ji free_wq: 26058bdfc5daSXin Ji if (platform->workqueue) 26068bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 26078bdfc5daSXin Ji 2608cd1637c7SXin Ji free_hdcp_wq: 2609cd1637c7SXin Ji if (platform->hdcp_workqueue) 2610cd1637c7SXin Ji destroy_workqueue(platform->hdcp_workqueue); 2611cd1637c7SXin Ji 26128bdfc5daSXin Ji free_platform: 26138bdfc5daSXin Ji kfree(platform); 26148bdfc5daSXin Ji 26158bdfc5daSXin Ji return ret; 26168bdfc5daSXin Ji } 26178bdfc5daSXin Ji 26188bdfc5daSXin Ji static int anx7625_i2c_remove(struct i2c_client *client) 26198bdfc5daSXin Ji { 26208bdfc5daSXin Ji struct anx7625_data *platform = i2c_get_clientdata(client); 26218bdfc5daSXin Ji 26228bdfc5daSXin Ji drm_bridge_remove(&platform->bridge); 26238bdfc5daSXin Ji 26248bdfc5daSXin Ji if (platform->pdata.intp_irq) 26258bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 26268bdfc5daSXin Ji 2627cd1637c7SXin Ji if (platform->hdcp_workqueue) { 2628cd1637c7SXin Ji cancel_delayed_work(&platform->hdcp_work); 2629cd1637c7SXin Ji flush_workqueue(platform->workqueue); 2630cd1637c7SXin Ji destroy_workqueue(platform->workqueue); 2631cd1637c7SXin Ji } 2632cd1637c7SXin Ji 263360487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) 263460487584SPi-Hsun Shih pm_runtime_put_sync_suspend(&client->dev); 263560487584SPi-Hsun Shih 26368bdfc5daSXin Ji anx7625_unregister_i2c_dummy_clients(platform); 26378bdfc5daSXin Ji 2638566fef12SXin Ji if (platform->pdata.audio_en) 2639566fef12SXin Ji anx7625_unregister_audio(platform); 2640566fef12SXin Ji 26418bdfc5daSXin Ji kfree(platform); 26428bdfc5daSXin Ji return 0; 26438bdfc5daSXin Ji } 26448bdfc5daSXin Ji 26458bdfc5daSXin Ji static const struct i2c_device_id anx7625_id[] = { 26468bdfc5daSXin Ji {"anx7625", 0}, 26478bdfc5daSXin Ji {} 26488bdfc5daSXin Ji }; 26498bdfc5daSXin Ji 26508bdfc5daSXin Ji MODULE_DEVICE_TABLE(i2c, anx7625_id); 26518bdfc5daSXin Ji 26528bdfc5daSXin Ji static const struct of_device_id anx_match_table[] = { 26538bdfc5daSXin Ji {.compatible = "analogix,anx7625",}, 26548bdfc5daSXin Ji {}, 26558bdfc5daSXin Ji }; 2656ad5fd900SYu Jiahua MODULE_DEVICE_TABLE(of, anx_match_table); 26578bdfc5daSXin Ji 26588bdfc5daSXin Ji static struct i2c_driver anx7625_driver = { 26598bdfc5daSXin Ji .driver = { 26608bdfc5daSXin Ji .name = "anx7625", 26618bdfc5daSXin Ji .of_match_table = anx_match_table, 266260487584SPi-Hsun Shih .pm = &anx7625_pm_ops, 26638bdfc5daSXin Ji }, 26648bdfc5daSXin Ji .probe = anx7625_i2c_probe, 26658bdfc5daSXin Ji .remove = anx7625_i2c_remove, 26668bdfc5daSXin Ji 26678bdfc5daSXin Ji .id_table = anx7625_id, 26688bdfc5daSXin Ji }; 26698bdfc5daSXin Ji 26708bdfc5daSXin Ji module_i2c_driver(anx7625_driver); 26718bdfc5daSXin Ji 26728bdfc5daSXin Ji MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 26738bdfc5daSXin Ji MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 26748bdfc5daSXin Ji MODULE_LICENSE("GPL v2"); 26758bdfc5daSXin Ji MODULE_VERSION(ANX7625_DRV_VERSION); 2676