18bdfc5daSXin Ji // SPDX-License-Identifier: GPL-2.0-only 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji #include <linux/gcd.h> 78bdfc5daSXin Ji #include <linux/gpio/consumer.h> 88bdfc5daSXin Ji #include <linux/i2c.h> 98bdfc5daSXin Ji #include <linux/interrupt.h> 108bdfc5daSXin Ji #include <linux/iopoll.h> 118bdfc5daSXin Ji #include <linux/kernel.h> 128bdfc5daSXin Ji #include <linux/module.h> 138bdfc5daSXin Ji #include <linux/mutex.h> 1460487584SPi-Hsun Shih #include <linux/pm_runtime.h> 156c744983SHsin-Yi Wang #include <linux/regulator/consumer.h> 168bdfc5daSXin Ji #include <linux/slab.h> 178bdfc5daSXin Ji #include <linux/types.h> 188bdfc5daSXin Ji #include <linux/workqueue.h> 198bdfc5daSXin Ji 208bdfc5daSXin Ji #include <linux/of_gpio.h> 218bdfc5daSXin Ji #include <linux/of_graph.h> 228bdfc5daSXin Ji #include <linux/of_platform.h> 238bdfc5daSXin Ji 248bdfc5daSXin Ji #include <drm/drm_atomic_helper.h> 258bdfc5daSXin Ji #include <drm/drm_bridge.h> 268bdfc5daSXin Ji #include <drm/drm_crtc_helper.h> 275b529e8dSThomas Zimmermann #include <drm/dp/drm_dp_helper.h> 288bdfc5daSXin Ji #include <drm/drm_edid.h> 29cd1637c7SXin Ji #include <drm/drm_hdcp.h> 308bdfc5daSXin Ji #include <drm/drm_mipi_dsi.h> 318bdfc5daSXin Ji #include <drm/drm_of.h> 328bdfc5daSXin Ji #include <drm/drm_panel.h> 338bdfc5daSXin Ji #include <drm/drm_print.h> 348bdfc5daSXin Ji #include <drm/drm_probe_helper.h> 358bdfc5daSXin Ji 36fd0310b6SXin Ji #include <media/v4l2-fwnode.h> 37566fef12SXin Ji #include <sound/hdmi-codec.h> 388bdfc5daSXin Ji #include <video/display_timing.h> 398bdfc5daSXin Ji 408bdfc5daSXin Ji #include "anx7625.h" 418bdfc5daSXin Ji 428bdfc5daSXin Ji /* 438bdfc5daSXin Ji * There is a sync issue while access I2C register between AP(CPU) and 448bdfc5daSXin Ji * internal firmware(OCM), to avoid the race condition, AP should access 458bdfc5daSXin Ji * the reserved slave address before slave address occurs changes. 468bdfc5daSXin Ji */ 478bdfc5daSXin Ji static int i2c_access_workaround(struct anx7625_data *ctx, 488bdfc5daSXin Ji struct i2c_client *client) 498bdfc5daSXin Ji { 508bdfc5daSXin Ji u8 offset; 518bdfc5daSXin Ji struct device *dev = &client->dev; 528bdfc5daSXin Ji int ret; 538bdfc5daSXin Ji 548bdfc5daSXin Ji if (client == ctx->last_client) 558bdfc5daSXin Ji return 0; 568bdfc5daSXin Ji 578bdfc5daSXin Ji ctx->last_client = client; 588bdfc5daSXin Ji 598bdfc5daSXin Ji if (client == ctx->i2c.tcpc_client) 608bdfc5daSXin Ji offset = RSVD_00_ADDR; 618bdfc5daSXin Ji else if (client == ctx->i2c.tx_p0_client) 628bdfc5daSXin Ji offset = RSVD_D1_ADDR; 638bdfc5daSXin Ji else if (client == ctx->i2c.tx_p1_client) 648bdfc5daSXin Ji offset = RSVD_60_ADDR; 658bdfc5daSXin Ji else if (client == ctx->i2c.rx_p0_client) 668bdfc5daSXin Ji offset = RSVD_39_ADDR; 678bdfc5daSXin Ji else if (client == ctx->i2c.rx_p1_client) 688bdfc5daSXin Ji offset = RSVD_7F_ADDR; 698bdfc5daSXin Ji else 708bdfc5daSXin Ji offset = RSVD_00_ADDR; 718bdfc5daSXin Ji 728bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, offset, 0x00); 738bdfc5daSXin Ji if (ret < 0) 748bdfc5daSXin Ji DRM_DEV_ERROR(dev, 758bdfc5daSXin Ji "fail to access i2c id=%x\n:%x", 768bdfc5daSXin Ji client->addr, offset); 778bdfc5daSXin Ji 788bdfc5daSXin Ji return ret; 798bdfc5daSXin Ji } 808bdfc5daSXin Ji 818bdfc5daSXin Ji static int anx7625_reg_read(struct anx7625_data *ctx, 828bdfc5daSXin Ji struct i2c_client *client, u8 reg_addr) 838bdfc5daSXin Ji { 848bdfc5daSXin Ji int ret; 858bdfc5daSXin Ji struct device *dev = &client->dev; 868bdfc5daSXin Ji 878bdfc5daSXin Ji i2c_access_workaround(ctx, client); 888bdfc5daSXin Ji 898bdfc5daSXin Ji ret = i2c_smbus_read_byte_data(client, reg_addr); 908bdfc5daSXin Ji if (ret < 0) 918bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 928bdfc5daSXin Ji client->addr, reg_addr); 938bdfc5daSXin Ji 948bdfc5daSXin Ji return ret; 958bdfc5daSXin Ji } 968bdfc5daSXin Ji 978bdfc5daSXin Ji static int anx7625_reg_block_read(struct anx7625_data *ctx, 988bdfc5daSXin Ji struct i2c_client *client, 998bdfc5daSXin Ji u8 reg_addr, u8 len, u8 *buf) 1008bdfc5daSXin Ji { 1018bdfc5daSXin Ji int ret; 1028bdfc5daSXin Ji struct device *dev = &client->dev; 1038bdfc5daSXin Ji 1048bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1058bdfc5daSXin Ji 1068bdfc5daSXin Ji ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 1078bdfc5daSXin Ji if (ret < 0) 1088bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 1098bdfc5daSXin Ji client->addr, reg_addr); 1108bdfc5daSXin Ji 1118bdfc5daSXin Ji return ret; 1128bdfc5daSXin Ji } 1138bdfc5daSXin Ji 1148bdfc5daSXin Ji static int anx7625_reg_write(struct anx7625_data *ctx, 1158bdfc5daSXin Ji struct i2c_client *client, 1168bdfc5daSXin Ji u8 reg_addr, u8 reg_val) 1178bdfc5daSXin Ji { 1188bdfc5daSXin Ji int ret; 1198bdfc5daSXin Ji struct device *dev = &client->dev; 1208bdfc5daSXin Ji 1218bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1228bdfc5daSXin Ji 1238bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 1248bdfc5daSXin Ji 1258bdfc5daSXin Ji if (ret < 0) 1268bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 1278bdfc5daSXin Ji client->addr, reg_addr); 1288bdfc5daSXin Ji 1298bdfc5daSXin Ji return ret; 1308bdfc5daSXin Ji } 1318bdfc5daSXin Ji 132*548b512eSXin Ji static int anx7625_reg_block_write(struct anx7625_data *ctx, 133*548b512eSXin Ji struct i2c_client *client, 134*548b512eSXin Ji u8 reg_addr, u8 len, u8 *buf) 135*548b512eSXin Ji { 136*548b512eSXin Ji int ret; 137*548b512eSXin Ji struct device *dev = &client->dev; 138*548b512eSXin Ji 139*548b512eSXin Ji i2c_access_workaround(ctx, client); 140*548b512eSXin Ji 141*548b512eSXin Ji ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 142*548b512eSXin Ji if (ret < 0) 143*548b512eSXin Ji dev_err(dev, "write i2c block failed id=%x\n:%x", 144*548b512eSXin Ji client->addr, reg_addr); 145*548b512eSXin Ji 146*548b512eSXin Ji return ret; 147*548b512eSXin Ji } 148*548b512eSXin Ji 1498bdfc5daSXin Ji static int anx7625_write_or(struct anx7625_data *ctx, 1508bdfc5daSXin Ji struct i2c_client *client, 1518bdfc5daSXin Ji u8 offset, u8 mask) 1528bdfc5daSXin Ji { 1538bdfc5daSXin Ji int val; 1548bdfc5daSXin Ji 1558bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1568bdfc5daSXin Ji if (val < 0) 1578bdfc5daSXin Ji return val; 1588bdfc5daSXin Ji 1598bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val | (mask))); 1608bdfc5daSXin Ji } 1618bdfc5daSXin Ji 1628bdfc5daSXin Ji static int anx7625_write_and(struct anx7625_data *ctx, 1638bdfc5daSXin Ji struct i2c_client *client, 1648bdfc5daSXin Ji u8 offset, u8 mask) 1658bdfc5daSXin Ji { 1668bdfc5daSXin Ji int val; 1678bdfc5daSXin Ji 1688bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1698bdfc5daSXin Ji if (val < 0) 1708bdfc5daSXin Ji return val; 1718bdfc5daSXin Ji 1728bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val & (mask))); 1738bdfc5daSXin Ji } 1748bdfc5daSXin Ji 175566fef12SXin Ji static int anx7625_write_and_or(struct anx7625_data *ctx, 176566fef12SXin Ji struct i2c_client *client, 177566fef12SXin Ji u8 offset, u8 and_mask, u8 or_mask) 178566fef12SXin Ji { 179566fef12SXin Ji int val; 180566fef12SXin Ji 181566fef12SXin Ji val = anx7625_reg_read(ctx, client, offset); 182566fef12SXin Ji if (val < 0) 183566fef12SXin Ji return val; 184566fef12SXin Ji 185566fef12SXin Ji return anx7625_reg_write(ctx, client, 186566fef12SXin Ji offset, (val & and_mask) | (or_mask)); 187566fef12SXin Ji } 188566fef12SXin Ji 189fd0310b6SXin Ji static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 1908bdfc5daSXin Ji { 191fd0310b6SXin Ji int i, ret; 1928bdfc5daSXin Ji 193fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 194fd0310b6SXin Ji AUDIO_CONTROL_REGISTER, 0x80); 195fd0310b6SXin Ji for (i = 0; i < 13; i++) 196fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 197fd0310b6SXin Ji VIDEO_BIT_MATRIX_12 + i, 198fd0310b6SXin Ji 0x18 + i); 1998bdfc5daSXin Ji 200fd0310b6SXin Ji return ret; 2018bdfc5daSXin Ji } 2028bdfc5daSXin Ji 2038bdfc5daSXin Ji static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 2048bdfc5daSXin Ji { 2058bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 2068bdfc5daSXin Ji } 2078bdfc5daSXin Ji 2088bdfc5daSXin Ji static int wait_aux_op_finish(struct anx7625_data *ctx) 2098bdfc5daSXin Ji { 2108bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 2118bdfc5daSXin Ji int val; 2128bdfc5daSXin Ji int ret; 2138bdfc5daSXin Ji 2148bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 2158bdfc5daSXin Ji ctx, val, 2168bdfc5daSXin Ji (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 2178bdfc5daSXin Ji 2000, 2188bdfc5daSXin Ji 2000 * 150); 2198bdfc5daSXin Ji if (ret) { 2208bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux operation fail!\n"); 2218bdfc5daSXin Ji return -EIO; 2228bdfc5daSXin Ji } 2238bdfc5daSXin Ji 2248bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 2258bdfc5daSXin Ji AP_AUX_CTRL_STATUS); 2268bdfc5daSXin Ji if (val < 0 || (val & 0x0F)) { 2278bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux status %02x\n", val); 2289a7e49bdSXin Ji return -EIO; 2298bdfc5daSXin Ji } 2308bdfc5daSXin Ji 2319a7e49bdSXin Ji return 0; 2328bdfc5daSXin Ji } 2338bdfc5daSXin Ji 234*548b512eSXin Ji static int anx7625_aux_dpcd_trans(struct anx7625_data *ctx, u8 op, 235cd1637c7SXin Ji u32 address, u8 len, u8 *buf) 236cd1637c7SXin Ji { 237cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 238cd1637c7SXin Ji int ret; 239cd1637c7SXin Ji u8 addrh, addrm, addrl; 240cd1637c7SXin Ji u8 cmd; 241cd1637c7SXin Ji 242cd1637c7SXin Ji if (len > MAX_DPCD_BUFFER_SIZE) { 243cd1637c7SXin Ji dev_err(dev, "exceed aux buffer len.\n"); 244cd1637c7SXin Ji return -EINVAL; 245cd1637c7SXin Ji } 246cd1637c7SXin Ji 247cd1637c7SXin Ji addrl = address & 0xFF; 248cd1637c7SXin Ji addrm = (address >> 8) & 0xFF; 249cd1637c7SXin Ji addrh = (address >> 16) & 0xFF; 250cd1637c7SXin Ji 251*548b512eSXin Ji cmd = DPCD_CMD(len, op); 252cd1637c7SXin Ji 253cd1637c7SXin Ji /* Set command and length */ 254cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 255cd1637c7SXin Ji AP_AUX_COMMAND, cmd); 256cd1637c7SXin Ji 257cd1637c7SXin Ji /* Set aux access address */ 258cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 259cd1637c7SXin Ji AP_AUX_ADDR_7_0, addrl); 260cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 261cd1637c7SXin Ji AP_AUX_ADDR_15_8, addrm); 262cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 263cd1637c7SXin Ji AP_AUX_ADDR_19_16, addrh); 264cd1637c7SXin Ji 265*548b512eSXin Ji if (op == DP_AUX_NATIVE_WRITE) 266*548b512eSXin Ji ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 267*548b512eSXin Ji AP_AUX_BUFF_START, len, buf); 268cd1637c7SXin Ji /* Enable aux access */ 269cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 270cd1637c7SXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 271cd1637c7SXin Ji 272cd1637c7SXin Ji if (ret < 0) { 273cd1637c7SXin Ji dev_err(dev, "cannot access aux related register.\n"); 274cd1637c7SXin Ji return -EIO; 275cd1637c7SXin Ji } 276cd1637c7SXin Ji 277cd1637c7SXin Ji ret = wait_aux_op_finish(ctx); 278cd1637c7SXin Ji if (ret) { 279cd1637c7SXin Ji dev_err(dev, "aux IO error: wait aux op finish.\n"); 280cd1637c7SXin Ji return ret; 281cd1637c7SXin Ji } 282cd1637c7SXin Ji 283*548b512eSXin Ji /* Write done */ 284*548b512eSXin Ji if (op == DP_AUX_NATIVE_WRITE) 285*548b512eSXin Ji return 0; 286*548b512eSXin Ji 287*548b512eSXin Ji /* Read done, read out dpcd data */ 288cd1637c7SXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 289cd1637c7SXin Ji AP_AUX_BUFF_START, len, buf); 290cd1637c7SXin Ji if (ret < 0) { 291cd1637c7SXin Ji dev_err(dev, "read dpcd register failed\n"); 292cd1637c7SXin Ji return -EIO; 293cd1637c7SXin Ji } 294cd1637c7SXin Ji 295cd1637c7SXin Ji return 0; 296cd1637c7SXin Ji } 297cd1637c7SXin Ji 2988bdfc5daSXin Ji static int anx7625_video_mute_control(struct anx7625_data *ctx, 2998bdfc5daSXin Ji u8 status) 3008bdfc5daSXin Ji { 3018bdfc5daSXin Ji int ret; 3028bdfc5daSXin Ji 3038bdfc5daSXin Ji if (status) { 3048bdfc5daSXin Ji /* Set mute on flag */ 3058bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 3068bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_MUTE); 3078bdfc5daSXin Ji /* Clear mipi RX en */ 3088bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 3098bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 3108bdfc5daSXin Ji } else { 3118bdfc5daSXin Ji /* Mute off flag */ 3128bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 3138bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 3148bdfc5daSXin Ji /* Set MIPI RX EN */ 3158bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 3168bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 3178bdfc5daSXin Ji } 3188bdfc5daSXin Ji 3198bdfc5daSXin Ji return ret; 3208bdfc5daSXin Ji } 3218bdfc5daSXin Ji 3228bdfc5daSXin Ji /* Reduction of fraction a/b */ 3238bdfc5daSXin Ji static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 3248bdfc5daSXin Ji { 3258bdfc5daSXin Ji unsigned long gcd_num; 3268bdfc5daSXin Ji unsigned long tmp_a, tmp_b; 3278bdfc5daSXin Ji u32 i = 1; 3288bdfc5daSXin Ji 3298bdfc5daSXin Ji gcd_num = gcd(*a, *b); 3308bdfc5daSXin Ji *a /= gcd_num; 3318bdfc5daSXin Ji *b /= gcd_num; 3328bdfc5daSXin Ji 3338bdfc5daSXin Ji tmp_a = *a; 3348bdfc5daSXin Ji tmp_b = *b; 3358bdfc5daSXin Ji 3368bdfc5daSXin Ji while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 3378bdfc5daSXin Ji i++; 3388bdfc5daSXin Ji *a = tmp_a / i; 3398bdfc5daSXin Ji *b = tmp_b / i; 3408bdfc5daSXin Ji } 3418bdfc5daSXin Ji 3428bdfc5daSXin Ji /* 3438bdfc5daSXin Ji * In the end, make a, b larger to have higher ODFC PLL 3448bdfc5daSXin Ji * output frequency accuracy 3458bdfc5daSXin Ji */ 3468bdfc5daSXin Ji while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 3478bdfc5daSXin Ji *a <<= 1; 3488bdfc5daSXin Ji *b <<= 1; 3498bdfc5daSXin Ji } 3508bdfc5daSXin Ji 3518bdfc5daSXin Ji *a >>= 1; 3528bdfc5daSXin Ji *b >>= 1; 3538bdfc5daSXin Ji } 3548bdfc5daSXin Ji 3558bdfc5daSXin Ji static int anx7625_calculate_m_n(u32 pixelclock, 3568bdfc5daSXin Ji unsigned long *m, 3578bdfc5daSXin Ji unsigned long *n, 3588bdfc5daSXin Ji u8 *post_divider) 3598bdfc5daSXin Ji { 3608bdfc5daSXin Ji if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 3618bdfc5daSXin Ji /* Pixel clock frequency is too high */ 3628bdfc5daSXin Ji DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 3638bdfc5daSXin Ji pixelclock, 3648bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 3658bdfc5daSXin Ji return -EINVAL; 3668bdfc5daSXin Ji } 3678bdfc5daSXin Ji 3688bdfc5daSXin Ji if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 3698bdfc5daSXin Ji /* Pixel clock frequency is too low */ 3708bdfc5daSXin Ji DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 3718bdfc5daSXin Ji pixelclock, 3728bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 3738bdfc5daSXin Ji return -EINVAL; 3748bdfc5daSXin Ji } 3758bdfc5daSXin Ji 3768bdfc5daSXin Ji for (*post_divider = 1; 3778bdfc5daSXin Ji pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 3788bdfc5daSXin Ji *post_divider += 1; 3798bdfc5daSXin Ji 3808bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3818bdfc5daSXin Ji for (*post_divider = 1; 3828bdfc5daSXin Ji (pixelclock < 3838bdfc5daSXin Ji (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 3848bdfc5daSXin Ji *post_divider += 1; 3858bdfc5daSXin Ji 3868bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3878bdfc5daSXin Ji DRM_ERROR("cannot find property post_divider(%d)\n", 3888bdfc5daSXin Ji *post_divider); 3898bdfc5daSXin Ji return -EDOM; 3908bdfc5daSXin Ji } 3918bdfc5daSXin Ji } 3928bdfc5daSXin Ji 3938bdfc5daSXin Ji /* Patch to improve the accuracy */ 3948bdfc5daSXin Ji if (*post_divider == 7) { 3958bdfc5daSXin Ji /* 27,000,000 is not divisible by 7 */ 3968bdfc5daSXin Ji *post_divider = 8; 3978bdfc5daSXin Ji } else if (*post_divider == 11) { 3988bdfc5daSXin Ji /* 27,000,000 is not divisible by 11 */ 3998bdfc5daSXin Ji *post_divider = 12; 4008bdfc5daSXin Ji } else if ((*post_divider == 13) || (*post_divider == 14)) { 4018bdfc5daSXin Ji /* 27,000,000 is not divisible by 13 or 14 */ 4028bdfc5daSXin Ji *post_divider = 15; 4038bdfc5daSXin Ji } 4048bdfc5daSXin Ji 4058bdfc5daSXin Ji if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 4068bdfc5daSXin Ji DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 4078bdfc5daSXin Ji pixelclock * (*post_divider), 4088bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX); 4098bdfc5daSXin Ji return -EDOM; 4108bdfc5daSXin Ji } 4118bdfc5daSXin Ji 4128bdfc5daSXin Ji *m = pixelclock; 4138bdfc5daSXin Ji *n = XTAL_FRQ / (*post_divider); 4148bdfc5daSXin Ji 4158bdfc5daSXin Ji anx7625_reduction_of_a_fraction(m, n); 4168bdfc5daSXin Ji 4178bdfc5daSXin Ji return 0; 4188bdfc5daSXin Ji } 4198bdfc5daSXin Ji 4208bdfc5daSXin Ji static int anx7625_odfc_config(struct anx7625_data *ctx, 4218bdfc5daSXin Ji u8 post_divider) 4228bdfc5daSXin Ji { 4238bdfc5daSXin Ji int ret; 4248bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4258bdfc5daSXin Ji 4268bdfc5daSXin Ji /* Config input reference clock frequency 27MHz/19.2MHz */ 4278bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 4288bdfc5daSXin Ji ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 4298bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 4308bdfc5daSXin Ji (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 4318bdfc5daSXin Ji /* Post divider */ 4328bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4338bdfc5daSXin Ji MIPI_DIGITAL_PLL_8, 0x0f); 4348bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 4358bdfc5daSXin Ji post_divider << 4); 4368bdfc5daSXin Ji 4378bdfc5daSXin Ji /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 4388bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4398bdfc5daSXin Ji ~MIPI_PLL_VCO_TUNE_REG_VAL); 4408bdfc5daSXin Ji 4418bdfc5daSXin Ji /* Reset ODFC PLL */ 4428bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4438bdfc5daSXin Ji ~MIPI_PLL_RESET_N); 4448bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4458bdfc5daSXin Ji MIPI_PLL_RESET_N); 4468bdfc5daSXin Ji 4478bdfc5daSXin Ji if (ret < 0) 4488bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error.\n"); 4498bdfc5daSXin Ji 4508bdfc5daSXin Ji return ret; 4518bdfc5daSXin Ji } 4528bdfc5daSXin Ji 4537d066dc7SXin Ji /* 4547d066dc7SXin Ji * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 4557d066dc7SXin Ji * anx7625 defined K ratio for matching MIPI input video clock and 4567d066dc7SXin Ji * DP output video clock. Increase K value can match bigger video data 4577d066dc7SXin Ji * variation. IVO panel has small variation than DP CTS spec, need 4587d066dc7SXin Ji * decrease the K value. 4597d066dc7SXin Ji */ 4607d066dc7SXin Ji static int anx7625_set_k_value(struct anx7625_data *ctx) 4617d066dc7SXin Ji { 4627d066dc7SXin Ji struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 4637d066dc7SXin Ji 4647d066dc7SXin Ji if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 4657d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4667d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3B); 4677d066dc7SXin Ji 4687d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4697d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3D); 4707d066dc7SXin Ji } 4717d066dc7SXin Ji 4728bdfc5daSXin Ji static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 4738bdfc5daSXin Ji { 4748bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4758bdfc5daSXin Ji unsigned long m, n; 4768bdfc5daSXin Ji u16 htotal; 4778bdfc5daSXin Ji int ret; 4788bdfc5daSXin Ji u8 post_divider = 0; 4798bdfc5daSXin Ji 4808bdfc5daSXin Ji ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 4818bdfc5daSXin Ji &m, &n, &post_divider); 4828bdfc5daSXin Ji 4838bdfc5daSXin Ji if (ret) { 4848bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 4858bdfc5daSXin Ji return ret; 4868bdfc5daSXin Ji } 4878bdfc5daSXin Ji 4888bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 4898bdfc5daSXin Ji m, n, post_divider); 4908bdfc5daSXin Ji 4918bdfc5daSXin Ji /* Configure pixel clock */ 4928bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 4938bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) & 0xFF); 4948bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 4958bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) >> 8); 4968bdfc5daSXin Ji /* Lane count */ 4978bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4988bdfc5daSXin Ji MIPI_LANE_CTRL_0, 0xfc); 4998bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 500fd0310b6SXin Ji MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 5018bdfc5daSXin Ji 5028bdfc5daSXin Ji /* Htotal */ 5038bdfc5daSXin Ji htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 5048bdfc5daSXin Ji ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 5058bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5068bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 5078bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5088bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 5098bdfc5daSXin Ji /* Hactive */ 5108bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5118bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 5128bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5138bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 5148bdfc5daSXin Ji /* HFP */ 5158bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5168bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 5178bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5188bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_H, 5198bdfc5daSXin Ji ctx->dt.hfront_porch.min >> 8); 5208bdfc5daSXin Ji /* HWS */ 5218bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5228bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 5238bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5248bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 5258bdfc5daSXin Ji /* HBP */ 5268bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5278bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 5288bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5298bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 5308bdfc5daSXin Ji /* Vactive */ 5318bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 5328bdfc5daSXin Ji ctx->dt.vactive.min); 5338bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 5348bdfc5daSXin Ji ctx->dt.vactive.min >> 8); 5358bdfc5daSXin Ji /* VFP */ 5368bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5378bdfc5daSXin Ji VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 5388bdfc5daSXin Ji /* VWS */ 5398bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5408bdfc5daSXin Ji VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 5418bdfc5daSXin Ji /* VBP */ 5428bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5438bdfc5daSXin Ji VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 5448bdfc5daSXin Ji /* M value */ 5458bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5468bdfc5daSXin Ji MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 5478bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5488bdfc5daSXin Ji MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 5498bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5508bdfc5daSXin Ji MIPI_PLL_M_NUM_7_0, (m & 0xff)); 5518bdfc5daSXin Ji /* N value */ 5528bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5538bdfc5daSXin Ji MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 5548bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5558bdfc5daSXin Ji MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 5568bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 5578bdfc5daSXin Ji (n & 0xff)); 5587d066dc7SXin Ji 5597d066dc7SXin Ji anx7625_set_k_value(ctx); 5608bdfc5daSXin Ji 5618bdfc5daSXin Ji ret |= anx7625_odfc_config(ctx, post_divider - 1); 5628bdfc5daSXin Ji 5638bdfc5daSXin Ji if (ret < 0) 5648bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 5658bdfc5daSXin Ji 5668bdfc5daSXin Ji return ret; 5678bdfc5daSXin Ji } 5688bdfc5daSXin Ji 5698bdfc5daSXin Ji static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 5708bdfc5daSXin Ji { 5718bdfc5daSXin Ji int val; 5728bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5738bdfc5daSXin Ji 5748bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5758bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 5768bdfc5daSXin Ji if (val < 0) { 5778bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 5788bdfc5daSXin Ji return -EIO; 5798bdfc5daSXin Ji } 5808bdfc5daSXin Ji 5818bdfc5daSXin Ji val |= (1 << MIPI_SWAP_CH3); 5828bdfc5daSXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 5838bdfc5daSXin Ji } 5848bdfc5daSXin Ji 5858bdfc5daSXin Ji static int anx7625_api_dsi_config(struct anx7625_data *ctx) 5868bdfc5daSXin Ji 5878bdfc5daSXin Ji { 5888bdfc5daSXin Ji int val, ret; 5898bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5908bdfc5daSXin Ji 5918bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5928bdfc5daSXin Ji ret = anx7625_swap_dsi_lane3(ctx); 5938bdfc5daSXin Ji if (ret < 0) { 5948bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 5958bdfc5daSXin Ji return ret; 5968bdfc5daSXin Ji } 5978bdfc5daSXin Ji 5988bdfc5daSXin Ji /* DSI clock settings */ 5998bdfc5daSXin Ji val = (0 << MIPI_HS_PWD_CLK) | 6008bdfc5daSXin Ji (0 << MIPI_HS_RT_CLK) | 6018bdfc5daSXin Ji (0 << MIPI_PD_CLK) | 6028bdfc5daSXin Ji (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 6038bdfc5daSXin Ji (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 6048bdfc5daSXin Ji (0 << MIPI_CLK_DET_DET_BYPASS) | 6058bdfc5daSXin Ji (0 << MIPI_CLK_MISS_CTRL) | 6068bdfc5daSXin Ji (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 6078bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6088bdfc5daSXin Ji MIPI_PHY_CONTROL_3, val); 6098bdfc5daSXin Ji 6108bdfc5daSXin Ji /* 6118bdfc5daSXin Ji * Decreased HS prepare timing delay from 160ns to 80ns work with 6128bdfc5daSXin Ji * a) Dragon board 810 series (Qualcomm AP) 6138bdfc5daSXin Ji * b) Moving Pixel DSI source (PG3A pattern generator + 6148bdfc5daSXin Ji * P332 D-PHY Probe) default D-PHY timing 6158bdfc5daSXin Ji * 5ns/step 6168bdfc5daSXin Ji */ 6178bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6188bdfc5daSXin Ji MIPI_TIME_HS_PRPR, 0x10); 6198bdfc5daSXin Ji 6208bdfc5daSXin Ji /* Enable DSI mode*/ 6218bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 6228bdfc5daSXin Ji SELECT_DSI << MIPI_DPI_SELECT); 6238bdfc5daSXin Ji 6248bdfc5daSXin Ji ret |= anx7625_dsi_video_timing_config(ctx); 6258bdfc5daSXin Ji if (ret < 0) { 6268bdfc5daSXin Ji DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 6278bdfc5daSXin Ji return ret; 6288bdfc5daSXin Ji } 6298bdfc5daSXin Ji 6308bdfc5daSXin Ji /* Toggle m, n ready */ 6318bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 6328bdfc5daSXin Ji ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 6338bdfc5daSXin Ji usleep_range(1000, 1100); 6348bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 6358bdfc5daSXin Ji MIPI_M_NUM_READY | MIPI_N_NUM_READY); 6368bdfc5daSXin Ji 6378bdfc5daSXin Ji /* Configure integer stable register */ 6388bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6398bdfc5daSXin Ji MIPI_VIDEO_STABLE_CNT, 0x02); 6408bdfc5daSXin Ji /* Power on MIPI RX */ 6418bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6428bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x00); 6438bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6448bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x80); 6458bdfc5daSXin Ji 6468bdfc5daSXin Ji if (ret < 0) 6478bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 6488bdfc5daSXin Ji 6498bdfc5daSXin Ji return ret; 6508bdfc5daSXin Ji } 6518bdfc5daSXin Ji 6528bdfc5daSXin Ji static int anx7625_dsi_config(struct anx7625_data *ctx) 6538bdfc5daSXin Ji { 6548bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6558bdfc5daSXin Ji int ret; 6568bdfc5daSXin Ji 6578bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 6588bdfc5daSXin Ji 6598bdfc5daSXin Ji /* DSC disable */ 6608bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 6618bdfc5daSXin Ji R_DSC_CTRL_0, ~DSC_EN); 6628bdfc5daSXin Ji 6638bdfc5daSXin Ji ret |= anx7625_api_dsi_config(ctx); 6648bdfc5daSXin Ji 6658bdfc5daSXin Ji if (ret < 0) { 6668bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 6678bdfc5daSXin Ji return ret; 6688bdfc5daSXin Ji } 6698bdfc5daSXin Ji 6708bdfc5daSXin Ji /* Set MIPI RX EN */ 6718bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 6728bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 6738bdfc5daSXin Ji /* Clear mute flag */ 6748bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 6758bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 6768bdfc5daSXin Ji if (ret < 0) 6778bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 6788bdfc5daSXin Ji else 6798bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 6808bdfc5daSXin Ji 6818bdfc5daSXin Ji return ret; 6828bdfc5daSXin Ji } 6838bdfc5daSXin Ji 684fd0310b6SXin Ji static int anx7625_api_dpi_config(struct anx7625_data *ctx) 685fd0310b6SXin Ji { 686fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 687fd0310b6SXin Ji u16 freq = ctx->dt.pixelclock.min / 1000; 688fd0310b6SXin Ji int ret; 689fd0310b6SXin Ji 690fd0310b6SXin Ji /* configure pixel clock */ 691fd0310b6SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 692fd0310b6SXin Ji PIXEL_CLOCK_L, freq & 0xFF); 693fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 694fd0310b6SXin Ji PIXEL_CLOCK_H, (freq >> 8)); 695fd0310b6SXin Ji 696fd0310b6SXin Ji /* set DPI mode */ 697fd0310b6SXin Ji /* set to DPI PLL module sel */ 698fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 699fd0310b6SXin Ji MIPI_DIGITAL_PLL_9, 0x20); 700fd0310b6SXin Ji /* power down MIPI */ 701fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 702fd0310b6SXin Ji MIPI_LANE_CTRL_10, 0x08); 703fd0310b6SXin Ji /* enable DPI mode */ 704fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 705fd0310b6SXin Ji MIPI_DIGITAL_PLL_18, 0x1C); 706fd0310b6SXin Ji /* set first edge */ 707fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 708fd0310b6SXin Ji VIDEO_CONTROL_0, 0x06); 709fd0310b6SXin Ji if (ret < 0) 710fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 711fd0310b6SXin Ji 712fd0310b6SXin Ji return ret; 713fd0310b6SXin Ji } 714fd0310b6SXin Ji 715fd0310b6SXin Ji static int anx7625_dpi_config(struct anx7625_data *ctx) 716fd0310b6SXin Ji { 717fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 718fd0310b6SXin Ji int ret; 719fd0310b6SXin Ji 720fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 721fd0310b6SXin Ji 722fd0310b6SXin Ji /* DSC disable */ 723fd0310b6SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 724fd0310b6SXin Ji R_DSC_CTRL_0, ~DSC_EN); 725fd0310b6SXin Ji if (ret < 0) { 726fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 727fd0310b6SXin Ji return ret; 728fd0310b6SXin Ji } 729fd0310b6SXin Ji 730fd0310b6SXin Ji ret = anx7625_config_bit_matrix(ctx); 731fd0310b6SXin Ji if (ret < 0) { 732fd0310b6SXin Ji DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 733fd0310b6SXin Ji return ret; 734fd0310b6SXin Ji } 735fd0310b6SXin Ji 736fd0310b6SXin Ji ret = anx7625_api_dpi_config(ctx); 737fd0310b6SXin Ji if (ret < 0) { 738fd0310b6SXin Ji DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 739fd0310b6SXin Ji return ret; 740fd0310b6SXin Ji } 741fd0310b6SXin Ji 742fd0310b6SXin Ji /* set MIPI RX EN */ 743fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 744fd0310b6SXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 745fd0310b6SXin Ji /* clear mute flag */ 746fd0310b6SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 747fd0310b6SXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 748fd0310b6SXin Ji if (ret < 0) 749fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 750fd0310b6SXin Ji 751fd0310b6SXin Ji return ret; 752fd0310b6SXin Ji } 753fd0310b6SXin Ji 754cd1637c7SXin Ji static int anx7625_read_flash_status(struct anx7625_data *ctx) 755cd1637c7SXin Ji { 756cd1637c7SXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 757cd1637c7SXin Ji } 758cd1637c7SXin Ji 759cd1637c7SXin Ji static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 760cd1637c7SXin Ji { 761cd1637c7SXin Ji int ret, val; 762cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 763cd1637c7SXin Ji u8 ident[FLASH_BUF_LEN]; 764cd1637c7SXin Ji 765cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 766cd1637c7SXin Ji FLASH_ADDR_HIGH, 0x91); 767cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 768cd1637c7SXin Ji FLASH_ADDR_LOW, 0xA0); 769cd1637c7SXin Ji if (ret < 0) { 770cd1637c7SXin Ji dev_err(dev, "IO error : set key flash address.\n"); 771cd1637c7SXin Ji return ret; 772cd1637c7SXin Ji } 773cd1637c7SXin Ji 774cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 775cd1637c7SXin Ji FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 776cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 777cd1637c7SXin Ji FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 778cd1637c7SXin Ji if (ret < 0) { 779cd1637c7SXin Ji dev_err(dev, "IO error : set key flash len.\n"); 780cd1637c7SXin Ji return ret; 781cd1637c7SXin Ji } 782cd1637c7SXin Ji 783cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 784cd1637c7SXin Ji R_FLASH_RW_CTRL, FLASH_READ); 785cd1637c7SXin Ji ret |= readx_poll_timeout(anx7625_read_flash_status, 786cd1637c7SXin Ji ctx, val, 787cd1637c7SXin Ji ((val & FLASH_DONE) || (val < 0)), 788cd1637c7SXin Ji 2000, 789cd1637c7SXin Ji 2000 * 150); 790cd1637c7SXin Ji if (ret) { 791cd1637c7SXin Ji dev_err(dev, "flash read access fail!\n"); 792cd1637c7SXin Ji return -EIO; 793cd1637c7SXin Ji } 794cd1637c7SXin Ji 795cd1637c7SXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 796cd1637c7SXin Ji FLASH_BUF_BASE_ADDR, 797cd1637c7SXin Ji FLASH_BUF_LEN, ident); 798cd1637c7SXin Ji if (ret < 0) { 799cd1637c7SXin Ji dev_err(dev, "read flash data fail!\n"); 800cd1637c7SXin Ji return -EIO; 801cd1637c7SXin Ji } 802cd1637c7SXin Ji 803cd1637c7SXin Ji if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 804cd1637c7SXin Ji return -EINVAL; 805cd1637c7SXin Ji 806cd1637c7SXin Ji return 0; 807cd1637c7SXin Ji } 808cd1637c7SXin Ji 809cd1637c7SXin Ji static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 810cd1637c7SXin Ji { 811cd1637c7SXin Ji int ret; 812cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 813cd1637c7SXin Ji 814cd1637c7SXin Ji /* Select HDCP 1.4 KEY */ 815cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 816cd1637c7SXin Ji R_BOOT_RETRY, 0x12); 817cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 818cd1637c7SXin Ji FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 819cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 820cd1637c7SXin Ji FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 821cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 822cd1637c7SXin Ji R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 823cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 824cd1637c7SXin Ji R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 825cd1637c7SXin Ji 826cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827cd1637c7SXin Ji R_RAM_ADDR_H, 0); 828cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829cd1637c7SXin Ji R_RAM_ADDR_L, 0); 830cd1637c7SXin Ji /* Enable HDCP 1.4 KEY load */ 831cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 832cd1637c7SXin Ji R_RAM_CTRL, DECRYPT_EN | LOAD_START); 833cd1637c7SXin Ji dev_dbg(dev, "load HDCP 1.4 key done\n"); 834cd1637c7SXin Ji return ret; 835cd1637c7SXin Ji } 836cd1637c7SXin Ji 837cd1637c7SXin Ji static int anx7625_hdcp_disable(struct anx7625_data *ctx) 838cd1637c7SXin Ji { 839cd1637c7SXin Ji int ret; 840cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 841cd1637c7SXin Ji 842cd1637c7SXin Ji dev_dbg(dev, "disable HDCP 1.4\n"); 843cd1637c7SXin Ji 844cd1637c7SXin Ji /* Disable HDCP */ 845cd1637c7SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 846cd1637c7SXin Ji /* Try auth flag */ 847cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 848cd1637c7SXin Ji /* Interrupt for DRM */ 849cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 850cd1637c7SXin Ji if (ret < 0) 851cd1637c7SXin Ji dev_err(dev, "fail to disable HDCP\n"); 852cd1637c7SXin Ji 853cd1637c7SXin Ji return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 854cd1637c7SXin Ji TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 855cd1637c7SXin Ji } 856cd1637c7SXin Ji 857cd1637c7SXin Ji static int anx7625_hdcp_enable(struct anx7625_data *ctx) 858cd1637c7SXin Ji { 859cd1637c7SXin Ji u8 bcap; 860cd1637c7SXin Ji int ret; 861cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 862cd1637c7SXin Ji 863cd1637c7SXin Ji ret = anx7625_hdcp_key_probe(ctx); 864cd1637c7SXin Ji if (ret) { 865cd1637c7SXin Ji dev_dbg(dev, "no key found, not to do hdcp\n"); 866cd1637c7SXin Ji return ret; 867cd1637c7SXin Ji } 868cd1637c7SXin Ji 869cd1637c7SXin Ji /* Read downstream capability */ 870*548b512eSXin Ji anx7625_aux_dpcd_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap); 871cd1637c7SXin Ji if (!(bcap & 0x01)) { 872cd1637c7SXin Ji pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 873cd1637c7SXin Ji return 0; 874cd1637c7SXin Ji } 875cd1637c7SXin Ji 876cd1637c7SXin Ji dev_dbg(dev, "enable HDCP 1.4\n"); 877cd1637c7SXin Ji 878cd1637c7SXin Ji /* First clear HDCP state */ 879cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 880cd1637c7SXin Ji TX_HDCP_CTRL0, 881cd1637c7SXin Ji KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 882cd1637c7SXin Ji usleep_range(1000, 1100); 883cd1637c7SXin Ji /* Second clear HDCP state */ 884cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 885cd1637c7SXin Ji TX_HDCP_CTRL0, 886cd1637c7SXin Ji KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 887cd1637c7SXin Ji 888cd1637c7SXin Ji /* Set time for waiting KSVR */ 889cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 890cd1637c7SXin Ji SP_TX_WAIT_KSVR_TIME, 0xc8); 891cd1637c7SXin Ji /* Set time for waiting R0 */ 892cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 893cd1637c7SXin Ji SP_TX_WAIT_R0_TIME, 0xb0); 894cd1637c7SXin Ji ret |= anx7625_hdcp_key_load(ctx); 895cd1637c7SXin Ji if (ret) { 896cd1637c7SXin Ji pr_warn("prepare HDCP key failed.\n"); 897cd1637c7SXin Ji return ret; 898cd1637c7SXin Ji } 899cd1637c7SXin Ji 900cd1637c7SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 901cd1637c7SXin Ji 902cd1637c7SXin Ji /* Try auth flag */ 903cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 904cd1637c7SXin Ji /* Interrupt for DRM */ 905cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 906cd1637c7SXin Ji if (ret < 0) 907cd1637c7SXin Ji dev_err(dev, "fail to enable HDCP\n"); 908cd1637c7SXin Ji 909cd1637c7SXin Ji return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 910cd1637c7SXin Ji TX_HDCP_CTRL0, HARD_AUTH_EN); 911cd1637c7SXin Ji } 912cd1637c7SXin Ji 9138bdfc5daSXin Ji static void anx7625_dp_start(struct anx7625_data *ctx) 9148bdfc5daSXin Ji { 9158bdfc5daSXin Ji int ret; 9168bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9178bdfc5daSXin Ji 9188bdfc5daSXin Ji if (!ctx->display_timing_valid) { 9198bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 9208bdfc5daSXin Ji return; 9218bdfc5daSXin Ji } 9228bdfc5daSXin Ji 923cd1637c7SXin Ji /* Disable HDCP */ 924cd1637c7SXin Ji anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 925cd1637c7SXin Ji 926fd0310b6SXin Ji if (ctx->pdata.is_dpi) 927fd0310b6SXin Ji ret = anx7625_dpi_config(ctx); 928fd0310b6SXin Ji else 9298bdfc5daSXin Ji ret = anx7625_dsi_config(ctx); 9308bdfc5daSXin Ji 9318bdfc5daSXin Ji if (ret < 0) 9328bdfc5daSXin Ji DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 933cd1637c7SXin Ji 934cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 935cd1637c7SXin Ji 936cd1637c7SXin Ji ctx->dp_en = 1; 9378bdfc5daSXin Ji } 9388bdfc5daSXin Ji 9398bdfc5daSXin Ji static void anx7625_dp_stop(struct anx7625_data *ctx) 9408bdfc5daSXin Ji { 9418bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9428bdfc5daSXin Ji int ret; 943*548b512eSXin Ji u8 data; 9448bdfc5daSXin Ji 9458bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 9468bdfc5daSXin Ji 9478bdfc5daSXin Ji /* 9488bdfc5daSXin Ji * Video disable: 0x72:08 bit 7 = 0; 9498bdfc5daSXin Ji * Audio disable: 0x70:87 bit 0 = 0; 9508bdfc5daSXin Ji */ 9518bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 9528bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 9538bdfc5daSXin Ji 9548bdfc5daSXin Ji ret |= anx7625_video_mute_control(ctx, 1); 955*548b512eSXin Ji 956*548b512eSXin Ji dev_dbg(dev, "notify downstream enter into standby\n"); 957*548b512eSXin Ji /* Downstream monitor enter into standby mode */ 958*548b512eSXin Ji data = 2; 959*548b512eSXin Ji ret |= anx7625_aux_dpcd_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data); 9608bdfc5daSXin Ji if (ret < 0) 9618bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 962cd1637c7SXin Ji 963cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 964cd1637c7SXin Ji 965cd1637c7SXin Ji ctx->dp_en = 0; 9668bdfc5daSXin Ji } 9678bdfc5daSXin Ji 9688bdfc5daSXin Ji static int sp_tx_rst_aux(struct anx7625_data *ctx) 9698bdfc5daSXin Ji { 9708bdfc5daSXin Ji int ret; 9718bdfc5daSXin Ji 9728bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 9738bdfc5daSXin Ji AUX_RST); 9748bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 9758bdfc5daSXin Ji ~AUX_RST); 9768bdfc5daSXin Ji return ret; 9778bdfc5daSXin Ji } 9788bdfc5daSXin Ji 9798bdfc5daSXin Ji static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 9808bdfc5daSXin Ji { 9818bdfc5daSXin Ji int ret; 9828bdfc5daSXin Ji 9838bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9848bdfc5daSXin Ji AP_AUX_BUFF_START, offset); 9858bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9868bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 9878bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 9888bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 9898bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 9908bdfc5daSXin Ji } 9918bdfc5daSXin Ji 9928bdfc5daSXin Ji static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 9938bdfc5daSXin Ji { 9948bdfc5daSXin Ji int ret; 9958bdfc5daSXin Ji 9968bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 9978bdfc5daSXin Ji AP_AUX_COMMAND, len_cmd); 9988bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 9998bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 10008bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 10018bdfc5daSXin Ji } 10028bdfc5daSXin Ji 10038bdfc5daSXin Ji static int sp_tx_get_edid_block(struct anx7625_data *ctx) 10048bdfc5daSXin Ji { 10058bdfc5daSXin Ji int c = 0; 10068bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10078bdfc5daSXin Ji 10088bdfc5daSXin Ji sp_tx_aux_wr(ctx, 0x7e); 10098bdfc5daSXin Ji sp_tx_aux_rd(ctx, 0x01); 10108bdfc5daSXin Ji c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 10118bdfc5daSXin Ji if (c < 0) { 10128bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 10138bdfc5daSXin Ji return -EIO; 10148bdfc5daSXin Ji } 10158bdfc5daSXin Ji 10168bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 10178bdfc5daSXin Ji 10188bdfc5daSXin Ji if (c > MAX_EDID_BLOCK) 10198bdfc5daSXin Ji c = 1; 10208bdfc5daSXin Ji 10218bdfc5daSXin Ji return c; 10228bdfc5daSXin Ji } 10238bdfc5daSXin Ji 10248bdfc5daSXin Ji static int edid_read(struct anx7625_data *ctx, 10258bdfc5daSXin Ji u8 offset, u8 *pblock_buf) 10268bdfc5daSXin Ji { 10278bdfc5daSXin Ji int ret, cnt; 10288bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10298bdfc5daSXin Ji 10308bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 10318bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 10328bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 10338bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 10348bdfc5daSXin Ji 10358bdfc5daSXin Ji if (ret) { 10367f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 10378bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 10388bdfc5daSXin Ji } else { 10398bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 10408bdfc5daSXin Ji AP_AUX_BUFF_START, 10418bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, 10428bdfc5daSXin Ji pblock_buf); 10438bdfc5daSXin Ji if (ret > 0) 10448bdfc5daSXin Ji break; 10458bdfc5daSXin Ji } 10468bdfc5daSXin Ji } 10478bdfc5daSXin Ji 10488bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 10498bdfc5daSXin Ji return -EIO; 10508bdfc5daSXin Ji 10517f16d0f3SRobert Foss return ret; 10528bdfc5daSXin Ji } 10538bdfc5daSXin Ji 10548bdfc5daSXin Ji static int segments_edid_read(struct anx7625_data *ctx, 10558bdfc5daSXin Ji u8 segment, u8 *buf, u8 offset) 10568bdfc5daSXin Ji { 10578bdfc5daSXin Ji u8 cnt; 10588bdfc5daSXin Ji int ret; 10598bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10608bdfc5daSXin Ji 10618bdfc5daSXin Ji /* Write address only */ 10628bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10638bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x30); 10648bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10658bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 10668bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10678bdfc5daSXin Ji AP_AUX_CTRL_STATUS, 10688bdfc5daSXin Ji AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 10698bdfc5daSXin Ji 10708bdfc5daSXin Ji ret |= wait_aux_op_finish(ctx); 10718bdfc5daSXin Ji /* Write segment address */ 10728bdfc5daSXin Ji ret |= sp_tx_aux_wr(ctx, segment); 10738bdfc5daSXin Ji /* Data read */ 10748bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10758bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 10768bdfc5daSXin Ji if (ret) { 10778bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 10788bdfc5daSXin Ji return ret; 10798bdfc5daSXin Ji } 10808bdfc5daSXin Ji 10818bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 10828bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 10838bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 10848bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 10858bdfc5daSXin Ji 10868bdfc5daSXin Ji if (ret) { 10878bdfc5daSXin Ji ret = sp_tx_rst_aux(ctx); 10888bdfc5daSXin Ji DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 10898bdfc5daSXin Ji } else { 10908bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 10918bdfc5daSXin Ji AP_AUX_BUFF_START, 10928bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, buf); 10938bdfc5daSXin Ji if (ret > 0) 10948bdfc5daSXin Ji break; 10958bdfc5daSXin Ji } 10968bdfc5daSXin Ji } 10978bdfc5daSXin Ji 10988bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 10998bdfc5daSXin Ji return -EIO; 11008bdfc5daSXin Ji 11017f16d0f3SRobert Foss return ret; 11028bdfc5daSXin Ji } 11038bdfc5daSXin Ji 11048bdfc5daSXin Ji static int sp_tx_edid_read(struct anx7625_data *ctx, 11058bdfc5daSXin Ji u8 *pedid_blocks_buf) 11068bdfc5daSXin Ji { 11078bdfc5daSXin Ji u8 offset, edid_pos; 11088bdfc5daSXin Ji int count, blocks_num; 11098bdfc5daSXin Ji u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 11108bdfc5daSXin Ji u8 i, j; 11110bae5687SHsin-Yi Wang int g_edid_break = 0; 11128bdfc5daSXin Ji int ret; 11138bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11148bdfc5daSXin Ji 11158bdfc5daSXin Ji /* Address initial */ 11168bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11178bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 11188bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11198bdfc5daSXin Ji AP_AUX_ADDR_15_8, 0); 11208bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 11218bdfc5daSXin Ji AP_AUX_ADDR_19_16, 0xf0); 11228bdfc5daSXin Ji if (ret < 0) { 11238bdfc5daSXin Ji DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 11248bdfc5daSXin Ji return -EIO; 11258bdfc5daSXin Ji } 11268bdfc5daSXin Ji 11278bdfc5daSXin Ji blocks_num = sp_tx_get_edid_block(ctx); 11288bdfc5daSXin Ji if (blocks_num < 0) 11298bdfc5daSXin Ji return blocks_num; 11308bdfc5daSXin Ji 11318bdfc5daSXin Ji count = 0; 11328bdfc5daSXin Ji 11338bdfc5daSXin Ji do { 11348bdfc5daSXin Ji switch (count) { 11358bdfc5daSXin Ji case 0: 11368bdfc5daSXin Ji case 1: 11378bdfc5daSXin Ji for (i = 0; i < 8; i++) { 11388bdfc5daSXin Ji offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 11398bdfc5daSXin Ji g_edid_break = edid_read(ctx, offset, 11408bdfc5daSXin Ji pblock_buf); 11418bdfc5daSXin Ji 11420bae5687SHsin-Yi Wang if (g_edid_break < 0) 11438bdfc5daSXin Ji break; 11448bdfc5daSXin Ji 11458bdfc5daSXin Ji memcpy(&pedid_blocks_buf[offset], 11468bdfc5daSXin Ji pblock_buf, 11478bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11488bdfc5daSXin Ji } 11498bdfc5daSXin Ji 11508bdfc5daSXin Ji break; 11518bdfc5daSXin Ji case 2: 11528bdfc5daSXin Ji offset = 0x00; 11538bdfc5daSXin Ji 11548bdfc5daSXin Ji for (j = 0; j < 8; j++) { 11558bdfc5daSXin Ji edid_pos = (j + count * 8) * 11568bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 11578bdfc5daSXin Ji 11588bdfc5daSXin Ji if (g_edid_break == 1) 11598bdfc5daSXin Ji break; 11608bdfc5daSXin Ji 1161a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 11628bdfc5daSXin Ji pblock_buf, offset); 1163a23e0a2aSRobert Foss if (ret < 0) 1164a23e0a2aSRobert Foss return ret; 1165a23e0a2aSRobert Foss 11668bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 11678bdfc5daSXin Ji pblock_buf, 11688bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11698bdfc5daSXin Ji offset = offset + 0x10; 11708bdfc5daSXin Ji } 11718bdfc5daSXin Ji 11728bdfc5daSXin Ji break; 11738bdfc5daSXin Ji case 3: 11748bdfc5daSXin Ji offset = 0x80; 11758bdfc5daSXin Ji 11768bdfc5daSXin Ji for (j = 0; j < 8; j++) { 11778bdfc5daSXin Ji edid_pos = (j + count * 8) * 11788bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 11798bdfc5daSXin Ji if (g_edid_break == 1) 11808bdfc5daSXin Ji break; 11818bdfc5daSXin Ji 1182a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 11838bdfc5daSXin Ji pblock_buf, offset); 1184a23e0a2aSRobert Foss if (ret < 0) 1185a23e0a2aSRobert Foss return ret; 1186a23e0a2aSRobert Foss 11878bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 11888bdfc5daSXin Ji pblock_buf, 11898bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11908bdfc5daSXin Ji offset = offset + 0x10; 11918bdfc5daSXin Ji } 11928bdfc5daSXin Ji 11938bdfc5daSXin Ji break; 11948bdfc5daSXin Ji default: 11958bdfc5daSXin Ji break; 11968bdfc5daSXin Ji } 11978bdfc5daSXin Ji 11988bdfc5daSXin Ji count++; 11998bdfc5daSXin Ji 12008bdfc5daSXin Ji } while (blocks_num >= count); 12018bdfc5daSXin Ji 12028bdfc5daSXin Ji /* Check edid data */ 12038bdfc5daSXin Ji if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 12048bdfc5daSXin Ji DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 12058bdfc5daSXin Ji return -EINVAL; 12068bdfc5daSXin Ji } 12078bdfc5daSXin Ji 12088bdfc5daSXin Ji /* Reset aux channel */ 12097f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 12107f16d0f3SRobert Foss if (ret < 0) { 12117f16d0f3SRobert Foss DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 12127f16d0f3SRobert Foss return ret; 12137f16d0f3SRobert Foss } 12148bdfc5daSXin Ji 12158bdfc5daSXin Ji return (blocks_num + 1); 12168bdfc5daSXin Ji } 12178bdfc5daSXin Ji 12188bdfc5daSXin Ji static void anx7625_power_on(struct anx7625_data *ctx) 12198bdfc5daSXin Ji { 12208bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12216c744983SHsin-Yi Wang int ret, i; 12228bdfc5daSXin Ji 12238bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 12248bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 12258bdfc5daSXin Ji return; 12268bdfc5daSXin Ji } 12278bdfc5daSXin Ji 12286c744983SHsin-Yi Wang for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 12296c744983SHsin-Yi Wang ret = regulator_enable(ctx->pdata.supplies[i].consumer); 12306c744983SHsin-Yi Wang if (ret < 0) { 12316c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 12326c744983SHsin-Yi Wang i, ret); 12336c744983SHsin-Yi Wang goto reg_err; 12346c744983SHsin-Yi Wang } 12356c744983SHsin-Yi Wang usleep_range(2000, 2100); 12366c744983SHsin-Yi Wang } 12376c744983SHsin-Yi Wang 12381fcf24fbSHsin-Yi Wang usleep_range(11000, 12000); 12396c744983SHsin-Yi Wang 12408bdfc5daSXin Ji /* Power on pin enable */ 12418bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 1); 12428bdfc5daSXin Ji usleep_range(10000, 11000); 12438bdfc5daSXin Ji /* Power reset pin enable */ 12448bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 1); 12458bdfc5daSXin Ji usleep_range(10000, 11000); 12468bdfc5daSXin Ji 12478bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 12486c744983SHsin-Yi Wang return; 12496c744983SHsin-Yi Wang reg_err: 12506c744983SHsin-Yi Wang for (--i; i >= 0; i--) 12516c744983SHsin-Yi Wang regulator_disable(ctx->pdata.supplies[i].consumer); 12528bdfc5daSXin Ji } 12538bdfc5daSXin Ji 12548bdfc5daSXin Ji static void anx7625_power_standby(struct anx7625_data *ctx) 12558bdfc5daSXin Ji { 12568bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12576c744983SHsin-Yi Wang int ret; 12588bdfc5daSXin Ji 12598bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 12608bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 12618bdfc5daSXin Ji return; 12628bdfc5daSXin Ji } 12638bdfc5daSXin Ji 12648bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 0); 12658bdfc5daSXin Ji usleep_range(1000, 1100); 12668bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 0); 12678bdfc5daSXin Ji usleep_range(1000, 1100); 12686c744983SHsin-Yi Wang 12696c744983SHsin-Yi Wang ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 12706c744983SHsin-Yi Wang ctx->pdata.supplies); 12716c744983SHsin-Yi Wang if (ret < 0) 12726c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 12736c744983SHsin-Yi Wang 12748bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 12758bdfc5daSXin Ji } 12768bdfc5daSXin Ji 12778bdfc5daSXin Ji /* Basic configurations of ANX7625 */ 12788bdfc5daSXin Ji static void anx7625_config(struct anx7625_data *ctx) 12798bdfc5daSXin Ji { 12808bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12818bdfc5daSXin Ji XTAL_FRQ_SEL, XTAL_FRQ_27M); 12828bdfc5daSXin Ji } 12838bdfc5daSXin Ji 12848bdfc5daSXin Ji static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 12858bdfc5daSXin Ji { 12868bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12878bdfc5daSXin Ji int ret; 12888bdfc5daSXin Ji 12898bdfc5daSXin Ji /* Reset main ocm */ 12908bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 12918bdfc5daSXin Ji /* Disable PD */ 12928bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12938bdfc5daSXin Ji AP_AV_STATUS, AP_DISABLE_PD); 12948bdfc5daSXin Ji /* Release main ocm */ 12958bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 12968bdfc5daSXin Ji 12978bdfc5daSXin Ji if (ret < 0) 12988bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 12998bdfc5daSXin Ji else 13008bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 13018bdfc5daSXin Ji } 13028bdfc5daSXin Ji 13038bdfc5daSXin Ji static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 13048bdfc5daSXin Ji { 13058bdfc5daSXin Ji int ret; 13068bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13078bdfc5daSXin Ji 13088bdfc5daSXin Ji /* Check interface workable */ 13098bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 13108bdfc5daSXin Ji FLASH_LOAD_STA); 13118bdfc5daSXin Ji if (ret < 0) { 13128bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 13138bdfc5daSXin Ji return ret; 13148bdfc5daSXin Ji } 13158bdfc5daSXin Ji if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 13168bdfc5daSXin Ji return -ENODEV; 13178bdfc5daSXin Ji 13188bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 13198bdfc5daSXin Ji 13208bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 13218bdfc5daSXin Ji anx7625_reg_read(ctx, 13228bdfc5daSXin Ji ctx->i2c.rx_p0_client, 13238bdfc5daSXin Ji OCM_FW_VERSION), 13248bdfc5daSXin Ji anx7625_reg_read(ctx, 13258bdfc5daSXin Ji ctx->i2c.rx_p0_client, 13268bdfc5daSXin Ji OCM_FW_REVERSION)); 13278bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 13288bdfc5daSXin Ji ANX7625_DRV_VERSION); 13298bdfc5daSXin Ji 13308bdfc5daSXin Ji return 0; 13318bdfc5daSXin Ji } 13328bdfc5daSXin Ji 13338bdfc5daSXin Ji static void anx7625_power_on_init(struct anx7625_data *ctx) 13348bdfc5daSXin Ji { 13358bdfc5daSXin Ji int retry_count, i; 13368bdfc5daSXin Ji 13378bdfc5daSXin Ji for (retry_count = 0; retry_count < 3; retry_count++) { 13388bdfc5daSXin Ji anx7625_power_on(ctx); 13398bdfc5daSXin Ji anx7625_config(ctx); 13408bdfc5daSXin Ji 13418bdfc5daSXin Ji for (i = 0; i < OCM_LOADING_TIME; i++) { 13428bdfc5daSXin Ji if (!anx7625_ocm_loading_check(ctx)) 13438bdfc5daSXin Ji return; 13448bdfc5daSXin Ji usleep_range(1000, 1100); 13458bdfc5daSXin Ji } 13468bdfc5daSXin Ji anx7625_power_standby(ctx); 13478bdfc5daSXin Ji } 13488bdfc5daSXin Ji } 13498bdfc5daSXin Ji 13508bdfc5daSXin Ji static void anx7625_init_gpio(struct anx7625_data *platform) 13518bdfc5daSXin Ji { 13528bdfc5daSXin Ji struct device *dev = &platform->client->dev; 13538bdfc5daSXin Ji 13548bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 13558bdfc5daSXin Ji 13568bdfc5daSXin Ji /* Gpio for chip power enable */ 13578bdfc5daSXin Ji platform->pdata.gpio_p_on = 13588bdfc5daSXin Ji devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 13597020449bSXin Ji if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 13607020449bSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 13617020449bSXin Ji platform->pdata.gpio_p_on = NULL; 13627020449bSXin Ji } 13637020449bSXin Ji 13648bdfc5daSXin Ji /* Gpio for chip reset */ 13658bdfc5daSXin Ji platform->pdata.gpio_reset = 13668bdfc5daSXin Ji devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 13677020449bSXin Ji if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 13687020449bSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 13697020449bSXin Ji platform->pdata.gpio_reset = NULL; 13707020449bSXin Ji } 13718bdfc5daSXin Ji 13728bdfc5daSXin Ji if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 13738bdfc5daSXin Ji platform->pdata.low_power_mode = 1; 13748bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 13758bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_p_on), 13768bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_reset)); 13778bdfc5daSXin Ji } else { 13788bdfc5daSXin Ji platform->pdata.low_power_mode = 0; 13798bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 13808bdfc5daSXin Ji } 13818bdfc5daSXin Ji } 13828bdfc5daSXin Ji 13838bdfc5daSXin Ji static void anx7625_stop_dp_work(struct anx7625_data *ctx) 13848bdfc5daSXin Ji { 13858bdfc5daSXin Ji ctx->hpd_status = 0; 13868bdfc5daSXin Ji ctx->hpd_high_cnt = 0; 13878bdfc5daSXin Ji ctx->display_timing_valid = 0; 13888bdfc5daSXin Ji } 13898bdfc5daSXin Ji 13908bdfc5daSXin Ji static void anx7625_start_dp_work(struct anx7625_data *ctx) 13918bdfc5daSXin Ji { 13928bdfc5daSXin Ji int ret; 13938bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13948bdfc5daSXin Ji 13958bdfc5daSXin Ji if (ctx->hpd_high_cnt >= 2) { 13968bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 13978bdfc5daSXin Ji return; 13988bdfc5daSXin Ji } 13998bdfc5daSXin Ji 1400fd0310b6SXin Ji ctx->hpd_status = 1; 14018bdfc5daSXin Ji ctx->hpd_high_cnt++; 14028bdfc5daSXin Ji 14038bdfc5daSXin Ji /* Not support HDCP */ 14048bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 14058bdfc5daSXin Ji 14068bdfc5daSXin Ji /* Try auth flag */ 14078bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 14088bdfc5daSXin Ji /* Interrupt for DRM */ 14098bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1410fd0310b6SXin Ji if (ret < 0) { 1411fd0310b6SXin Ji DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 14128bdfc5daSXin Ji return; 1413fd0310b6SXin Ji } 14148bdfc5daSXin Ji 14158bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 14168bdfc5daSXin Ji if (ret < 0) 14178bdfc5daSXin Ji return; 14188bdfc5daSXin Ji 14198bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 14208bdfc5daSXin Ji } 14218bdfc5daSXin Ji 14228bdfc5daSXin Ji static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 14238bdfc5daSXin Ji { 14248bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 14258bdfc5daSXin Ji } 14268bdfc5daSXin Ji 14278bdfc5daSXin Ji static void anx7625_hpd_polling(struct anx7625_data *ctx) 14288bdfc5daSXin Ji { 14298bdfc5daSXin Ji int ret, val; 14308bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14318bdfc5daSXin Ji 1432fd0310b6SXin Ji /* Interrupt mode, no need poll HPD status, just return */ 1433fd0310b6SXin Ji if (ctx->pdata.intp_irq) 1434fd0310b6SXin Ji return; 1435fd0310b6SXin Ji 14368bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 14378bdfc5daSXin Ji ctx, val, 14388bdfc5daSXin Ji ((val & HPD_STATUS) || (val < 0)), 14398bdfc5daSXin Ji 5000, 14408bdfc5daSXin Ji 5000 * 100); 14418bdfc5daSXin Ji if (ret) { 144260487584SPi-Hsun Shih DRM_DEV_ERROR(dev, "no hpd.\n"); 144360487584SPi-Hsun Shih return; 144460487584SPi-Hsun Shih } 144560487584SPi-Hsun Shih 144660487584SPi-Hsun Shih DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 14478bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 14488bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 14498bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 14508bdfc5daSXin Ji INTERFACE_CHANGE_INT, 0); 14518bdfc5daSXin Ji 14528bdfc5daSXin Ji anx7625_start_dp_work(ctx); 14538bdfc5daSXin Ji 145460487584SPi-Hsun Shih if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 145560487584SPi-Hsun Shih drm_helper_hpd_irq_event(ctx->bridge.dev); 14568bdfc5daSXin Ji } 14578bdfc5daSXin Ji 14588bdfc5daSXin Ji static void anx7625_remove_edid(struct anx7625_data *ctx) 14598bdfc5daSXin Ji { 14608bdfc5daSXin Ji ctx->slimport_edid_p.edid_block_num = -1; 14618bdfc5daSXin Ji } 14628bdfc5daSXin Ji 1463fd0310b6SXin Ji static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1464fd0310b6SXin Ji { 1465fd0310b6SXin Ji int i; 1466fd0310b6SXin Ji 1467fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1468fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1469fd0310b6SXin Ji DP_TX_LANE0_SWING_REG0 + i, 1470fd0310b6SXin Ji ctx->pdata.lane0_reg_data[i] & 0xFF); 1471fd0310b6SXin Ji 1472fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1473fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1474fd0310b6SXin Ji DP_TX_LANE1_SWING_REG0 + i, 1475fd0310b6SXin Ji ctx->pdata.lane1_reg_data[i] & 0xFF); 1476fd0310b6SXin Ji } 1477fd0310b6SXin Ji 14788bdfc5daSXin Ji static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 14798bdfc5daSXin Ji { 14808bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14818bdfc5daSXin Ji 14828bdfc5daSXin Ji /* HPD changed */ 14838bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 14848bdfc5daSXin Ji (u32)on); 14858bdfc5daSXin Ji 14868bdfc5daSXin Ji if (on == 0) { 14878bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 14888bdfc5daSXin Ji anx7625_remove_edid(ctx); 14898bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 14908bdfc5daSXin Ji } else { 14918bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 14928bdfc5daSXin Ji anx7625_start_dp_work(ctx); 1493fd0310b6SXin Ji anx7625_dp_adjust_swing(ctx); 14948bdfc5daSXin Ji } 14958bdfc5daSXin Ji } 14968bdfc5daSXin Ji 14978bdfc5daSXin Ji static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 14988bdfc5daSXin Ji { 14998bdfc5daSXin Ji int intr_vector, status; 15008bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 15018bdfc5daSXin Ji 15028bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 15038bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 15048bdfc5daSXin Ji if (status < 0) { 15058bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 15068bdfc5daSXin Ji return status; 15078bdfc5daSXin Ji } 15088bdfc5daSXin Ji 15098bdfc5daSXin Ji intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 15108bdfc5daSXin Ji INTERFACE_CHANGE_INT); 15118bdfc5daSXin Ji if (intr_vector < 0) { 15128bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 15138bdfc5daSXin Ji return intr_vector; 15148bdfc5daSXin Ji } 15158bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 15168bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 15178bdfc5daSXin Ji INTERFACE_CHANGE_INT, 15188bdfc5daSXin Ji intr_vector & (~intr_vector)); 15198bdfc5daSXin Ji if (status < 0) { 15208bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 15218bdfc5daSXin Ji return status; 15228bdfc5daSXin Ji } 15238bdfc5daSXin Ji 15248bdfc5daSXin Ji if (!(intr_vector & HPD_STATUS_CHANGE)) 15258bdfc5daSXin Ji return -ENOENT; 15268bdfc5daSXin Ji 15278bdfc5daSXin Ji status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 15288bdfc5daSXin Ji SYSTEM_STSTUS); 15298bdfc5daSXin Ji if (status < 0) { 15308bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 15318bdfc5daSXin Ji return status; 15328bdfc5daSXin Ji } 15338bdfc5daSXin Ji 15348bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 15358bdfc5daSXin Ji dp_hpd_change_handler(ctx, status & HPD_STATUS); 15368bdfc5daSXin Ji 15378bdfc5daSXin Ji return 0; 15388bdfc5daSXin Ji } 15398bdfc5daSXin Ji 15408bdfc5daSXin Ji static void anx7625_work_func(struct work_struct *work) 15418bdfc5daSXin Ji { 15428bdfc5daSXin Ji int event; 15438bdfc5daSXin Ji struct anx7625_data *ctx = container_of(work, 15448bdfc5daSXin Ji struct anx7625_data, work); 15458bdfc5daSXin Ji 15468bdfc5daSXin Ji mutex_lock(&ctx->lock); 154760487584SPi-Hsun Shih 154860487584SPi-Hsun Shih if (pm_runtime_suspended(&ctx->client->dev)) 154960487584SPi-Hsun Shih goto unlock; 155060487584SPi-Hsun Shih 15518bdfc5daSXin Ji event = anx7625_hpd_change_detect(ctx); 15528bdfc5daSXin Ji if (event < 0) 155360487584SPi-Hsun Shih goto unlock; 15548bdfc5daSXin Ji 15558bdfc5daSXin Ji if (ctx->bridge_attached) 15568bdfc5daSXin Ji drm_helper_hpd_irq_event(ctx->bridge.dev); 155760487584SPi-Hsun Shih 155860487584SPi-Hsun Shih unlock: 155960487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 15608bdfc5daSXin Ji } 15618bdfc5daSXin Ji 15628bdfc5daSXin Ji static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 15638bdfc5daSXin Ji { 15648bdfc5daSXin Ji struct anx7625_data *ctx = (struct anx7625_data *)data; 15658bdfc5daSXin Ji 15668bdfc5daSXin Ji queue_work(ctx->workqueue, &ctx->work); 15678bdfc5daSXin Ji 15688bdfc5daSXin Ji return IRQ_HANDLED; 15698bdfc5daSXin Ji } 15708bdfc5daSXin Ji 1571fd0310b6SXin Ji static int anx7625_get_swing_setting(struct device *dev, 1572fd0310b6SXin Ji struct anx7625_platform_data *pdata) 1573fd0310b6SXin Ji { 1574fd0310b6SXin Ji int num_regs; 1575fd0310b6SXin Ji 1576fd0310b6SXin Ji if (of_get_property(dev->of_node, 1577fd0310b6SXin Ji "analogix,lane0-swing", &num_regs)) { 1578fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1579fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1580fd0310b6SXin Ji 1581fd0310b6SXin Ji pdata->dp_lane0_swing_reg_cnt = num_regs; 1582fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1583fd0310b6SXin Ji pdata->lane0_reg_data, num_regs); 1584fd0310b6SXin Ji } 1585fd0310b6SXin Ji 1586fd0310b6SXin Ji if (of_get_property(dev->of_node, 1587fd0310b6SXin Ji "analogix,lane1-swing", &num_regs)) { 1588fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1589fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1590fd0310b6SXin Ji 1591fd0310b6SXin Ji pdata->dp_lane1_swing_reg_cnt = num_regs; 1592fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1593fd0310b6SXin Ji pdata->lane1_reg_data, num_regs); 1594fd0310b6SXin Ji } 1595fd0310b6SXin Ji 1596fd0310b6SXin Ji return 0; 1597fd0310b6SXin Ji } 1598fd0310b6SXin Ji 15998bdfc5daSXin Ji static int anx7625_parse_dt(struct device *dev, 16008bdfc5daSXin Ji struct anx7625_platform_data *pdata) 16018bdfc5daSXin Ji { 1602fd0310b6SXin Ji struct device_node *np = dev->of_node, *ep0; 16038bdfc5daSXin Ji struct drm_panel *panel; 16048bdfc5daSXin Ji int ret; 1605fd0310b6SXin Ji int bus_type, mipi_lanes; 16068bdfc5daSXin Ji 1607fd0310b6SXin Ji anx7625_get_swing_setting(dev, pdata); 1608fd0310b6SXin Ji 1609fd0310b6SXin Ji pdata->is_dpi = 1; /* default dpi mode */ 16108bdfc5daSXin Ji pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 16118bdfc5daSXin Ji if (!pdata->mipi_host_node) { 16128bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 16138bdfc5daSXin Ji return -ENODEV; 16148bdfc5daSXin Ji } 16158bdfc5daSXin Ji 1616fd0310b6SXin Ji bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1617fd0310b6SXin Ji mipi_lanes = MAX_LANES_SUPPORT; 1618fd0310b6SXin Ji ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1619fd0310b6SXin Ji if (ep0) { 1620fd0310b6SXin Ji if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1621fd0310b6SXin Ji bus_type = 0; 1622fd0310b6SXin Ji 1623fd0310b6SXin Ji mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1624fd0310b6SXin Ji } 1625fd0310b6SXin Ji 1626fd0310b6SXin Ji if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1627fd0310b6SXin Ji pdata->is_dpi = 0; 1628fd0310b6SXin Ji 1629fd0310b6SXin Ji pdata->mipi_lanes = mipi_lanes; 1630fd0310b6SXin Ji if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1631fd0310b6SXin Ji pdata->mipi_lanes = MAX_LANES_SUPPORT; 1632fd0310b6SXin Ji 1633fd0310b6SXin Ji if (pdata->is_dpi) 1634fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1635fd0310b6SXin Ji else 1636fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 16378bdfc5daSXin Ji 1638566fef12SXin Ji if (of_property_read_bool(np, "analogix,audio-enable")) 1639566fef12SXin Ji pdata->audio_en = 1; 1640566fef12SXin Ji 16418bdfc5daSXin Ji ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 16428bdfc5daSXin Ji if (ret < 0) { 16438bdfc5daSXin Ji if (ret == -ENODEV) 16448bdfc5daSXin Ji return 0; 16458bdfc5daSXin Ji return ret; 16468bdfc5daSXin Ji } 16478bdfc5daSXin Ji if (!panel) 16488bdfc5daSXin Ji return -ENODEV; 16498bdfc5daSXin Ji 16508bdfc5daSXin Ji pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 16518bdfc5daSXin Ji if (IS_ERR(pdata->panel_bridge)) 16528bdfc5daSXin Ji return PTR_ERR(pdata->panel_bridge); 16538bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 16548bdfc5daSXin Ji 16558bdfc5daSXin Ji return 0; 16568bdfc5daSXin Ji } 16578bdfc5daSXin Ji 16588bdfc5daSXin Ji static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 16598bdfc5daSXin Ji { 16608bdfc5daSXin Ji return container_of(bridge, struct anx7625_data, bridge); 16618bdfc5daSXin Ji } 16628bdfc5daSXin Ji 16638bdfc5daSXin Ji static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 16648bdfc5daSXin Ji { 16658bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 16668bdfc5daSXin Ji struct s_edid_data *p_edid = &ctx->slimport_edid_p; 16678bdfc5daSXin Ji int edid_num; 16688bdfc5daSXin Ji u8 *edid; 16698bdfc5daSXin Ji 16708bdfc5daSXin Ji edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 16718bdfc5daSXin Ji if (!edid) { 16728bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 16738bdfc5daSXin Ji return NULL; 16748bdfc5daSXin Ji } 16758bdfc5daSXin Ji 16768bdfc5daSXin Ji if (ctx->slimport_edid_p.edid_block_num > 0) { 16778bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 16788bdfc5daSXin Ji FOUR_BLOCK_SIZE); 16798bdfc5daSXin Ji return (struct edid *)edid; 16808bdfc5daSXin Ji } 16818bdfc5daSXin Ji 168260487584SPi-Hsun Shih pm_runtime_get_sync(dev); 16838bdfc5daSXin Ji edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 16843203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 16858bdfc5daSXin Ji 16868bdfc5daSXin Ji if (edid_num < 1) { 16878bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 16888bdfc5daSXin Ji kfree(edid); 16898bdfc5daSXin Ji return NULL; 16908bdfc5daSXin Ji } 16918bdfc5daSXin Ji 16928bdfc5daSXin Ji p_edid->edid_block_num = edid_num; 16938bdfc5daSXin Ji 16948bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 16958bdfc5daSXin Ji return (struct edid *)edid; 16968bdfc5daSXin Ji } 16978bdfc5daSXin Ji 16988bdfc5daSXin Ji static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 16998bdfc5daSXin Ji { 17008bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17018bdfc5daSXin Ji 1702fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 17038bdfc5daSXin Ji 1704fd0310b6SXin Ji if (ctx->pdata.panel_bridge) 17058bdfc5daSXin Ji return connector_status_connected; 1706fd0310b6SXin Ji 1707fd0310b6SXin Ji return ctx->hpd_status ? connector_status_connected : 1708fd0310b6SXin Ji connector_status_disconnected; 17098bdfc5daSXin Ji } 17108bdfc5daSXin Ji 1711566fef12SXin Ji static int anx7625_audio_hw_params(struct device *dev, void *data, 1712566fef12SXin Ji struct hdmi_codec_daifmt *fmt, 1713566fef12SXin Ji struct hdmi_codec_params *params) 1714566fef12SXin Ji { 1715566fef12SXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 1716566fef12SXin Ji int wl, ch, rate; 1717566fef12SXin Ji int ret = 0; 1718566fef12SXin Ji 1719566fef12SXin Ji if (fmt->fmt != HDMI_DSP_A) { 1720566fef12SXin Ji DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1721566fef12SXin Ji return -EINVAL; 1722566fef12SXin Ji } 1723566fef12SXin Ji 1724566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1725566fef12SXin Ji params->sample_rate, params->sample_width, 1726566fef12SXin Ji params->cea.channels); 1727566fef12SXin Ji 1728566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1729566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 1730566fef12SXin Ji ~I2S_SLAVE_MODE, 1731566fef12SXin Ji TDM_SLAVE_MODE); 1732566fef12SXin Ji 1733566fef12SXin Ji /* Word length */ 1734566fef12SXin Ji switch (params->sample_width) { 1735566fef12SXin Ji case 16: 1736566fef12SXin Ji wl = AUDIO_W_LEN_16_20MAX; 1737566fef12SXin Ji break; 1738566fef12SXin Ji case 18: 1739566fef12SXin Ji wl = AUDIO_W_LEN_18_20MAX; 1740566fef12SXin Ji break; 1741566fef12SXin Ji case 20: 1742566fef12SXin Ji wl = AUDIO_W_LEN_20_20MAX; 1743566fef12SXin Ji break; 1744566fef12SXin Ji case 24: 1745566fef12SXin Ji wl = AUDIO_W_LEN_24_24MAX; 1746566fef12SXin Ji break; 1747566fef12SXin Ji default: 1748566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1749566fef12SXin Ji params->sample_width); 1750566fef12SXin Ji return -EINVAL; 1751566fef12SXin Ji } 1752566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1753566fef12SXin Ji AUDIO_CHANNEL_STATUS_5, 1754566fef12SXin Ji 0xf0, wl); 1755566fef12SXin Ji 1756566fef12SXin Ji /* Channel num */ 1757566fef12SXin Ji switch (params->cea.channels) { 1758566fef12SXin Ji case 2: 1759566fef12SXin Ji ch = I2S_CH_2; 1760566fef12SXin Ji break; 1761566fef12SXin Ji case 4: 1762566fef12SXin Ji ch = TDM_CH_4; 1763566fef12SXin Ji break; 1764566fef12SXin Ji case 6: 1765566fef12SXin Ji ch = TDM_CH_6; 1766566fef12SXin Ji break; 1767566fef12SXin Ji case 8: 1768566fef12SXin Ji ch = TDM_CH_8; 1769566fef12SXin Ji break; 1770566fef12SXin Ji default: 1771566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1772566fef12SXin Ji params->cea.channels); 1773566fef12SXin Ji return -EINVAL; 1774566fef12SXin Ji } 1775566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1776566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1777566fef12SXin Ji if (ch > I2S_CH_2) 1778566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1779566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1780566fef12SXin Ji else 1781566fef12SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1782566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1783566fef12SXin Ji 1784566fef12SXin Ji /* FS */ 1785566fef12SXin Ji switch (params->sample_rate) { 1786566fef12SXin Ji case 32000: 1787566fef12SXin Ji rate = AUDIO_FS_32K; 1788566fef12SXin Ji break; 1789566fef12SXin Ji case 44100: 1790566fef12SXin Ji rate = AUDIO_FS_441K; 1791566fef12SXin Ji break; 1792566fef12SXin Ji case 48000: 1793566fef12SXin Ji rate = AUDIO_FS_48K; 1794566fef12SXin Ji break; 1795566fef12SXin Ji case 88200: 1796566fef12SXin Ji rate = AUDIO_FS_882K; 1797566fef12SXin Ji break; 1798566fef12SXin Ji case 96000: 1799566fef12SXin Ji rate = AUDIO_FS_96K; 1800566fef12SXin Ji break; 1801566fef12SXin Ji case 176400: 1802566fef12SXin Ji rate = AUDIO_FS_1764K; 1803566fef12SXin Ji break; 1804566fef12SXin Ji case 192000: 1805566fef12SXin Ji rate = AUDIO_FS_192K; 1806566fef12SXin Ji break; 1807566fef12SXin Ji default: 1808566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1809566fef12SXin Ji params->sample_rate); 1810566fef12SXin Ji return -EINVAL; 1811566fef12SXin Ji } 1812566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1813566fef12SXin Ji AUDIO_CHANNEL_STATUS_4, 1814566fef12SXin Ji 0xf0, rate); 1815566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1816566fef12SXin Ji AP_AV_STATUS, AP_AUDIO_CHG); 1817566fef12SXin Ji if (ret < 0) { 1818566fef12SXin Ji DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1819566fef12SXin Ji return -EIO; 1820566fef12SXin Ji } 1821566fef12SXin Ji 1822566fef12SXin Ji return 0; 1823566fef12SXin Ji } 1824566fef12SXin Ji 1825566fef12SXin Ji static void anx7625_audio_shutdown(struct device *dev, void *data) 1826566fef12SXin Ji { 1827566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1828566fef12SXin Ji } 1829566fef12SXin Ji 1830566fef12SXin Ji static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1831566fef12SXin Ji struct device_node *endpoint) 1832566fef12SXin Ji { 1833566fef12SXin Ji struct of_endpoint of_ep; 1834566fef12SXin Ji int ret; 1835566fef12SXin Ji 1836566fef12SXin Ji ret = of_graph_parse_endpoint(endpoint, &of_ep); 1837566fef12SXin Ji if (ret < 0) 1838566fef12SXin Ji return ret; 1839566fef12SXin Ji 1840566fef12SXin Ji /* 1841566fef12SXin Ji * HDMI sound should be located at external DPI port 1842566fef12SXin Ji * Didn't have good way to check where is internal(DSI) 1843566fef12SXin Ji * or external(DPI) bridge 1844566fef12SXin Ji */ 1845566fef12SXin Ji return 0; 1846566fef12SXin Ji } 1847566fef12SXin Ji 1848566fef12SXin Ji static void 1849566fef12SXin Ji anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1850566fef12SXin Ji enum drm_connector_status status) 1851566fef12SXin Ji { 1852566fef12SXin Ji if (ctx->plugged_cb && ctx->codec_dev) { 1853566fef12SXin Ji ctx->plugged_cb(ctx->codec_dev, 1854566fef12SXin Ji status == connector_status_connected); 1855566fef12SXin Ji } 1856566fef12SXin Ji } 1857566fef12SXin Ji 1858566fef12SXin Ji static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1859566fef12SXin Ji hdmi_codec_plugged_cb fn, 1860566fef12SXin Ji struct device *codec_dev) 1861566fef12SXin Ji { 1862566fef12SXin Ji struct anx7625_data *ctx = data; 1863566fef12SXin Ji 1864566fef12SXin Ji ctx->plugged_cb = fn; 1865566fef12SXin Ji ctx->codec_dev = codec_dev; 1866566fef12SXin Ji anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1867566fef12SXin Ji 1868566fef12SXin Ji return 0; 1869566fef12SXin Ji } 1870566fef12SXin Ji 1871607a264eSXin Ji static int anx7625_audio_get_eld(struct device *dev, void *data, 1872607a264eSXin Ji u8 *buf, size_t len) 1873607a264eSXin Ji { 1874607a264eSXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 1875607a264eSXin Ji 1876607a264eSXin Ji if (!ctx->connector) { 1877607a264eSXin Ji dev_err(dev, "connector not initial\n"); 1878607a264eSXin Ji return -EINVAL; 1879607a264eSXin Ji } 1880607a264eSXin Ji 1881607a264eSXin Ji dev_dbg(dev, "audio copy eld\n"); 1882607a264eSXin Ji memcpy(buf, ctx->connector->eld, 1883607a264eSXin Ji min(sizeof(ctx->connector->eld), len)); 1884607a264eSXin Ji 1885607a264eSXin Ji return 0; 1886607a264eSXin Ji } 1887607a264eSXin Ji 1888566fef12SXin Ji static const struct hdmi_codec_ops anx7625_codec_ops = { 1889566fef12SXin Ji .hw_params = anx7625_audio_hw_params, 1890566fef12SXin Ji .audio_shutdown = anx7625_audio_shutdown, 1891607a264eSXin Ji .get_eld = anx7625_audio_get_eld, 1892566fef12SXin Ji .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1893566fef12SXin Ji .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1894566fef12SXin Ji }; 1895566fef12SXin Ji 1896566fef12SXin Ji static void anx7625_unregister_audio(struct anx7625_data *ctx) 1897566fef12SXin Ji { 1898566fef12SXin Ji struct device *dev = &ctx->client->dev; 1899566fef12SXin Ji 1900566fef12SXin Ji if (ctx->audio_pdev) { 1901566fef12SXin Ji platform_device_unregister(ctx->audio_pdev); 1902566fef12SXin Ji ctx->audio_pdev = NULL; 1903566fef12SXin Ji } 1904566fef12SXin Ji 1905566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1906566fef12SXin Ji } 1907566fef12SXin Ji 1908566fef12SXin Ji static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1909566fef12SXin Ji { 1910566fef12SXin Ji struct hdmi_codec_pdata codec_data = { 1911566fef12SXin Ji .ops = &anx7625_codec_ops, 1912566fef12SXin Ji .max_i2s_channels = 8, 1913566fef12SXin Ji .i2s = 1, 1914566fef12SXin Ji .data = ctx, 1915566fef12SXin Ji }; 1916566fef12SXin Ji 1917566fef12SXin Ji ctx->audio_pdev = platform_device_register_data(dev, 1918566fef12SXin Ji HDMI_CODEC_DRV_NAME, 1919566fef12SXin Ji PLATFORM_DEVID_AUTO, 1920566fef12SXin Ji &codec_data, 1921566fef12SXin Ji sizeof(codec_data)); 1922566fef12SXin Ji 1923566fef12SXin Ji if (IS_ERR(ctx->audio_pdev)) 192483ddd806SDan Carpenter return PTR_ERR(ctx->audio_pdev); 1925566fef12SXin Ji 1926566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1927566fef12SXin Ji 1928566fef12SXin Ji return 0; 1929566fef12SXin Ji } 1930566fef12SXin Ji 19318bdfc5daSXin Ji static int anx7625_attach_dsi(struct anx7625_data *ctx) 19328bdfc5daSXin Ji { 19338bdfc5daSXin Ji struct mipi_dsi_device *dsi; 19348bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 19358bdfc5daSXin Ji struct mipi_dsi_host *host; 19368bdfc5daSXin Ji const struct mipi_dsi_device_info info = { 19378bdfc5daSXin Ji .type = "anx7625", 19388bdfc5daSXin Ji .channel = 0, 19398bdfc5daSXin Ji .node = NULL, 19408bdfc5daSXin Ji }; 194125a390a9SMaxime Ripard int ret; 19428bdfc5daSXin Ji 19438bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 19448bdfc5daSXin Ji 19458bdfc5daSXin Ji host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 19468bdfc5daSXin Ji if (!host) { 19478bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 194826933299Sowen return -EPROBE_DEFER; 19498bdfc5daSXin Ji } 19508bdfc5daSXin Ji 195125a390a9SMaxime Ripard dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 19528bdfc5daSXin Ji if (IS_ERR(dsi)) { 19538bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 19548bdfc5daSXin Ji return -EINVAL; 19558bdfc5daSXin Ji } 19568bdfc5daSXin Ji 1957fd0310b6SXin Ji dsi->lanes = ctx->pdata.mipi_lanes; 19588bdfc5daSXin Ji dsi->format = MIPI_DSI_FMT_RGB888; 19598bdfc5daSXin Ji dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 19608bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 19618bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_HSE; 19628bdfc5daSXin Ji 196325a390a9SMaxime Ripard ret = devm_mipi_dsi_attach(dev, dsi); 196425a390a9SMaxime Ripard if (ret) { 19658bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 196625a390a9SMaxime Ripard return ret; 19678bdfc5daSXin Ji } 19688bdfc5daSXin Ji 19698bdfc5daSXin Ji ctx->dsi = dsi; 19708bdfc5daSXin Ji 19718bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 19728bdfc5daSXin Ji 19738bdfc5daSXin Ji return 0; 19748bdfc5daSXin Ji } 19758bdfc5daSXin Ji 1976cd1637c7SXin Ji static void hdcp_check_work_func(struct work_struct *work) 1977cd1637c7SXin Ji { 1978cd1637c7SXin Ji u8 status; 1979cd1637c7SXin Ji struct delayed_work *dwork; 1980cd1637c7SXin Ji struct anx7625_data *ctx; 1981cd1637c7SXin Ji struct device *dev; 1982cd1637c7SXin Ji struct drm_device *drm_dev; 1983cd1637c7SXin Ji 1984cd1637c7SXin Ji dwork = to_delayed_work(work); 1985cd1637c7SXin Ji ctx = container_of(dwork, struct anx7625_data, hdcp_work); 1986cd1637c7SXin Ji dev = &ctx->client->dev; 1987cd1637c7SXin Ji 1988cd1637c7SXin Ji if (!ctx->connector) { 1989cd1637c7SXin Ji dev_err(dev, "HDCP connector is null!"); 1990cd1637c7SXin Ji return; 1991cd1637c7SXin Ji } 1992cd1637c7SXin Ji 1993cd1637c7SXin Ji drm_dev = ctx->connector->dev; 1994cd1637c7SXin Ji drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1995cd1637c7SXin Ji mutex_lock(&ctx->hdcp_wq_lock); 1996cd1637c7SXin Ji 1997cd1637c7SXin Ji status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 1998cd1637c7SXin Ji dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 1999cd1637c7SXin Ji if (status & BIT(1)) { 2000cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2001cd1637c7SXin Ji drm_hdcp_update_content_protection(ctx->connector, 2002cd1637c7SXin Ji ctx->hdcp_cp); 2003cd1637c7SXin Ji dev_dbg(dev, "update CP to ENABLE\n"); 2004cd1637c7SXin Ji } 2005cd1637c7SXin Ji 2006cd1637c7SXin Ji mutex_unlock(&ctx->hdcp_wq_lock); 2007cd1637c7SXin Ji drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2008cd1637c7SXin Ji } 2009cd1637c7SXin Ji 2010cd1637c7SXin Ji static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2011cd1637c7SXin Ji struct drm_connector_state *state) 2012cd1637c7SXin Ji { 2013cd1637c7SXin Ji struct device *dev = &ctx->client->dev; 2014cd1637c7SXin Ji int cp; 2015cd1637c7SXin Ji 2016cd1637c7SXin Ji dev_dbg(dev, "hdcp state check\n"); 2017cd1637c7SXin Ji cp = state->content_protection; 2018cd1637c7SXin Ji 2019cd1637c7SXin Ji if (cp == ctx->hdcp_cp) 2020cd1637c7SXin Ji return 0; 2021cd1637c7SXin Ji 2022cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2023cd1637c7SXin Ji if (ctx->dp_en) { 2024cd1637c7SXin Ji dev_dbg(dev, "enable HDCP\n"); 2025cd1637c7SXin Ji anx7625_hdcp_enable(ctx); 2026cd1637c7SXin Ji 2027cd1637c7SXin Ji queue_delayed_work(ctx->hdcp_workqueue, 2028cd1637c7SXin Ji &ctx->hdcp_work, 2029cd1637c7SXin Ji msecs_to_jiffies(2000)); 2030cd1637c7SXin Ji } 2031cd1637c7SXin Ji } 2032cd1637c7SXin Ji 2033cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2034cd1637c7SXin Ji if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2035cd1637c7SXin Ji dev_err(dev, "current CP is not ENABLED\n"); 2036cd1637c7SXin Ji return -EINVAL; 2037cd1637c7SXin Ji } 2038cd1637c7SXin Ji anx7625_hdcp_disable(ctx); 2039cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2040cd1637c7SXin Ji drm_hdcp_update_content_protection(ctx->connector, 2041cd1637c7SXin Ji ctx->hdcp_cp); 2042cd1637c7SXin Ji dev_dbg(dev, "update CP to UNDESIRE\n"); 2043cd1637c7SXin Ji } 2044cd1637c7SXin Ji 2045cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2046cd1637c7SXin Ji dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2047cd1637c7SXin Ji return -EINVAL; 2048cd1637c7SXin Ji } 2049cd1637c7SXin Ji 2050cd1637c7SXin Ji return 0; 2051cd1637c7SXin Ji } 2052cd1637c7SXin Ji 20538bdfc5daSXin Ji static int anx7625_bridge_attach(struct drm_bridge *bridge, 20548bdfc5daSXin Ji enum drm_bridge_attach_flags flags) 20558bdfc5daSXin Ji { 20568bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 20578bdfc5daSXin Ji int err; 20588bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 20598bdfc5daSXin Ji 20608bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 20618bdfc5daSXin Ji if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 20628bdfc5daSXin Ji return -EINVAL; 20638bdfc5daSXin Ji 20648bdfc5daSXin Ji if (!bridge->encoder) { 20658bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Parent encoder object not found"); 20668bdfc5daSXin Ji return -ENODEV; 20678bdfc5daSXin Ji } 20688bdfc5daSXin Ji 20698bdfc5daSXin Ji if (ctx->pdata.panel_bridge) { 20708bdfc5daSXin Ji err = drm_bridge_attach(bridge->encoder, 20718bdfc5daSXin Ji ctx->pdata.panel_bridge, 20728bdfc5daSXin Ji &ctx->bridge, flags); 2073fb8d617fSLaurent Pinchart if (err) 20748bdfc5daSXin Ji return err; 20758bdfc5daSXin Ji } 20768bdfc5daSXin Ji 20778bdfc5daSXin Ji ctx->bridge_attached = 1; 20788bdfc5daSXin Ji 20798bdfc5daSXin Ji return 0; 20808bdfc5daSXin Ji } 20818bdfc5daSXin Ji 20828bdfc5daSXin Ji static enum drm_mode_status 20838bdfc5daSXin Ji anx7625_bridge_mode_valid(struct drm_bridge *bridge, 20848bdfc5daSXin Ji const struct drm_display_info *info, 20858bdfc5daSXin Ji const struct drm_display_mode *mode) 20868bdfc5daSXin Ji { 20878bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 20888bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 20898bdfc5daSXin Ji 20908bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 20918bdfc5daSXin Ji 20928bdfc5daSXin Ji /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 20938bdfc5daSXin Ji if (mode->clock > SUPPORT_PIXEL_CLOCK) { 20948bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, 20958bdfc5daSXin Ji "drm mode invalid, pixelclock too high.\n"); 20968bdfc5daSXin Ji return MODE_CLOCK_HIGH; 20978bdfc5daSXin Ji } 20988bdfc5daSXin Ji 20998bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 21008bdfc5daSXin Ji 21018bdfc5daSXin Ji return MODE_OK; 21028bdfc5daSXin Ji } 21038bdfc5daSXin Ji 21048bdfc5daSXin Ji static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 21058bdfc5daSXin Ji const struct drm_display_mode *old_mode, 21068bdfc5daSXin Ji const struct drm_display_mode *mode) 21078bdfc5daSXin Ji { 21088bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 21098bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 21108bdfc5daSXin Ji 21118bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 21128bdfc5daSXin Ji 21138bdfc5daSXin Ji ctx->dt.pixelclock.min = mode->clock; 21148bdfc5daSXin Ji ctx->dt.hactive.min = mode->hdisplay; 21158bdfc5daSXin Ji ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 21168bdfc5daSXin Ji ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 21178bdfc5daSXin Ji ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 21188bdfc5daSXin Ji ctx->dt.vactive.min = mode->vdisplay; 21198bdfc5daSXin Ji ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 21208bdfc5daSXin Ji ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 21218bdfc5daSXin Ji ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 21228bdfc5daSXin Ji 21238bdfc5daSXin Ji ctx->display_timing_valid = 1; 21248bdfc5daSXin Ji 21258bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 21268bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 21278bdfc5daSXin Ji ctx->dt.hactive.min, 21288bdfc5daSXin Ji ctx->dt.hsync_len.min, 21298bdfc5daSXin Ji ctx->dt.hfront_porch.min, 21308bdfc5daSXin Ji ctx->dt.hback_porch.min); 21318bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 21328bdfc5daSXin Ji ctx->dt.vactive.min, 21338bdfc5daSXin Ji ctx->dt.vsync_len.min, 21348bdfc5daSXin Ji ctx->dt.vfront_porch.min, 21358bdfc5daSXin Ji ctx->dt.vback_porch.min); 21368bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 21378bdfc5daSXin Ji mode->hdisplay, 21388bdfc5daSXin Ji mode->hsync_start); 21398bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 21408bdfc5daSXin Ji mode->hsync_end, 21418bdfc5daSXin Ji mode->htotal); 21428bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 21438bdfc5daSXin Ji mode->vdisplay, 21448bdfc5daSXin Ji mode->vsync_start); 21458bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 21468bdfc5daSXin Ji mode->vsync_end, 21478bdfc5daSXin Ji mode->vtotal); 21488bdfc5daSXin Ji } 21498bdfc5daSXin Ji 21508bdfc5daSXin Ji static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 21518bdfc5daSXin Ji const struct drm_display_mode *mode, 21528bdfc5daSXin Ji struct drm_display_mode *adj) 21538bdfc5daSXin Ji { 21548bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 21558bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 21568bdfc5daSXin Ji u32 hsync, hfp, hbp, hblanking; 21578bdfc5daSXin Ji u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 21588bdfc5daSXin Ji u32 vref, adj_clock; 21598bdfc5daSXin Ji 21608bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 21618bdfc5daSXin Ji 2162fd0310b6SXin Ji /* No need fixup for external monitor */ 2163fd0310b6SXin Ji if (!ctx->pdata.panel_bridge) 2164fd0310b6SXin Ji return true; 2165fd0310b6SXin Ji 21668bdfc5daSXin Ji hsync = mode->hsync_end - mode->hsync_start; 21678bdfc5daSXin Ji hfp = mode->hsync_start - mode->hdisplay; 21688bdfc5daSXin Ji hbp = mode->htotal - mode->hsync_end; 21698bdfc5daSXin Ji hblanking = mode->htotal - mode->hdisplay; 21708bdfc5daSXin Ji 21718bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 21728bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 21738bdfc5daSXin Ji hsync, hfp, hbp, adj->clock); 21748bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 21758bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 21768bdfc5daSXin Ji 21778bdfc5daSXin Ji adj_hfp = hfp; 21788bdfc5daSXin Ji adj_hsync = hsync; 21798bdfc5daSXin Ji adj_hbp = hbp; 21808bdfc5daSXin Ji adj_hblanking = hblanking; 21818bdfc5daSXin Ji 21828bdfc5daSXin Ji /* HFP needs to be even */ 21838bdfc5daSXin Ji if (hfp & 0x1) { 21848bdfc5daSXin Ji adj_hfp += 1; 21858bdfc5daSXin Ji adj_hblanking += 1; 21868bdfc5daSXin Ji } 21878bdfc5daSXin Ji 21888bdfc5daSXin Ji /* HBP needs to be even */ 21898bdfc5daSXin Ji if (hbp & 0x1) { 21908bdfc5daSXin Ji adj_hbp -= 1; 21918bdfc5daSXin Ji adj_hblanking -= 1; 21928bdfc5daSXin Ji } 21938bdfc5daSXin Ji 21948bdfc5daSXin Ji /* HSYNC needs to be even */ 21958bdfc5daSXin Ji if (hsync & 0x1) { 21968bdfc5daSXin Ji if (adj_hblanking < hblanking) 21978bdfc5daSXin Ji adj_hsync += 1; 21988bdfc5daSXin Ji else 21998bdfc5daSXin Ji adj_hsync -= 1; 22008bdfc5daSXin Ji } 22018bdfc5daSXin Ji 22028bdfc5daSXin Ji /* 22038bdfc5daSXin Ji * Once illegal timing detected, use default HFP, HSYNC, HBP 22048bdfc5daSXin Ji * This adjusting made for built-in eDP panel, for the externel 22058bdfc5daSXin Ji * DP monitor, may need return false. 22068bdfc5daSXin Ji */ 22078bdfc5daSXin Ji if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 22088bdfc5daSXin Ji adj_hsync = SYNC_LEN_DEF; 22098bdfc5daSXin Ji adj_hfp = HFP_HBP_DEF; 22108bdfc5daSXin Ji adj_hbp = HFP_HBP_DEF; 22118bdfc5daSXin Ji vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 22128bdfc5daSXin Ji if (hblanking < HBLANKING_MIN) { 22138bdfc5daSXin Ji delta_adj = HBLANKING_MIN - hblanking; 22148bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 22158bdfc5daSXin Ji adj->clock += DIV_ROUND_UP(adj_clock, 1000); 22168bdfc5daSXin Ji } else { 22178bdfc5daSXin Ji delta_adj = hblanking - HBLANKING_MIN; 22188bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 22198bdfc5daSXin Ji adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 22208bdfc5daSXin Ji } 22218bdfc5daSXin Ji 22228bdfc5daSXin Ji DRM_WARN("illegal hblanking timing, use default.\n"); 22238bdfc5daSXin Ji DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 22248bdfc5daSXin Ji } else if (adj_hfp < HP_MIN) { 22258bdfc5daSXin Ji /* Adjust hfp if hfp less than HP_MIN */ 22268bdfc5daSXin Ji delta_adj = HP_MIN - adj_hfp; 22278bdfc5daSXin Ji adj_hfp = HP_MIN; 22288bdfc5daSXin Ji 22298bdfc5daSXin Ji /* 22308bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP does not have enough 22318bdfc5daSXin Ji * space, adjust HSYNC length, otherwise adjust HBP 22328bdfc5daSXin Ji */ 22338bdfc5daSXin Ji if ((adj_hbp - delta_adj) < HP_MIN) 22348bdfc5daSXin Ji /* HBP not enough space */ 22358bdfc5daSXin Ji adj_hsync -= delta_adj; 22368bdfc5daSXin Ji else 22378bdfc5daSXin Ji adj_hbp -= delta_adj; 22388bdfc5daSXin Ji } else if (adj_hbp < HP_MIN) { 22398bdfc5daSXin Ji delta_adj = HP_MIN - adj_hbp; 22408bdfc5daSXin Ji adj_hbp = HP_MIN; 22418bdfc5daSXin Ji 22428bdfc5daSXin Ji /* 22438bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP hasn't enough space, 22448bdfc5daSXin Ji * adjust HSYNC length, otherwize adjust HBP 22458bdfc5daSXin Ji */ 22468bdfc5daSXin Ji if ((adj_hfp - delta_adj) < HP_MIN) 22478bdfc5daSXin Ji /* HFP not enough space */ 22488bdfc5daSXin Ji adj_hsync -= delta_adj; 22498bdfc5daSXin Ji else 22508bdfc5daSXin Ji adj_hfp -= delta_adj; 22518bdfc5daSXin Ji } 22528bdfc5daSXin Ji 22538bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 22548bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 22558bdfc5daSXin Ji adj_hsync, adj_hfp, adj_hbp, adj->clock); 22568bdfc5daSXin Ji 22578bdfc5daSXin Ji /* Reconstruct timing */ 22588bdfc5daSXin Ji adj->hsync_start = adj->hdisplay + adj_hfp; 22598bdfc5daSXin Ji adj->hsync_end = adj->hsync_start + adj_hsync; 22608bdfc5daSXin Ji adj->htotal = adj->hsync_end + adj_hbp; 22618bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 22628bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 22638bdfc5daSXin Ji 22648bdfc5daSXin Ji return true; 22658bdfc5daSXin Ji } 22668bdfc5daSXin Ji 2267191be002SXin Ji static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2268191be002SXin Ji struct drm_bridge_state *bridge_state, 2269191be002SXin Ji struct drm_crtc_state *crtc_state, 2270191be002SXin Ji struct drm_connector_state *conn_state) 22718bdfc5daSXin Ji { 22728bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 22738bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 22748bdfc5daSXin Ji 2275191be002SXin Ji dev_dbg(dev, "drm bridge atomic check\n"); 2276cd1637c7SXin Ji 2277cd1637c7SXin Ji anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2278191be002SXin Ji &crtc_state->adjusted_mode); 2279cd1637c7SXin Ji 2280cd1637c7SXin Ji return anx7625_connector_atomic_check(ctx, conn_state); 2281191be002SXin Ji } 2282191be002SXin Ji 2283191be002SXin Ji static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2284191be002SXin Ji struct drm_bridge_state *state) 2285191be002SXin Ji { 2286191be002SXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2287191be002SXin Ji struct device *dev = &ctx->client->dev; 2288191be002SXin Ji struct drm_connector *connector; 2289191be002SXin Ji 2290191be002SXin Ji dev_dbg(dev, "drm atomic enable\n"); 2291191be002SXin Ji 2292191be002SXin Ji if (!bridge->encoder) { 2293191be002SXin Ji dev_err(dev, "Parent encoder object not found"); 2294191be002SXin Ji return; 2295191be002SXin Ji } 2296191be002SXin Ji 2297191be002SXin Ji connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2298191be002SXin Ji bridge->encoder); 2299191be002SXin Ji if (!connector) 2300191be002SXin Ji return; 2301191be002SXin Ji 2302191be002SXin Ji ctx->connector = connector; 23038bdfc5daSXin Ji 230460487584SPi-Hsun Shih pm_runtime_get_sync(dev); 23058bdfc5daSXin Ji 23068bdfc5daSXin Ji anx7625_dp_start(ctx); 23078bdfc5daSXin Ji } 23088bdfc5daSXin Ji 2309191be002SXin Ji static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2310191be002SXin Ji struct drm_bridge_state *old) 23118bdfc5daSXin Ji { 23128bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 23138bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 23148bdfc5daSXin Ji 2315191be002SXin Ji dev_dbg(dev, "drm atomic disable\n"); 23168bdfc5daSXin Ji 2317191be002SXin Ji ctx->connector = NULL; 23188bdfc5daSXin Ji anx7625_dp_stop(ctx); 23198bdfc5daSXin Ji 23203203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 23218bdfc5daSXin Ji } 23228bdfc5daSXin Ji 23238bdfc5daSXin Ji static enum drm_connector_status 23248bdfc5daSXin Ji anx7625_bridge_detect(struct drm_bridge *bridge) 23258bdfc5daSXin Ji { 23268bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 23278bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 23288bdfc5daSXin Ji 23298bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 23308bdfc5daSXin Ji 23318bdfc5daSXin Ji return anx7625_sink_detect(ctx); 23328bdfc5daSXin Ji } 23338bdfc5daSXin Ji 23348bdfc5daSXin Ji static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 23358bdfc5daSXin Ji struct drm_connector *connector) 23368bdfc5daSXin Ji { 23378bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 23388bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 23398bdfc5daSXin Ji 23408bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 23418bdfc5daSXin Ji 23428bdfc5daSXin Ji return anx7625_get_edid(ctx); 23438bdfc5daSXin Ji } 23448bdfc5daSXin Ji 23458bdfc5daSXin Ji static const struct drm_bridge_funcs anx7625_bridge_funcs = { 23468bdfc5daSXin Ji .attach = anx7625_bridge_attach, 23478bdfc5daSXin Ji .mode_valid = anx7625_bridge_mode_valid, 23488bdfc5daSXin Ji .mode_set = anx7625_bridge_mode_set, 2349191be002SXin Ji .atomic_check = anx7625_bridge_atomic_check, 2350191be002SXin Ji .atomic_enable = anx7625_bridge_atomic_enable, 2351191be002SXin Ji .atomic_disable = anx7625_bridge_atomic_disable, 2352191be002SXin Ji .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2353191be002SXin Ji .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2354191be002SXin Ji .atomic_reset = drm_atomic_helper_bridge_reset, 23558bdfc5daSXin Ji .detect = anx7625_bridge_detect, 23568bdfc5daSXin Ji .get_edid = anx7625_bridge_get_edid, 23578bdfc5daSXin Ji }; 23588bdfc5daSXin Ji 23598bdfc5daSXin Ji static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 23608bdfc5daSXin Ji struct i2c_client *client) 23618bdfc5daSXin Ji { 2362f5f05ddcSMiaoqian Lin int err = 0; 2363f5f05ddcSMiaoqian Lin 23648bdfc5daSXin Ji ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 23658bdfc5daSXin Ji TX_P0_ADDR >> 1); 2366f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p0_client)) 2367f5f05ddcSMiaoqian Lin return PTR_ERR(ctx->i2c.tx_p0_client); 23688bdfc5daSXin Ji 23698bdfc5daSXin Ji ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 23708bdfc5daSXin Ji TX_P1_ADDR >> 1); 2371f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p1_client)) { 2372f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tx_p1_client); 23738bdfc5daSXin Ji goto free_tx_p0; 2374f5f05ddcSMiaoqian Lin } 23758bdfc5daSXin Ji 23768bdfc5daSXin Ji ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 23778bdfc5daSXin Ji TX_P2_ADDR >> 1); 2378f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p2_client)) { 2379f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tx_p2_client); 23808bdfc5daSXin Ji goto free_tx_p1; 2381f5f05ddcSMiaoqian Lin } 23828bdfc5daSXin Ji 23838bdfc5daSXin Ji ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 23848bdfc5daSXin Ji RX_P0_ADDR >> 1); 2385f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p0_client)) { 2386f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p0_client); 23878bdfc5daSXin Ji goto free_tx_p2; 2388f5f05ddcSMiaoqian Lin } 23898bdfc5daSXin Ji 23908bdfc5daSXin Ji ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 23918bdfc5daSXin Ji RX_P1_ADDR >> 1); 2392f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p1_client)) { 2393f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p1_client); 23948bdfc5daSXin Ji goto free_rx_p0; 2395f5f05ddcSMiaoqian Lin } 23968bdfc5daSXin Ji 23978bdfc5daSXin Ji ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 23988bdfc5daSXin Ji RX_P2_ADDR >> 1); 2399f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.rx_p2_client)) { 2400f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.rx_p2_client); 24018bdfc5daSXin Ji goto free_rx_p1; 2402f5f05ddcSMiaoqian Lin } 24038bdfc5daSXin Ji 24048bdfc5daSXin Ji ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 24058bdfc5daSXin Ji TCPC_INTERFACE_ADDR >> 1); 2406f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tcpc_client)) { 2407f5f05ddcSMiaoqian Lin err = PTR_ERR(ctx->i2c.tcpc_client); 24088bdfc5daSXin Ji goto free_rx_p2; 2409f5f05ddcSMiaoqian Lin } 24108bdfc5daSXin Ji 24118bdfc5daSXin Ji return 0; 24128bdfc5daSXin Ji 24138bdfc5daSXin Ji free_rx_p2: 24148bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 24158bdfc5daSXin Ji free_rx_p1: 24168bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 24178bdfc5daSXin Ji free_rx_p0: 24188bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 24198bdfc5daSXin Ji free_tx_p2: 24208bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 24218bdfc5daSXin Ji free_tx_p1: 24228bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 24238bdfc5daSXin Ji free_tx_p0: 24248bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 24258bdfc5daSXin Ji 2426f5f05ddcSMiaoqian Lin return err; 24278bdfc5daSXin Ji } 24288bdfc5daSXin Ji 24298bdfc5daSXin Ji static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 24308bdfc5daSXin Ji { 24318bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 24328bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 24338bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 24348bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 24358bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 24368bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 24378bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tcpc_client); 24388bdfc5daSXin Ji } 24398bdfc5daSXin Ji 244060487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 244160487584SPi-Hsun Shih { 244260487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 244360487584SPi-Hsun Shih 244460487584SPi-Hsun Shih mutex_lock(&ctx->lock); 244560487584SPi-Hsun Shih 244660487584SPi-Hsun Shih anx7625_stop_dp_work(ctx); 244760487584SPi-Hsun Shih anx7625_power_standby(ctx); 244860487584SPi-Hsun Shih 244960487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 245060487584SPi-Hsun Shih 245160487584SPi-Hsun Shih return 0; 245260487584SPi-Hsun Shih } 245360487584SPi-Hsun Shih 245460487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 245560487584SPi-Hsun Shih { 245660487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 245760487584SPi-Hsun Shih 245860487584SPi-Hsun Shih mutex_lock(&ctx->lock); 245960487584SPi-Hsun Shih 246060487584SPi-Hsun Shih anx7625_power_on_init(ctx); 246160487584SPi-Hsun Shih anx7625_hpd_polling(ctx); 246260487584SPi-Hsun Shih 246360487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 246460487584SPi-Hsun Shih 246560487584SPi-Hsun Shih return 0; 246660487584SPi-Hsun Shih } 246760487584SPi-Hsun Shih 2468409776faSPi-Hsun Shih static int __maybe_unused anx7625_resume(struct device *dev) 2469409776faSPi-Hsun Shih { 2470409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 2471409776faSPi-Hsun Shih 2472409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 2473409776faSPi-Hsun Shih return 0; 2474409776faSPi-Hsun Shih 2475409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2476409776faSPi-Hsun Shih enable_irq(ctx->pdata.intp_irq); 2477409776faSPi-Hsun Shih anx7625_runtime_pm_resume(dev); 2478409776faSPi-Hsun Shih } 2479409776faSPi-Hsun Shih 2480409776faSPi-Hsun Shih return 0; 2481409776faSPi-Hsun Shih } 2482409776faSPi-Hsun Shih 2483409776faSPi-Hsun Shih static int __maybe_unused anx7625_suspend(struct device *dev) 2484409776faSPi-Hsun Shih { 2485409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 2486409776faSPi-Hsun Shih 2487409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 2488409776faSPi-Hsun Shih return 0; 2489409776faSPi-Hsun Shih 2490409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2491409776faSPi-Hsun Shih anx7625_runtime_pm_suspend(dev); 2492409776faSPi-Hsun Shih disable_irq(ctx->pdata.intp_irq); 2493409776faSPi-Hsun Shih } 2494409776faSPi-Hsun Shih 2495409776faSPi-Hsun Shih return 0; 2496409776faSPi-Hsun Shih } 2497409776faSPi-Hsun Shih 249860487584SPi-Hsun Shih static const struct dev_pm_ops anx7625_pm_ops = { 2499409776faSPi-Hsun Shih SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 250060487584SPi-Hsun Shih SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 250160487584SPi-Hsun Shih anx7625_runtime_pm_resume, NULL) 250260487584SPi-Hsun Shih }; 250360487584SPi-Hsun Shih 25048bdfc5daSXin Ji static int anx7625_i2c_probe(struct i2c_client *client, 25058bdfc5daSXin Ji const struct i2c_device_id *id) 25068bdfc5daSXin Ji { 25078bdfc5daSXin Ji struct anx7625_data *platform; 25088bdfc5daSXin Ji struct anx7625_platform_data *pdata; 25098bdfc5daSXin Ji int ret = 0; 25108bdfc5daSXin Ji struct device *dev = &client->dev; 25118bdfc5daSXin Ji 25128bdfc5daSXin Ji if (!i2c_check_functionality(client->adapter, 25138bdfc5daSXin Ji I2C_FUNC_SMBUS_I2C_BLOCK)) { 25148bdfc5daSXin Ji DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 25158bdfc5daSXin Ji return -ENODEV; 25168bdfc5daSXin Ji } 25178bdfc5daSXin Ji 25188bdfc5daSXin Ji platform = kzalloc(sizeof(*platform), GFP_KERNEL); 25198bdfc5daSXin Ji if (!platform) { 25208bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 25218bdfc5daSXin Ji return -ENOMEM; 25228bdfc5daSXin Ji } 25238bdfc5daSXin Ji 25248bdfc5daSXin Ji pdata = &platform->pdata; 25258bdfc5daSXin Ji 25268bdfc5daSXin Ji ret = anx7625_parse_dt(dev, pdata); 25278bdfc5daSXin Ji if (ret) { 25288bdfc5daSXin Ji if (ret != -EPROBE_DEFER) 25298bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 25308bdfc5daSXin Ji goto free_platform; 25318bdfc5daSXin Ji } 25328bdfc5daSXin Ji 25338bdfc5daSXin Ji platform->client = client; 25348bdfc5daSXin Ji i2c_set_clientdata(client, platform); 25358bdfc5daSXin Ji 25366c744983SHsin-Yi Wang pdata->supplies[0].supply = "vdd10"; 25376c744983SHsin-Yi Wang pdata->supplies[1].supply = "vdd18"; 25386c744983SHsin-Yi Wang pdata->supplies[2].supply = "vdd33"; 25396c744983SHsin-Yi Wang ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 25406c744983SHsin-Yi Wang pdata->supplies); 25416c744983SHsin-Yi Wang if (ret) { 25426c744983SHsin-Yi Wang DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 25436c744983SHsin-Yi Wang return ret; 25446c744983SHsin-Yi Wang } 25458bdfc5daSXin Ji anx7625_init_gpio(platform); 25468bdfc5daSXin Ji 25478bdfc5daSXin Ji mutex_init(&platform->lock); 2548cd1637c7SXin Ji mutex_init(&platform->hdcp_wq_lock); 2549cd1637c7SXin Ji 2550cd1637c7SXin Ji INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2551cd1637c7SXin Ji platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2552cd1637c7SXin Ji if (!platform->hdcp_workqueue) { 2553cd1637c7SXin Ji dev_err(dev, "fail to create work queue\n"); 2554cd1637c7SXin Ji ret = -ENOMEM; 2555cd1637c7SXin Ji goto free_platform; 2556cd1637c7SXin Ji } 25578bdfc5daSXin Ji 25588bdfc5daSXin Ji platform->pdata.intp_irq = client->irq; 25598bdfc5daSXin Ji if (platform->pdata.intp_irq) { 25608bdfc5daSXin Ji INIT_WORK(&platform->work, anx7625_work_func); 2561f03ab662SPi-Hsun Shih platform->workqueue = alloc_workqueue("anx7625_work", 2562f03ab662SPi-Hsun Shih WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 25638bdfc5daSXin Ji if (!platform->workqueue) { 25648bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create work queue\n"); 25658bdfc5daSXin Ji ret = -ENOMEM; 2566cd1637c7SXin Ji goto free_hdcp_wq; 25678bdfc5daSXin Ji } 25688bdfc5daSXin Ji 25698bdfc5daSXin Ji ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 25708bdfc5daSXin Ji NULL, anx7625_intr_hpd_isr, 25718bdfc5daSXin Ji IRQF_TRIGGER_FALLING | 25728bdfc5daSXin Ji IRQF_ONESHOT, 25738bdfc5daSXin Ji "anx7625-intp", platform); 25748bdfc5daSXin Ji if (ret) { 25758bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to request irq\n"); 25768bdfc5daSXin Ji goto free_wq; 25778bdfc5daSXin Ji } 25788bdfc5daSXin Ji } 25798bdfc5daSXin Ji 25808bdfc5daSXin Ji if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 25818bdfc5daSXin Ji ret = -ENOMEM; 25828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 25838bdfc5daSXin Ji goto free_wq; 25848bdfc5daSXin Ji } 25858bdfc5daSXin Ji 258660487584SPi-Hsun Shih pm_runtime_enable(dev); 258760487584SPi-Hsun Shih 258860487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) { 25898bdfc5daSXin Ji anx7625_disable_pd_protocol(platform); 259060487584SPi-Hsun Shih pm_runtime_get_sync(dev); 25918bdfc5daSXin Ji } 25928bdfc5daSXin Ji 25938bdfc5daSXin Ji /* Add work function */ 25948bdfc5daSXin Ji if (platform->pdata.intp_irq) 25958bdfc5daSXin Ji queue_work(platform->workqueue, &platform->work); 25968bdfc5daSXin Ji 25978bdfc5daSXin Ji platform->bridge.funcs = &anx7625_bridge_funcs; 25988bdfc5daSXin Ji platform->bridge.of_node = client->dev.of_node; 2599fd0310b6SXin Ji platform->bridge.ops = DRM_BRIDGE_OP_EDID; 2600fd0310b6SXin Ji if (!platform->pdata.panel_bridge) 2601fd0310b6SXin Ji platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2602fd0310b6SXin Ji DRM_BRIDGE_OP_DETECT; 2603fd0310b6SXin Ji platform->bridge.type = platform->pdata.panel_bridge ? 2604fd0310b6SXin Ji DRM_MODE_CONNECTOR_eDP : 2605fd0310b6SXin Ji DRM_MODE_CONNECTOR_DisplayPort; 2606fd0310b6SXin Ji 26078bdfc5daSXin Ji drm_bridge_add(&platform->bridge); 26088bdfc5daSXin Ji 2609fd0310b6SXin Ji if (!platform->pdata.is_dpi) { 261049e61beeSMaxime Ripard ret = anx7625_attach_dsi(platform); 261149e61beeSMaxime Ripard if (ret) { 261249e61beeSMaxime Ripard DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 261349e61beeSMaxime Ripard goto unregister_bridge; 261449e61beeSMaxime Ripard } 2615fd0310b6SXin Ji } 261649e61beeSMaxime Ripard 2617566fef12SXin Ji if (platform->pdata.audio_en) 2618566fef12SXin Ji anx7625_register_audio(dev, platform); 2619566fef12SXin Ji 26208bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 26218bdfc5daSXin Ji 26228bdfc5daSXin Ji return 0; 26238bdfc5daSXin Ji 262449e61beeSMaxime Ripard unregister_bridge: 262549e61beeSMaxime Ripard drm_bridge_remove(&platform->bridge); 262649e61beeSMaxime Ripard 262749e61beeSMaxime Ripard if (!platform->pdata.low_power_mode) 262849e61beeSMaxime Ripard pm_runtime_put_sync_suspend(&client->dev); 262949e61beeSMaxime Ripard 263049e61beeSMaxime Ripard anx7625_unregister_i2c_dummy_clients(platform); 263149e61beeSMaxime Ripard 26328bdfc5daSXin Ji free_wq: 26338bdfc5daSXin Ji if (platform->workqueue) 26348bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 26358bdfc5daSXin Ji 2636cd1637c7SXin Ji free_hdcp_wq: 2637cd1637c7SXin Ji if (platform->hdcp_workqueue) 2638cd1637c7SXin Ji destroy_workqueue(platform->hdcp_workqueue); 2639cd1637c7SXin Ji 26408bdfc5daSXin Ji free_platform: 26418bdfc5daSXin Ji kfree(platform); 26428bdfc5daSXin Ji 26438bdfc5daSXin Ji return ret; 26448bdfc5daSXin Ji } 26458bdfc5daSXin Ji 26468bdfc5daSXin Ji static int anx7625_i2c_remove(struct i2c_client *client) 26478bdfc5daSXin Ji { 26488bdfc5daSXin Ji struct anx7625_data *platform = i2c_get_clientdata(client); 26498bdfc5daSXin Ji 26508bdfc5daSXin Ji drm_bridge_remove(&platform->bridge); 26518bdfc5daSXin Ji 26528bdfc5daSXin Ji if (platform->pdata.intp_irq) 26538bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 26548bdfc5daSXin Ji 2655cd1637c7SXin Ji if (platform->hdcp_workqueue) { 2656cd1637c7SXin Ji cancel_delayed_work(&platform->hdcp_work); 2657cd1637c7SXin Ji flush_workqueue(platform->workqueue); 2658cd1637c7SXin Ji destroy_workqueue(platform->workqueue); 2659cd1637c7SXin Ji } 2660cd1637c7SXin Ji 266160487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) 266260487584SPi-Hsun Shih pm_runtime_put_sync_suspend(&client->dev); 266360487584SPi-Hsun Shih 26648bdfc5daSXin Ji anx7625_unregister_i2c_dummy_clients(platform); 26658bdfc5daSXin Ji 2666566fef12SXin Ji if (platform->pdata.audio_en) 2667566fef12SXin Ji anx7625_unregister_audio(platform); 2668566fef12SXin Ji 26698bdfc5daSXin Ji kfree(platform); 26708bdfc5daSXin Ji return 0; 26718bdfc5daSXin Ji } 26728bdfc5daSXin Ji 26738bdfc5daSXin Ji static const struct i2c_device_id anx7625_id[] = { 26748bdfc5daSXin Ji {"anx7625", 0}, 26758bdfc5daSXin Ji {} 26768bdfc5daSXin Ji }; 26778bdfc5daSXin Ji 26788bdfc5daSXin Ji MODULE_DEVICE_TABLE(i2c, anx7625_id); 26798bdfc5daSXin Ji 26808bdfc5daSXin Ji static const struct of_device_id anx_match_table[] = { 26818bdfc5daSXin Ji {.compatible = "analogix,anx7625",}, 26828bdfc5daSXin Ji {}, 26838bdfc5daSXin Ji }; 2684ad5fd900SYu Jiahua MODULE_DEVICE_TABLE(of, anx_match_table); 26858bdfc5daSXin Ji 26868bdfc5daSXin Ji static struct i2c_driver anx7625_driver = { 26878bdfc5daSXin Ji .driver = { 26888bdfc5daSXin Ji .name = "anx7625", 26898bdfc5daSXin Ji .of_match_table = anx_match_table, 269060487584SPi-Hsun Shih .pm = &anx7625_pm_ops, 26918bdfc5daSXin Ji }, 26928bdfc5daSXin Ji .probe = anx7625_i2c_probe, 26938bdfc5daSXin Ji .remove = anx7625_i2c_remove, 26948bdfc5daSXin Ji 26958bdfc5daSXin Ji .id_table = anx7625_id, 26968bdfc5daSXin Ji }; 26978bdfc5daSXin Ji 26988bdfc5daSXin Ji module_i2c_driver(anx7625_driver); 26998bdfc5daSXin Ji 27008bdfc5daSXin Ji MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 27018bdfc5daSXin Ji MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 27028bdfc5daSXin Ji MODULE_LICENSE("GPL v2"); 27038bdfc5daSXin Ji MODULE_VERSION(ANX7625_DRV_VERSION); 2704