18bdfc5daSXin Ji // SPDX-License-Identifier: GPL-2.0-only 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji #include <linux/gcd.h> 78bdfc5daSXin Ji #include <linux/gpio/consumer.h> 88bdfc5daSXin Ji #include <linux/i2c.h> 98bdfc5daSXin Ji #include <linux/interrupt.h> 108bdfc5daSXin Ji #include <linux/iopoll.h> 118bdfc5daSXin Ji #include <linux/kernel.h> 128bdfc5daSXin Ji #include <linux/module.h> 138bdfc5daSXin Ji #include <linux/mutex.h> 1460487584SPi-Hsun Shih #include <linux/pm_runtime.h> 156c744983SHsin-Yi Wang #include <linux/regulator/consumer.h> 168bdfc5daSXin Ji #include <linux/slab.h> 178bdfc5daSXin Ji #include <linux/types.h> 188bdfc5daSXin Ji #include <linux/workqueue.h> 198bdfc5daSXin Ji 208bdfc5daSXin Ji #include <linux/of_graph.h> 218bdfc5daSXin Ji #include <linux/of_platform.h> 228bdfc5daSXin Ji 23da68386dSThomas Zimmermann #include <drm/display/drm_dp_aux_bus.h> 24da68386dSThomas Zimmermann #include <drm/display/drm_dp_helper.h> 256a99099fSThomas Zimmermann #include <drm/display/drm_hdcp_helper.h> 268bdfc5daSXin Ji #include <drm/drm_atomic_helper.h> 278bdfc5daSXin Ji #include <drm/drm_bridge.h> 288bdfc5daSXin Ji #include <drm/drm_edid.h> 298bdfc5daSXin Ji #include <drm/drm_mipi_dsi.h> 308bdfc5daSXin Ji #include <drm/drm_of.h> 318bdfc5daSXin Ji #include <drm/drm_panel.h> 328bdfc5daSXin Ji #include <drm/drm_print.h> 338bdfc5daSXin Ji #include <drm/drm_probe_helper.h> 348bdfc5daSXin Ji 35fd0310b6SXin Ji #include <media/v4l2-fwnode.h> 36566fef12SXin Ji #include <sound/hdmi-codec.h> 378bdfc5daSXin Ji #include <video/display_timing.h> 388bdfc5daSXin Ji 398bdfc5daSXin Ji #include "anx7625.h" 408bdfc5daSXin Ji 418bdfc5daSXin Ji /* 428bdfc5daSXin Ji * There is a sync issue while access I2C register between AP(CPU) and 438bdfc5daSXin Ji * internal firmware(OCM), to avoid the race condition, AP should access 448bdfc5daSXin Ji * the reserved slave address before slave address occurs changes. 458bdfc5daSXin Ji */ 468bdfc5daSXin Ji static int i2c_access_workaround(struct anx7625_data *ctx, 478bdfc5daSXin Ji struct i2c_client *client) 488bdfc5daSXin Ji { 498bdfc5daSXin Ji u8 offset; 508bdfc5daSXin Ji struct device *dev = &client->dev; 518bdfc5daSXin Ji int ret; 528bdfc5daSXin Ji 538bdfc5daSXin Ji if (client == ctx->last_client) 548bdfc5daSXin Ji return 0; 558bdfc5daSXin Ji 568bdfc5daSXin Ji ctx->last_client = client; 578bdfc5daSXin Ji 588bdfc5daSXin Ji if (client == ctx->i2c.tcpc_client) 598bdfc5daSXin Ji offset = RSVD_00_ADDR; 608bdfc5daSXin Ji else if (client == ctx->i2c.tx_p0_client) 618bdfc5daSXin Ji offset = RSVD_D1_ADDR; 628bdfc5daSXin Ji else if (client == ctx->i2c.tx_p1_client) 638bdfc5daSXin Ji offset = RSVD_60_ADDR; 648bdfc5daSXin Ji else if (client == ctx->i2c.rx_p0_client) 658bdfc5daSXin Ji offset = RSVD_39_ADDR; 668bdfc5daSXin Ji else if (client == ctx->i2c.rx_p1_client) 678bdfc5daSXin Ji offset = RSVD_7F_ADDR; 688bdfc5daSXin Ji else 698bdfc5daSXin Ji offset = RSVD_00_ADDR; 708bdfc5daSXin Ji 718bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, offset, 0x00); 728bdfc5daSXin Ji if (ret < 0) 738bdfc5daSXin Ji DRM_DEV_ERROR(dev, 748bdfc5daSXin Ji "fail to access i2c id=%x\n:%x", 758bdfc5daSXin Ji client->addr, offset); 768bdfc5daSXin Ji 778bdfc5daSXin Ji return ret; 788bdfc5daSXin Ji } 798bdfc5daSXin Ji 808bdfc5daSXin Ji static int anx7625_reg_read(struct anx7625_data *ctx, 818bdfc5daSXin Ji struct i2c_client *client, u8 reg_addr) 828bdfc5daSXin Ji { 838bdfc5daSXin Ji int ret; 848bdfc5daSXin Ji struct device *dev = &client->dev; 858bdfc5daSXin Ji 868bdfc5daSXin Ji i2c_access_workaround(ctx, client); 878bdfc5daSXin Ji 888bdfc5daSXin Ji ret = i2c_smbus_read_byte_data(client, reg_addr); 898bdfc5daSXin Ji if (ret < 0) 908bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 918bdfc5daSXin Ji client->addr, reg_addr); 928bdfc5daSXin Ji 938bdfc5daSXin Ji return ret; 948bdfc5daSXin Ji } 958bdfc5daSXin Ji 968bdfc5daSXin Ji static int anx7625_reg_block_read(struct anx7625_data *ctx, 978bdfc5daSXin Ji struct i2c_client *client, 988bdfc5daSXin Ji u8 reg_addr, u8 len, u8 *buf) 998bdfc5daSXin Ji { 1008bdfc5daSXin Ji int ret; 1018bdfc5daSXin Ji struct device *dev = &client->dev; 1028bdfc5daSXin Ji 1038bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1048bdfc5daSXin Ji 1058bdfc5daSXin Ji ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 1068bdfc5daSXin Ji if (ret < 0) 1078bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 1088bdfc5daSXin Ji client->addr, reg_addr); 1098bdfc5daSXin Ji 1108bdfc5daSXin Ji return ret; 1118bdfc5daSXin Ji } 1128bdfc5daSXin Ji 1138bdfc5daSXin Ji static int anx7625_reg_write(struct anx7625_data *ctx, 1148bdfc5daSXin Ji struct i2c_client *client, 1158bdfc5daSXin Ji u8 reg_addr, u8 reg_val) 1168bdfc5daSXin Ji { 1178bdfc5daSXin Ji int ret; 1188bdfc5daSXin Ji struct device *dev = &client->dev; 1198bdfc5daSXin Ji 1208bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1218bdfc5daSXin Ji 1228bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 1238bdfc5daSXin Ji 1248bdfc5daSXin Ji if (ret < 0) 1258bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 1268bdfc5daSXin Ji client->addr, reg_addr); 1278bdfc5daSXin Ji 1288bdfc5daSXin Ji return ret; 1298bdfc5daSXin Ji } 1308bdfc5daSXin Ji 131548b512eSXin Ji static int anx7625_reg_block_write(struct anx7625_data *ctx, 132548b512eSXin Ji struct i2c_client *client, 133548b512eSXin Ji u8 reg_addr, u8 len, u8 *buf) 134548b512eSXin Ji { 135548b512eSXin Ji int ret; 136548b512eSXin Ji struct device *dev = &client->dev; 137548b512eSXin Ji 138548b512eSXin Ji i2c_access_workaround(ctx, client); 139548b512eSXin Ji 140548b512eSXin Ji ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 141548b512eSXin Ji if (ret < 0) 142548b512eSXin Ji dev_err(dev, "write i2c block failed id=%x\n:%x", 143548b512eSXin Ji client->addr, reg_addr); 144548b512eSXin Ji 145548b512eSXin Ji return ret; 146548b512eSXin Ji } 147548b512eSXin Ji 1488bdfc5daSXin Ji static int anx7625_write_or(struct anx7625_data *ctx, 1498bdfc5daSXin Ji struct i2c_client *client, 1508bdfc5daSXin Ji u8 offset, u8 mask) 1518bdfc5daSXin Ji { 1528bdfc5daSXin Ji int val; 1538bdfc5daSXin Ji 1548bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1558bdfc5daSXin Ji if (val < 0) 1568bdfc5daSXin Ji return val; 1578bdfc5daSXin Ji 1588bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val | (mask))); 1598bdfc5daSXin Ji } 1608bdfc5daSXin Ji 1618bdfc5daSXin Ji static int anx7625_write_and(struct anx7625_data *ctx, 1628bdfc5daSXin Ji struct i2c_client *client, 1638bdfc5daSXin Ji u8 offset, u8 mask) 1648bdfc5daSXin Ji { 1658bdfc5daSXin Ji int val; 1668bdfc5daSXin Ji 1678bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1688bdfc5daSXin Ji if (val < 0) 1698bdfc5daSXin Ji return val; 1708bdfc5daSXin Ji 1718bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val & (mask))); 1728bdfc5daSXin Ji } 1738bdfc5daSXin Ji 174566fef12SXin Ji static int anx7625_write_and_or(struct anx7625_data *ctx, 175566fef12SXin Ji struct i2c_client *client, 176566fef12SXin Ji u8 offset, u8 and_mask, u8 or_mask) 177566fef12SXin Ji { 178566fef12SXin Ji int val; 179566fef12SXin Ji 180566fef12SXin Ji val = anx7625_reg_read(ctx, client, offset); 181566fef12SXin Ji if (val < 0) 182566fef12SXin Ji return val; 183566fef12SXin Ji 184566fef12SXin Ji return anx7625_reg_write(ctx, client, 185566fef12SXin Ji offset, (val & and_mask) | (or_mask)); 186566fef12SXin Ji } 187566fef12SXin Ji 188fd0310b6SXin Ji static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 1898bdfc5daSXin Ji { 190fd0310b6SXin Ji int i, ret; 1918bdfc5daSXin Ji 192fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 193fd0310b6SXin Ji AUDIO_CONTROL_REGISTER, 0x80); 194fd0310b6SXin Ji for (i = 0; i < 13; i++) 195fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 196fd0310b6SXin Ji VIDEO_BIT_MATRIX_12 + i, 197fd0310b6SXin Ji 0x18 + i); 1988bdfc5daSXin Ji 199fd0310b6SXin Ji return ret; 2008bdfc5daSXin Ji } 2018bdfc5daSXin Ji 2028bdfc5daSXin Ji static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 2038bdfc5daSXin Ji { 2048bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 2058bdfc5daSXin Ji } 2068bdfc5daSXin Ji 2078bdfc5daSXin Ji static int wait_aux_op_finish(struct anx7625_data *ctx) 2088bdfc5daSXin Ji { 209d65feac2SPin-yen Lin struct device *dev = ctx->dev; 2108bdfc5daSXin Ji int val; 2118bdfc5daSXin Ji int ret; 2128bdfc5daSXin Ji 2138bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 2148bdfc5daSXin Ji ctx, val, 2158bdfc5daSXin Ji (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 2168bdfc5daSXin Ji 2000, 2178bdfc5daSXin Ji 2000 * 150); 2188bdfc5daSXin Ji if (ret) { 2198bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux operation fail!\n"); 2208bdfc5daSXin Ji return -EIO; 2218bdfc5daSXin Ji } 2228bdfc5daSXin Ji 2238bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 2248bdfc5daSXin Ji AP_AUX_CTRL_STATUS); 2258bdfc5daSXin Ji if (val < 0 || (val & 0x0F)) { 2268bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux status %02x\n", val); 2279a7e49bdSXin Ji return -EIO; 2288bdfc5daSXin Ji } 2298bdfc5daSXin Ji 2309a7e49bdSXin Ji return 0; 2318bdfc5daSXin Ji } 2328bdfc5daSXin Ji 233adca62ecSHsin-Yi Wang static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 234adca62ecSHsin-Yi Wang u8 len, u8 *buf) 235cd1637c7SXin Ji { 236d65feac2SPin-yen Lin struct device *dev = ctx->dev; 237cd1637c7SXin Ji int ret; 238cd1637c7SXin Ji u8 addrh, addrm, addrl; 239cd1637c7SXin Ji u8 cmd; 240adca62ecSHsin-Yi Wang bool is_write = !(op & DP_AUX_I2C_READ); 241cd1637c7SXin Ji 242adca62ecSHsin-Yi Wang if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 243cd1637c7SXin Ji dev_err(dev, "exceed aux buffer len.\n"); 244cd1637c7SXin Ji return -EINVAL; 245cd1637c7SXin Ji } 246cd1637c7SXin Ji 247adca62ecSHsin-Yi Wang if (!len) 248adca62ecSHsin-Yi Wang return len; 249adca62ecSHsin-Yi Wang 250cd1637c7SXin Ji addrl = address & 0xFF; 251cd1637c7SXin Ji addrm = (address >> 8) & 0xFF; 252cd1637c7SXin Ji addrh = (address >> 16) & 0xFF; 253cd1637c7SXin Ji 254c0bbed90SHsin-Yi Wang if (!is_write) 255c0bbed90SHsin-Yi Wang op &= ~DP_AUX_I2C_MOT; 256548b512eSXin Ji cmd = DPCD_CMD(len, op); 257cd1637c7SXin Ji 258cd1637c7SXin Ji /* Set command and length */ 259cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 260cd1637c7SXin Ji AP_AUX_COMMAND, cmd); 261cd1637c7SXin Ji 262cd1637c7SXin Ji /* Set aux access address */ 263cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 264cd1637c7SXin Ji AP_AUX_ADDR_7_0, addrl); 265cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 266cd1637c7SXin Ji AP_AUX_ADDR_15_8, addrm); 267cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 268cd1637c7SXin Ji AP_AUX_ADDR_19_16, addrh); 269cd1637c7SXin Ji 270adca62ecSHsin-Yi Wang if (is_write) 271548b512eSXin Ji ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 272548b512eSXin Ji AP_AUX_BUFF_START, len, buf); 273cd1637c7SXin Ji /* Enable aux access */ 274cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 275cd1637c7SXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 276cd1637c7SXin Ji 277cd1637c7SXin Ji if (ret < 0) { 278cd1637c7SXin Ji dev_err(dev, "cannot access aux related register.\n"); 279cd1637c7SXin Ji return -EIO; 280cd1637c7SXin Ji } 281cd1637c7SXin Ji 282cd1637c7SXin Ji ret = wait_aux_op_finish(ctx); 283adca62ecSHsin-Yi Wang if (ret < 0) { 284cd1637c7SXin Ji dev_err(dev, "aux IO error: wait aux op finish.\n"); 285cd1637c7SXin Ji return ret; 286cd1637c7SXin Ji } 287cd1637c7SXin Ji 288548b512eSXin Ji /* Write done */ 289adca62ecSHsin-Yi Wang if (is_write) 290adca62ecSHsin-Yi Wang return len; 291548b512eSXin Ji 292548b512eSXin Ji /* Read done, read out dpcd data */ 293cd1637c7SXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 294cd1637c7SXin Ji AP_AUX_BUFF_START, len, buf); 295cd1637c7SXin Ji if (ret < 0) { 296cd1637c7SXin Ji dev_err(dev, "read dpcd register failed\n"); 297cd1637c7SXin Ji return -EIO; 298cd1637c7SXin Ji } 299cd1637c7SXin Ji 300adca62ecSHsin-Yi Wang return len; 301cd1637c7SXin Ji } 302cd1637c7SXin Ji 3038bdfc5daSXin Ji static int anx7625_video_mute_control(struct anx7625_data *ctx, 3048bdfc5daSXin Ji u8 status) 3058bdfc5daSXin Ji { 3068bdfc5daSXin Ji int ret; 3078bdfc5daSXin Ji 3088bdfc5daSXin Ji if (status) { 3098bdfc5daSXin Ji /* Set mute on flag */ 3108bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 3118bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_MUTE); 3128bdfc5daSXin Ji /* Clear mipi RX en */ 3138bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 3148bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 3158bdfc5daSXin Ji } else { 3168bdfc5daSXin Ji /* Mute off flag */ 3178bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 3188bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 3198bdfc5daSXin Ji /* Set MIPI RX EN */ 3208bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 3218bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 3228bdfc5daSXin Ji } 3238bdfc5daSXin Ji 3248bdfc5daSXin Ji return ret; 3258bdfc5daSXin Ji } 3268bdfc5daSXin Ji 3278bdfc5daSXin Ji /* Reduction of fraction a/b */ 3288bdfc5daSXin Ji static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 3298bdfc5daSXin Ji { 3308bdfc5daSXin Ji unsigned long gcd_num; 3318bdfc5daSXin Ji unsigned long tmp_a, tmp_b; 3328bdfc5daSXin Ji u32 i = 1; 3338bdfc5daSXin Ji 3348bdfc5daSXin Ji gcd_num = gcd(*a, *b); 3358bdfc5daSXin Ji *a /= gcd_num; 3368bdfc5daSXin Ji *b /= gcd_num; 3378bdfc5daSXin Ji 3388bdfc5daSXin Ji tmp_a = *a; 3398bdfc5daSXin Ji tmp_b = *b; 3408bdfc5daSXin Ji 3418bdfc5daSXin Ji while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 3428bdfc5daSXin Ji i++; 3438bdfc5daSXin Ji *a = tmp_a / i; 3448bdfc5daSXin Ji *b = tmp_b / i; 3458bdfc5daSXin Ji } 3468bdfc5daSXin Ji 3478bdfc5daSXin Ji /* 3488bdfc5daSXin Ji * In the end, make a, b larger to have higher ODFC PLL 3498bdfc5daSXin Ji * output frequency accuracy 3508bdfc5daSXin Ji */ 3518bdfc5daSXin Ji while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 3528bdfc5daSXin Ji *a <<= 1; 3538bdfc5daSXin Ji *b <<= 1; 3548bdfc5daSXin Ji } 3558bdfc5daSXin Ji 3568bdfc5daSXin Ji *a >>= 1; 3578bdfc5daSXin Ji *b >>= 1; 3588bdfc5daSXin Ji } 3598bdfc5daSXin Ji 3608bdfc5daSXin Ji static int anx7625_calculate_m_n(u32 pixelclock, 3618bdfc5daSXin Ji unsigned long *m, 3628bdfc5daSXin Ji unsigned long *n, 3638bdfc5daSXin Ji u8 *post_divider) 3648bdfc5daSXin Ji { 3658bdfc5daSXin Ji if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 3668bdfc5daSXin Ji /* Pixel clock frequency is too high */ 3678bdfc5daSXin Ji DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 3688bdfc5daSXin Ji pixelclock, 3698bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 3708bdfc5daSXin Ji return -EINVAL; 3718bdfc5daSXin Ji } 3728bdfc5daSXin Ji 3738bdfc5daSXin Ji if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 3748bdfc5daSXin Ji /* Pixel clock frequency is too low */ 3758bdfc5daSXin Ji DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 3768bdfc5daSXin Ji pixelclock, 3778bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 3788bdfc5daSXin Ji return -EINVAL; 3798bdfc5daSXin Ji } 3808bdfc5daSXin Ji 3818bdfc5daSXin Ji for (*post_divider = 1; 3828bdfc5daSXin Ji pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 3838bdfc5daSXin Ji *post_divider += 1; 3848bdfc5daSXin Ji 3858bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3868bdfc5daSXin Ji for (*post_divider = 1; 3878bdfc5daSXin Ji (pixelclock < 3888bdfc5daSXin Ji (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 3898bdfc5daSXin Ji *post_divider += 1; 3908bdfc5daSXin Ji 3918bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3928bdfc5daSXin Ji DRM_ERROR("cannot find property post_divider(%d)\n", 3938bdfc5daSXin Ji *post_divider); 3948bdfc5daSXin Ji return -EDOM; 3958bdfc5daSXin Ji } 3968bdfc5daSXin Ji } 3978bdfc5daSXin Ji 3988bdfc5daSXin Ji /* Patch to improve the accuracy */ 3998bdfc5daSXin Ji if (*post_divider == 7) { 4008bdfc5daSXin Ji /* 27,000,000 is not divisible by 7 */ 4018bdfc5daSXin Ji *post_divider = 8; 4028bdfc5daSXin Ji } else if (*post_divider == 11) { 4038bdfc5daSXin Ji /* 27,000,000 is not divisible by 11 */ 4048bdfc5daSXin Ji *post_divider = 12; 4058bdfc5daSXin Ji } else if ((*post_divider == 13) || (*post_divider == 14)) { 4068bdfc5daSXin Ji /* 27,000,000 is not divisible by 13 or 14 */ 4078bdfc5daSXin Ji *post_divider = 15; 4088bdfc5daSXin Ji } 4098bdfc5daSXin Ji 4108bdfc5daSXin Ji if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 4118bdfc5daSXin Ji DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 4128bdfc5daSXin Ji pixelclock * (*post_divider), 4138bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX); 4148bdfc5daSXin Ji return -EDOM; 4158bdfc5daSXin Ji } 4168bdfc5daSXin Ji 4178bdfc5daSXin Ji *m = pixelclock; 4188bdfc5daSXin Ji *n = XTAL_FRQ / (*post_divider); 4198bdfc5daSXin Ji 4208bdfc5daSXin Ji anx7625_reduction_of_a_fraction(m, n); 4218bdfc5daSXin Ji 4228bdfc5daSXin Ji return 0; 4238bdfc5daSXin Ji } 4248bdfc5daSXin Ji 4258bdfc5daSXin Ji static int anx7625_odfc_config(struct anx7625_data *ctx, 4268bdfc5daSXin Ji u8 post_divider) 4278bdfc5daSXin Ji { 4288bdfc5daSXin Ji int ret; 429d65feac2SPin-yen Lin struct device *dev = ctx->dev; 4308bdfc5daSXin Ji 4318bdfc5daSXin Ji /* Config input reference clock frequency 27MHz/19.2MHz */ 4328bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 4338bdfc5daSXin Ji ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 4348bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 4358bdfc5daSXin Ji (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 4368bdfc5daSXin Ji /* Post divider */ 4378bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4388bdfc5daSXin Ji MIPI_DIGITAL_PLL_8, 0x0f); 4398bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 4408bdfc5daSXin Ji post_divider << 4); 4418bdfc5daSXin Ji 4428bdfc5daSXin Ji /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 4438bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4448bdfc5daSXin Ji ~MIPI_PLL_VCO_TUNE_REG_VAL); 4458bdfc5daSXin Ji 4468bdfc5daSXin Ji /* Reset ODFC PLL */ 4478bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4488bdfc5daSXin Ji ~MIPI_PLL_RESET_N); 4498bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 4508bdfc5daSXin Ji MIPI_PLL_RESET_N); 4518bdfc5daSXin Ji 4528bdfc5daSXin Ji if (ret < 0) 4538bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error.\n"); 4548bdfc5daSXin Ji 4558bdfc5daSXin Ji return ret; 4568bdfc5daSXin Ji } 4578bdfc5daSXin Ji 4587d066dc7SXin Ji /* 4597d066dc7SXin Ji * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 4607d066dc7SXin Ji * anx7625 defined K ratio for matching MIPI input video clock and 4617d066dc7SXin Ji * DP output video clock. Increase K value can match bigger video data 4627d066dc7SXin Ji * variation. IVO panel has small variation than DP CTS spec, need 4637d066dc7SXin Ji * decrease the K value. 4647d066dc7SXin Ji */ 4657d066dc7SXin Ji static int anx7625_set_k_value(struct anx7625_data *ctx) 4667d066dc7SXin Ji { 4677d066dc7SXin Ji struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 4687d066dc7SXin Ji 4697d066dc7SXin Ji if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 4707d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4717d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3B); 4727d066dc7SXin Ji 4737d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4747d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3D); 4757d066dc7SXin Ji } 4767d066dc7SXin Ji 4778bdfc5daSXin Ji static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 4788bdfc5daSXin Ji { 479d65feac2SPin-yen Lin struct device *dev = ctx->dev; 4808bdfc5daSXin Ji unsigned long m, n; 4818bdfc5daSXin Ji u16 htotal; 4828bdfc5daSXin Ji int ret; 4838bdfc5daSXin Ji u8 post_divider = 0; 4848bdfc5daSXin Ji 4858bdfc5daSXin Ji ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 4868bdfc5daSXin Ji &m, &n, &post_divider); 4878bdfc5daSXin Ji 4888bdfc5daSXin Ji if (ret) { 4898bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 4908bdfc5daSXin Ji return ret; 4918bdfc5daSXin Ji } 4928bdfc5daSXin Ji 4938bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 4948bdfc5daSXin Ji m, n, post_divider); 4958bdfc5daSXin Ji 4968bdfc5daSXin Ji /* Configure pixel clock */ 4978bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 4988bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) & 0xFF); 4998bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 5008bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) >> 8); 5018bdfc5daSXin Ji /* Lane count */ 5028bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 5038bdfc5daSXin Ji MIPI_LANE_CTRL_0, 0xfc); 5048bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 505fd0310b6SXin Ji MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 5068bdfc5daSXin Ji 5078bdfc5daSXin Ji /* Htotal */ 5088bdfc5daSXin Ji htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 5098bdfc5daSXin Ji ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 5108bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5118bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 5128bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5138bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 5148bdfc5daSXin Ji /* Hactive */ 5158bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5168bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 5178bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5188bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 5198bdfc5daSXin Ji /* HFP */ 5208bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5218bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 5228bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5238bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_H, 5248bdfc5daSXin Ji ctx->dt.hfront_porch.min >> 8); 5258bdfc5daSXin Ji /* HWS */ 5268bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5278bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 5288bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5298bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 5308bdfc5daSXin Ji /* HBP */ 5318bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5328bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 5338bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5348bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 5358bdfc5daSXin Ji /* Vactive */ 5368bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 5378bdfc5daSXin Ji ctx->dt.vactive.min); 5388bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 5398bdfc5daSXin Ji ctx->dt.vactive.min >> 8); 5408bdfc5daSXin Ji /* VFP */ 5418bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5428bdfc5daSXin Ji VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 5438bdfc5daSXin Ji /* VWS */ 5448bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5458bdfc5daSXin Ji VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 5468bdfc5daSXin Ji /* VBP */ 5478bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 5488bdfc5daSXin Ji VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 5498bdfc5daSXin Ji /* M value */ 5508bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5518bdfc5daSXin Ji MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 5528bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5538bdfc5daSXin Ji MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 5548bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5558bdfc5daSXin Ji MIPI_PLL_M_NUM_7_0, (m & 0xff)); 5568bdfc5daSXin Ji /* N value */ 5578bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5588bdfc5daSXin Ji MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 5598bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5608bdfc5daSXin Ji MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 5618bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 5628bdfc5daSXin Ji (n & 0xff)); 5637d066dc7SXin Ji 5647d066dc7SXin Ji anx7625_set_k_value(ctx); 5658bdfc5daSXin Ji 5668bdfc5daSXin Ji ret |= anx7625_odfc_config(ctx, post_divider - 1); 5678bdfc5daSXin Ji 5688bdfc5daSXin Ji if (ret < 0) 5698bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 5708bdfc5daSXin Ji 5718bdfc5daSXin Ji return ret; 5728bdfc5daSXin Ji } 5738bdfc5daSXin Ji 5748bdfc5daSXin Ji static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 5758bdfc5daSXin Ji { 5768bdfc5daSXin Ji int val; 577d65feac2SPin-yen Lin struct device *dev = ctx->dev; 5788bdfc5daSXin Ji 5798bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5808bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 5818bdfc5daSXin Ji if (val < 0) { 5828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 5838bdfc5daSXin Ji return -EIO; 5848bdfc5daSXin Ji } 5858bdfc5daSXin Ji 5868bdfc5daSXin Ji val |= (1 << MIPI_SWAP_CH3); 5878bdfc5daSXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 5888bdfc5daSXin Ji } 5898bdfc5daSXin Ji 5908bdfc5daSXin Ji static int anx7625_api_dsi_config(struct anx7625_data *ctx) 5918bdfc5daSXin Ji 5928bdfc5daSXin Ji { 5938bdfc5daSXin Ji int val, ret; 594d65feac2SPin-yen Lin struct device *dev = ctx->dev; 5958bdfc5daSXin Ji 5968bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5978bdfc5daSXin Ji ret = anx7625_swap_dsi_lane3(ctx); 5988bdfc5daSXin Ji if (ret < 0) { 5998bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 6008bdfc5daSXin Ji return ret; 6018bdfc5daSXin Ji } 6028bdfc5daSXin Ji 6038bdfc5daSXin Ji /* DSI clock settings */ 6048bdfc5daSXin Ji val = (0 << MIPI_HS_PWD_CLK) | 6058bdfc5daSXin Ji (0 << MIPI_HS_RT_CLK) | 6068bdfc5daSXin Ji (0 << MIPI_PD_CLK) | 6078bdfc5daSXin Ji (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 6088bdfc5daSXin Ji (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 6098bdfc5daSXin Ji (0 << MIPI_CLK_DET_DET_BYPASS) | 6108bdfc5daSXin Ji (0 << MIPI_CLK_MISS_CTRL) | 6118bdfc5daSXin Ji (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 6128bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6138bdfc5daSXin Ji MIPI_PHY_CONTROL_3, val); 6148bdfc5daSXin Ji 6158bdfc5daSXin Ji /* 6168bdfc5daSXin Ji * Decreased HS prepare timing delay from 160ns to 80ns work with 6178bdfc5daSXin Ji * a) Dragon board 810 series (Qualcomm AP) 6188bdfc5daSXin Ji * b) Moving Pixel DSI source (PG3A pattern generator + 6198bdfc5daSXin Ji * P332 D-PHY Probe) default D-PHY timing 6208bdfc5daSXin Ji * 5ns/step 6218bdfc5daSXin Ji */ 6228bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6238bdfc5daSXin Ji MIPI_TIME_HS_PRPR, 0x10); 6248bdfc5daSXin Ji 6258bdfc5daSXin Ji /* Enable DSI mode*/ 6268bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 6278bdfc5daSXin Ji SELECT_DSI << MIPI_DPI_SELECT); 6288bdfc5daSXin Ji 6298bdfc5daSXin Ji ret |= anx7625_dsi_video_timing_config(ctx); 6308bdfc5daSXin Ji if (ret < 0) { 6318bdfc5daSXin Ji DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 6328bdfc5daSXin Ji return ret; 6338bdfc5daSXin Ji } 6348bdfc5daSXin Ji 6358bdfc5daSXin Ji /* Toggle m, n ready */ 6368bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 6378bdfc5daSXin Ji ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 6388bdfc5daSXin Ji usleep_range(1000, 1100); 6398bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 6408bdfc5daSXin Ji MIPI_M_NUM_READY | MIPI_N_NUM_READY); 6418bdfc5daSXin Ji 6428bdfc5daSXin Ji /* Configure integer stable register */ 6438bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6448bdfc5daSXin Ji MIPI_VIDEO_STABLE_CNT, 0x02); 6458bdfc5daSXin Ji /* Power on MIPI RX */ 6468bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6478bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x00); 6488bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 6498bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x80); 6508bdfc5daSXin Ji 6518bdfc5daSXin Ji if (ret < 0) 6528bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 6538bdfc5daSXin Ji 6548bdfc5daSXin Ji return ret; 6558bdfc5daSXin Ji } 6568bdfc5daSXin Ji 6578bdfc5daSXin Ji static int anx7625_dsi_config(struct anx7625_data *ctx) 6588bdfc5daSXin Ji { 659d65feac2SPin-yen Lin struct device *dev = ctx->dev; 6608bdfc5daSXin Ji int ret; 6618bdfc5daSXin Ji 6628bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 6638bdfc5daSXin Ji 6648bdfc5daSXin Ji /* DSC disable */ 6658bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 6668bdfc5daSXin Ji R_DSC_CTRL_0, ~DSC_EN); 6678bdfc5daSXin Ji 6688bdfc5daSXin Ji ret |= anx7625_api_dsi_config(ctx); 6698bdfc5daSXin Ji 6708bdfc5daSXin Ji if (ret < 0) { 6718bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 6728bdfc5daSXin Ji return ret; 6738bdfc5daSXin Ji } 6748bdfc5daSXin Ji 6758bdfc5daSXin Ji /* Set MIPI RX EN */ 6768bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 6778bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 6788bdfc5daSXin Ji /* Clear mute flag */ 6798bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 6808bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 6818bdfc5daSXin Ji if (ret < 0) 6828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 6838bdfc5daSXin Ji else 6848bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 6858bdfc5daSXin Ji 6868bdfc5daSXin Ji return ret; 6878bdfc5daSXin Ji } 6888bdfc5daSXin Ji 689fd0310b6SXin Ji static int anx7625_api_dpi_config(struct anx7625_data *ctx) 690fd0310b6SXin Ji { 691d65feac2SPin-yen Lin struct device *dev = ctx->dev; 692fd0310b6SXin Ji u16 freq = ctx->dt.pixelclock.min / 1000; 693fd0310b6SXin Ji int ret; 694fd0310b6SXin Ji 695fd0310b6SXin Ji /* configure pixel clock */ 696fd0310b6SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 697fd0310b6SXin Ji PIXEL_CLOCK_L, freq & 0xFF); 698fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 699fd0310b6SXin Ji PIXEL_CLOCK_H, (freq >> 8)); 700fd0310b6SXin Ji 701fd0310b6SXin Ji /* set DPI mode */ 702fd0310b6SXin Ji /* set to DPI PLL module sel */ 703fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 704fd0310b6SXin Ji MIPI_DIGITAL_PLL_9, 0x20); 705fd0310b6SXin Ji /* power down MIPI */ 706fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 707fd0310b6SXin Ji MIPI_LANE_CTRL_10, 0x08); 708fd0310b6SXin Ji /* enable DPI mode */ 709fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 710fd0310b6SXin Ji MIPI_DIGITAL_PLL_18, 0x1C); 711fd0310b6SXin Ji /* set first edge */ 712fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 713fd0310b6SXin Ji VIDEO_CONTROL_0, 0x06); 714fd0310b6SXin Ji if (ret < 0) 715fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 716fd0310b6SXin Ji 717fd0310b6SXin Ji return ret; 718fd0310b6SXin Ji } 719fd0310b6SXin Ji 720fd0310b6SXin Ji static int anx7625_dpi_config(struct anx7625_data *ctx) 721fd0310b6SXin Ji { 722d65feac2SPin-yen Lin struct device *dev = ctx->dev; 723fd0310b6SXin Ji int ret; 724fd0310b6SXin Ji 725fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 726fd0310b6SXin Ji 727fd0310b6SXin Ji /* DSC disable */ 728fd0310b6SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 729fd0310b6SXin Ji R_DSC_CTRL_0, ~DSC_EN); 730fd0310b6SXin Ji if (ret < 0) { 731fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 732fd0310b6SXin Ji return ret; 733fd0310b6SXin Ji } 734fd0310b6SXin Ji 735fd0310b6SXin Ji ret = anx7625_config_bit_matrix(ctx); 736fd0310b6SXin Ji if (ret < 0) { 737fd0310b6SXin Ji DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 738fd0310b6SXin Ji return ret; 739fd0310b6SXin Ji } 740fd0310b6SXin Ji 741fd0310b6SXin Ji ret = anx7625_api_dpi_config(ctx); 742fd0310b6SXin Ji if (ret < 0) { 743fd0310b6SXin Ji DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 744fd0310b6SXin Ji return ret; 745fd0310b6SXin Ji } 746fd0310b6SXin Ji 747fd0310b6SXin Ji /* set MIPI RX EN */ 748fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 749fd0310b6SXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 750fd0310b6SXin Ji /* clear mute flag */ 751fd0310b6SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 752fd0310b6SXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 753fd0310b6SXin Ji if (ret < 0) 754fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 755fd0310b6SXin Ji 756fd0310b6SXin Ji return ret; 757fd0310b6SXin Ji } 758fd0310b6SXin Ji 759cd1637c7SXin Ji static int anx7625_read_flash_status(struct anx7625_data *ctx) 760cd1637c7SXin Ji { 761cd1637c7SXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 762cd1637c7SXin Ji } 763cd1637c7SXin Ji 764cd1637c7SXin Ji static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 765cd1637c7SXin Ji { 766cd1637c7SXin Ji int ret, val; 767d65feac2SPin-yen Lin struct device *dev = ctx->dev; 768cd1637c7SXin Ji u8 ident[FLASH_BUF_LEN]; 769cd1637c7SXin Ji 770cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 771cd1637c7SXin Ji FLASH_ADDR_HIGH, 0x91); 772cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 773cd1637c7SXin Ji FLASH_ADDR_LOW, 0xA0); 774cd1637c7SXin Ji if (ret < 0) { 775cd1637c7SXin Ji dev_err(dev, "IO error : set key flash address.\n"); 776cd1637c7SXin Ji return ret; 777cd1637c7SXin Ji } 778cd1637c7SXin Ji 779cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 780cd1637c7SXin Ji FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 781cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 782cd1637c7SXin Ji FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 783cd1637c7SXin Ji if (ret < 0) { 784cd1637c7SXin Ji dev_err(dev, "IO error : set key flash len.\n"); 785cd1637c7SXin Ji return ret; 786cd1637c7SXin Ji } 787cd1637c7SXin Ji 788cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 789cd1637c7SXin Ji R_FLASH_RW_CTRL, FLASH_READ); 790cd1637c7SXin Ji ret |= readx_poll_timeout(anx7625_read_flash_status, 791cd1637c7SXin Ji ctx, val, 792cd1637c7SXin Ji ((val & FLASH_DONE) || (val < 0)), 793cd1637c7SXin Ji 2000, 794cd1637c7SXin Ji 2000 * 150); 795cd1637c7SXin Ji if (ret) { 796cd1637c7SXin Ji dev_err(dev, "flash read access fail!\n"); 797cd1637c7SXin Ji return -EIO; 798cd1637c7SXin Ji } 799cd1637c7SXin Ji 800cd1637c7SXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 801cd1637c7SXin Ji FLASH_BUF_BASE_ADDR, 802cd1637c7SXin Ji FLASH_BUF_LEN, ident); 803cd1637c7SXin Ji if (ret < 0) { 804cd1637c7SXin Ji dev_err(dev, "read flash data fail!\n"); 805cd1637c7SXin Ji return -EIO; 806cd1637c7SXin Ji } 807cd1637c7SXin Ji 808cd1637c7SXin Ji if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 809cd1637c7SXin Ji return -EINVAL; 810cd1637c7SXin Ji 811cd1637c7SXin Ji return 0; 812cd1637c7SXin Ji } 813cd1637c7SXin Ji 814cd1637c7SXin Ji static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 815cd1637c7SXin Ji { 816cd1637c7SXin Ji int ret; 817d65feac2SPin-yen Lin struct device *dev = ctx->dev; 818cd1637c7SXin Ji 819cd1637c7SXin Ji /* Select HDCP 1.4 KEY */ 820cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 821cd1637c7SXin Ji R_BOOT_RETRY, 0x12); 822cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 823cd1637c7SXin Ji FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 824cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 825cd1637c7SXin Ji FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 826cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827cd1637c7SXin Ji R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 828cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829cd1637c7SXin Ji R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 830cd1637c7SXin Ji 831cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 832cd1637c7SXin Ji R_RAM_ADDR_H, 0); 833cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 834cd1637c7SXin Ji R_RAM_ADDR_L, 0); 835cd1637c7SXin Ji /* Enable HDCP 1.4 KEY load */ 836cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 837cd1637c7SXin Ji R_RAM_CTRL, DECRYPT_EN | LOAD_START); 838cd1637c7SXin Ji dev_dbg(dev, "load HDCP 1.4 key done\n"); 839cd1637c7SXin Ji return ret; 840cd1637c7SXin Ji } 841cd1637c7SXin Ji 842cd1637c7SXin Ji static int anx7625_hdcp_disable(struct anx7625_data *ctx) 843cd1637c7SXin Ji { 844cd1637c7SXin Ji int ret; 845d65feac2SPin-yen Lin struct device *dev = ctx->dev; 846cd1637c7SXin Ji 847cd1637c7SXin Ji dev_dbg(dev, "disable HDCP 1.4\n"); 848cd1637c7SXin Ji 849cd1637c7SXin Ji /* Disable HDCP */ 850cd1637c7SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 851cd1637c7SXin Ji /* Try auth flag */ 852cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 853cd1637c7SXin Ji /* Interrupt for DRM */ 854cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 855cd1637c7SXin Ji if (ret < 0) 856cd1637c7SXin Ji dev_err(dev, "fail to disable HDCP\n"); 857cd1637c7SXin Ji 858cd1637c7SXin Ji return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 859cd1637c7SXin Ji TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 860cd1637c7SXin Ji } 861cd1637c7SXin Ji 862cd1637c7SXin Ji static int anx7625_hdcp_enable(struct anx7625_data *ctx) 863cd1637c7SXin Ji { 864cd1637c7SXin Ji u8 bcap; 865cd1637c7SXin Ji int ret; 866d65feac2SPin-yen Lin struct device *dev = ctx->dev; 867cd1637c7SXin Ji 868cd1637c7SXin Ji ret = anx7625_hdcp_key_probe(ctx); 869cd1637c7SXin Ji if (ret) { 870cd1637c7SXin Ji dev_dbg(dev, "no key found, not to do hdcp\n"); 871cd1637c7SXin Ji return ret; 872cd1637c7SXin Ji } 873cd1637c7SXin Ji 874cd1637c7SXin Ji /* Read downstream capability */ 87541639b3aSChen-Yu Tsai ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, DP_AUX_HDCP_BCAPS, 1, &bcap); 876d583e752STom Rix if (ret < 0) 877d583e752STom Rix return ret; 878d583e752STom Rix 87941639b3aSChen-Yu Tsai if (!(bcap & DP_BCAPS_HDCP_CAPABLE)) { 880cd1637c7SXin Ji pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 881cd1637c7SXin Ji return 0; 882cd1637c7SXin Ji } 883cd1637c7SXin Ji 884cd1637c7SXin Ji dev_dbg(dev, "enable HDCP 1.4\n"); 885cd1637c7SXin Ji 886cd1637c7SXin Ji /* First clear HDCP state */ 887cd1637c7SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 888cd1637c7SXin Ji TX_HDCP_CTRL0, 889cd1637c7SXin Ji KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 890cd1637c7SXin Ji usleep_range(1000, 1100); 891cd1637c7SXin Ji /* Second clear HDCP state */ 892cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 893cd1637c7SXin Ji TX_HDCP_CTRL0, 894cd1637c7SXin Ji KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 895cd1637c7SXin Ji 896cd1637c7SXin Ji /* Set time for waiting KSVR */ 897cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 898cd1637c7SXin Ji SP_TX_WAIT_KSVR_TIME, 0xc8); 899cd1637c7SXin Ji /* Set time for waiting R0 */ 900cd1637c7SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 901cd1637c7SXin Ji SP_TX_WAIT_R0_TIME, 0xb0); 902cd1637c7SXin Ji ret |= anx7625_hdcp_key_load(ctx); 903cd1637c7SXin Ji if (ret) { 904cd1637c7SXin Ji pr_warn("prepare HDCP key failed.\n"); 905cd1637c7SXin Ji return ret; 906cd1637c7SXin Ji } 907cd1637c7SXin Ji 908cd1637c7SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 909cd1637c7SXin Ji 910cd1637c7SXin Ji /* Try auth flag */ 911cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 912cd1637c7SXin Ji /* Interrupt for DRM */ 913cd1637c7SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 914cd1637c7SXin Ji if (ret < 0) 915cd1637c7SXin Ji dev_err(dev, "fail to enable HDCP\n"); 916cd1637c7SXin Ji 917cd1637c7SXin Ji return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 918cd1637c7SXin Ji TX_HDCP_CTRL0, HARD_AUTH_EN); 919cd1637c7SXin Ji } 920cd1637c7SXin Ji 9218bdfc5daSXin Ji static void anx7625_dp_start(struct anx7625_data *ctx) 9228bdfc5daSXin Ji { 9238bdfc5daSXin Ji int ret; 924d65feac2SPin-yen Lin struct device *dev = ctx->dev; 92527f26359SXin Ji u8 data; 9268bdfc5daSXin Ji 9278bdfc5daSXin Ji if (!ctx->display_timing_valid) { 9288bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 9298bdfc5daSXin Ji return; 9308bdfc5daSXin Ji } 9318bdfc5daSXin Ji 93227f26359SXin Ji dev_dbg(dev, "set downstream sink into normal\n"); 93327f26359SXin Ji /* Downstream sink enter into normal mode */ 9342ba776f9SChen-Yu Tsai data = DP_SET_POWER_D0; 9352ba776f9SChen-Yu Tsai ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data); 93627f26359SXin Ji if (ret < 0) 93727f26359SXin Ji dev_err(dev, "IO error : set sink into normal mode fail\n"); 93827f26359SXin Ji 939cd1637c7SXin Ji /* Disable HDCP */ 940cd1637c7SXin Ji anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 941cd1637c7SXin Ji 942fd0310b6SXin Ji if (ctx->pdata.is_dpi) 943fd0310b6SXin Ji ret = anx7625_dpi_config(ctx); 944fd0310b6SXin Ji else 9458bdfc5daSXin Ji ret = anx7625_dsi_config(ctx); 9468bdfc5daSXin Ji 9478bdfc5daSXin Ji if (ret < 0) 9488bdfc5daSXin Ji DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 949cd1637c7SXin Ji 950cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 951cd1637c7SXin Ji 952cd1637c7SXin Ji ctx->dp_en = 1; 9538bdfc5daSXin Ji } 9548bdfc5daSXin Ji 9558bdfc5daSXin Ji static void anx7625_dp_stop(struct anx7625_data *ctx) 9568bdfc5daSXin Ji { 957d65feac2SPin-yen Lin struct device *dev = ctx->dev; 9588bdfc5daSXin Ji int ret; 959548b512eSXin Ji u8 data; 9608bdfc5daSXin Ji 9618bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 9628bdfc5daSXin Ji 9638bdfc5daSXin Ji /* 9648bdfc5daSXin Ji * Video disable: 0x72:08 bit 7 = 0; 9658bdfc5daSXin Ji * Audio disable: 0x70:87 bit 0 = 0; 9668bdfc5daSXin Ji */ 9678bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 9688bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 9698bdfc5daSXin Ji 9708bdfc5daSXin Ji ret |= anx7625_video_mute_control(ctx, 1); 971548b512eSXin Ji 972548b512eSXin Ji dev_dbg(dev, "notify downstream enter into standby\n"); 973548b512eSXin Ji /* Downstream monitor enter into standby mode */ 9742ba776f9SChen-Yu Tsai data = DP_SET_POWER_D3; 9752ba776f9SChen-Yu Tsai ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data); 9768bdfc5daSXin Ji if (ret < 0) 9778bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 978cd1637c7SXin Ji 979cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 980cd1637c7SXin Ji 981cd1637c7SXin Ji ctx->dp_en = 0; 9828bdfc5daSXin Ji } 9838bdfc5daSXin Ji 9848bdfc5daSXin Ji static int sp_tx_rst_aux(struct anx7625_data *ctx) 9858bdfc5daSXin Ji { 9868bdfc5daSXin Ji int ret; 9878bdfc5daSXin Ji 9888bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 9898bdfc5daSXin Ji AUX_RST); 9908bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 9918bdfc5daSXin Ji ~AUX_RST); 9928bdfc5daSXin Ji return ret; 9938bdfc5daSXin Ji } 9948bdfc5daSXin Ji 9958bdfc5daSXin Ji static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 9968bdfc5daSXin Ji { 9978bdfc5daSXin Ji int ret; 9988bdfc5daSXin Ji 9998bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10008bdfc5daSXin Ji AP_AUX_BUFF_START, offset); 10018bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10028bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 10038bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 10048bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 10058bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 10068bdfc5daSXin Ji } 10078bdfc5daSXin Ji 10088bdfc5daSXin Ji static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 10098bdfc5daSXin Ji { 10108bdfc5daSXin Ji int ret; 10118bdfc5daSXin Ji 10128bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10138bdfc5daSXin Ji AP_AUX_COMMAND, len_cmd); 10148bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 10158bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 10168bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 10178bdfc5daSXin Ji } 10188bdfc5daSXin Ji 10198bdfc5daSXin Ji static int sp_tx_get_edid_block(struct anx7625_data *ctx) 10208bdfc5daSXin Ji { 10218bdfc5daSXin Ji int c = 0; 1022d65feac2SPin-yen Lin struct device *dev = ctx->dev; 10238bdfc5daSXin Ji 10248bdfc5daSXin Ji sp_tx_aux_wr(ctx, 0x7e); 10258bdfc5daSXin Ji sp_tx_aux_rd(ctx, 0x01); 10268bdfc5daSXin Ji c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 10278bdfc5daSXin Ji if (c < 0) { 10288bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 10298bdfc5daSXin Ji return -EIO; 10308bdfc5daSXin Ji } 10318bdfc5daSXin Ji 10328bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 10338bdfc5daSXin Ji 10348bdfc5daSXin Ji if (c > MAX_EDID_BLOCK) 10358bdfc5daSXin Ji c = 1; 10368bdfc5daSXin Ji 10378bdfc5daSXin Ji return c; 10388bdfc5daSXin Ji } 10398bdfc5daSXin Ji 10408bdfc5daSXin Ji static int edid_read(struct anx7625_data *ctx, 10418bdfc5daSXin Ji u8 offset, u8 *pblock_buf) 10428bdfc5daSXin Ji { 10438bdfc5daSXin Ji int ret, cnt; 1044d65feac2SPin-yen Lin struct device *dev = ctx->dev; 10458bdfc5daSXin Ji 10468bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 10478bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 10488bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 10498bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 10508bdfc5daSXin Ji 10518bdfc5daSXin Ji if (ret) { 10527f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 10538bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 10548bdfc5daSXin Ji } else { 10558bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 10568bdfc5daSXin Ji AP_AUX_BUFF_START, 10578bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, 10588bdfc5daSXin Ji pblock_buf); 10598bdfc5daSXin Ji if (ret > 0) 10608bdfc5daSXin Ji break; 10618bdfc5daSXin Ji } 10628bdfc5daSXin Ji } 10638bdfc5daSXin Ji 10648bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 10658bdfc5daSXin Ji return -EIO; 10668bdfc5daSXin Ji 10677f16d0f3SRobert Foss return ret; 10688bdfc5daSXin Ji } 10698bdfc5daSXin Ji 10708bdfc5daSXin Ji static int segments_edid_read(struct anx7625_data *ctx, 10718bdfc5daSXin Ji u8 segment, u8 *buf, u8 offset) 10728bdfc5daSXin Ji { 10738bdfc5daSXin Ji u8 cnt; 10748bdfc5daSXin Ji int ret; 1075d65feac2SPin-yen Lin struct device *dev = ctx->dev; 10768bdfc5daSXin Ji 10778bdfc5daSXin Ji /* Write address only */ 10788bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10798bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x30); 10808bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10818bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 10828bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10838bdfc5daSXin Ji AP_AUX_CTRL_STATUS, 10848bdfc5daSXin Ji AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 10858bdfc5daSXin Ji 10868bdfc5daSXin Ji ret |= wait_aux_op_finish(ctx); 10878bdfc5daSXin Ji /* Write segment address */ 10888bdfc5daSXin Ji ret |= sp_tx_aux_wr(ctx, segment); 10898bdfc5daSXin Ji /* Data read */ 10908bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10918bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 10928bdfc5daSXin Ji if (ret) { 10938bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 10948bdfc5daSXin Ji return ret; 10958bdfc5daSXin Ji } 10968bdfc5daSXin Ji 10978bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 10988bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 10998bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 11008bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 11018bdfc5daSXin Ji 11028bdfc5daSXin Ji if (ret) { 11038bdfc5daSXin Ji ret = sp_tx_rst_aux(ctx); 11048bdfc5daSXin Ji DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 11058bdfc5daSXin Ji } else { 11068bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 11078bdfc5daSXin Ji AP_AUX_BUFF_START, 11088bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, buf); 11098bdfc5daSXin Ji if (ret > 0) 11108bdfc5daSXin Ji break; 11118bdfc5daSXin Ji } 11128bdfc5daSXin Ji } 11138bdfc5daSXin Ji 11148bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 11158bdfc5daSXin Ji return -EIO; 11168bdfc5daSXin Ji 11177f16d0f3SRobert Foss return ret; 11188bdfc5daSXin Ji } 11198bdfc5daSXin Ji 11208bdfc5daSXin Ji static int sp_tx_edid_read(struct anx7625_data *ctx, 11218bdfc5daSXin Ji u8 *pedid_blocks_buf) 11228bdfc5daSXin Ji { 1123d5c6f647SPin-Yen Lin u8 offset; 1124d5c6f647SPin-Yen Lin int edid_pos; 11258bdfc5daSXin Ji int count, blocks_num; 11268bdfc5daSXin Ji u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 11278bdfc5daSXin Ji u8 i, j; 11280bae5687SHsin-Yi Wang int g_edid_break = 0; 11298bdfc5daSXin Ji int ret; 1130d65feac2SPin-yen Lin struct device *dev = ctx->dev; 11318bdfc5daSXin Ji 11328bdfc5daSXin Ji /* Address initial */ 11338bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11348bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 11358bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11368bdfc5daSXin Ji AP_AUX_ADDR_15_8, 0); 11378bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 11388bdfc5daSXin Ji AP_AUX_ADDR_19_16, 0xf0); 11398bdfc5daSXin Ji if (ret < 0) { 11408bdfc5daSXin Ji DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 11418bdfc5daSXin Ji return -EIO; 11428bdfc5daSXin Ji } 11438bdfc5daSXin Ji 11448bdfc5daSXin Ji blocks_num = sp_tx_get_edid_block(ctx); 11458bdfc5daSXin Ji if (blocks_num < 0) 11468bdfc5daSXin Ji return blocks_num; 11478bdfc5daSXin Ji 11488bdfc5daSXin Ji count = 0; 11498bdfc5daSXin Ji 11508bdfc5daSXin Ji do { 11518bdfc5daSXin Ji switch (count) { 11528bdfc5daSXin Ji case 0: 11538bdfc5daSXin Ji case 1: 11548bdfc5daSXin Ji for (i = 0; i < 8; i++) { 11558bdfc5daSXin Ji offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 11568bdfc5daSXin Ji g_edid_break = edid_read(ctx, offset, 11578bdfc5daSXin Ji pblock_buf); 11588bdfc5daSXin Ji 11590bae5687SHsin-Yi Wang if (g_edid_break < 0) 11608bdfc5daSXin Ji break; 11618bdfc5daSXin Ji 11628bdfc5daSXin Ji memcpy(&pedid_blocks_buf[offset], 11638bdfc5daSXin Ji pblock_buf, 11648bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11658bdfc5daSXin Ji } 11668bdfc5daSXin Ji 11678bdfc5daSXin Ji break; 11688bdfc5daSXin Ji case 2: 11698bdfc5daSXin Ji offset = 0x00; 11708bdfc5daSXin Ji 11718bdfc5daSXin Ji for (j = 0; j < 8; j++) { 11728bdfc5daSXin Ji edid_pos = (j + count * 8) * 11738bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 11748bdfc5daSXin Ji 11758bdfc5daSXin Ji if (g_edid_break == 1) 11768bdfc5daSXin Ji break; 11778bdfc5daSXin Ji 1178a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 11798bdfc5daSXin Ji pblock_buf, offset); 1180a23e0a2aSRobert Foss if (ret < 0) 1181a23e0a2aSRobert Foss return ret; 1182a23e0a2aSRobert Foss 11838bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 11848bdfc5daSXin Ji pblock_buf, 11858bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 11868bdfc5daSXin Ji offset = offset + 0x10; 11878bdfc5daSXin Ji } 11888bdfc5daSXin Ji 11898bdfc5daSXin Ji break; 11908bdfc5daSXin Ji case 3: 11918bdfc5daSXin Ji offset = 0x80; 11928bdfc5daSXin Ji 11938bdfc5daSXin Ji for (j = 0; j < 8; j++) { 11948bdfc5daSXin Ji edid_pos = (j + count * 8) * 11958bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 11968bdfc5daSXin Ji if (g_edid_break == 1) 11978bdfc5daSXin Ji break; 11988bdfc5daSXin Ji 1199a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 12008bdfc5daSXin Ji pblock_buf, offset); 1201a23e0a2aSRobert Foss if (ret < 0) 1202a23e0a2aSRobert Foss return ret; 1203a23e0a2aSRobert Foss 12048bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 12058bdfc5daSXin Ji pblock_buf, 12068bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 12078bdfc5daSXin Ji offset = offset + 0x10; 12088bdfc5daSXin Ji } 12098bdfc5daSXin Ji 12108bdfc5daSXin Ji break; 12118bdfc5daSXin Ji default: 12128bdfc5daSXin Ji break; 12138bdfc5daSXin Ji } 12148bdfc5daSXin Ji 12158bdfc5daSXin Ji count++; 12168bdfc5daSXin Ji 12178bdfc5daSXin Ji } while (blocks_num >= count); 12188bdfc5daSXin Ji 12198bdfc5daSXin Ji /* Check edid data */ 12208bdfc5daSXin Ji if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 12218bdfc5daSXin Ji DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 12228bdfc5daSXin Ji return -EINVAL; 12238bdfc5daSXin Ji } 12248bdfc5daSXin Ji 12258bdfc5daSXin Ji /* Reset aux channel */ 12267f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 12277f16d0f3SRobert Foss if (ret < 0) { 12287f16d0f3SRobert Foss DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 12297f16d0f3SRobert Foss return ret; 12307f16d0f3SRobert Foss } 12318bdfc5daSXin Ji 12328bdfc5daSXin Ji return (blocks_num + 1); 12338bdfc5daSXin Ji } 12348bdfc5daSXin Ji 12358bdfc5daSXin Ji static void anx7625_power_on(struct anx7625_data *ctx) 12368bdfc5daSXin Ji { 1237d65feac2SPin-yen Lin struct device *dev = ctx->dev; 12386c744983SHsin-Yi Wang int ret, i; 12398bdfc5daSXin Ji 12408bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 12418bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 12428bdfc5daSXin Ji return; 12438bdfc5daSXin Ji } 12448bdfc5daSXin Ji 12456c744983SHsin-Yi Wang for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 12466c744983SHsin-Yi Wang ret = regulator_enable(ctx->pdata.supplies[i].consumer); 12476c744983SHsin-Yi Wang if (ret < 0) { 12486c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 12496c744983SHsin-Yi Wang i, ret); 12506c744983SHsin-Yi Wang goto reg_err; 12516c744983SHsin-Yi Wang } 12526c744983SHsin-Yi Wang usleep_range(2000, 2100); 12536c744983SHsin-Yi Wang } 12546c744983SHsin-Yi Wang 12551fcf24fbSHsin-Yi Wang usleep_range(11000, 12000); 12566c744983SHsin-Yi Wang 12578bdfc5daSXin Ji /* Power on pin enable */ 12588bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 1); 12598bdfc5daSXin Ji usleep_range(10000, 11000); 12608bdfc5daSXin Ji /* Power reset pin enable */ 12618bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 1); 12628bdfc5daSXin Ji usleep_range(10000, 11000); 12638bdfc5daSXin Ji 12648bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 12656c744983SHsin-Yi Wang return; 12666c744983SHsin-Yi Wang reg_err: 12676c744983SHsin-Yi Wang for (--i; i >= 0; i--) 12686c744983SHsin-Yi Wang regulator_disable(ctx->pdata.supplies[i].consumer); 12698bdfc5daSXin Ji } 12708bdfc5daSXin Ji 12718bdfc5daSXin Ji static void anx7625_power_standby(struct anx7625_data *ctx) 12728bdfc5daSXin Ji { 1273d65feac2SPin-yen Lin struct device *dev = ctx->dev; 12746c744983SHsin-Yi Wang int ret; 12758bdfc5daSXin Ji 12768bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 12778bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 12788bdfc5daSXin Ji return; 12798bdfc5daSXin Ji } 12808bdfc5daSXin Ji 12818bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 0); 12828bdfc5daSXin Ji usleep_range(1000, 1100); 12838bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 0); 12848bdfc5daSXin Ji usleep_range(1000, 1100); 12856c744983SHsin-Yi Wang 12866c744983SHsin-Yi Wang ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 12876c744983SHsin-Yi Wang ctx->pdata.supplies); 12886c744983SHsin-Yi Wang if (ret < 0) 12896c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 12906c744983SHsin-Yi Wang 12918bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 12928bdfc5daSXin Ji } 12938bdfc5daSXin Ji 12948bdfc5daSXin Ji /* Basic configurations of ANX7625 */ 12958bdfc5daSXin Ji static void anx7625_config(struct anx7625_data *ctx) 12968bdfc5daSXin Ji { 12978bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12988bdfc5daSXin Ji XTAL_FRQ_SEL, XTAL_FRQ_27M); 12998bdfc5daSXin Ji } 13008bdfc5daSXin Ji 13011e0635bcSXin Ji static int anx7625_hpd_timer_config(struct anx7625_data *ctx) 13021e0635bcSXin Ji { 13031e0635bcSXin Ji int ret; 13041e0635bcSXin Ji 13051e0635bcSXin Ji /* Set irq detect window to 2ms */ 13061e0635bcSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 13071e0635bcSXin Ji HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF); 13081e0635bcSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 13091e0635bcSXin Ji HPD_DET_TIMER_BIT8_15, 13101e0635bcSXin Ji (HPD_TIME >> 8) & 0xFF); 13111e0635bcSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 13121e0635bcSXin Ji HPD_DET_TIMER_BIT16_23, 13131e0635bcSXin Ji (HPD_TIME >> 16) & 0xFF); 13141e0635bcSXin Ji 13151e0635bcSXin Ji return ret; 13161e0635bcSXin Ji } 13171e0635bcSXin Ji 13181e0635bcSXin Ji static int anx7625_read_hpd_gpio_config_status(struct anx7625_data *ctx) 13191e0635bcSXin Ji { 13201e0635bcSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, GPIO_CTRL_2); 13211e0635bcSXin Ji } 13221e0635bcSXin Ji 13238bdfc5daSXin Ji static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 13248bdfc5daSXin Ji { 1325d65feac2SPin-yen Lin struct device *dev = ctx->dev; 13261e0635bcSXin Ji int ret, val; 13278bdfc5daSXin Ji 13288bdfc5daSXin Ji /* Reset main ocm */ 13298bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 13308bdfc5daSXin Ji /* Disable PD */ 13318bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 13328bdfc5daSXin Ji AP_AV_STATUS, AP_DISABLE_PD); 13338bdfc5daSXin Ji /* Release main ocm */ 13348bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 13358bdfc5daSXin Ji 13368bdfc5daSXin Ji if (ret < 0) 13378bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 13388bdfc5daSXin Ji else 13398bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 13401e0635bcSXin Ji 13411e0635bcSXin Ji /* 13421e0635bcSXin Ji * Make sure the HPD GPIO already be configured after OCM release before 13431e0635bcSXin Ji * setting HPD detect window register. Here we poll the status register 13441e0635bcSXin Ji * at maximum 40ms, then config HPD irq detect window register 13451e0635bcSXin Ji */ 13461e0635bcSXin Ji readx_poll_timeout(anx7625_read_hpd_gpio_config_status, 13471e0635bcSXin Ji ctx, val, 13481e0635bcSXin Ji ((val & HPD_SOURCE) || (val < 0)), 13491e0635bcSXin Ji 2000, 2000 * 20); 13501e0635bcSXin Ji 13511e0635bcSXin Ji /* Set HPD irq detect window to 2ms */ 13521e0635bcSXin Ji anx7625_hpd_timer_config(ctx); 13538bdfc5daSXin Ji } 13548bdfc5daSXin Ji 13558bdfc5daSXin Ji static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 13568bdfc5daSXin Ji { 13578bdfc5daSXin Ji int ret; 1358d65feac2SPin-yen Lin struct device *dev = ctx->dev; 13598bdfc5daSXin Ji 13608bdfc5daSXin Ji /* Check interface workable */ 13618bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 13628bdfc5daSXin Ji FLASH_LOAD_STA); 13638bdfc5daSXin Ji if (ret < 0) { 13648bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 13658bdfc5daSXin Ji return ret; 13668bdfc5daSXin Ji } 13678bdfc5daSXin Ji if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 13688bdfc5daSXin Ji return -ENODEV; 13698bdfc5daSXin Ji 13708bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 13718bdfc5daSXin Ji 13728bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 13738bdfc5daSXin Ji anx7625_reg_read(ctx, 13748bdfc5daSXin Ji ctx->i2c.rx_p0_client, 13758bdfc5daSXin Ji OCM_FW_VERSION), 13768bdfc5daSXin Ji anx7625_reg_read(ctx, 13778bdfc5daSXin Ji ctx->i2c.rx_p0_client, 13788bdfc5daSXin Ji OCM_FW_REVERSION)); 13798bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 13808bdfc5daSXin Ji ANX7625_DRV_VERSION); 13818bdfc5daSXin Ji 13828bdfc5daSXin Ji return 0; 13838bdfc5daSXin Ji } 13848bdfc5daSXin Ji 13858bdfc5daSXin Ji static void anx7625_power_on_init(struct anx7625_data *ctx) 13868bdfc5daSXin Ji { 13878bdfc5daSXin Ji int retry_count, i; 13888bdfc5daSXin Ji 13898bdfc5daSXin Ji for (retry_count = 0; retry_count < 3; retry_count++) { 13908bdfc5daSXin Ji anx7625_power_on(ctx); 13918bdfc5daSXin Ji anx7625_config(ctx); 13928bdfc5daSXin Ji 13938bdfc5daSXin Ji for (i = 0; i < OCM_LOADING_TIME; i++) { 13948bdfc5daSXin Ji if (!anx7625_ocm_loading_check(ctx)) 13958bdfc5daSXin Ji return; 13968bdfc5daSXin Ji usleep_range(1000, 1100); 13978bdfc5daSXin Ji } 13988bdfc5daSXin Ji anx7625_power_standby(ctx); 13998bdfc5daSXin Ji } 14008bdfc5daSXin Ji } 14018bdfc5daSXin Ji 14028bdfc5daSXin Ji static void anx7625_init_gpio(struct anx7625_data *platform) 14038bdfc5daSXin Ji { 1404d65feac2SPin-yen Lin struct device *dev = platform->dev; 14058bdfc5daSXin Ji 14068bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 14078bdfc5daSXin Ji 14088bdfc5daSXin Ji /* Gpio for chip power enable */ 14098bdfc5daSXin Ji platform->pdata.gpio_p_on = 14108bdfc5daSXin Ji devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 14117020449bSXin Ji if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 14127020449bSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 14137020449bSXin Ji platform->pdata.gpio_p_on = NULL; 14147020449bSXin Ji } 14157020449bSXin Ji 14168bdfc5daSXin Ji /* Gpio for chip reset */ 14178bdfc5daSXin Ji platform->pdata.gpio_reset = 14188bdfc5daSXin Ji devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 14197020449bSXin Ji if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 14207020449bSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 14217020449bSXin Ji platform->pdata.gpio_reset = NULL; 14227020449bSXin Ji } 14238bdfc5daSXin Ji 14248bdfc5daSXin Ji if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 14258bdfc5daSXin Ji platform->pdata.low_power_mode = 1; 14268bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 14278bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_p_on), 14288bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_reset)); 14298bdfc5daSXin Ji } else { 14308bdfc5daSXin Ji platform->pdata.low_power_mode = 0; 14318bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 14328bdfc5daSXin Ji } 14338bdfc5daSXin Ji } 14348bdfc5daSXin Ji 14358bdfc5daSXin Ji static void anx7625_stop_dp_work(struct anx7625_data *ctx) 14368bdfc5daSXin Ji { 14378bdfc5daSXin Ji ctx->hpd_status = 0; 14388bdfc5daSXin Ji ctx->hpd_high_cnt = 0; 14398bdfc5daSXin Ji } 14408bdfc5daSXin Ji 14418bdfc5daSXin Ji static void anx7625_start_dp_work(struct anx7625_data *ctx) 14428bdfc5daSXin Ji { 14438bdfc5daSXin Ji int ret; 1444d65feac2SPin-yen Lin struct device *dev = ctx->dev; 14458bdfc5daSXin Ji 14468bdfc5daSXin Ji if (ctx->hpd_high_cnt >= 2) { 14478bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 14488bdfc5daSXin Ji return; 14498bdfc5daSXin Ji } 14508bdfc5daSXin Ji 1451fd0310b6SXin Ji ctx->hpd_status = 1; 14528bdfc5daSXin Ji ctx->hpd_high_cnt++; 14538bdfc5daSXin Ji 14548bdfc5daSXin Ji /* Not support HDCP */ 14558bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 14568bdfc5daSXin Ji 14578bdfc5daSXin Ji /* Try auth flag */ 14588bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 14598bdfc5daSXin Ji /* Interrupt for DRM */ 14608bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1461fd0310b6SXin Ji if (ret < 0) { 1462fd0310b6SXin Ji DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 14638bdfc5daSXin Ji return; 1464fd0310b6SXin Ji } 14658bdfc5daSXin Ji 14668bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 14678bdfc5daSXin Ji if (ret < 0) 14688bdfc5daSXin Ji return; 14698bdfc5daSXin Ji 14708bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 14718bdfc5daSXin Ji } 14728bdfc5daSXin Ji 14738bdfc5daSXin Ji static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 14748bdfc5daSXin Ji { 14758bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 14768bdfc5daSXin Ji } 14778bdfc5daSXin Ji 1478a57e7345SHsin-Yi Wang static int _anx7625_hpd_polling(struct anx7625_data *ctx, 1479a57e7345SHsin-Yi Wang unsigned long wait_us) 14808bdfc5daSXin Ji { 14818bdfc5daSXin Ji int ret, val; 1482d65feac2SPin-yen Lin struct device *dev = ctx->dev; 14838bdfc5daSXin Ji 1484fd0310b6SXin Ji /* Interrupt mode, no need poll HPD status, just return */ 1485fd0310b6SXin Ji if (ctx->pdata.intp_irq) 1486a57e7345SHsin-Yi Wang return 0; 1487fd0310b6SXin Ji 14888bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 14898bdfc5daSXin Ji ctx, val, 14908bdfc5daSXin Ji ((val & HPD_STATUS) || (val < 0)), 1491a57e7345SHsin-Yi Wang wait_us / 100, 1492a57e7345SHsin-Yi Wang wait_us); 14938bdfc5daSXin Ji if (ret) { 149460487584SPi-Hsun Shih DRM_DEV_ERROR(dev, "no hpd.\n"); 1495a57e7345SHsin-Yi Wang return ret; 149660487584SPi-Hsun Shih } 149760487584SPi-Hsun Shih 149860487584SPi-Hsun Shih DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 14998bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 15008bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 15018bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 15028bdfc5daSXin Ji INTERFACE_CHANGE_INT, 0); 15038bdfc5daSXin Ji 15048bdfc5daSXin Ji anx7625_start_dp_work(ctx); 15058bdfc5daSXin Ji 150660487584SPi-Hsun Shih if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 150760487584SPi-Hsun Shih drm_helper_hpd_irq_event(ctx->bridge.dev); 1508a57e7345SHsin-Yi Wang 1509a57e7345SHsin-Yi Wang return 0; 1510a57e7345SHsin-Yi Wang } 1511a57e7345SHsin-Yi Wang 1512a57e7345SHsin-Yi Wang static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux, 1513a57e7345SHsin-Yi Wang unsigned long wait_us) 1514a57e7345SHsin-Yi Wang { 1515a57e7345SHsin-Yi Wang struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1516d65feac2SPin-yen Lin struct device *dev = ctx->dev; 1517a57e7345SHsin-Yi Wang int ret; 1518a57e7345SHsin-Yi Wang 1519a57e7345SHsin-Yi Wang pm_runtime_get_sync(dev); 1520a57e7345SHsin-Yi Wang ret = _anx7625_hpd_polling(ctx, wait_us); 1521a57e7345SHsin-Yi Wang pm_runtime_mark_last_busy(dev); 1522a57e7345SHsin-Yi Wang pm_runtime_put_autosuspend(dev); 1523a57e7345SHsin-Yi Wang 1524a57e7345SHsin-Yi Wang return ret; 15258bdfc5daSXin Ji } 15268bdfc5daSXin Ji 15278bdfc5daSXin Ji static void anx7625_remove_edid(struct anx7625_data *ctx) 15288bdfc5daSXin Ji { 15298bdfc5daSXin Ji ctx->slimport_edid_p.edid_block_num = -1; 15308bdfc5daSXin Ji } 15318bdfc5daSXin Ji 1532fd0310b6SXin Ji static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1533fd0310b6SXin Ji { 1534fd0310b6SXin Ji int i; 1535fd0310b6SXin Ji 1536fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1537fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1538fd0310b6SXin Ji DP_TX_LANE0_SWING_REG0 + i, 1539fb8da7f3SNícolas F. R. A. Prado ctx->pdata.lane0_reg_data[i]); 1540fd0310b6SXin Ji 1541fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1542fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1543fd0310b6SXin Ji DP_TX_LANE1_SWING_REG0 + i, 1544fb8da7f3SNícolas F. R. A. Prado ctx->pdata.lane1_reg_data[i]); 1545fd0310b6SXin Ji } 1546fd0310b6SXin Ji 15478bdfc5daSXin Ji static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 15488bdfc5daSXin Ji { 1549d65feac2SPin-yen Lin struct device *dev = ctx->dev; 15508bdfc5daSXin Ji 15518bdfc5daSXin Ji /* HPD changed */ 15528bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 15538bdfc5daSXin Ji (u32)on); 15548bdfc5daSXin Ji 15558bdfc5daSXin Ji if (on == 0) { 15568bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 15578bdfc5daSXin Ji anx7625_remove_edid(ctx); 15588bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 15598bdfc5daSXin Ji } else { 15608bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 15618bdfc5daSXin Ji anx7625_start_dp_work(ctx); 1562fd0310b6SXin Ji anx7625_dp_adjust_swing(ctx); 15638bdfc5daSXin Ji } 15648bdfc5daSXin Ji } 15658bdfc5daSXin Ji 15668bdfc5daSXin Ji static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 15678bdfc5daSXin Ji { 15688bdfc5daSXin Ji int intr_vector, status; 1569d65feac2SPin-yen Lin struct device *dev = ctx->dev; 15708bdfc5daSXin Ji 15718bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 15728bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 15738bdfc5daSXin Ji if (status < 0) { 15748bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 15758bdfc5daSXin Ji return status; 15768bdfc5daSXin Ji } 15778bdfc5daSXin Ji 15788bdfc5daSXin Ji intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 15798bdfc5daSXin Ji INTERFACE_CHANGE_INT); 15808bdfc5daSXin Ji if (intr_vector < 0) { 15818bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 15828bdfc5daSXin Ji return intr_vector; 15838bdfc5daSXin Ji } 15848bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 15858bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 15868bdfc5daSXin Ji INTERFACE_CHANGE_INT, 15878bdfc5daSXin Ji intr_vector & (~intr_vector)); 15888bdfc5daSXin Ji if (status < 0) { 15898bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 15908bdfc5daSXin Ji return status; 15918bdfc5daSXin Ji } 15928bdfc5daSXin Ji 15938bdfc5daSXin Ji if (!(intr_vector & HPD_STATUS_CHANGE)) 15948bdfc5daSXin Ji return -ENOENT; 15958bdfc5daSXin Ji 15968bdfc5daSXin Ji status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 15978bdfc5daSXin Ji SYSTEM_STSTUS); 15988bdfc5daSXin Ji if (status < 0) { 15998bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 16008bdfc5daSXin Ji return status; 16018bdfc5daSXin Ji } 16028bdfc5daSXin Ji 16038bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 16048bdfc5daSXin Ji dp_hpd_change_handler(ctx, status & HPD_STATUS); 16058bdfc5daSXin Ji 16068bdfc5daSXin Ji return 0; 16078bdfc5daSXin Ji } 16088bdfc5daSXin Ji 16098bdfc5daSXin Ji static void anx7625_work_func(struct work_struct *work) 16108bdfc5daSXin Ji { 16118bdfc5daSXin Ji int event; 16128bdfc5daSXin Ji struct anx7625_data *ctx = container_of(work, 16138bdfc5daSXin Ji struct anx7625_data, work); 16148bdfc5daSXin Ji 16158bdfc5daSXin Ji mutex_lock(&ctx->lock); 161660487584SPi-Hsun Shih 1617d65feac2SPin-yen Lin if (pm_runtime_suspended(ctx->dev)) { 1618f2cca20fSChen-Yu Tsai mutex_unlock(&ctx->lock); 1619f2cca20fSChen-Yu Tsai return; 1620f2cca20fSChen-Yu Tsai } 162160487584SPi-Hsun Shih 16228bdfc5daSXin Ji event = anx7625_hpd_change_detect(ctx); 1623f2cca20fSChen-Yu Tsai 1624f2cca20fSChen-Yu Tsai mutex_unlock(&ctx->lock); 1625f2cca20fSChen-Yu Tsai 16268bdfc5daSXin Ji if (event < 0) 1627f2cca20fSChen-Yu Tsai return; 16288bdfc5daSXin Ji 16298bdfc5daSXin Ji if (ctx->bridge_attached) 16308bdfc5daSXin Ji drm_helper_hpd_irq_event(ctx->bridge.dev); 16318bdfc5daSXin Ji } 16328bdfc5daSXin Ji 16338bdfc5daSXin Ji static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 16348bdfc5daSXin Ji { 16358bdfc5daSXin Ji struct anx7625_data *ctx = (struct anx7625_data *)data; 16368bdfc5daSXin Ji 16378bdfc5daSXin Ji queue_work(ctx->workqueue, &ctx->work); 16388bdfc5daSXin Ji 16398bdfc5daSXin Ji return IRQ_HANDLED; 16408bdfc5daSXin Ji } 16418bdfc5daSXin Ji 1642fd0310b6SXin Ji static int anx7625_get_swing_setting(struct device *dev, 1643fd0310b6SXin Ji struct anx7625_platform_data *pdata) 1644fd0310b6SXin Ji { 1645fd0310b6SXin Ji int num_regs; 1646fd0310b6SXin Ji 1647fd0310b6SXin Ji if (of_get_property(dev->of_node, 1648fd0310b6SXin Ji "analogix,lane0-swing", &num_regs)) { 1649fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1650fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1651fd0310b6SXin Ji 1652fd0310b6SXin Ji pdata->dp_lane0_swing_reg_cnt = num_regs; 1653fb8da7f3SNícolas F. R. A. Prado of_property_read_u8_array(dev->of_node, "analogix,lane0-swing", 1654fd0310b6SXin Ji pdata->lane0_reg_data, num_regs); 1655fd0310b6SXin Ji } 1656fd0310b6SXin Ji 1657fd0310b6SXin Ji if (of_get_property(dev->of_node, 1658fd0310b6SXin Ji "analogix,lane1-swing", &num_regs)) { 1659fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1660fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1661fd0310b6SXin Ji 1662fd0310b6SXin Ji pdata->dp_lane1_swing_reg_cnt = num_regs; 1663fb8da7f3SNícolas F. R. A. Prado of_property_read_u8_array(dev->of_node, "analogix,lane1-swing", 1664fd0310b6SXin Ji pdata->lane1_reg_data, num_regs); 1665fd0310b6SXin Ji } 1666fd0310b6SXin Ji 1667fd0310b6SXin Ji return 0; 1668fd0310b6SXin Ji } 1669fd0310b6SXin Ji 16708bdfc5daSXin Ji static int anx7625_parse_dt(struct device *dev, 16718bdfc5daSXin Ji struct anx7625_platform_data *pdata) 16728bdfc5daSXin Ji { 1673fd0310b6SXin Ji struct device_node *np = dev->of_node, *ep0; 1674fd0310b6SXin Ji int bus_type, mipi_lanes; 16758bdfc5daSXin Ji 1676fd0310b6SXin Ji anx7625_get_swing_setting(dev, pdata); 1677fd0310b6SXin Ji 1678b708b36aSXin Ji pdata->is_dpi = 0; /* default dsi mode */ 16791d43a512SLiang He of_node_put(pdata->mipi_host_node); 16808bdfc5daSXin Ji pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 16818bdfc5daSXin Ji if (!pdata->mipi_host_node) { 16828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 16838bdfc5daSXin Ji return -ENODEV; 16848bdfc5daSXin Ji } 16858bdfc5daSXin Ji 1686b708b36aSXin Ji bus_type = 0; 1687fd0310b6SXin Ji mipi_lanes = MAX_LANES_SUPPORT; 1688fd0310b6SXin Ji ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1689fd0310b6SXin Ji if (ep0) { 1690fd0310b6SXin Ji if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1691fd0310b6SXin Ji bus_type = 0; 1692fd0310b6SXin Ji 1693930e7cbaSMarek Vasut mipi_lanes = drm_of_get_data_lanes_count(ep0, 1, MAX_LANES_SUPPORT); 1694670c87fdSMarek Vasut of_node_put(ep0); 1695fd0310b6SXin Ji } 1696fd0310b6SXin Ji 1697b708b36aSXin Ji if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */ 1698b708b36aSXin Ji pdata->is_dpi = 1; 1699fd0310b6SXin Ji 1700fd0310b6SXin Ji pdata->mipi_lanes = MAX_LANES_SUPPORT; 1701930e7cbaSMarek Vasut if (mipi_lanes > 0) 1702930e7cbaSMarek Vasut pdata->mipi_lanes = mipi_lanes; 1703fd0310b6SXin Ji 1704fd0310b6SXin Ji if (pdata->is_dpi) 1705fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1706fd0310b6SXin Ji else 1707fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 17088bdfc5daSXin Ji 1709566fef12SXin Ji if (of_property_read_bool(np, "analogix,audio-enable")) 1710566fef12SXin Ji pdata->audio_en = 1; 1711566fef12SXin Ji 17121464e48dSNícolas F. R. A. Prado return 0; 17131464e48dSNícolas F. R. A. Prado } 17141464e48dSNícolas F. R. A. Prado 17151464e48dSNícolas F. R. A. Prado static int anx7625_parse_dt_panel(struct device *dev, 17161464e48dSNícolas F. R. A. Prado struct anx7625_platform_data *pdata) 17171464e48dSNícolas F. R. A. Prado { 17181464e48dSNícolas F. R. A. Prado struct device_node *np = dev->of_node; 17191464e48dSNícolas F. R. A. Prado 17209e82ea0fSJosé Expósito pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); 17219e82ea0fSJosé Expósito if (IS_ERR(pdata->panel_bridge)) { 17223f49f759SNícolas F. R. A. Prado if (PTR_ERR(pdata->panel_bridge) == -ENODEV) { 17233f49f759SNícolas F. R. A. Prado pdata->panel_bridge = NULL; 17248bdfc5daSXin Ji return 0; 17253f49f759SNícolas F. R. A. Prado } 17268bdfc5daSXin Ji 17278bdfc5daSXin Ji return PTR_ERR(pdata->panel_bridge); 17289e82ea0fSJosé Expósito } 17299e82ea0fSJosé Expósito 17308bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 17318bdfc5daSXin Ji 17328bdfc5daSXin Ji return 0; 17338bdfc5daSXin Ji } 17348bdfc5daSXin Ji 1735adca62ecSHsin-Yi Wang static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1736adca62ecSHsin-Yi Wang { 1737adca62ecSHsin-Yi Wang struct device_node *bus, *panel; 1738adca62ecSHsin-Yi Wang 1739adca62ecSHsin-Yi Wang bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1740adca62ecSHsin-Yi Wang if (!bus) 1741adca62ecSHsin-Yi Wang return false; 1742adca62ecSHsin-Yi Wang 1743adca62ecSHsin-Yi Wang panel = of_get_child_by_name(bus, "panel"); 1744adca62ecSHsin-Yi Wang of_node_put(bus); 1745adca62ecSHsin-Yi Wang if (!panel) 1746adca62ecSHsin-Yi Wang return false; 1747adca62ecSHsin-Yi Wang of_node_put(panel); 1748adca62ecSHsin-Yi Wang 1749adca62ecSHsin-Yi Wang return true; 1750adca62ecSHsin-Yi Wang } 1751adca62ecSHsin-Yi Wang 17528bdfc5daSXin Ji static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 17538bdfc5daSXin Ji { 17548bdfc5daSXin Ji return container_of(bridge, struct anx7625_data, bridge); 17558bdfc5daSXin Ji } 17568bdfc5daSXin Ji 1757adca62ecSHsin-Yi Wang static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1758adca62ecSHsin-Yi Wang struct drm_dp_aux_msg *msg) 1759adca62ecSHsin-Yi Wang { 1760adca62ecSHsin-Yi Wang struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1761d65feac2SPin-yen Lin struct device *dev = ctx->dev; 1762adca62ecSHsin-Yi Wang u8 request = msg->request & ~DP_AUX_I2C_MOT; 1763adca62ecSHsin-Yi Wang int ret = 0; 1764adca62ecSHsin-Yi Wang 1765ee4a2ef1SHsin-Yi Wang mutex_lock(&ctx->aux_lock); 1766adca62ecSHsin-Yi Wang pm_runtime_get_sync(dev); 1767adca62ecSHsin-Yi Wang msg->reply = 0; 1768adca62ecSHsin-Yi Wang switch (request) { 1769adca62ecSHsin-Yi Wang case DP_AUX_NATIVE_WRITE: 1770adca62ecSHsin-Yi Wang case DP_AUX_I2C_WRITE: 1771adca62ecSHsin-Yi Wang case DP_AUX_NATIVE_READ: 1772adca62ecSHsin-Yi Wang case DP_AUX_I2C_READ: 1773adca62ecSHsin-Yi Wang break; 1774adca62ecSHsin-Yi Wang default: 1775adca62ecSHsin-Yi Wang ret = -EINVAL; 1776adca62ecSHsin-Yi Wang } 1777adca62ecSHsin-Yi Wang if (!ret) 1778adca62ecSHsin-Yi Wang ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1779adca62ecSHsin-Yi Wang msg->size, msg->buffer); 1780adca62ecSHsin-Yi Wang pm_runtime_mark_last_busy(dev); 1781adca62ecSHsin-Yi Wang pm_runtime_put_autosuspend(dev); 1782ee4a2ef1SHsin-Yi Wang mutex_unlock(&ctx->aux_lock); 1783adca62ecSHsin-Yi Wang 1784adca62ecSHsin-Yi Wang return ret; 1785adca62ecSHsin-Yi Wang } 1786adca62ecSHsin-Yi Wang 17878bdfc5daSXin Ji static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 17888bdfc5daSXin Ji { 1789d65feac2SPin-yen Lin struct device *dev = ctx->dev; 17908bdfc5daSXin Ji struct s_edid_data *p_edid = &ctx->slimport_edid_p; 17918bdfc5daSXin Ji int edid_num; 17928bdfc5daSXin Ji u8 *edid; 17938bdfc5daSXin Ji 17948bdfc5daSXin Ji edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 17958bdfc5daSXin Ji if (!edid) { 17968bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 17978bdfc5daSXin Ji return NULL; 17988bdfc5daSXin Ji } 17998bdfc5daSXin Ji 18008bdfc5daSXin Ji if (ctx->slimport_edid_p.edid_block_num > 0) { 18018bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 18028bdfc5daSXin Ji FOUR_BLOCK_SIZE); 18038bdfc5daSXin Ji return (struct edid *)edid; 18048bdfc5daSXin Ji } 18058bdfc5daSXin Ji 180660487584SPi-Hsun Shih pm_runtime_get_sync(dev); 1807a57e7345SHsin-Yi Wang _anx7625_hpd_polling(ctx, 5000 * 100); 18088bdfc5daSXin Ji edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 18093203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 18108bdfc5daSXin Ji 18118bdfc5daSXin Ji if (edid_num < 1) { 18128bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 18138bdfc5daSXin Ji kfree(edid); 18148bdfc5daSXin Ji return NULL; 18158bdfc5daSXin Ji } 18168bdfc5daSXin Ji 18178bdfc5daSXin Ji p_edid->edid_block_num = edid_num; 18188bdfc5daSXin Ji 18198bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 18208bdfc5daSXin Ji return (struct edid *)edid; 18218bdfc5daSXin Ji } 18228bdfc5daSXin Ji 18238bdfc5daSXin Ji static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 18248bdfc5daSXin Ji { 1825d65feac2SPin-yen Lin struct device *dev = ctx->dev; 18268bdfc5daSXin Ji 1827fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 18288bdfc5daSXin Ji 1829fd0310b6SXin Ji if (ctx->pdata.panel_bridge) 18308bdfc5daSXin Ji return connector_status_connected; 1831fd0310b6SXin Ji 1832fd0310b6SXin Ji return ctx->hpd_status ? connector_status_connected : 1833fd0310b6SXin Ji connector_status_disconnected; 18348bdfc5daSXin Ji } 18358bdfc5daSXin Ji 1836566fef12SXin Ji static int anx7625_audio_hw_params(struct device *dev, void *data, 1837566fef12SXin Ji struct hdmi_codec_daifmt *fmt, 1838566fef12SXin Ji struct hdmi_codec_params *params) 1839566fef12SXin Ji { 1840566fef12SXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 1841566fef12SXin Ji int wl, ch, rate; 1842566fef12SXin Ji int ret = 0; 1843566fef12SXin Ji 1844f8e1fa0fSXin Ji if (anx7625_sink_detect(ctx) == connector_status_disconnected) { 1845f8e1fa0fSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "DP not connected\n"); 1846f8e1fa0fSXin Ji return 0; 1847f8e1fa0fSXin Ji } 1848f8e1fa0fSXin Ji 1849f8e1fa0fSXin Ji if (fmt->fmt != HDMI_DSP_A && fmt->fmt != HDMI_I2S) { 1850f8e1fa0fSXin Ji DRM_DEV_ERROR(dev, "only supports DSP_A & I2S\n"); 1851566fef12SXin Ji return -EINVAL; 1852566fef12SXin Ji } 1853566fef12SXin Ji 1854566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1855566fef12SXin Ji params->sample_rate, params->sample_width, 1856566fef12SXin Ji params->cea.channels); 1857566fef12SXin Ji 1858f8e1fa0fSXin Ji if (fmt->fmt == HDMI_DSP_A) 1859f8e1fa0fSXin Ji ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1860566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 1861566fef12SXin Ji ~I2S_SLAVE_MODE, 1862566fef12SXin Ji TDM_SLAVE_MODE); 1863f8e1fa0fSXin Ji else 1864f8e1fa0fSXin Ji ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1865f8e1fa0fSXin Ji AUDIO_CHANNEL_STATUS_6, 1866f8e1fa0fSXin Ji ~TDM_SLAVE_MODE, 1867f8e1fa0fSXin Ji I2S_SLAVE_MODE); 1868566fef12SXin Ji 1869566fef12SXin Ji /* Word length */ 1870566fef12SXin Ji switch (params->sample_width) { 1871566fef12SXin Ji case 16: 1872566fef12SXin Ji wl = AUDIO_W_LEN_16_20MAX; 1873566fef12SXin Ji break; 1874566fef12SXin Ji case 18: 1875566fef12SXin Ji wl = AUDIO_W_LEN_18_20MAX; 1876566fef12SXin Ji break; 1877566fef12SXin Ji case 20: 1878566fef12SXin Ji wl = AUDIO_W_LEN_20_20MAX; 1879566fef12SXin Ji break; 1880566fef12SXin Ji case 24: 1881566fef12SXin Ji wl = AUDIO_W_LEN_24_24MAX; 1882566fef12SXin Ji break; 1883566fef12SXin Ji default: 1884566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1885566fef12SXin Ji params->sample_width); 1886566fef12SXin Ji return -EINVAL; 1887566fef12SXin Ji } 1888566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1889566fef12SXin Ji AUDIO_CHANNEL_STATUS_5, 1890566fef12SXin Ji 0xf0, wl); 1891566fef12SXin Ji 1892566fef12SXin Ji /* Channel num */ 1893566fef12SXin Ji switch (params->cea.channels) { 1894566fef12SXin Ji case 2: 1895566fef12SXin Ji ch = I2S_CH_2; 1896566fef12SXin Ji break; 1897566fef12SXin Ji case 4: 1898566fef12SXin Ji ch = TDM_CH_4; 1899566fef12SXin Ji break; 1900566fef12SXin Ji case 6: 1901566fef12SXin Ji ch = TDM_CH_6; 1902566fef12SXin Ji break; 1903566fef12SXin Ji case 8: 1904566fef12SXin Ji ch = TDM_CH_8; 1905566fef12SXin Ji break; 1906566fef12SXin Ji default: 1907566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1908566fef12SXin Ji params->cea.channels); 1909566fef12SXin Ji return -EINVAL; 1910566fef12SXin Ji } 1911566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1912566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1913566fef12SXin Ji if (ch > I2S_CH_2) 1914566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1915566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1916566fef12SXin Ji else 1917566fef12SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1918566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1919566fef12SXin Ji 1920566fef12SXin Ji /* FS */ 1921566fef12SXin Ji switch (params->sample_rate) { 1922566fef12SXin Ji case 32000: 1923566fef12SXin Ji rate = AUDIO_FS_32K; 1924566fef12SXin Ji break; 1925566fef12SXin Ji case 44100: 1926566fef12SXin Ji rate = AUDIO_FS_441K; 1927566fef12SXin Ji break; 1928566fef12SXin Ji case 48000: 1929566fef12SXin Ji rate = AUDIO_FS_48K; 1930566fef12SXin Ji break; 1931566fef12SXin Ji case 88200: 1932566fef12SXin Ji rate = AUDIO_FS_882K; 1933566fef12SXin Ji break; 1934566fef12SXin Ji case 96000: 1935566fef12SXin Ji rate = AUDIO_FS_96K; 1936566fef12SXin Ji break; 1937566fef12SXin Ji case 176400: 1938566fef12SXin Ji rate = AUDIO_FS_1764K; 1939566fef12SXin Ji break; 1940566fef12SXin Ji case 192000: 1941566fef12SXin Ji rate = AUDIO_FS_192K; 1942566fef12SXin Ji break; 1943566fef12SXin Ji default: 1944566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1945566fef12SXin Ji params->sample_rate); 1946566fef12SXin Ji return -EINVAL; 1947566fef12SXin Ji } 1948566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1949566fef12SXin Ji AUDIO_CHANNEL_STATUS_4, 1950566fef12SXin Ji 0xf0, rate); 1951566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1952566fef12SXin Ji AP_AV_STATUS, AP_AUDIO_CHG); 1953566fef12SXin Ji if (ret < 0) { 1954566fef12SXin Ji DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1955566fef12SXin Ji return -EIO; 1956566fef12SXin Ji } 1957566fef12SXin Ji 1958566fef12SXin Ji return 0; 1959566fef12SXin Ji } 1960566fef12SXin Ji 1961566fef12SXin Ji static void anx7625_audio_shutdown(struct device *dev, void *data) 1962566fef12SXin Ji { 1963566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1964566fef12SXin Ji } 1965566fef12SXin Ji 1966566fef12SXin Ji static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1967566fef12SXin Ji struct device_node *endpoint) 1968566fef12SXin Ji { 1969566fef12SXin Ji struct of_endpoint of_ep; 1970566fef12SXin Ji int ret; 1971566fef12SXin Ji 1972566fef12SXin Ji ret = of_graph_parse_endpoint(endpoint, &of_ep); 1973566fef12SXin Ji if (ret < 0) 1974566fef12SXin Ji return ret; 1975566fef12SXin Ji 1976566fef12SXin Ji /* 1977566fef12SXin Ji * HDMI sound should be located at external DPI port 1978566fef12SXin Ji * Didn't have good way to check where is internal(DSI) 1979566fef12SXin Ji * or external(DPI) bridge 1980566fef12SXin Ji */ 1981566fef12SXin Ji return 0; 1982566fef12SXin Ji } 1983566fef12SXin Ji 1984566fef12SXin Ji static void 1985566fef12SXin Ji anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1986566fef12SXin Ji enum drm_connector_status status) 1987566fef12SXin Ji { 1988566fef12SXin Ji if (ctx->plugged_cb && ctx->codec_dev) { 1989566fef12SXin Ji ctx->plugged_cb(ctx->codec_dev, 1990566fef12SXin Ji status == connector_status_connected); 1991566fef12SXin Ji } 1992566fef12SXin Ji } 1993566fef12SXin Ji 1994566fef12SXin Ji static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1995566fef12SXin Ji hdmi_codec_plugged_cb fn, 1996566fef12SXin Ji struct device *codec_dev) 1997566fef12SXin Ji { 1998566fef12SXin Ji struct anx7625_data *ctx = data; 1999566fef12SXin Ji 2000566fef12SXin Ji ctx->plugged_cb = fn; 2001566fef12SXin Ji ctx->codec_dev = codec_dev; 2002566fef12SXin Ji anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 2003566fef12SXin Ji 2004566fef12SXin Ji return 0; 2005566fef12SXin Ji } 2006566fef12SXin Ji 2007607a264eSXin Ji static int anx7625_audio_get_eld(struct device *dev, void *data, 2008607a264eSXin Ji u8 *buf, size_t len) 2009607a264eSXin Ji { 2010607a264eSXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 2011607a264eSXin Ji 2012607a264eSXin Ji if (!ctx->connector) { 201397f2c684SHsin-Yi Wang /* Pass en empty ELD if connector not available */ 201497f2c684SHsin-Yi Wang memset(buf, 0, len); 201597f2c684SHsin-Yi Wang } else { 2016607a264eSXin Ji dev_dbg(dev, "audio copy eld\n"); 2017607a264eSXin Ji memcpy(buf, ctx->connector->eld, 2018607a264eSXin Ji min(sizeof(ctx->connector->eld), len)); 201997f2c684SHsin-Yi Wang } 2020607a264eSXin Ji 2021607a264eSXin Ji return 0; 2022607a264eSXin Ji } 2023607a264eSXin Ji 2024566fef12SXin Ji static const struct hdmi_codec_ops anx7625_codec_ops = { 2025566fef12SXin Ji .hw_params = anx7625_audio_hw_params, 2026566fef12SXin Ji .audio_shutdown = anx7625_audio_shutdown, 2027607a264eSXin Ji .get_eld = anx7625_audio_get_eld, 2028566fef12SXin Ji .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 2029566fef12SXin Ji .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 2030566fef12SXin Ji }; 2031566fef12SXin Ji 2032566fef12SXin Ji static void anx7625_unregister_audio(struct anx7625_data *ctx) 2033566fef12SXin Ji { 2034d65feac2SPin-yen Lin struct device *dev = ctx->dev; 2035566fef12SXin Ji 2036566fef12SXin Ji if (ctx->audio_pdev) { 2037566fef12SXin Ji platform_device_unregister(ctx->audio_pdev); 2038566fef12SXin Ji ctx->audio_pdev = NULL; 2039566fef12SXin Ji } 2040566fef12SXin Ji 2041566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 2042566fef12SXin Ji } 2043566fef12SXin Ji 2044566fef12SXin Ji static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 2045566fef12SXin Ji { 2046566fef12SXin Ji struct hdmi_codec_pdata codec_data = { 2047566fef12SXin Ji .ops = &anx7625_codec_ops, 2048566fef12SXin Ji .max_i2s_channels = 8, 2049566fef12SXin Ji .i2s = 1, 2050566fef12SXin Ji .data = ctx, 2051566fef12SXin Ji }; 2052566fef12SXin Ji 2053566fef12SXin Ji ctx->audio_pdev = platform_device_register_data(dev, 2054566fef12SXin Ji HDMI_CODEC_DRV_NAME, 2055566fef12SXin Ji PLATFORM_DEVID_AUTO, 2056566fef12SXin Ji &codec_data, 2057566fef12SXin Ji sizeof(codec_data)); 2058566fef12SXin Ji 2059566fef12SXin Ji if (IS_ERR(ctx->audio_pdev)) 206083ddd806SDan Carpenter return PTR_ERR(ctx->audio_pdev); 2061566fef12SXin Ji 2062566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 2063566fef12SXin Ji 2064566fef12SXin Ji return 0; 2065566fef12SXin Ji } 2066566fef12SXin Ji 20671464e48dSNícolas F. R. A. Prado static int anx7625_setup_dsi_device(struct anx7625_data *ctx) 20688bdfc5daSXin Ji { 20698bdfc5daSXin Ji struct mipi_dsi_device *dsi; 2070d65feac2SPin-yen Lin struct device *dev = ctx->dev; 20718bdfc5daSXin Ji struct mipi_dsi_host *host; 20728bdfc5daSXin Ji const struct mipi_dsi_device_info info = { 20738bdfc5daSXin Ji .type = "anx7625", 20748bdfc5daSXin Ji .channel = 0, 20758bdfc5daSXin Ji .node = NULL, 20768bdfc5daSXin Ji }; 20778bdfc5daSXin Ji 20788bdfc5daSXin Ji host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 207944865765SNícolas F. R. A. Prado if (!host) 208044865765SNícolas F. R. A. Prado return dev_err_probe(dev, -EPROBE_DEFER, "fail to find dsi host.\n"); 20818bdfc5daSXin Ji 208225a390a9SMaxime Ripard dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 20838bdfc5daSXin Ji if (IS_ERR(dsi)) { 20848bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 20858bdfc5daSXin Ji return -EINVAL; 20868bdfc5daSXin Ji } 20878bdfc5daSXin Ji 2088fd0310b6SXin Ji dsi->lanes = ctx->pdata.mipi_lanes; 20898bdfc5daSXin Ji dsi->format = MIPI_DSI_FMT_RGB888; 20908bdfc5daSXin Ji dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 20918bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 20924404cdb5SRex-BC Chen MIPI_DSI_MODE_VIDEO_HSE | 20934404cdb5SRex-BC Chen MIPI_DSI_HS_PKT_END_ALIGNED; 20948bdfc5daSXin Ji 20951464e48dSNícolas F. R. A. Prado ctx->dsi = dsi; 20961464e48dSNícolas F. R. A. Prado 20971464e48dSNícolas F. R. A. Prado return 0; 20981464e48dSNícolas F. R. A. Prado } 20991464e48dSNícolas F. R. A. Prado 21001464e48dSNícolas F. R. A. Prado static int anx7625_attach_dsi(struct anx7625_data *ctx) 21011464e48dSNícolas F. R. A. Prado { 2102d65feac2SPin-yen Lin struct device *dev = ctx->dev; 21031464e48dSNícolas F. R. A. Prado int ret; 21041464e48dSNícolas F. R. A. Prado 21051464e48dSNícolas F. R. A. Prado DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 21061464e48dSNícolas F. R. A. Prado 21071464e48dSNícolas F. R. A. Prado ret = devm_mipi_dsi_attach(dev, ctx->dsi); 210825a390a9SMaxime Ripard if (ret) { 21098bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 211025a390a9SMaxime Ripard return ret; 21118bdfc5daSXin Ji } 21128bdfc5daSXin Ji 21138bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 21148bdfc5daSXin Ji 21158bdfc5daSXin Ji return 0; 21168bdfc5daSXin Ji } 21178bdfc5daSXin Ji 2118cd1637c7SXin Ji static void hdcp_check_work_func(struct work_struct *work) 2119cd1637c7SXin Ji { 2120cd1637c7SXin Ji u8 status; 2121cd1637c7SXin Ji struct delayed_work *dwork; 2122cd1637c7SXin Ji struct anx7625_data *ctx; 2123cd1637c7SXin Ji struct device *dev; 2124cd1637c7SXin Ji struct drm_device *drm_dev; 2125cd1637c7SXin Ji 2126cd1637c7SXin Ji dwork = to_delayed_work(work); 2127cd1637c7SXin Ji ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2128d65feac2SPin-yen Lin dev = ctx->dev; 2129cd1637c7SXin Ji 2130cd1637c7SXin Ji if (!ctx->connector) { 2131cd1637c7SXin Ji dev_err(dev, "HDCP connector is null!"); 2132cd1637c7SXin Ji return; 2133cd1637c7SXin Ji } 2134cd1637c7SXin Ji 2135cd1637c7SXin Ji drm_dev = ctx->connector->dev; 2136cd1637c7SXin Ji drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2137cd1637c7SXin Ji mutex_lock(&ctx->hdcp_wq_lock); 2138cd1637c7SXin Ji 2139cd1637c7SXin Ji status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2140cd1637c7SXin Ji dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2141cd1637c7SXin Ji if (status & BIT(1)) { 2142cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2143cd1637c7SXin Ji drm_hdcp_update_content_protection(ctx->connector, 2144cd1637c7SXin Ji ctx->hdcp_cp); 2145cd1637c7SXin Ji dev_dbg(dev, "update CP to ENABLE\n"); 2146cd1637c7SXin Ji } 2147cd1637c7SXin Ji 2148cd1637c7SXin Ji mutex_unlock(&ctx->hdcp_wq_lock); 2149cd1637c7SXin Ji drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2150cd1637c7SXin Ji } 2151cd1637c7SXin Ji 2152cd1637c7SXin Ji static int anx7625_connector_atomic_check(struct anx7625_data *ctx, 2153cd1637c7SXin Ji struct drm_connector_state *state) 2154cd1637c7SXin Ji { 2155d65feac2SPin-yen Lin struct device *dev = ctx->dev; 2156cd1637c7SXin Ji int cp; 2157cd1637c7SXin Ji 2158cd1637c7SXin Ji dev_dbg(dev, "hdcp state check\n"); 2159cd1637c7SXin Ji cp = state->content_protection; 2160cd1637c7SXin Ji 2161cd1637c7SXin Ji if (cp == ctx->hdcp_cp) 2162cd1637c7SXin Ji return 0; 2163cd1637c7SXin Ji 2164cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2165cd1637c7SXin Ji if (ctx->dp_en) { 2166cd1637c7SXin Ji dev_dbg(dev, "enable HDCP\n"); 2167cd1637c7SXin Ji anx7625_hdcp_enable(ctx); 2168cd1637c7SXin Ji 2169cd1637c7SXin Ji queue_delayed_work(ctx->hdcp_workqueue, 2170cd1637c7SXin Ji &ctx->hdcp_work, 2171cd1637c7SXin Ji msecs_to_jiffies(2000)); 2172cd1637c7SXin Ji } 2173cd1637c7SXin Ji } 2174cd1637c7SXin Ji 2175cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2176cd1637c7SXin Ji if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2177cd1637c7SXin Ji dev_err(dev, "current CP is not ENABLED\n"); 2178cd1637c7SXin Ji return -EINVAL; 2179cd1637c7SXin Ji } 2180cd1637c7SXin Ji anx7625_hdcp_disable(ctx); 2181cd1637c7SXin Ji ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 2182cd1637c7SXin Ji drm_hdcp_update_content_protection(ctx->connector, 2183cd1637c7SXin Ji ctx->hdcp_cp); 2184cd1637c7SXin Ji dev_dbg(dev, "update CP to UNDESIRE\n"); 2185cd1637c7SXin Ji } 2186cd1637c7SXin Ji 2187cd1637c7SXin Ji if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2188cd1637c7SXin Ji dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n"); 2189cd1637c7SXin Ji return -EINVAL; 2190cd1637c7SXin Ji } 2191cd1637c7SXin Ji 2192cd1637c7SXin Ji return 0; 2193cd1637c7SXin Ji } 2194cd1637c7SXin Ji 21958bdfc5daSXin Ji static int anx7625_bridge_attach(struct drm_bridge *bridge, 21968bdfc5daSXin Ji enum drm_bridge_attach_flags flags) 21978bdfc5daSXin Ji { 21988bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 21998bdfc5daSXin Ji int err; 2200d65feac2SPin-yen Lin struct device *dev = ctx->dev; 22018bdfc5daSXin Ji 22028bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 22038bdfc5daSXin Ji if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 22048bdfc5daSXin Ji return -EINVAL; 22058bdfc5daSXin Ji 22068bdfc5daSXin Ji if (!bridge->encoder) { 22078bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Parent encoder object not found"); 22088bdfc5daSXin Ji return -ENODEV; 22098bdfc5daSXin Ji } 22108bdfc5daSXin Ji 2211adca62ecSHsin-Yi Wang ctx->aux.drm_dev = bridge->dev; 2212adca62ecSHsin-Yi Wang err = drm_dp_aux_register(&ctx->aux); 2213adca62ecSHsin-Yi Wang if (err) { 2214adca62ecSHsin-Yi Wang dev_err(dev, "failed to register aux channel: %d\n", err); 2215adca62ecSHsin-Yi Wang return err; 2216adca62ecSHsin-Yi Wang } 2217adca62ecSHsin-Yi Wang 22188bdfc5daSXin Ji if (ctx->pdata.panel_bridge) { 22198bdfc5daSXin Ji err = drm_bridge_attach(bridge->encoder, 22208bdfc5daSXin Ji ctx->pdata.panel_bridge, 22218bdfc5daSXin Ji &ctx->bridge, flags); 2222fb8d617fSLaurent Pinchart if (err) 22238bdfc5daSXin Ji return err; 22248bdfc5daSXin Ji } 22258bdfc5daSXin Ji 22268bdfc5daSXin Ji ctx->bridge_attached = 1; 22278bdfc5daSXin Ji 22288bdfc5daSXin Ji return 0; 22298bdfc5daSXin Ji } 22308bdfc5daSXin Ji 2231adca62ecSHsin-Yi Wang static void anx7625_bridge_detach(struct drm_bridge *bridge) 2232adca62ecSHsin-Yi Wang { 2233adca62ecSHsin-Yi Wang struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2234adca62ecSHsin-Yi Wang 2235adca62ecSHsin-Yi Wang drm_dp_aux_unregister(&ctx->aux); 2236adca62ecSHsin-Yi Wang } 2237adca62ecSHsin-Yi Wang 22388bdfc5daSXin Ji static enum drm_mode_status 22398bdfc5daSXin Ji anx7625_bridge_mode_valid(struct drm_bridge *bridge, 22408bdfc5daSXin Ji const struct drm_display_info *info, 22418bdfc5daSXin Ji const struct drm_display_mode *mode) 22428bdfc5daSXin Ji { 22438bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2244d65feac2SPin-yen Lin struct device *dev = ctx->dev; 22458bdfc5daSXin Ji 22468bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 22478bdfc5daSXin Ji 22488bdfc5daSXin Ji /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 22498bdfc5daSXin Ji if (mode->clock > SUPPORT_PIXEL_CLOCK) { 22508bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, 22518bdfc5daSXin Ji "drm mode invalid, pixelclock too high.\n"); 22528bdfc5daSXin Ji return MODE_CLOCK_HIGH; 22538bdfc5daSXin Ji } 22548bdfc5daSXin Ji 22558bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 22568bdfc5daSXin Ji 22578bdfc5daSXin Ji return MODE_OK; 22588bdfc5daSXin Ji } 22598bdfc5daSXin Ji 22608bdfc5daSXin Ji static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 22618bdfc5daSXin Ji const struct drm_display_mode *old_mode, 22628bdfc5daSXin Ji const struct drm_display_mode *mode) 22638bdfc5daSXin Ji { 22648bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2265d65feac2SPin-yen Lin struct device *dev = ctx->dev; 22668bdfc5daSXin Ji 22678bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 22688bdfc5daSXin Ji 22698bdfc5daSXin Ji ctx->dt.pixelclock.min = mode->clock; 22708bdfc5daSXin Ji ctx->dt.hactive.min = mode->hdisplay; 22718bdfc5daSXin Ji ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 22728bdfc5daSXin Ji ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 22738bdfc5daSXin Ji ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 22748bdfc5daSXin Ji ctx->dt.vactive.min = mode->vdisplay; 22758bdfc5daSXin Ji ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 22768bdfc5daSXin Ji ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 22778bdfc5daSXin Ji ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 22788bdfc5daSXin Ji 22798bdfc5daSXin Ji ctx->display_timing_valid = 1; 22808bdfc5daSXin Ji 22818bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 22828bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 22838bdfc5daSXin Ji ctx->dt.hactive.min, 22848bdfc5daSXin Ji ctx->dt.hsync_len.min, 22858bdfc5daSXin Ji ctx->dt.hfront_porch.min, 22868bdfc5daSXin Ji ctx->dt.hback_porch.min); 22878bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 22888bdfc5daSXin Ji ctx->dt.vactive.min, 22898bdfc5daSXin Ji ctx->dt.vsync_len.min, 22908bdfc5daSXin Ji ctx->dt.vfront_porch.min, 22918bdfc5daSXin Ji ctx->dt.vback_porch.min); 22928bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 22938bdfc5daSXin Ji mode->hdisplay, 22948bdfc5daSXin Ji mode->hsync_start); 22958bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 22968bdfc5daSXin Ji mode->hsync_end, 22978bdfc5daSXin Ji mode->htotal); 22988bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 22998bdfc5daSXin Ji mode->vdisplay, 23008bdfc5daSXin Ji mode->vsync_start); 23018bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 23028bdfc5daSXin Ji mode->vsync_end, 23038bdfc5daSXin Ji mode->vtotal); 23048bdfc5daSXin Ji } 23058bdfc5daSXin Ji 23068bdfc5daSXin Ji static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 23078bdfc5daSXin Ji const struct drm_display_mode *mode, 23088bdfc5daSXin Ji struct drm_display_mode *adj) 23098bdfc5daSXin Ji { 23108bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2311d65feac2SPin-yen Lin struct device *dev = ctx->dev; 23128bdfc5daSXin Ji u32 hsync, hfp, hbp, hblanking; 23138bdfc5daSXin Ji u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 23148bdfc5daSXin Ji u32 vref, adj_clock; 23158bdfc5daSXin Ji 23168bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 23178bdfc5daSXin Ji 2318fd0310b6SXin Ji /* No need fixup for external monitor */ 2319fd0310b6SXin Ji if (!ctx->pdata.panel_bridge) 2320fd0310b6SXin Ji return true; 2321fd0310b6SXin Ji 23228bdfc5daSXin Ji hsync = mode->hsync_end - mode->hsync_start; 23238bdfc5daSXin Ji hfp = mode->hsync_start - mode->hdisplay; 23248bdfc5daSXin Ji hbp = mode->htotal - mode->hsync_end; 23258bdfc5daSXin Ji hblanking = mode->htotal - mode->hdisplay; 23268bdfc5daSXin Ji 23278bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 23288bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 23298bdfc5daSXin Ji hsync, hfp, hbp, adj->clock); 23308bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 23318bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 23328bdfc5daSXin Ji 23338bdfc5daSXin Ji adj_hfp = hfp; 23348bdfc5daSXin Ji adj_hsync = hsync; 23358bdfc5daSXin Ji adj_hbp = hbp; 23368bdfc5daSXin Ji adj_hblanking = hblanking; 23378bdfc5daSXin Ji 23388bdfc5daSXin Ji /* HFP needs to be even */ 23398bdfc5daSXin Ji if (hfp & 0x1) { 23408bdfc5daSXin Ji adj_hfp += 1; 23418bdfc5daSXin Ji adj_hblanking += 1; 23428bdfc5daSXin Ji } 23438bdfc5daSXin Ji 23448bdfc5daSXin Ji /* HBP needs to be even */ 23458bdfc5daSXin Ji if (hbp & 0x1) { 23468bdfc5daSXin Ji adj_hbp -= 1; 23478bdfc5daSXin Ji adj_hblanking -= 1; 23488bdfc5daSXin Ji } 23498bdfc5daSXin Ji 23508bdfc5daSXin Ji /* HSYNC needs to be even */ 23518bdfc5daSXin Ji if (hsync & 0x1) { 23528bdfc5daSXin Ji if (adj_hblanking < hblanking) 23538bdfc5daSXin Ji adj_hsync += 1; 23548bdfc5daSXin Ji else 23558bdfc5daSXin Ji adj_hsync -= 1; 23568bdfc5daSXin Ji } 23578bdfc5daSXin Ji 23588bdfc5daSXin Ji /* 23598bdfc5daSXin Ji * Once illegal timing detected, use default HFP, HSYNC, HBP 23608bdfc5daSXin Ji * This adjusting made for built-in eDP panel, for the externel 23618bdfc5daSXin Ji * DP monitor, may need return false. 23628bdfc5daSXin Ji */ 23638bdfc5daSXin Ji if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 23648bdfc5daSXin Ji adj_hsync = SYNC_LEN_DEF; 23658bdfc5daSXin Ji adj_hfp = HFP_HBP_DEF; 23668bdfc5daSXin Ji adj_hbp = HFP_HBP_DEF; 23678bdfc5daSXin Ji vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 23688bdfc5daSXin Ji if (hblanking < HBLANKING_MIN) { 23698bdfc5daSXin Ji delta_adj = HBLANKING_MIN - hblanking; 23708bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 23718bdfc5daSXin Ji adj->clock += DIV_ROUND_UP(adj_clock, 1000); 23728bdfc5daSXin Ji } else { 23738bdfc5daSXin Ji delta_adj = hblanking - HBLANKING_MIN; 23748bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 23758bdfc5daSXin Ji adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 23768bdfc5daSXin Ji } 23778bdfc5daSXin Ji 23788bdfc5daSXin Ji DRM_WARN("illegal hblanking timing, use default.\n"); 23798bdfc5daSXin Ji DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 23808bdfc5daSXin Ji } else if (adj_hfp < HP_MIN) { 23818bdfc5daSXin Ji /* Adjust hfp if hfp less than HP_MIN */ 23828bdfc5daSXin Ji delta_adj = HP_MIN - adj_hfp; 23838bdfc5daSXin Ji adj_hfp = HP_MIN; 23848bdfc5daSXin Ji 23858bdfc5daSXin Ji /* 23868bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP does not have enough 23878bdfc5daSXin Ji * space, adjust HSYNC length, otherwise adjust HBP 23888bdfc5daSXin Ji */ 23898bdfc5daSXin Ji if ((adj_hbp - delta_adj) < HP_MIN) 23908bdfc5daSXin Ji /* HBP not enough space */ 23918bdfc5daSXin Ji adj_hsync -= delta_adj; 23928bdfc5daSXin Ji else 23938bdfc5daSXin Ji adj_hbp -= delta_adj; 23948bdfc5daSXin Ji } else if (adj_hbp < HP_MIN) { 23958bdfc5daSXin Ji delta_adj = HP_MIN - adj_hbp; 23968bdfc5daSXin Ji adj_hbp = HP_MIN; 23978bdfc5daSXin Ji 23988bdfc5daSXin Ji /* 23998bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP hasn't enough space, 24008bdfc5daSXin Ji * adjust HSYNC length, otherwize adjust HBP 24018bdfc5daSXin Ji */ 24028bdfc5daSXin Ji if ((adj_hfp - delta_adj) < HP_MIN) 24038bdfc5daSXin Ji /* HFP not enough space */ 24048bdfc5daSXin Ji adj_hsync -= delta_adj; 24058bdfc5daSXin Ji else 24068bdfc5daSXin Ji adj_hfp -= delta_adj; 24078bdfc5daSXin Ji } 24088bdfc5daSXin Ji 24098bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 24108bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 24118bdfc5daSXin Ji adj_hsync, adj_hfp, adj_hbp, adj->clock); 24128bdfc5daSXin Ji 24138bdfc5daSXin Ji /* Reconstruct timing */ 24148bdfc5daSXin Ji adj->hsync_start = adj->hdisplay + adj_hfp; 24158bdfc5daSXin Ji adj->hsync_end = adj->hsync_start + adj_hsync; 24168bdfc5daSXin Ji adj->htotal = adj->hsync_end + adj_hbp; 24178bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 24188bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 24198bdfc5daSXin Ji 24208bdfc5daSXin Ji return true; 24218bdfc5daSXin Ji } 24228bdfc5daSXin Ji 2423191be002SXin Ji static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2424191be002SXin Ji struct drm_bridge_state *bridge_state, 2425191be002SXin Ji struct drm_crtc_state *crtc_state, 2426191be002SXin Ji struct drm_connector_state *conn_state) 24278bdfc5daSXin Ji { 24288bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2429d65feac2SPin-yen Lin struct device *dev = ctx->dev; 24308bdfc5daSXin Ji 2431191be002SXin Ji dev_dbg(dev, "drm bridge atomic check\n"); 2432cd1637c7SXin Ji 2433cd1637c7SXin Ji anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2434191be002SXin Ji &crtc_state->adjusted_mode); 2435cd1637c7SXin Ji 2436cd1637c7SXin Ji return anx7625_connector_atomic_check(ctx, conn_state); 2437191be002SXin Ji } 2438191be002SXin Ji 2439191be002SXin Ji static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2440191be002SXin Ji struct drm_bridge_state *state) 2441191be002SXin Ji { 2442191be002SXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2443d65feac2SPin-yen Lin struct device *dev = ctx->dev; 2444191be002SXin Ji struct drm_connector *connector; 2445191be002SXin Ji 2446191be002SXin Ji dev_dbg(dev, "drm atomic enable\n"); 2447191be002SXin Ji 2448191be002SXin Ji if (!bridge->encoder) { 2449191be002SXin Ji dev_err(dev, "Parent encoder object not found"); 2450191be002SXin Ji return; 2451191be002SXin Ji } 2452191be002SXin Ji 2453191be002SXin Ji connector = drm_atomic_get_new_connector_for_encoder(state->base.state, 2454191be002SXin Ji bridge->encoder); 2455191be002SXin Ji if (!connector) 2456191be002SXin Ji return; 2457191be002SXin Ji 2458191be002SXin Ji ctx->connector = connector; 24598bdfc5daSXin Ji 246060487584SPi-Hsun Shih pm_runtime_get_sync(dev); 2461a57e7345SHsin-Yi Wang _anx7625_hpd_polling(ctx, 5000 * 100); 24628bdfc5daSXin Ji 24638bdfc5daSXin Ji anx7625_dp_start(ctx); 24648bdfc5daSXin Ji } 24658bdfc5daSXin Ji 2466191be002SXin Ji static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2467191be002SXin Ji struct drm_bridge_state *old) 24688bdfc5daSXin Ji { 24698bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2470d65feac2SPin-yen Lin struct device *dev = ctx->dev; 24718bdfc5daSXin Ji 2472191be002SXin Ji dev_dbg(dev, "drm atomic disable\n"); 24738bdfc5daSXin Ji 2474191be002SXin Ji ctx->connector = NULL; 24758bdfc5daSXin Ji anx7625_dp_stop(ctx); 24768bdfc5daSXin Ji 2477ee4a2ef1SHsin-Yi Wang mutex_lock(&ctx->aux_lock); 2478ee4a2ef1SHsin-Yi Wang pm_runtime_put_sync_suspend(dev); 2479ee4a2ef1SHsin-Yi Wang mutex_unlock(&ctx->aux_lock); 24808bdfc5daSXin Ji } 24818bdfc5daSXin Ji 24828bdfc5daSXin Ji static enum drm_connector_status 24838bdfc5daSXin Ji anx7625_bridge_detect(struct drm_bridge *bridge) 24848bdfc5daSXin Ji { 24858bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2486d65feac2SPin-yen Lin struct device *dev = ctx->dev; 24878bdfc5daSXin Ji 24888bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 24898bdfc5daSXin Ji 24908bdfc5daSXin Ji return anx7625_sink_detect(ctx); 24918bdfc5daSXin Ji } 24928bdfc5daSXin Ji 24938bdfc5daSXin Ji static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 24948bdfc5daSXin Ji struct drm_connector *connector) 24958bdfc5daSXin Ji { 24968bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2497d65feac2SPin-yen Lin struct device *dev = ctx->dev; 24988bdfc5daSXin Ji 24998bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 25008bdfc5daSXin Ji 25018bdfc5daSXin Ji return anx7625_get_edid(ctx); 25028bdfc5daSXin Ji } 25038bdfc5daSXin Ji 25048bdfc5daSXin Ji static const struct drm_bridge_funcs anx7625_bridge_funcs = { 25058bdfc5daSXin Ji .attach = anx7625_bridge_attach, 2506adca62ecSHsin-Yi Wang .detach = anx7625_bridge_detach, 25078bdfc5daSXin Ji .mode_valid = anx7625_bridge_mode_valid, 25088bdfc5daSXin Ji .mode_set = anx7625_bridge_mode_set, 2509191be002SXin Ji .atomic_check = anx7625_bridge_atomic_check, 2510191be002SXin Ji .atomic_enable = anx7625_bridge_atomic_enable, 2511191be002SXin Ji .atomic_disable = anx7625_bridge_atomic_disable, 2512191be002SXin Ji .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2513191be002SXin Ji .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2514191be002SXin Ji .atomic_reset = drm_atomic_helper_bridge_reset, 25158bdfc5daSXin Ji .detect = anx7625_bridge_detect, 25168bdfc5daSXin Ji .get_edid = anx7625_bridge_get_edid, 25178bdfc5daSXin Ji }; 25188bdfc5daSXin Ji 25198bdfc5daSXin Ji static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 25208bdfc5daSXin Ji struct i2c_client *client) 25218bdfc5daSXin Ji { 2522d65feac2SPin-yen Lin struct device *dev = ctx->dev; 2523f5f05ddcSMiaoqian Lin 2524e660916bSHsin-Yi Wang ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter, 25258bdfc5daSXin Ji TX_P0_ADDR >> 1); 2526f5f05ddcSMiaoqian Lin if (IS_ERR(ctx->i2c.tx_p0_client)) 2527f5f05ddcSMiaoqian Lin return PTR_ERR(ctx->i2c.tx_p0_client); 25288bdfc5daSXin Ji 2529e660916bSHsin-Yi Wang ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter, 25308bdfc5daSXin Ji TX_P1_ADDR >> 1); 2531e660916bSHsin-Yi Wang if (IS_ERR(ctx->i2c.tx_p1_client)) 2532e660916bSHsin-Yi Wang return PTR_ERR(ctx->i2c.tx_p1_client); 25338bdfc5daSXin Ji 2534e660916bSHsin-Yi Wang ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter, 25358bdfc5daSXin Ji TX_P2_ADDR >> 1); 2536e660916bSHsin-Yi Wang if (IS_ERR(ctx->i2c.tx_p2_client)) 2537e660916bSHsin-Yi Wang return PTR_ERR(ctx->i2c.tx_p2_client); 25388bdfc5daSXin Ji 2539e660916bSHsin-Yi Wang ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter, 25408bdfc5daSXin Ji RX_P0_ADDR >> 1); 2541e660916bSHsin-Yi Wang if (IS_ERR(ctx->i2c.rx_p0_client)) 2542e660916bSHsin-Yi Wang return PTR_ERR(ctx->i2c.rx_p0_client); 25438bdfc5daSXin Ji 2544e660916bSHsin-Yi Wang ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter, 25458bdfc5daSXin Ji RX_P1_ADDR >> 1); 2546e660916bSHsin-Yi Wang if (IS_ERR(ctx->i2c.rx_p1_client)) 2547e660916bSHsin-Yi Wang return PTR_ERR(ctx->i2c.rx_p1_client); 25488bdfc5daSXin Ji 2549e660916bSHsin-Yi Wang ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter, 25508bdfc5daSXin Ji RX_P2_ADDR >> 1); 2551e660916bSHsin-Yi Wang if (IS_ERR(ctx->i2c.rx_p2_client)) 2552e660916bSHsin-Yi Wang return PTR_ERR(ctx->i2c.rx_p2_client); 25538bdfc5daSXin Ji 2554e660916bSHsin-Yi Wang ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter, 25558bdfc5daSXin Ji TCPC_INTERFACE_ADDR >> 1); 2556e660916bSHsin-Yi Wang if (IS_ERR(ctx->i2c.tcpc_client)) 2557e660916bSHsin-Yi Wang return PTR_ERR(ctx->i2c.tcpc_client); 25588bdfc5daSXin Ji 25598bdfc5daSXin Ji return 0; 25608bdfc5daSXin Ji } 25618bdfc5daSXin Ji 256260487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 256360487584SPi-Hsun Shih { 256460487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 256560487584SPi-Hsun Shih 256660487584SPi-Hsun Shih mutex_lock(&ctx->lock); 256760487584SPi-Hsun Shih 256860487584SPi-Hsun Shih anx7625_stop_dp_work(ctx); 256960487584SPi-Hsun Shih anx7625_power_standby(ctx); 257060487584SPi-Hsun Shih 257160487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 257260487584SPi-Hsun Shih 257360487584SPi-Hsun Shih return 0; 257460487584SPi-Hsun Shih } 257560487584SPi-Hsun Shih 257660487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 257760487584SPi-Hsun Shih { 257860487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 257960487584SPi-Hsun Shih 258060487584SPi-Hsun Shih mutex_lock(&ctx->lock); 258160487584SPi-Hsun Shih 258260487584SPi-Hsun Shih anx7625_power_on_init(ctx); 258360487584SPi-Hsun Shih 258460487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 258560487584SPi-Hsun Shih 258660487584SPi-Hsun Shih return 0; 258760487584SPi-Hsun Shih } 258860487584SPi-Hsun Shih 258960487584SPi-Hsun Shih static const struct dev_pm_ops anx7625_pm_ops = { 2590aa196597SHsin-Yi Wang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2591aa196597SHsin-Yi Wang pm_runtime_force_resume) 259260487584SPi-Hsun Shih SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 259360487584SPi-Hsun Shih anx7625_runtime_pm_resume, NULL) 259460487584SPi-Hsun Shih }; 259560487584SPi-Hsun Shih 2596adca62ecSHsin-Yi Wang static void anx7625_runtime_disable(void *data) 2597adca62ecSHsin-Yi Wang { 2598adca62ecSHsin-Yi Wang pm_runtime_dont_use_autosuspend(data); 2599adca62ecSHsin-Yi Wang pm_runtime_disable(data); 2600adca62ecSHsin-Yi Wang } 2601adca62ecSHsin-Yi Wang 26021464e48dSNícolas F. R. A. Prado static int anx7625_link_bridge(struct drm_dp_aux *aux) 26031464e48dSNícolas F. R. A. Prado { 26041464e48dSNícolas F. R. A. Prado struct anx7625_data *platform = container_of(aux, struct anx7625_data, aux); 26051464e48dSNícolas F. R. A. Prado struct device *dev = aux->dev; 26061464e48dSNícolas F. R. A. Prado int ret; 26071464e48dSNícolas F. R. A. Prado 26081464e48dSNícolas F. R. A. Prado ret = anx7625_parse_dt_panel(dev, &platform->pdata); 26091464e48dSNícolas F. R. A. Prado if (ret) { 26101464e48dSNícolas F. R. A. Prado DRM_DEV_ERROR(dev, "fail to parse DT for panel : %d\n", ret); 26111464e48dSNícolas F. R. A. Prado return ret; 26121464e48dSNícolas F. R. A. Prado } 26131464e48dSNícolas F. R. A. Prado 26141464e48dSNícolas F. R. A. Prado platform->bridge.funcs = &anx7625_bridge_funcs; 26151464e48dSNícolas F. R. A. Prado platform->bridge.of_node = dev->of_node; 26161464e48dSNícolas F. R. A. Prado if (!anx7625_of_panel_on_aux_bus(dev)) 26171464e48dSNícolas F. R. A. Prado platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 26181464e48dSNícolas F. R. A. Prado if (!platform->pdata.panel_bridge) 26191464e48dSNícolas F. R. A. Prado platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 26201464e48dSNícolas F. R. A. Prado DRM_BRIDGE_OP_DETECT; 26211464e48dSNícolas F. R. A. Prado platform->bridge.type = platform->pdata.panel_bridge ? 26221464e48dSNícolas F. R. A. Prado DRM_MODE_CONNECTOR_eDP : 26231464e48dSNícolas F. R. A. Prado DRM_MODE_CONNECTOR_DisplayPort; 26241464e48dSNícolas F. R. A. Prado 26251464e48dSNícolas F. R. A. Prado drm_bridge_add(&platform->bridge); 26261464e48dSNícolas F. R. A. Prado 26271464e48dSNícolas F. R. A. Prado if (!platform->pdata.is_dpi) { 26281464e48dSNícolas F. R. A. Prado ret = anx7625_attach_dsi(platform); 26291464e48dSNícolas F. R. A. Prado if (ret) 26301464e48dSNícolas F. R. A. Prado drm_bridge_remove(&platform->bridge); 26311464e48dSNícolas F. R. A. Prado } 26321464e48dSNícolas F. R. A. Prado 26331464e48dSNícolas F. R. A. Prado return ret; 26341464e48dSNícolas F. R. A. Prado } 26351464e48dSNícolas F. R. A. Prado 263671450f8cSUwe Kleine-König static int anx7625_i2c_probe(struct i2c_client *client) 26378bdfc5daSXin Ji { 26388bdfc5daSXin Ji struct anx7625_data *platform; 26398bdfc5daSXin Ji struct anx7625_platform_data *pdata; 26408bdfc5daSXin Ji int ret = 0; 26418bdfc5daSXin Ji struct device *dev = &client->dev; 26428bdfc5daSXin Ji 26438bdfc5daSXin Ji if (!i2c_check_functionality(client->adapter, 26448bdfc5daSXin Ji I2C_FUNC_SMBUS_I2C_BLOCK)) { 26458bdfc5daSXin Ji DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 26468bdfc5daSXin Ji return -ENODEV; 26478bdfc5daSXin Ji } 26488bdfc5daSXin Ji 264957bfb34aSHsin-Yi Wang platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL); 26508bdfc5daSXin Ji if (!platform) { 26518bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 26528bdfc5daSXin Ji return -ENOMEM; 26538bdfc5daSXin Ji } 26548bdfc5daSXin Ji 26558bdfc5daSXin Ji pdata = &platform->pdata; 26568bdfc5daSXin Ji 2657d65feac2SPin-yen Lin platform->dev = &client->dev; 26588bdfc5daSXin Ji i2c_set_clientdata(client, platform); 26598bdfc5daSXin Ji 26606c744983SHsin-Yi Wang pdata->supplies[0].supply = "vdd10"; 26616c744983SHsin-Yi Wang pdata->supplies[1].supply = "vdd18"; 26626c744983SHsin-Yi Wang pdata->supplies[2].supply = "vdd33"; 26636c744983SHsin-Yi Wang ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 26646c744983SHsin-Yi Wang pdata->supplies); 26656c744983SHsin-Yi Wang if (ret) { 26666c744983SHsin-Yi Wang DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 26676c744983SHsin-Yi Wang return ret; 26686c744983SHsin-Yi Wang } 26698bdfc5daSXin Ji anx7625_init_gpio(platform); 26708bdfc5daSXin Ji 26718bdfc5daSXin Ji mutex_init(&platform->lock); 2672cd1637c7SXin Ji mutex_init(&platform->hdcp_wq_lock); 2673ee4a2ef1SHsin-Yi Wang mutex_init(&platform->aux_lock); 2674cd1637c7SXin Ji 2675cd1637c7SXin Ji INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2676cd1637c7SXin Ji platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2677cd1637c7SXin Ji if (!platform->hdcp_workqueue) { 2678cd1637c7SXin Ji dev_err(dev, "fail to create work queue\n"); 2679cd1637c7SXin Ji ret = -ENOMEM; 268057bfb34aSHsin-Yi Wang return ret; 2681cd1637c7SXin Ji } 26828bdfc5daSXin Ji 26838bdfc5daSXin Ji platform->pdata.intp_irq = client->irq; 26848bdfc5daSXin Ji if (platform->pdata.intp_irq) { 26858bdfc5daSXin Ji INIT_WORK(&platform->work, anx7625_work_func); 2686f03ab662SPi-Hsun Shih platform->workqueue = alloc_workqueue("anx7625_work", 2687f03ab662SPi-Hsun Shih WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 26888bdfc5daSXin Ji if (!platform->workqueue) { 26898bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create work queue\n"); 26908bdfc5daSXin Ji ret = -ENOMEM; 2691cd1637c7SXin Ji goto free_hdcp_wq; 26928bdfc5daSXin Ji } 26938bdfc5daSXin Ji 26948bdfc5daSXin Ji ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 26958bdfc5daSXin Ji NULL, anx7625_intr_hpd_isr, 26968bdfc5daSXin Ji IRQF_TRIGGER_FALLING | 26978bdfc5daSXin Ji IRQF_ONESHOT, 26988bdfc5daSXin Ji "anx7625-intp", platform); 26998bdfc5daSXin Ji if (ret) { 27008bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to request irq\n"); 27018bdfc5daSXin Ji goto free_wq; 27028bdfc5daSXin Ji } 27038bdfc5daSXin Ji } 27048bdfc5daSXin Ji 2705adca62ecSHsin-Yi Wang platform->aux.name = "anx7625-aux"; 2706adca62ecSHsin-Yi Wang platform->aux.dev = dev; 2707adca62ecSHsin-Yi Wang platform->aux.transfer = anx7625_aux_transfer; 2708a57e7345SHsin-Yi Wang platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted; 2709adca62ecSHsin-Yi Wang drm_dp_aux_init(&platform->aux); 2710adca62ecSHsin-Yi Wang 27111464e48dSNícolas F. R. A. Prado ret = anx7625_parse_dt(dev, pdata); 27121464e48dSNícolas F. R. A. Prado if (ret) { 27131464e48dSNícolas F. R. A. Prado if (ret != -EPROBE_DEFER) 27141464e48dSNícolas F. R. A. Prado DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 27151464e48dSNícolas F. R. A. Prado goto free_wq; 27161464e48dSNícolas F. R. A. Prado } 27171464e48dSNícolas F. R. A. Prado 27181464e48dSNícolas F. R. A. Prado if (!platform->pdata.is_dpi) { 27191464e48dSNícolas F. R. A. Prado ret = anx7625_setup_dsi_device(platform); 27201464e48dSNícolas F. R. A. Prado if (ret < 0) 27211464e48dSNícolas F. R. A. Prado goto free_wq; 27221464e48dSNícolas F. R. A. Prado } 27231464e48dSNícolas F. R. A. Prado 27241464e48dSNícolas F. R. A. Prado /* 27251464e48dSNícolas F. R. A. Prado * Registering the i2c devices will retrigger deferred probe, so it 27261464e48dSNícolas F. R. A. Prado * needs to be done after calls that might return EPROBE_DEFER, 27271464e48dSNícolas F. R. A. Prado * otherwise we can get an infinite loop. 27281464e48dSNícolas F. R. A. Prado */ 27298bdfc5daSXin Ji if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 27308bdfc5daSXin Ji ret = -ENOMEM; 27318bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 27328bdfc5daSXin Ji goto free_wq; 27338bdfc5daSXin Ji } 27348bdfc5daSXin Ji 273560487584SPi-Hsun Shih pm_runtime_enable(dev); 2736adca62ecSHsin-Yi Wang pm_runtime_set_autosuspend_delay(dev, 1000); 2737adca62ecSHsin-Yi Wang pm_runtime_use_autosuspend(dev); 2738adca62ecSHsin-Yi Wang pm_suspend_ignore_children(dev, true); 2739adca62ecSHsin-Yi Wang ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev); 2740adca62ecSHsin-Yi Wang if (ret) 27416f5efd11SYang Yingliang goto free_wq; 274260487584SPi-Hsun Shih 27431464e48dSNícolas F. R. A. Prado /* 27441464e48dSNícolas F. R. A. Prado * Populating the aux bus will retrigger deferred probe, so it needs to 27451464e48dSNícolas F. R. A. Prado * be done after calls that might return EPROBE_DEFER, otherwise we can 27461464e48dSNícolas F. R. A. Prado * get an infinite loop. 27471464e48dSNícolas F. R. A. Prado */ 27481464e48dSNícolas F. R. A. Prado ret = devm_of_dp_aux_populate_bus(&platform->aux, anx7625_link_bridge); 2749dfb02eb6SHsin-Yi Wang if (ret) { 27501464e48dSNícolas F. R. A. Prado if (ret != -ENODEV) { 27511464e48dSNícolas F. R. A. Prado DRM_DEV_ERROR(dev, "failed to populate aux bus : %d\n", ret); 27521464e48dSNícolas F. R. A. Prado goto free_wq; 27531464e48dSNícolas F. R. A. Prado } 27541464e48dSNícolas F. R. A. Prado 27551464e48dSNícolas F. R. A. Prado ret = anx7625_link_bridge(&platform->aux); 27561464e48dSNícolas F. R. A. Prado if (ret) 2757dfb02eb6SHsin-Yi Wang goto free_wq; 2758dfb02eb6SHsin-Yi Wang } 2759dfb02eb6SHsin-Yi Wang 276060487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) { 27618bdfc5daSXin Ji anx7625_disable_pd_protocol(platform); 276260487584SPi-Hsun Shih pm_runtime_get_sync(dev); 2763a57e7345SHsin-Yi Wang _anx7625_hpd_polling(platform, 5000 * 100); 27648bdfc5daSXin Ji } 27658bdfc5daSXin Ji 27668bdfc5daSXin Ji /* Add work function */ 27678bdfc5daSXin Ji if (platform->pdata.intp_irq) 27688bdfc5daSXin Ji queue_work(platform->workqueue, &platform->work); 27698bdfc5daSXin Ji 2770566fef12SXin Ji if (platform->pdata.audio_en) 2771566fef12SXin Ji anx7625_register_audio(dev, platform); 2772566fef12SXin Ji 27738bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 27748bdfc5daSXin Ji 27758bdfc5daSXin Ji return 0; 27768bdfc5daSXin Ji 27778bdfc5daSXin Ji free_wq: 27788bdfc5daSXin Ji if (platform->workqueue) 27798bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 27808bdfc5daSXin Ji 2781cd1637c7SXin Ji free_hdcp_wq: 2782cd1637c7SXin Ji if (platform->hdcp_workqueue) 2783cd1637c7SXin Ji destroy_workqueue(platform->hdcp_workqueue); 2784cd1637c7SXin Ji 27858bdfc5daSXin Ji return ret; 27868bdfc5daSXin Ji } 27878bdfc5daSXin Ji 2788ed5c2f5fSUwe Kleine-König static void anx7625_i2c_remove(struct i2c_client *client) 27898bdfc5daSXin Ji { 27908bdfc5daSXin Ji struct anx7625_data *platform = i2c_get_clientdata(client); 27918bdfc5daSXin Ji 27928bdfc5daSXin Ji drm_bridge_remove(&platform->bridge); 27938bdfc5daSXin Ji 27948bdfc5daSXin Ji if (platform->pdata.intp_irq) 27958bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 27968bdfc5daSXin Ji 2797cd1637c7SXin Ji if (platform->hdcp_workqueue) { 2798cd1637c7SXin Ji cancel_delayed_work(&platform->hdcp_work); 2799beac7709SXin Ji flush_workqueue(platform->hdcp_workqueue); 2800beac7709SXin Ji destroy_workqueue(platform->hdcp_workqueue); 2801cd1637c7SXin Ji } 2802cd1637c7SXin Ji 280360487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) 280460487584SPi-Hsun Shih pm_runtime_put_sync_suspend(&client->dev); 280560487584SPi-Hsun Shih 2806566fef12SXin Ji if (platform->pdata.audio_en) 2807566fef12SXin Ji anx7625_unregister_audio(platform); 28088bdfc5daSXin Ji } 28098bdfc5daSXin Ji 28108bdfc5daSXin Ji static const struct i2c_device_id anx7625_id[] = { 28118bdfc5daSXin Ji {"anx7625", 0}, 28128bdfc5daSXin Ji {} 28138bdfc5daSXin Ji }; 28148bdfc5daSXin Ji 28158bdfc5daSXin Ji MODULE_DEVICE_TABLE(i2c, anx7625_id); 28168bdfc5daSXin Ji 28178bdfc5daSXin Ji static const struct of_device_id anx_match_table[] = { 28188bdfc5daSXin Ji {.compatible = "analogix,anx7625",}, 28198bdfc5daSXin Ji {}, 28208bdfc5daSXin Ji }; 2821ad5fd900SYu Jiahua MODULE_DEVICE_TABLE(of, anx_match_table); 28228bdfc5daSXin Ji 28238bdfc5daSXin Ji static struct i2c_driver anx7625_driver = { 28248bdfc5daSXin Ji .driver = { 28258bdfc5daSXin Ji .name = "anx7625", 28268bdfc5daSXin Ji .of_match_table = anx_match_table, 282760487584SPi-Hsun Shih .pm = &anx7625_pm_ops, 28288bdfc5daSXin Ji }, 2829332af828SUwe Kleine-König .probe = anx7625_i2c_probe, 28308bdfc5daSXin Ji .remove = anx7625_i2c_remove, 28318bdfc5daSXin Ji 28328bdfc5daSXin Ji .id_table = anx7625_id, 28338bdfc5daSXin Ji }; 28348bdfc5daSXin Ji 28358bdfc5daSXin Ji module_i2c_driver(anx7625_driver); 28368bdfc5daSXin Ji 28378bdfc5daSXin Ji MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 28388bdfc5daSXin Ji MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 28398bdfc5daSXin Ji MODULE_LICENSE("GPL v2"); 28408bdfc5daSXin Ji MODULE_VERSION(ANX7625_DRV_VERSION); 2841