18bdfc5daSXin Ji // SPDX-License-Identifier: GPL-2.0-only 28bdfc5daSXin Ji /* 38bdfc5daSXin Ji * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 48bdfc5daSXin Ji * 58bdfc5daSXin Ji */ 68bdfc5daSXin Ji #include <linux/gcd.h> 78bdfc5daSXin Ji #include <linux/gpio/consumer.h> 88bdfc5daSXin Ji #include <linux/i2c.h> 98bdfc5daSXin Ji #include <linux/interrupt.h> 108bdfc5daSXin Ji #include <linux/iopoll.h> 118bdfc5daSXin Ji #include <linux/kernel.h> 128bdfc5daSXin Ji #include <linux/module.h> 138bdfc5daSXin Ji #include <linux/mutex.h> 1460487584SPi-Hsun Shih #include <linux/pm_runtime.h> 156c744983SHsin-Yi Wang #include <linux/regulator/consumer.h> 168bdfc5daSXin Ji #include <linux/slab.h> 178bdfc5daSXin Ji #include <linux/types.h> 188bdfc5daSXin Ji #include <linux/workqueue.h> 198bdfc5daSXin Ji 208bdfc5daSXin Ji #include <linux/of_gpio.h> 218bdfc5daSXin Ji #include <linux/of_graph.h> 228bdfc5daSXin Ji #include <linux/of_platform.h> 238bdfc5daSXin Ji 248bdfc5daSXin Ji #include <drm/drm_atomic_helper.h> 258bdfc5daSXin Ji #include <drm/drm_bridge.h> 268bdfc5daSXin Ji #include <drm/drm_crtc_helper.h> 278bdfc5daSXin Ji #include <drm/drm_dp_helper.h> 288bdfc5daSXin Ji #include <drm/drm_edid.h> 298bdfc5daSXin Ji #include <drm/drm_mipi_dsi.h> 308bdfc5daSXin Ji #include <drm/drm_of.h> 318bdfc5daSXin Ji #include <drm/drm_panel.h> 328bdfc5daSXin Ji #include <drm/drm_print.h> 338bdfc5daSXin Ji #include <drm/drm_probe_helper.h> 348bdfc5daSXin Ji 35fd0310b6SXin Ji #include <media/v4l2-fwnode.h> 36566fef12SXin Ji #include <sound/hdmi-codec.h> 378bdfc5daSXin Ji #include <video/display_timing.h> 388bdfc5daSXin Ji 398bdfc5daSXin Ji #include "anx7625.h" 408bdfc5daSXin Ji 418bdfc5daSXin Ji /* 428bdfc5daSXin Ji * There is a sync issue while access I2C register between AP(CPU) and 438bdfc5daSXin Ji * internal firmware(OCM), to avoid the race condition, AP should access 448bdfc5daSXin Ji * the reserved slave address before slave address occurs changes. 458bdfc5daSXin Ji */ 468bdfc5daSXin Ji static int i2c_access_workaround(struct anx7625_data *ctx, 478bdfc5daSXin Ji struct i2c_client *client) 488bdfc5daSXin Ji { 498bdfc5daSXin Ji u8 offset; 508bdfc5daSXin Ji struct device *dev = &client->dev; 518bdfc5daSXin Ji int ret; 528bdfc5daSXin Ji 538bdfc5daSXin Ji if (client == ctx->last_client) 548bdfc5daSXin Ji return 0; 558bdfc5daSXin Ji 568bdfc5daSXin Ji ctx->last_client = client; 578bdfc5daSXin Ji 588bdfc5daSXin Ji if (client == ctx->i2c.tcpc_client) 598bdfc5daSXin Ji offset = RSVD_00_ADDR; 608bdfc5daSXin Ji else if (client == ctx->i2c.tx_p0_client) 618bdfc5daSXin Ji offset = RSVD_D1_ADDR; 628bdfc5daSXin Ji else if (client == ctx->i2c.tx_p1_client) 638bdfc5daSXin Ji offset = RSVD_60_ADDR; 648bdfc5daSXin Ji else if (client == ctx->i2c.rx_p0_client) 658bdfc5daSXin Ji offset = RSVD_39_ADDR; 668bdfc5daSXin Ji else if (client == ctx->i2c.rx_p1_client) 678bdfc5daSXin Ji offset = RSVD_7F_ADDR; 688bdfc5daSXin Ji else 698bdfc5daSXin Ji offset = RSVD_00_ADDR; 708bdfc5daSXin Ji 718bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, offset, 0x00); 728bdfc5daSXin Ji if (ret < 0) 738bdfc5daSXin Ji DRM_DEV_ERROR(dev, 748bdfc5daSXin Ji "fail to access i2c id=%x\n:%x", 758bdfc5daSXin Ji client->addr, offset); 768bdfc5daSXin Ji 778bdfc5daSXin Ji return ret; 788bdfc5daSXin Ji } 798bdfc5daSXin Ji 808bdfc5daSXin Ji static int anx7625_reg_read(struct anx7625_data *ctx, 818bdfc5daSXin Ji struct i2c_client *client, u8 reg_addr) 828bdfc5daSXin Ji { 838bdfc5daSXin Ji int ret; 848bdfc5daSXin Ji struct device *dev = &client->dev; 858bdfc5daSXin Ji 868bdfc5daSXin Ji i2c_access_workaround(ctx, client); 878bdfc5daSXin Ji 888bdfc5daSXin Ji ret = i2c_smbus_read_byte_data(client, reg_addr); 898bdfc5daSXin Ji if (ret < 0) 908bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 918bdfc5daSXin Ji client->addr, reg_addr); 928bdfc5daSXin Ji 938bdfc5daSXin Ji return ret; 948bdfc5daSXin Ji } 958bdfc5daSXin Ji 968bdfc5daSXin Ji static int anx7625_reg_block_read(struct anx7625_data *ctx, 978bdfc5daSXin Ji struct i2c_client *client, 988bdfc5daSXin Ji u8 reg_addr, u8 len, u8 *buf) 998bdfc5daSXin Ji { 1008bdfc5daSXin Ji int ret; 1018bdfc5daSXin Ji struct device *dev = &client->dev; 1028bdfc5daSXin Ji 1038bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1048bdfc5daSXin Ji 1058bdfc5daSXin Ji ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 1068bdfc5daSXin Ji if (ret < 0) 1078bdfc5daSXin Ji DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 1088bdfc5daSXin Ji client->addr, reg_addr); 1098bdfc5daSXin Ji 1108bdfc5daSXin Ji return ret; 1118bdfc5daSXin Ji } 1128bdfc5daSXin Ji 1138bdfc5daSXin Ji static int anx7625_reg_write(struct anx7625_data *ctx, 1148bdfc5daSXin Ji struct i2c_client *client, 1158bdfc5daSXin Ji u8 reg_addr, u8 reg_val) 1168bdfc5daSXin Ji { 1178bdfc5daSXin Ji int ret; 1188bdfc5daSXin Ji struct device *dev = &client->dev; 1198bdfc5daSXin Ji 1208bdfc5daSXin Ji i2c_access_workaround(ctx, client); 1218bdfc5daSXin Ji 1228bdfc5daSXin Ji ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 1238bdfc5daSXin Ji 1248bdfc5daSXin Ji if (ret < 0) 1258bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 1268bdfc5daSXin Ji client->addr, reg_addr); 1278bdfc5daSXin Ji 1288bdfc5daSXin Ji return ret; 1298bdfc5daSXin Ji } 1308bdfc5daSXin Ji 1318bdfc5daSXin Ji static int anx7625_write_or(struct anx7625_data *ctx, 1328bdfc5daSXin Ji struct i2c_client *client, 1338bdfc5daSXin Ji u8 offset, u8 mask) 1348bdfc5daSXin Ji { 1358bdfc5daSXin Ji int val; 1368bdfc5daSXin Ji 1378bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1388bdfc5daSXin Ji if (val < 0) 1398bdfc5daSXin Ji return val; 1408bdfc5daSXin Ji 1418bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val | (mask))); 1428bdfc5daSXin Ji } 1438bdfc5daSXin Ji 1448bdfc5daSXin Ji static int anx7625_write_and(struct anx7625_data *ctx, 1458bdfc5daSXin Ji struct i2c_client *client, 1468bdfc5daSXin Ji u8 offset, u8 mask) 1478bdfc5daSXin Ji { 1488bdfc5daSXin Ji int val; 1498bdfc5daSXin Ji 1508bdfc5daSXin Ji val = anx7625_reg_read(ctx, client, offset); 1518bdfc5daSXin Ji if (val < 0) 1528bdfc5daSXin Ji return val; 1538bdfc5daSXin Ji 1548bdfc5daSXin Ji return anx7625_reg_write(ctx, client, offset, (val & (mask))); 1558bdfc5daSXin Ji } 1568bdfc5daSXin Ji 157566fef12SXin Ji static int anx7625_write_and_or(struct anx7625_data *ctx, 158566fef12SXin Ji struct i2c_client *client, 159566fef12SXin Ji u8 offset, u8 and_mask, u8 or_mask) 160566fef12SXin Ji { 161566fef12SXin Ji int val; 162566fef12SXin Ji 163566fef12SXin Ji val = anx7625_reg_read(ctx, client, offset); 164566fef12SXin Ji if (val < 0) 165566fef12SXin Ji return val; 166566fef12SXin Ji 167566fef12SXin Ji return anx7625_reg_write(ctx, client, 168566fef12SXin Ji offset, (val & and_mask) | (or_mask)); 169566fef12SXin Ji } 170566fef12SXin Ji 171fd0310b6SXin Ji static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 1728bdfc5daSXin Ji { 173fd0310b6SXin Ji int i, ret; 1748bdfc5daSXin Ji 175fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 176fd0310b6SXin Ji AUDIO_CONTROL_REGISTER, 0x80); 177fd0310b6SXin Ji for (i = 0; i < 13; i++) 178fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 179fd0310b6SXin Ji VIDEO_BIT_MATRIX_12 + i, 180fd0310b6SXin Ji 0x18 + i); 1818bdfc5daSXin Ji 182fd0310b6SXin Ji return ret; 1838bdfc5daSXin Ji } 1848bdfc5daSXin Ji 1858bdfc5daSXin Ji static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 1868bdfc5daSXin Ji { 1878bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 1888bdfc5daSXin Ji } 1898bdfc5daSXin Ji 1908bdfc5daSXin Ji static int wait_aux_op_finish(struct anx7625_data *ctx) 1918bdfc5daSXin Ji { 1928bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 1938bdfc5daSXin Ji int val; 1948bdfc5daSXin Ji int ret; 1958bdfc5daSXin Ji 1968bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 1978bdfc5daSXin Ji ctx, val, 1988bdfc5daSXin Ji (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 1998bdfc5daSXin Ji 2000, 2008bdfc5daSXin Ji 2000 * 150); 2018bdfc5daSXin Ji if (ret) { 2028bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux operation fail!\n"); 2038bdfc5daSXin Ji return -EIO; 2048bdfc5daSXin Ji } 2058bdfc5daSXin Ji 2068bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 2078bdfc5daSXin Ji AP_AUX_CTRL_STATUS); 2088bdfc5daSXin Ji if (val < 0 || (val & 0x0F)) { 2098bdfc5daSXin Ji DRM_DEV_ERROR(dev, "aux status %02x\n", val); 2109a7e49bdSXin Ji return -EIO; 2118bdfc5daSXin Ji } 2128bdfc5daSXin Ji 2139a7e49bdSXin Ji return 0; 2148bdfc5daSXin Ji } 2158bdfc5daSXin Ji 2168bdfc5daSXin Ji static int anx7625_video_mute_control(struct anx7625_data *ctx, 2178bdfc5daSXin Ji u8 status) 2188bdfc5daSXin Ji { 2198bdfc5daSXin Ji int ret; 2208bdfc5daSXin Ji 2218bdfc5daSXin Ji if (status) { 2228bdfc5daSXin Ji /* Set mute on flag */ 2238bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2248bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_MUTE); 2258bdfc5daSXin Ji /* Clear mipi RX en */ 2268bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 2278bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 2288bdfc5daSXin Ji } else { 2298bdfc5daSXin Ji /* Mute off flag */ 2308bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 2318bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 2328bdfc5daSXin Ji /* Set MIPI RX EN */ 2338bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2348bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 2358bdfc5daSXin Ji } 2368bdfc5daSXin Ji 2378bdfc5daSXin Ji return ret; 2388bdfc5daSXin Ji } 2398bdfc5daSXin Ji 2408bdfc5daSXin Ji /* Reduction of fraction a/b */ 2418bdfc5daSXin Ji static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 2428bdfc5daSXin Ji { 2438bdfc5daSXin Ji unsigned long gcd_num; 2448bdfc5daSXin Ji unsigned long tmp_a, tmp_b; 2458bdfc5daSXin Ji u32 i = 1; 2468bdfc5daSXin Ji 2478bdfc5daSXin Ji gcd_num = gcd(*a, *b); 2488bdfc5daSXin Ji *a /= gcd_num; 2498bdfc5daSXin Ji *b /= gcd_num; 2508bdfc5daSXin Ji 2518bdfc5daSXin Ji tmp_a = *a; 2528bdfc5daSXin Ji tmp_b = *b; 2538bdfc5daSXin Ji 2548bdfc5daSXin Ji while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 2558bdfc5daSXin Ji i++; 2568bdfc5daSXin Ji *a = tmp_a / i; 2578bdfc5daSXin Ji *b = tmp_b / i; 2588bdfc5daSXin Ji } 2598bdfc5daSXin Ji 2608bdfc5daSXin Ji /* 2618bdfc5daSXin Ji * In the end, make a, b larger to have higher ODFC PLL 2628bdfc5daSXin Ji * output frequency accuracy 2638bdfc5daSXin Ji */ 2648bdfc5daSXin Ji while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 2658bdfc5daSXin Ji *a <<= 1; 2668bdfc5daSXin Ji *b <<= 1; 2678bdfc5daSXin Ji } 2688bdfc5daSXin Ji 2698bdfc5daSXin Ji *a >>= 1; 2708bdfc5daSXin Ji *b >>= 1; 2718bdfc5daSXin Ji } 2728bdfc5daSXin Ji 2738bdfc5daSXin Ji static int anx7625_calculate_m_n(u32 pixelclock, 2748bdfc5daSXin Ji unsigned long *m, 2758bdfc5daSXin Ji unsigned long *n, 2768bdfc5daSXin Ji u8 *post_divider) 2778bdfc5daSXin Ji { 2788bdfc5daSXin Ji if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 2798bdfc5daSXin Ji /* Pixel clock frequency is too high */ 2808bdfc5daSXin Ji DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 2818bdfc5daSXin Ji pixelclock, 2828bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 2838bdfc5daSXin Ji return -EINVAL; 2848bdfc5daSXin Ji } 2858bdfc5daSXin Ji 2868bdfc5daSXin Ji if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 2878bdfc5daSXin Ji /* Pixel clock frequency is too low */ 2888bdfc5daSXin Ji DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 2898bdfc5daSXin Ji pixelclock, 2908bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 2918bdfc5daSXin Ji return -EINVAL; 2928bdfc5daSXin Ji } 2938bdfc5daSXin Ji 2948bdfc5daSXin Ji for (*post_divider = 1; 2958bdfc5daSXin Ji pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 2968bdfc5daSXin Ji *post_divider += 1; 2978bdfc5daSXin Ji 2988bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 2998bdfc5daSXin Ji for (*post_divider = 1; 3008bdfc5daSXin Ji (pixelclock < 3018bdfc5daSXin Ji (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 3028bdfc5daSXin Ji *post_divider += 1; 3038bdfc5daSXin Ji 3048bdfc5daSXin Ji if (*post_divider > POST_DIVIDER_MAX) { 3058bdfc5daSXin Ji DRM_ERROR("cannot find property post_divider(%d)\n", 3068bdfc5daSXin Ji *post_divider); 3078bdfc5daSXin Ji return -EDOM; 3088bdfc5daSXin Ji } 3098bdfc5daSXin Ji } 3108bdfc5daSXin Ji 3118bdfc5daSXin Ji /* Patch to improve the accuracy */ 3128bdfc5daSXin Ji if (*post_divider == 7) { 3138bdfc5daSXin Ji /* 27,000,000 is not divisible by 7 */ 3148bdfc5daSXin Ji *post_divider = 8; 3158bdfc5daSXin Ji } else if (*post_divider == 11) { 3168bdfc5daSXin Ji /* 27,000,000 is not divisible by 11 */ 3178bdfc5daSXin Ji *post_divider = 12; 3188bdfc5daSXin Ji } else if ((*post_divider == 13) || (*post_divider == 14)) { 3198bdfc5daSXin Ji /* 27,000,000 is not divisible by 13 or 14 */ 3208bdfc5daSXin Ji *post_divider = 15; 3218bdfc5daSXin Ji } 3228bdfc5daSXin Ji 3238bdfc5daSXin Ji if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 3248bdfc5daSXin Ji DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 3258bdfc5daSXin Ji pixelclock * (*post_divider), 3268bdfc5daSXin Ji PLL_OUT_FREQ_ABS_MAX); 3278bdfc5daSXin Ji return -EDOM; 3288bdfc5daSXin Ji } 3298bdfc5daSXin Ji 3308bdfc5daSXin Ji *m = pixelclock; 3318bdfc5daSXin Ji *n = XTAL_FRQ / (*post_divider); 3328bdfc5daSXin Ji 3338bdfc5daSXin Ji anx7625_reduction_of_a_fraction(m, n); 3348bdfc5daSXin Ji 3358bdfc5daSXin Ji return 0; 3368bdfc5daSXin Ji } 3378bdfc5daSXin Ji 3388bdfc5daSXin Ji static int anx7625_odfc_config(struct anx7625_data *ctx, 3398bdfc5daSXin Ji u8 post_divider) 3408bdfc5daSXin Ji { 3418bdfc5daSXin Ji int ret; 3428bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 3438bdfc5daSXin Ji 3448bdfc5daSXin Ji /* Config input reference clock frequency 27MHz/19.2MHz */ 3458bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 3468bdfc5daSXin Ji ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 3478bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 3488bdfc5daSXin Ji (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 3498bdfc5daSXin Ji /* Post divider */ 3508bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 3518bdfc5daSXin Ji MIPI_DIGITAL_PLL_8, 0x0f); 3528bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 3538bdfc5daSXin Ji post_divider << 4); 3548bdfc5daSXin Ji 3558bdfc5daSXin Ji /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 3568bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3578bdfc5daSXin Ji ~MIPI_PLL_VCO_TUNE_REG_VAL); 3588bdfc5daSXin Ji 3598bdfc5daSXin Ji /* Reset ODFC PLL */ 3608bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3618bdfc5daSXin Ji ~MIPI_PLL_RESET_N); 3628bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 3638bdfc5daSXin Ji MIPI_PLL_RESET_N); 3648bdfc5daSXin Ji 3658bdfc5daSXin Ji if (ret < 0) 3668bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error.\n"); 3678bdfc5daSXin Ji 3688bdfc5daSXin Ji return ret; 3698bdfc5daSXin Ji } 3708bdfc5daSXin Ji 3717d066dc7SXin Ji /* 3727d066dc7SXin Ji * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 3737d066dc7SXin Ji * anx7625 defined K ratio for matching MIPI input video clock and 3747d066dc7SXin Ji * DP output video clock. Increase K value can match bigger video data 3757d066dc7SXin Ji * variation. IVO panel has small variation than DP CTS spec, need 3767d066dc7SXin Ji * decrease the K value. 3777d066dc7SXin Ji */ 3787d066dc7SXin Ji static int anx7625_set_k_value(struct anx7625_data *ctx) 3797d066dc7SXin Ji { 3807d066dc7SXin Ji struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data; 3817d066dc7SXin Ji 3827d066dc7SXin Ji if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1) 3837d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 3847d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3B); 3857d066dc7SXin Ji 3867d066dc7SXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 3877d066dc7SXin Ji MIPI_DIGITAL_ADJ_1, 0x3D); 3887d066dc7SXin Ji } 3897d066dc7SXin Ji 3908bdfc5daSXin Ji static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 3918bdfc5daSXin Ji { 3928bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 3938bdfc5daSXin Ji unsigned long m, n; 3948bdfc5daSXin Ji u16 htotal; 3958bdfc5daSXin Ji int ret; 3968bdfc5daSXin Ji u8 post_divider = 0; 3978bdfc5daSXin Ji 3988bdfc5daSXin Ji ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 3998bdfc5daSXin Ji &m, &n, &post_divider); 4008bdfc5daSXin Ji 4018bdfc5daSXin Ji if (ret) { 4028bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 4038bdfc5daSXin Ji return ret; 4048bdfc5daSXin Ji } 4058bdfc5daSXin Ji 4068bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 4078bdfc5daSXin Ji m, n, post_divider); 4088bdfc5daSXin Ji 4098bdfc5daSXin Ji /* Configure pixel clock */ 4108bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 4118bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) & 0xFF); 4128bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 4138bdfc5daSXin Ji (ctx->dt.pixelclock.min / 1000) >> 8); 4148bdfc5daSXin Ji /* Lane count */ 4158bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 4168bdfc5daSXin Ji MIPI_LANE_CTRL_0, 0xfc); 4178bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 418fd0310b6SXin Ji MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 4198bdfc5daSXin Ji 4208bdfc5daSXin Ji /* Htotal */ 4218bdfc5daSXin Ji htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 4228bdfc5daSXin Ji ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 4238bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4248bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 4258bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4268bdfc5daSXin Ji HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 4278bdfc5daSXin Ji /* Hactive */ 4288bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4298bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 4308bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4318bdfc5daSXin Ji HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 4328bdfc5daSXin Ji /* HFP */ 4338bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4348bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 4358bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4368bdfc5daSXin Ji HORIZONTAL_FRONT_PORCH_H, 4378bdfc5daSXin Ji ctx->dt.hfront_porch.min >> 8); 4388bdfc5daSXin Ji /* HWS */ 4398bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4408bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 4418bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4428bdfc5daSXin Ji HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 4438bdfc5daSXin Ji /* HBP */ 4448bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4458bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 4468bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4478bdfc5daSXin Ji HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 4488bdfc5daSXin Ji /* Vactive */ 4498bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 4508bdfc5daSXin Ji ctx->dt.vactive.min); 4518bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 4528bdfc5daSXin Ji ctx->dt.vactive.min >> 8); 4538bdfc5daSXin Ji /* VFP */ 4548bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4558bdfc5daSXin Ji VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 4568bdfc5daSXin Ji /* VWS */ 4578bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4588bdfc5daSXin Ji VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 4598bdfc5daSXin Ji /* VBP */ 4608bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 4618bdfc5daSXin Ji VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 4628bdfc5daSXin Ji /* M value */ 4638bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4648bdfc5daSXin Ji MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 4658bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4668bdfc5daSXin Ji MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 4678bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4688bdfc5daSXin Ji MIPI_PLL_M_NUM_7_0, (m & 0xff)); 4698bdfc5daSXin Ji /* N value */ 4708bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4718bdfc5daSXin Ji MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 4728bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 4738bdfc5daSXin Ji MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 4748bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 4758bdfc5daSXin Ji (n & 0xff)); 4767d066dc7SXin Ji 4777d066dc7SXin Ji anx7625_set_k_value(ctx); 4788bdfc5daSXin Ji 4798bdfc5daSXin Ji ret |= anx7625_odfc_config(ctx, post_divider - 1); 4808bdfc5daSXin Ji 4818bdfc5daSXin Ji if (ret < 0) 4828bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 4838bdfc5daSXin Ji 4848bdfc5daSXin Ji return ret; 4858bdfc5daSXin Ji } 4868bdfc5daSXin Ji 4878bdfc5daSXin Ji static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 4888bdfc5daSXin Ji { 4898bdfc5daSXin Ji int val; 4908bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 4918bdfc5daSXin Ji 4928bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 4938bdfc5daSXin Ji val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 4948bdfc5daSXin Ji if (val < 0) { 4958bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 4968bdfc5daSXin Ji return -EIO; 4978bdfc5daSXin Ji } 4988bdfc5daSXin Ji 4998bdfc5daSXin Ji val |= (1 << MIPI_SWAP_CH3); 5008bdfc5daSXin Ji return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 5018bdfc5daSXin Ji } 5028bdfc5daSXin Ji 5038bdfc5daSXin Ji static int anx7625_api_dsi_config(struct anx7625_data *ctx) 5048bdfc5daSXin Ji 5058bdfc5daSXin Ji { 5068bdfc5daSXin Ji int val, ret; 5078bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5088bdfc5daSXin Ji 5098bdfc5daSXin Ji /* Swap MIPI-DSI data lane 3 P and N */ 5108bdfc5daSXin Ji ret = anx7625_swap_dsi_lane3(ctx); 5118bdfc5daSXin Ji if (ret < 0) { 5128bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 5138bdfc5daSXin Ji return ret; 5148bdfc5daSXin Ji } 5158bdfc5daSXin Ji 5168bdfc5daSXin Ji /* DSI clock settings */ 5178bdfc5daSXin Ji val = (0 << MIPI_HS_PWD_CLK) | 5188bdfc5daSXin Ji (0 << MIPI_HS_RT_CLK) | 5198bdfc5daSXin Ji (0 << MIPI_PD_CLK) | 5208bdfc5daSXin Ji (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 5218bdfc5daSXin Ji (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 5228bdfc5daSXin Ji (0 << MIPI_CLK_DET_DET_BYPASS) | 5238bdfc5daSXin Ji (0 << MIPI_CLK_MISS_CTRL) | 5248bdfc5daSXin Ji (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 5258bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5268bdfc5daSXin Ji MIPI_PHY_CONTROL_3, val); 5278bdfc5daSXin Ji 5288bdfc5daSXin Ji /* 5298bdfc5daSXin Ji * Decreased HS prepare timing delay from 160ns to 80ns work with 5308bdfc5daSXin Ji * a) Dragon board 810 series (Qualcomm AP) 5318bdfc5daSXin Ji * b) Moving Pixel DSI source (PG3A pattern generator + 5328bdfc5daSXin Ji * P332 D-PHY Probe) default D-PHY timing 5338bdfc5daSXin Ji * 5ns/step 5348bdfc5daSXin Ji */ 5358bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5368bdfc5daSXin Ji MIPI_TIME_HS_PRPR, 0x10); 5378bdfc5daSXin Ji 5388bdfc5daSXin Ji /* Enable DSI mode*/ 5398bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 5408bdfc5daSXin Ji SELECT_DSI << MIPI_DPI_SELECT); 5418bdfc5daSXin Ji 5428bdfc5daSXin Ji ret |= anx7625_dsi_video_timing_config(ctx); 5438bdfc5daSXin Ji if (ret < 0) { 5448bdfc5daSXin Ji DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 5458bdfc5daSXin Ji return ret; 5468bdfc5daSXin Ji } 5478bdfc5daSXin Ji 5488bdfc5daSXin Ji /* Toggle m, n ready */ 5498bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 5508bdfc5daSXin Ji ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 5518bdfc5daSXin Ji usleep_range(1000, 1100); 5528bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 5538bdfc5daSXin Ji MIPI_M_NUM_READY | MIPI_N_NUM_READY); 5548bdfc5daSXin Ji 5558bdfc5daSXin Ji /* Configure integer stable register */ 5568bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5578bdfc5daSXin Ji MIPI_VIDEO_STABLE_CNT, 0x02); 5588bdfc5daSXin Ji /* Power on MIPI RX */ 5598bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5608bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x00); 5618bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 5628bdfc5daSXin Ji MIPI_LANE_CTRL_10, 0x80); 5638bdfc5daSXin Ji 5648bdfc5daSXin Ji if (ret < 0) 5658bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 5668bdfc5daSXin Ji 5678bdfc5daSXin Ji return ret; 5688bdfc5daSXin Ji } 5698bdfc5daSXin Ji 5708bdfc5daSXin Ji static int anx7625_dsi_config(struct anx7625_data *ctx) 5718bdfc5daSXin Ji { 5728bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 5738bdfc5daSXin Ji int ret; 5748bdfc5daSXin Ji 5758bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 5768bdfc5daSXin Ji 5778bdfc5daSXin Ji /* DSC disable */ 5788bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 5798bdfc5daSXin Ji R_DSC_CTRL_0, ~DSC_EN); 5808bdfc5daSXin Ji 5818bdfc5daSXin Ji ret |= anx7625_api_dsi_config(ctx); 5828bdfc5daSXin Ji 5838bdfc5daSXin Ji if (ret < 0) { 5848bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 5858bdfc5daSXin Ji return ret; 5868bdfc5daSXin Ji } 5878bdfc5daSXin Ji 5888bdfc5daSXin Ji /* Set MIPI RX EN */ 5898bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 5908bdfc5daSXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 5918bdfc5daSXin Ji /* Clear mute flag */ 5928bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 5938bdfc5daSXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 5948bdfc5daSXin Ji if (ret < 0) 5958bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 5968bdfc5daSXin Ji else 5978bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 5988bdfc5daSXin Ji 5998bdfc5daSXin Ji return ret; 6008bdfc5daSXin Ji } 6018bdfc5daSXin Ji 602fd0310b6SXin Ji static int anx7625_api_dpi_config(struct anx7625_data *ctx) 603fd0310b6SXin Ji { 604fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 605fd0310b6SXin Ji u16 freq = ctx->dt.pixelclock.min / 1000; 606fd0310b6SXin Ji int ret; 607fd0310b6SXin Ji 608fd0310b6SXin Ji /* configure pixel clock */ 609fd0310b6SXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 610fd0310b6SXin Ji PIXEL_CLOCK_L, freq & 0xFF); 611fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 612fd0310b6SXin Ji PIXEL_CLOCK_H, (freq >> 8)); 613fd0310b6SXin Ji 614fd0310b6SXin Ji /* set DPI mode */ 615fd0310b6SXin Ji /* set to DPI PLL module sel */ 616fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 617fd0310b6SXin Ji MIPI_DIGITAL_PLL_9, 0x20); 618fd0310b6SXin Ji /* power down MIPI */ 619fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 620fd0310b6SXin Ji MIPI_LANE_CTRL_10, 0x08); 621fd0310b6SXin Ji /* enable DPI mode */ 622fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 623fd0310b6SXin Ji MIPI_DIGITAL_PLL_18, 0x1C); 624fd0310b6SXin Ji /* set first edge */ 625fd0310b6SXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 626fd0310b6SXin Ji VIDEO_CONTROL_0, 0x06); 627fd0310b6SXin Ji if (ret < 0) 628fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 629fd0310b6SXin Ji 630fd0310b6SXin Ji return ret; 631fd0310b6SXin Ji } 632fd0310b6SXin Ji 633fd0310b6SXin Ji static int anx7625_dpi_config(struct anx7625_data *ctx) 634fd0310b6SXin Ji { 635fd0310b6SXin Ji struct device *dev = &ctx->client->dev; 636fd0310b6SXin Ji int ret; 637fd0310b6SXin Ji 638fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 639fd0310b6SXin Ji 640fd0310b6SXin Ji /* DSC disable */ 641fd0310b6SXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 642fd0310b6SXin Ji R_DSC_CTRL_0, ~DSC_EN); 643fd0310b6SXin Ji if (ret < 0) { 644fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 645fd0310b6SXin Ji return ret; 646fd0310b6SXin Ji } 647fd0310b6SXin Ji 648fd0310b6SXin Ji ret = anx7625_config_bit_matrix(ctx); 649fd0310b6SXin Ji if (ret < 0) { 650fd0310b6SXin Ji DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 651fd0310b6SXin Ji return ret; 652fd0310b6SXin Ji } 653fd0310b6SXin Ji 654fd0310b6SXin Ji ret = anx7625_api_dpi_config(ctx); 655fd0310b6SXin Ji if (ret < 0) { 656fd0310b6SXin Ji DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 657fd0310b6SXin Ji return ret; 658fd0310b6SXin Ji } 659fd0310b6SXin Ji 660fd0310b6SXin Ji /* set MIPI RX EN */ 661fd0310b6SXin Ji ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 662fd0310b6SXin Ji AP_AV_STATUS, AP_MIPI_RX_EN); 663fd0310b6SXin Ji /* clear mute flag */ 664fd0310b6SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 665fd0310b6SXin Ji AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 666fd0310b6SXin Ji if (ret < 0) 667fd0310b6SXin Ji DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 668fd0310b6SXin Ji 669fd0310b6SXin Ji return ret; 670fd0310b6SXin Ji } 671fd0310b6SXin Ji 6728bdfc5daSXin Ji static void anx7625_dp_start(struct anx7625_data *ctx) 6738bdfc5daSXin Ji { 6748bdfc5daSXin Ji int ret; 6758bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6768bdfc5daSXin Ji 6778bdfc5daSXin Ji if (!ctx->display_timing_valid) { 6788bdfc5daSXin Ji DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 6798bdfc5daSXin Ji return; 6808bdfc5daSXin Ji } 6818bdfc5daSXin Ji 682fd0310b6SXin Ji if (ctx->pdata.is_dpi) 683fd0310b6SXin Ji ret = anx7625_dpi_config(ctx); 684fd0310b6SXin Ji else 6858bdfc5daSXin Ji ret = anx7625_dsi_config(ctx); 6868bdfc5daSXin Ji 6878bdfc5daSXin Ji if (ret < 0) 6888bdfc5daSXin Ji DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 6898bdfc5daSXin Ji } 6908bdfc5daSXin Ji 6918bdfc5daSXin Ji static void anx7625_dp_stop(struct anx7625_data *ctx) 6928bdfc5daSXin Ji { 6938bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 6948bdfc5daSXin Ji int ret; 6958bdfc5daSXin Ji 6968bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 6978bdfc5daSXin Ji 6988bdfc5daSXin Ji /* 6998bdfc5daSXin Ji * Video disable: 0x72:08 bit 7 = 0; 7008bdfc5daSXin Ji * Audio disable: 0x70:87 bit 0 = 0; 7018bdfc5daSXin Ji */ 7028bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 7038bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 7048bdfc5daSXin Ji 7058bdfc5daSXin Ji ret |= anx7625_video_mute_control(ctx, 1); 7068bdfc5daSXin Ji if (ret < 0) 7078bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 7088bdfc5daSXin Ji } 7098bdfc5daSXin Ji 7108bdfc5daSXin Ji static int sp_tx_rst_aux(struct anx7625_data *ctx) 7118bdfc5daSXin Ji { 7128bdfc5daSXin Ji int ret; 7138bdfc5daSXin Ji 7148bdfc5daSXin Ji ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 7158bdfc5daSXin Ji AUX_RST); 7168bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 7178bdfc5daSXin Ji ~AUX_RST); 7188bdfc5daSXin Ji return ret; 7198bdfc5daSXin Ji } 7208bdfc5daSXin Ji 7218bdfc5daSXin Ji static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 7228bdfc5daSXin Ji { 7238bdfc5daSXin Ji int ret; 7248bdfc5daSXin Ji 7258bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7268bdfc5daSXin Ji AP_AUX_BUFF_START, offset); 7278bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7288bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 7298bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 7308bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 7318bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 7328bdfc5daSXin Ji } 7338bdfc5daSXin Ji 7348bdfc5daSXin Ji static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 7358bdfc5daSXin Ji { 7368bdfc5daSXin Ji int ret; 7378bdfc5daSXin Ji 7388bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 7398bdfc5daSXin Ji AP_AUX_COMMAND, len_cmd); 7408bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 7418bdfc5daSXin Ji AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 7428bdfc5daSXin Ji return (ret | wait_aux_op_finish(ctx)); 7438bdfc5daSXin Ji } 7448bdfc5daSXin Ji 7458bdfc5daSXin Ji static int sp_tx_get_edid_block(struct anx7625_data *ctx) 7468bdfc5daSXin Ji { 7478bdfc5daSXin Ji int c = 0; 7488bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 7498bdfc5daSXin Ji 7508bdfc5daSXin Ji sp_tx_aux_wr(ctx, 0x7e); 7518bdfc5daSXin Ji sp_tx_aux_rd(ctx, 0x01); 7528bdfc5daSXin Ji c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 7538bdfc5daSXin Ji if (c < 0) { 7548bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 7558bdfc5daSXin Ji return -EIO; 7568bdfc5daSXin Ji } 7578bdfc5daSXin Ji 7588bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 7598bdfc5daSXin Ji 7608bdfc5daSXin Ji if (c > MAX_EDID_BLOCK) 7618bdfc5daSXin Ji c = 1; 7628bdfc5daSXin Ji 7638bdfc5daSXin Ji return c; 7648bdfc5daSXin Ji } 7658bdfc5daSXin Ji 7668bdfc5daSXin Ji static int edid_read(struct anx7625_data *ctx, 7678bdfc5daSXin Ji u8 offset, u8 *pblock_buf) 7688bdfc5daSXin Ji { 7698bdfc5daSXin Ji int ret, cnt; 7708bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 7718bdfc5daSXin Ji 7728bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 7738bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 7748bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 7758bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 7768bdfc5daSXin Ji 7778bdfc5daSXin Ji if (ret) { 7787f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 7798bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 7808bdfc5daSXin Ji } else { 7818bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 7828bdfc5daSXin Ji AP_AUX_BUFF_START, 7838bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, 7848bdfc5daSXin Ji pblock_buf); 7858bdfc5daSXin Ji if (ret > 0) 7868bdfc5daSXin Ji break; 7878bdfc5daSXin Ji } 7888bdfc5daSXin Ji } 7898bdfc5daSXin Ji 7908bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 7918bdfc5daSXin Ji return -EIO; 7928bdfc5daSXin Ji 7937f16d0f3SRobert Foss return ret; 7948bdfc5daSXin Ji } 7958bdfc5daSXin Ji 7968bdfc5daSXin Ji static int segments_edid_read(struct anx7625_data *ctx, 7978bdfc5daSXin Ji u8 segment, u8 *buf, u8 offset) 7988bdfc5daSXin Ji { 7998bdfc5daSXin Ji u8 cnt; 8008bdfc5daSXin Ji int ret; 8018bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 8028bdfc5daSXin Ji 8038bdfc5daSXin Ji /* Write address only */ 8048bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8058bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x30); 8068bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8078bdfc5daSXin Ji AP_AUX_COMMAND, 0x04); 8088bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8098bdfc5daSXin Ji AP_AUX_CTRL_STATUS, 8108bdfc5daSXin Ji AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 8118bdfc5daSXin Ji 8128bdfc5daSXin Ji ret |= wait_aux_op_finish(ctx); 8138bdfc5daSXin Ji /* Write segment address */ 8148bdfc5daSXin Ji ret |= sp_tx_aux_wr(ctx, segment); 8158bdfc5daSXin Ji /* Data read */ 8168bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8178bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 8188bdfc5daSXin Ji if (ret) { 8198bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 8208bdfc5daSXin Ji return ret; 8218bdfc5daSXin Ji } 8228bdfc5daSXin Ji 8238bdfc5daSXin Ji for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 8248bdfc5daSXin Ji sp_tx_aux_wr(ctx, offset); 8258bdfc5daSXin Ji /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 8268bdfc5daSXin Ji ret = sp_tx_aux_rd(ctx, 0xf1); 8278bdfc5daSXin Ji 8288bdfc5daSXin Ji if (ret) { 8298bdfc5daSXin Ji ret = sp_tx_rst_aux(ctx); 8308bdfc5daSXin Ji DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 8318bdfc5daSXin Ji } else { 8328bdfc5daSXin Ji ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 8338bdfc5daSXin Ji AP_AUX_BUFF_START, 8348bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE, buf); 8358bdfc5daSXin Ji if (ret > 0) 8368bdfc5daSXin Ji break; 8378bdfc5daSXin Ji } 8388bdfc5daSXin Ji } 8398bdfc5daSXin Ji 8408bdfc5daSXin Ji if (cnt > EDID_TRY_CNT) 8418bdfc5daSXin Ji return -EIO; 8428bdfc5daSXin Ji 8437f16d0f3SRobert Foss return ret; 8448bdfc5daSXin Ji } 8458bdfc5daSXin Ji 8468bdfc5daSXin Ji static int sp_tx_edid_read(struct anx7625_data *ctx, 8478bdfc5daSXin Ji u8 *pedid_blocks_buf) 8488bdfc5daSXin Ji { 8498bdfc5daSXin Ji u8 offset, edid_pos; 8508bdfc5daSXin Ji int count, blocks_num; 8518bdfc5daSXin Ji u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 8528bdfc5daSXin Ji u8 i, j; 853*0bae5687SHsin-Yi Wang int g_edid_break = 0; 8548bdfc5daSXin Ji int ret; 8558bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 8568bdfc5daSXin Ji 8578bdfc5daSXin Ji /* Address initial */ 8588bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8598bdfc5daSXin Ji AP_AUX_ADDR_7_0, 0x50); 8608bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 8618bdfc5daSXin Ji AP_AUX_ADDR_15_8, 0); 8628bdfc5daSXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 8638bdfc5daSXin Ji AP_AUX_ADDR_19_16, 0xf0); 8648bdfc5daSXin Ji if (ret < 0) { 8658bdfc5daSXin Ji DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 8668bdfc5daSXin Ji return -EIO; 8678bdfc5daSXin Ji } 8688bdfc5daSXin Ji 8698bdfc5daSXin Ji blocks_num = sp_tx_get_edid_block(ctx); 8708bdfc5daSXin Ji if (blocks_num < 0) 8718bdfc5daSXin Ji return blocks_num; 8728bdfc5daSXin Ji 8738bdfc5daSXin Ji count = 0; 8748bdfc5daSXin Ji 8758bdfc5daSXin Ji do { 8768bdfc5daSXin Ji switch (count) { 8778bdfc5daSXin Ji case 0: 8788bdfc5daSXin Ji case 1: 8798bdfc5daSXin Ji for (i = 0; i < 8; i++) { 8808bdfc5daSXin Ji offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 8818bdfc5daSXin Ji g_edid_break = edid_read(ctx, offset, 8828bdfc5daSXin Ji pblock_buf); 8838bdfc5daSXin Ji 884*0bae5687SHsin-Yi Wang if (g_edid_break < 0) 8858bdfc5daSXin Ji break; 8868bdfc5daSXin Ji 8878bdfc5daSXin Ji memcpy(&pedid_blocks_buf[offset], 8888bdfc5daSXin Ji pblock_buf, 8898bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 8908bdfc5daSXin Ji } 8918bdfc5daSXin Ji 8928bdfc5daSXin Ji break; 8938bdfc5daSXin Ji case 2: 8948bdfc5daSXin Ji offset = 0x00; 8958bdfc5daSXin Ji 8968bdfc5daSXin Ji for (j = 0; j < 8; j++) { 8978bdfc5daSXin Ji edid_pos = (j + count * 8) * 8988bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 8998bdfc5daSXin Ji 9008bdfc5daSXin Ji if (g_edid_break == 1) 9018bdfc5daSXin Ji break; 9028bdfc5daSXin Ji 903a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 9048bdfc5daSXin Ji pblock_buf, offset); 905a23e0a2aSRobert Foss if (ret < 0) 906a23e0a2aSRobert Foss return ret; 907a23e0a2aSRobert Foss 9088bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 9098bdfc5daSXin Ji pblock_buf, 9108bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 9118bdfc5daSXin Ji offset = offset + 0x10; 9128bdfc5daSXin Ji } 9138bdfc5daSXin Ji 9148bdfc5daSXin Ji break; 9158bdfc5daSXin Ji case 3: 9168bdfc5daSXin Ji offset = 0x80; 9178bdfc5daSXin Ji 9188bdfc5daSXin Ji for (j = 0; j < 8; j++) { 9198bdfc5daSXin Ji edid_pos = (j + count * 8) * 9208bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE; 9218bdfc5daSXin Ji if (g_edid_break == 1) 9228bdfc5daSXin Ji break; 9238bdfc5daSXin Ji 924a23e0a2aSRobert Foss ret = segments_edid_read(ctx, count / 2, 9258bdfc5daSXin Ji pblock_buf, offset); 926a23e0a2aSRobert Foss if (ret < 0) 927a23e0a2aSRobert Foss return ret; 928a23e0a2aSRobert Foss 9298bdfc5daSXin Ji memcpy(&pedid_blocks_buf[edid_pos], 9308bdfc5daSXin Ji pblock_buf, 9318bdfc5daSXin Ji MAX_DPCD_BUFFER_SIZE); 9328bdfc5daSXin Ji offset = offset + 0x10; 9338bdfc5daSXin Ji } 9348bdfc5daSXin Ji 9358bdfc5daSXin Ji break; 9368bdfc5daSXin Ji default: 9378bdfc5daSXin Ji break; 9388bdfc5daSXin Ji } 9398bdfc5daSXin Ji 9408bdfc5daSXin Ji count++; 9418bdfc5daSXin Ji 9428bdfc5daSXin Ji } while (blocks_num >= count); 9438bdfc5daSXin Ji 9448bdfc5daSXin Ji /* Check edid data */ 9458bdfc5daSXin Ji if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 9468bdfc5daSXin Ji DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 9478bdfc5daSXin Ji return -EINVAL; 9488bdfc5daSXin Ji } 9498bdfc5daSXin Ji 9508bdfc5daSXin Ji /* Reset aux channel */ 9517f16d0f3SRobert Foss ret = sp_tx_rst_aux(ctx); 9527f16d0f3SRobert Foss if (ret < 0) { 9537f16d0f3SRobert Foss DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 9547f16d0f3SRobert Foss return ret; 9557f16d0f3SRobert Foss } 9568bdfc5daSXin Ji 9578bdfc5daSXin Ji return (blocks_num + 1); 9588bdfc5daSXin Ji } 9598bdfc5daSXin Ji 9608bdfc5daSXin Ji static void anx7625_power_on(struct anx7625_data *ctx) 9618bdfc5daSXin Ji { 9628bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9636c744983SHsin-Yi Wang int ret, i; 9648bdfc5daSXin Ji 9658bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 9668bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 9678bdfc5daSXin Ji return; 9688bdfc5daSXin Ji } 9698bdfc5daSXin Ji 9706c744983SHsin-Yi Wang for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 9716c744983SHsin-Yi Wang ret = regulator_enable(ctx->pdata.supplies[i].consumer); 9726c744983SHsin-Yi Wang if (ret < 0) { 9736c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 9746c744983SHsin-Yi Wang i, ret); 9756c744983SHsin-Yi Wang goto reg_err; 9766c744983SHsin-Yi Wang } 9776c744983SHsin-Yi Wang usleep_range(2000, 2100); 9786c744983SHsin-Yi Wang } 9796c744983SHsin-Yi Wang 9801fcf24fbSHsin-Yi Wang usleep_range(11000, 12000); 9816c744983SHsin-Yi Wang 9828bdfc5daSXin Ji /* Power on pin enable */ 9838bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 1); 9848bdfc5daSXin Ji usleep_range(10000, 11000); 9858bdfc5daSXin Ji /* Power reset pin enable */ 9868bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 1); 9878bdfc5daSXin Ji usleep_range(10000, 11000); 9888bdfc5daSXin Ji 9898bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 9906c744983SHsin-Yi Wang return; 9916c744983SHsin-Yi Wang reg_err: 9926c744983SHsin-Yi Wang for (--i; i >= 0; i--) 9936c744983SHsin-Yi Wang regulator_disable(ctx->pdata.supplies[i].consumer); 9948bdfc5daSXin Ji } 9958bdfc5daSXin Ji 9968bdfc5daSXin Ji static void anx7625_power_standby(struct anx7625_data *ctx) 9978bdfc5daSXin Ji { 9988bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 9996c744983SHsin-Yi Wang int ret; 10008bdfc5daSXin Ji 10018bdfc5daSXin Ji if (!ctx->pdata.low_power_mode) { 10028bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 10038bdfc5daSXin Ji return; 10048bdfc5daSXin Ji } 10058bdfc5daSXin Ji 10068bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_reset, 0); 10078bdfc5daSXin Ji usleep_range(1000, 1100); 10088bdfc5daSXin Ji gpiod_set_value(ctx->pdata.gpio_p_on, 0); 10098bdfc5daSXin Ji usleep_range(1000, 1100); 10106c744983SHsin-Yi Wang 10116c744983SHsin-Yi Wang ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 10126c744983SHsin-Yi Wang ctx->pdata.supplies); 10136c744983SHsin-Yi Wang if (ret < 0) 10146c744983SHsin-Yi Wang DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 10156c744983SHsin-Yi Wang 10168bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 10178bdfc5daSXin Ji } 10188bdfc5daSXin Ji 10198bdfc5daSXin Ji /* Basic configurations of ANX7625 */ 10208bdfc5daSXin Ji static void anx7625_config(struct anx7625_data *ctx) 10218bdfc5daSXin Ji { 10228bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10238bdfc5daSXin Ji XTAL_FRQ_SEL, XTAL_FRQ_27M); 10248bdfc5daSXin Ji } 10258bdfc5daSXin Ji 10268bdfc5daSXin Ji static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 10278bdfc5daSXin Ji { 10288bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10298bdfc5daSXin Ji int ret; 10308bdfc5daSXin Ji 10318bdfc5daSXin Ji /* Reset main ocm */ 10328bdfc5daSXin Ji ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 10338bdfc5daSXin Ji /* Disable PD */ 10348bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 10358bdfc5daSXin Ji AP_AV_STATUS, AP_DISABLE_PD); 10368bdfc5daSXin Ji /* Release main ocm */ 10378bdfc5daSXin Ji ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 10388bdfc5daSXin Ji 10398bdfc5daSXin Ji if (ret < 0) 10408bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 10418bdfc5daSXin Ji else 10428bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 10438bdfc5daSXin Ji } 10448bdfc5daSXin Ji 10458bdfc5daSXin Ji static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 10468bdfc5daSXin Ji { 10478bdfc5daSXin Ji int ret; 10488bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 10498bdfc5daSXin Ji 10508bdfc5daSXin Ji /* Check interface workable */ 10518bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 10528bdfc5daSXin Ji FLASH_LOAD_STA); 10538bdfc5daSXin Ji if (ret < 0) { 10548bdfc5daSXin Ji DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 10558bdfc5daSXin Ji return ret; 10568bdfc5daSXin Ji } 10578bdfc5daSXin Ji if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 10588bdfc5daSXin Ji return -ENODEV; 10598bdfc5daSXin Ji 10608bdfc5daSXin Ji anx7625_disable_pd_protocol(ctx); 10618bdfc5daSXin Ji 10628bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 10638bdfc5daSXin Ji anx7625_reg_read(ctx, 10648bdfc5daSXin Ji ctx->i2c.rx_p0_client, 10658bdfc5daSXin Ji OCM_FW_VERSION), 10668bdfc5daSXin Ji anx7625_reg_read(ctx, 10678bdfc5daSXin Ji ctx->i2c.rx_p0_client, 10688bdfc5daSXin Ji OCM_FW_REVERSION)); 10698bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 10708bdfc5daSXin Ji ANX7625_DRV_VERSION); 10718bdfc5daSXin Ji 10728bdfc5daSXin Ji return 0; 10738bdfc5daSXin Ji } 10748bdfc5daSXin Ji 10758bdfc5daSXin Ji static void anx7625_power_on_init(struct anx7625_data *ctx) 10768bdfc5daSXin Ji { 10778bdfc5daSXin Ji int retry_count, i; 10788bdfc5daSXin Ji 10798bdfc5daSXin Ji for (retry_count = 0; retry_count < 3; retry_count++) { 10808bdfc5daSXin Ji anx7625_power_on(ctx); 10818bdfc5daSXin Ji anx7625_config(ctx); 10828bdfc5daSXin Ji 10838bdfc5daSXin Ji for (i = 0; i < OCM_LOADING_TIME; i++) { 10848bdfc5daSXin Ji if (!anx7625_ocm_loading_check(ctx)) 10858bdfc5daSXin Ji return; 10868bdfc5daSXin Ji usleep_range(1000, 1100); 10878bdfc5daSXin Ji } 10888bdfc5daSXin Ji anx7625_power_standby(ctx); 10898bdfc5daSXin Ji } 10908bdfc5daSXin Ji } 10918bdfc5daSXin Ji 10928bdfc5daSXin Ji static void anx7625_init_gpio(struct anx7625_data *platform) 10938bdfc5daSXin Ji { 10948bdfc5daSXin Ji struct device *dev = &platform->client->dev; 10958bdfc5daSXin Ji 10968bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 10978bdfc5daSXin Ji 10988bdfc5daSXin Ji /* Gpio for chip power enable */ 10998bdfc5daSXin Ji platform->pdata.gpio_p_on = 11008bdfc5daSXin Ji devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 11018bdfc5daSXin Ji /* Gpio for chip reset */ 11028bdfc5daSXin Ji platform->pdata.gpio_reset = 11038bdfc5daSXin Ji devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 11048bdfc5daSXin Ji 11058bdfc5daSXin Ji if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 11068bdfc5daSXin Ji platform->pdata.low_power_mode = 1; 11078bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 11088bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_p_on), 11098bdfc5daSXin Ji desc_to_gpio(platform->pdata.gpio_reset)); 11108bdfc5daSXin Ji } else { 11118bdfc5daSXin Ji platform->pdata.low_power_mode = 0; 11128bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 11138bdfc5daSXin Ji } 11148bdfc5daSXin Ji } 11158bdfc5daSXin Ji 11168bdfc5daSXin Ji static void anx7625_stop_dp_work(struct anx7625_data *ctx) 11178bdfc5daSXin Ji { 11188bdfc5daSXin Ji ctx->hpd_status = 0; 11198bdfc5daSXin Ji ctx->hpd_high_cnt = 0; 11208bdfc5daSXin Ji ctx->display_timing_valid = 0; 11218bdfc5daSXin Ji } 11228bdfc5daSXin Ji 11238bdfc5daSXin Ji static void anx7625_start_dp_work(struct anx7625_data *ctx) 11248bdfc5daSXin Ji { 11258bdfc5daSXin Ji int ret; 11268bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11278bdfc5daSXin Ji 11288bdfc5daSXin Ji if (ctx->hpd_high_cnt >= 2) { 11298bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 11308bdfc5daSXin Ji return; 11318bdfc5daSXin Ji } 11328bdfc5daSXin Ji 1133fd0310b6SXin Ji ctx->hpd_status = 1; 11348bdfc5daSXin Ji ctx->hpd_high_cnt++; 11358bdfc5daSXin Ji 11368bdfc5daSXin Ji /* Not support HDCP */ 11378bdfc5daSXin Ji ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 11388bdfc5daSXin Ji 11398bdfc5daSXin Ji /* Try auth flag */ 11408bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 11418bdfc5daSXin Ji /* Interrupt for DRM */ 11428bdfc5daSXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1143fd0310b6SXin Ji if (ret < 0) { 1144fd0310b6SXin Ji DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 11458bdfc5daSXin Ji return; 1146fd0310b6SXin Ji } 11478bdfc5daSXin Ji 11488bdfc5daSXin Ji ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 11498bdfc5daSXin Ji if (ret < 0) 11508bdfc5daSXin Ji return; 11518bdfc5daSXin Ji 11528bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 11538bdfc5daSXin Ji } 11548bdfc5daSXin Ji 11558bdfc5daSXin Ji static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 11568bdfc5daSXin Ji { 11578bdfc5daSXin Ji return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 11588bdfc5daSXin Ji } 11598bdfc5daSXin Ji 11608bdfc5daSXin Ji static void anx7625_hpd_polling(struct anx7625_data *ctx) 11618bdfc5daSXin Ji { 11628bdfc5daSXin Ji int ret, val; 11638bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 11648bdfc5daSXin Ji 1165fd0310b6SXin Ji /* Interrupt mode, no need poll HPD status, just return */ 1166fd0310b6SXin Ji if (ctx->pdata.intp_irq) 1167fd0310b6SXin Ji return; 1168fd0310b6SXin Ji 11698bdfc5daSXin Ji ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 11708bdfc5daSXin Ji ctx, val, 11718bdfc5daSXin Ji ((val & HPD_STATUS) || (val < 0)), 11728bdfc5daSXin Ji 5000, 11738bdfc5daSXin Ji 5000 * 100); 11748bdfc5daSXin Ji if (ret) { 117560487584SPi-Hsun Shih DRM_DEV_ERROR(dev, "no hpd.\n"); 117660487584SPi-Hsun Shih return; 117760487584SPi-Hsun Shih } 117860487584SPi-Hsun Shih 117960487584SPi-Hsun Shih DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 11808bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 11818bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 11828bdfc5daSXin Ji anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 11838bdfc5daSXin Ji INTERFACE_CHANGE_INT, 0); 11848bdfc5daSXin Ji 11858bdfc5daSXin Ji anx7625_start_dp_work(ctx); 11868bdfc5daSXin Ji 118760487584SPi-Hsun Shih if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 118860487584SPi-Hsun Shih drm_helper_hpd_irq_event(ctx->bridge.dev); 11898bdfc5daSXin Ji } 11908bdfc5daSXin Ji 11918bdfc5daSXin Ji static void anx7625_remove_edid(struct anx7625_data *ctx) 11928bdfc5daSXin Ji { 11938bdfc5daSXin Ji ctx->slimport_edid_p.edid_block_num = -1; 11948bdfc5daSXin Ji } 11958bdfc5daSXin Ji 1196fd0310b6SXin Ji static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1197fd0310b6SXin Ji { 1198fd0310b6SXin Ji int i; 1199fd0310b6SXin Ji 1200fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1201fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1202fd0310b6SXin Ji DP_TX_LANE0_SWING_REG0 + i, 1203fd0310b6SXin Ji ctx->pdata.lane0_reg_data[i] & 0xFF); 1204fd0310b6SXin Ji 1205fd0310b6SXin Ji for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1206fd0310b6SXin Ji anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1207fd0310b6SXin Ji DP_TX_LANE1_SWING_REG0 + i, 1208fd0310b6SXin Ji ctx->pdata.lane1_reg_data[i] & 0xFF); 1209fd0310b6SXin Ji } 1210fd0310b6SXin Ji 12118bdfc5daSXin Ji static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 12128bdfc5daSXin Ji { 12138bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12148bdfc5daSXin Ji 12158bdfc5daSXin Ji /* HPD changed */ 12168bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 12178bdfc5daSXin Ji (u32)on); 12188bdfc5daSXin Ji 12198bdfc5daSXin Ji if (on == 0) { 12208bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 12218bdfc5daSXin Ji anx7625_remove_edid(ctx); 12228bdfc5daSXin Ji anx7625_stop_dp_work(ctx); 12238bdfc5daSXin Ji } else { 12248bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 12258bdfc5daSXin Ji anx7625_start_dp_work(ctx); 1226fd0310b6SXin Ji anx7625_dp_adjust_swing(ctx); 12278bdfc5daSXin Ji } 12288bdfc5daSXin Ji } 12298bdfc5daSXin Ji 12308bdfc5daSXin Ji static int anx7625_hpd_change_detect(struct anx7625_data *ctx) 12318bdfc5daSXin Ji { 12328bdfc5daSXin Ji int intr_vector, status; 12338bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 12348bdfc5daSXin Ji 12358bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 12368bdfc5daSXin Ji INTR_ALERT_1, 0xFF); 12378bdfc5daSXin Ji if (status < 0) { 12388bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 12398bdfc5daSXin Ji return status; 12408bdfc5daSXin Ji } 12418bdfc5daSXin Ji 12428bdfc5daSXin Ji intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 12438bdfc5daSXin Ji INTERFACE_CHANGE_INT); 12448bdfc5daSXin Ji if (intr_vector < 0) { 12458bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 12468bdfc5daSXin Ji return intr_vector; 12478bdfc5daSXin Ji } 12488bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 12498bdfc5daSXin Ji status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 12508bdfc5daSXin Ji INTERFACE_CHANGE_INT, 12518bdfc5daSXin Ji intr_vector & (~intr_vector)); 12528bdfc5daSXin Ji if (status < 0) { 12538bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 12548bdfc5daSXin Ji return status; 12558bdfc5daSXin Ji } 12568bdfc5daSXin Ji 12578bdfc5daSXin Ji if (!(intr_vector & HPD_STATUS_CHANGE)) 12588bdfc5daSXin Ji return -ENOENT; 12598bdfc5daSXin Ji 12608bdfc5daSXin Ji status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 12618bdfc5daSXin Ji SYSTEM_STSTUS); 12628bdfc5daSXin Ji if (status < 0) { 12638bdfc5daSXin Ji DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 12648bdfc5daSXin Ji return status; 12658bdfc5daSXin Ji } 12668bdfc5daSXin Ji 12678bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 12688bdfc5daSXin Ji dp_hpd_change_handler(ctx, status & HPD_STATUS); 12698bdfc5daSXin Ji 12708bdfc5daSXin Ji return 0; 12718bdfc5daSXin Ji } 12728bdfc5daSXin Ji 12738bdfc5daSXin Ji static void anx7625_work_func(struct work_struct *work) 12748bdfc5daSXin Ji { 12758bdfc5daSXin Ji int event; 12768bdfc5daSXin Ji struct anx7625_data *ctx = container_of(work, 12778bdfc5daSXin Ji struct anx7625_data, work); 12788bdfc5daSXin Ji 12798bdfc5daSXin Ji mutex_lock(&ctx->lock); 128060487584SPi-Hsun Shih 128160487584SPi-Hsun Shih if (pm_runtime_suspended(&ctx->client->dev)) 128260487584SPi-Hsun Shih goto unlock; 128360487584SPi-Hsun Shih 12848bdfc5daSXin Ji event = anx7625_hpd_change_detect(ctx); 12858bdfc5daSXin Ji if (event < 0) 128660487584SPi-Hsun Shih goto unlock; 12878bdfc5daSXin Ji 12888bdfc5daSXin Ji if (ctx->bridge_attached) 12898bdfc5daSXin Ji drm_helper_hpd_irq_event(ctx->bridge.dev); 129060487584SPi-Hsun Shih 129160487584SPi-Hsun Shih unlock: 129260487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 12938bdfc5daSXin Ji } 12948bdfc5daSXin Ji 12958bdfc5daSXin Ji static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 12968bdfc5daSXin Ji { 12978bdfc5daSXin Ji struct anx7625_data *ctx = (struct anx7625_data *)data; 12988bdfc5daSXin Ji 12998bdfc5daSXin Ji queue_work(ctx->workqueue, &ctx->work); 13008bdfc5daSXin Ji 13018bdfc5daSXin Ji return IRQ_HANDLED; 13028bdfc5daSXin Ji } 13038bdfc5daSXin Ji 1304fd0310b6SXin Ji static int anx7625_get_swing_setting(struct device *dev, 1305fd0310b6SXin Ji struct anx7625_platform_data *pdata) 1306fd0310b6SXin Ji { 1307fd0310b6SXin Ji int num_regs; 1308fd0310b6SXin Ji 1309fd0310b6SXin Ji if (of_get_property(dev->of_node, 1310fd0310b6SXin Ji "analogix,lane0-swing", &num_regs)) { 1311fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1312fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1313fd0310b6SXin Ji 1314fd0310b6SXin Ji pdata->dp_lane0_swing_reg_cnt = num_regs; 1315fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane0-swing", 1316fd0310b6SXin Ji pdata->lane0_reg_data, num_regs); 1317fd0310b6SXin Ji } 1318fd0310b6SXin Ji 1319fd0310b6SXin Ji if (of_get_property(dev->of_node, 1320fd0310b6SXin Ji "analogix,lane1-swing", &num_regs)) { 1321fd0310b6SXin Ji if (num_regs > DP_TX_SWING_REG_CNT) 1322fd0310b6SXin Ji num_regs = DP_TX_SWING_REG_CNT; 1323fd0310b6SXin Ji 1324fd0310b6SXin Ji pdata->dp_lane1_swing_reg_cnt = num_regs; 1325fd0310b6SXin Ji of_property_read_u32_array(dev->of_node, "analogix,lane1-swing", 1326fd0310b6SXin Ji pdata->lane1_reg_data, num_regs); 1327fd0310b6SXin Ji } 1328fd0310b6SXin Ji 1329fd0310b6SXin Ji return 0; 1330fd0310b6SXin Ji } 1331fd0310b6SXin Ji 13328bdfc5daSXin Ji static int anx7625_parse_dt(struct device *dev, 13338bdfc5daSXin Ji struct anx7625_platform_data *pdata) 13348bdfc5daSXin Ji { 1335fd0310b6SXin Ji struct device_node *np = dev->of_node, *ep0; 13368bdfc5daSXin Ji struct drm_panel *panel; 13378bdfc5daSXin Ji int ret; 1338fd0310b6SXin Ji int bus_type, mipi_lanes; 13398bdfc5daSXin Ji 1340fd0310b6SXin Ji anx7625_get_swing_setting(dev, pdata); 1341fd0310b6SXin Ji 1342fd0310b6SXin Ji pdata->is_dpi = 1; /* default dpi mode */ 13438bdfc5daSXin Ji pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 13448bdfc5daSXin Ji if (!pdata->mipi_host_node) { 13458bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 13468bdfc5daSXin Ji return -ENODEV; 13478bdfc5daSXin Ji } 13488bdfc5daSXin Ji 1349fd0310b6SXin Ji bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL; 1350fd0310b6SXin Ji mipi_lanes = MAX_LANES_SUPPORT; 1351fd0310b6SXin Ji ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1352fd0310b6SXin Ji if (ep0) { 1353fd0310b6SXin Ji if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1354fd0310b6SXin Ji bus_type = 0; 1355fd0310b6SXin Ji 1356fd0310b6SXin Ji mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes"); 1357fd0310b6SXin Ji } 1358fd0310b6SXin Ji 1359fd0310b6SXin Ji if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */ 1360fd0310b6SXin Ji pdata->is_dpi = 0; 1361fd0310b6SXin Ji 1362fd0310b6SXin Ji pdata->mipi_lanes = mipi_lanes; 1363fd0310b6SXin Ji if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0) 1364fd0310b6SXin Ji pdata->mipi_lanes = MAX_LANES_SUPPORT; 1365fd0310b6SXin Ji 1366fd0310b6SXin Ji if (pdata->is_dpi) 1367fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1368fd0310b6SXin Ji else 1369fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 13708bdfc5daSXin Ji 1371566fef12SXin Ji if (of_property_read_bool(np, "analogix,audio-enable")) 1372566fef12SXin Ji pdata->audio_en = 1; 1373566fef12SXin Ji 13748bdfc5daSXin Ji ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); 13758bdfc5daSXin Ji if (ret < 0) { 13768bdfc5daSXin Ji if (ret == -ENODEV) 13778bdfc5daSXin Ji return 0; 13788bdfc5daSXin Ji return ret; 13798bdfc5daSXin Ji } 13808bdfc5daSXin Ji if (!panel) 13818bdfc5daSXin Ji return -ENODEV; 13828bdfc5daSXin Ji 13838bdfc5daSXin Ji pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 13848bdfc5daSXin Ji if (IS_ERR(pdata->panel_bridge)) 13858bdfc5daSXin Ji return PTR_ERR(pdata->panel_bridge); 13868bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 13878bdfc5daSXin Ji 13888bdfc5daSXin Ji return 0; 13898bdfc5daSXin Ji } 13908bdfc5daSXin Ji 13918bdfc5daSXin Ji static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 13928bdfc5daSXin Ji { 13938bdfc5daSXin Ji return container_of(bridge, struct anx7625_data, bridge); 13948bdfc5daSXin Ji } 13958bdfc5daSXin Ji 13968bdfc5daSXin Ji static struct edid *anx7625_get_edid(struct anx7625_data *ctx) 13978bdfc5daSXin Ji { 13988bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 13998bdfc5daSXin Ji struct s_edid_data *p_edid = &ctx->slimport_edid_p; 14008bdfc5daSXin Ji int edid_num; 14018bdfc5daSXin Ji u8 *edid; 14028bdfc5daSXin Ji 14038bdfc5daSXin Ji edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 14048bdfc5daSXin Ji if (!edid) { 14058bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to allocate buffer\n"); 14068bdfc5daSXin Ji return NULL; 14078bdfc5daSXin Ji } 14088bdfc5daSXin Ji 14098bdfc5daSXin Ji if (ctx->slimport_edid_p.edid_block_num > 0) { 14108bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, 14118bdfc5daSXin Ji FOUR_BLOCK_SIZE); 14128bdfc5daSXin Ji return (struct edid *)edid; 14138bdfc5daSXin Ji } 14148bdfc5daSXin Ji 141560487584SPi-Hsun Shih pm_runtime_get_sync(dev); 14168bdfc5daSXin Ji edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data); 14173203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 14188bdfc5daSXin Ji 14198bdfc5daSXin Ji if (edid_num < 1) { 14208bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 14218bdfc5daSXin Ji kfree(edid); 14228bdfc5daSXin Ji return NULL; 14238bdfc5daSXin Ji } 14248bdfc5daSXin Ji 14258bdfc5daSXin Ji p_edid->edid_block_num = edid_num; 14268bdfc5daSXin Ji 14278bdfc5daSXin Ji memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE); 14288bdfc5daSXin Ji return (struct edid *)edid; 14298bdfc5daSXin Ji } 14308bdfc5daSXin Ji 14318bdfc5daSXin Ji static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 14328bdfc5daSXin Ji { 14338bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 14348bdfc5daSXin Ji 1435fd0310b6SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 14368bdfc5daSXin Ji 1437fd0310b6SXin Ji if (ctx->pdata.panel_bridge) 14388bdfc5daSXin Ji return connector_status_connected; 1439fd0310b6SXin Ji 1440fd0310b6SXin Ji return ctx->hpd_status ? connector_status_connected : 1441fd0310b6SXin Ji connector_status_disconnected; 14428bdfc5daSXin Ji } 14438bdfc5daSXin Ji 1444566fef12SXin Ji static int anx7625_audio_hw_params(struct device *dev, void *data, 1445566fef12SXin Ji struct hdmi_codec_daifmt *fmt, 1446566fef12SXin Ji struct hdmi_codec_params *params) 1447566fef12SXin Ji { 1448566fef12SXin Ji struct anx7625_data *ctx = dev_get_drvdata(dev); 1449566fef12SXin Ji int wl, ch, rate; 1450566fef12SXin Ji int ret = 0; 1451566fef12SXin Ji 1452566fef12SXin Ji if (fmt->fmt != HDMI_DSP_A) { 1453566fef12SXin Ji DRM_DEV_ERROR(dev, "only supports DSP_A\n"); 1454566fef12SXin Ji return -EINVAL; 1455566fef12SXin Ji } 1456566fef12SXin Ji 1457566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 1458566fef12SXin Ji params->sample_rate, params->sample_width, 1459566fef12SXin Ji params->cea.channels); 1460566fef12SXin Ji 1461566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1462566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 1463566fef12SXin Ji ~I2S_SLAVE_MODE, 1464566fef12SXin Ji TDM_SLAVE_MODE); 1465566fef12SXin Ji 1466566fef12SXin Ji /* Word length */ 1467566fef12SXin Ji switch (params->sample_width) { 1468566fef12SXin Ji case 16: 1469566fef12SXin Ji wl = AUDIO_W_LEN_16_20MAX; 1470566fef12SXin Ji break; 1471566fef12SXin Ji case 18: 1472566fef12SXin Ji wl = AUDIO_W_LEN_18_20MAX; 1473566fef12SXin Ji break; 1474566fef12SXin Ji case 20: 1475566fef12SXin Ji wl = AUDIO_W_LEN_20_20MAX; 1476566fef12SXin Ji break; 1477566fef12SXin Ji case 24: 1478566fef12SXin Ji wl = AUDIO_W_LEN_24_24MAX; 1479566fef12SXin Ji break; 1480566fef12SXin Ji default: 1481566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 1482566fef12SXin Ji params->sample_width); 1483566fef12SXin Ji return -EINVAL; 1484566fef12SXin Ji } 1485566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1486566fef12SXin Ji AUDIO_CHANNEL_STATUS_5, 1487566fef12SXin Ji 0xf0, wl); 1488566fef12SXin Ji 1489566fef12SXin Ji /* Channel num */ 1490566fef12SXin Ji switch (params->cea.channels) { 1491566fef12SXin Ji case 2: 1492566fef12SXin Ji ch = I2S_CH_2; 1493566fef12SXin Ji break; 1494566fef12SXin Ji case 4: 1495566fef12SXin Ji ch = TDM_CH_4; 1496566fef12SXin Ji break; 1497566fef12SXin Ji case 6: 1498566fef12SXin Ji ch = TDM_CH_6; 1499566fef12SXin Ji break; 1500566fef12SXin Ji case 8: 1501566fef12SXin Ji ch = TDM_CH_8; 1502566fef12SXin Ji break; 1503566fef12SXin Ji default: 1504566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 1505566fef12SXin Ji params->cea.channels); 1506566fef12SXin Ji return -EINVAL; 1507566fef12SXin Ji } 1508566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1509566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 1510566fef12SXin Ji if (ch > I2S_CH_2) 1511566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 1512566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 1513566fef12SXin Ji else 1514566fef12SXin Ji ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 1515566fef12SXin Ji AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 1516566fef12SXin Ji 1517566fef12SXin Ji /* FS */ 1518566fef12SXin Ji switch (params->sample_rate) { 1519566fef12SXin Ji case 32000: 1520566fef12SXin Ji rate = AUDIO_FS_32K; 1521566fef12SXin Ji break; 1522566fef12SXin Ji case 44100: 1523566fef12SXin Ji rate = AUDIO_FS_441K; 1524566fef12SXin Ji break; 1525566fef12SXin Ji case 48000: 1526566fef12SXin Ji rate = AUDIO_FS_48K; 1527566fef12SXin Ji break; 1528566fef12SXin Ji case 88200: 1529566fef12SXin Ji rate = AUDIO_FS_882K; 1530566fef12SXin Ji break; 1531566fef12SXin Ji case 96000: 1532566fef12SXin Ji rate = AUDIO_FS_96K; 1533566fef12SXin Ji break; 1534566fef12SXin Ji case 176400: 1535566fef12SXin Ji rate = AUDIO_FS_1764K; 1536566fef12SXin Ji break; 1537566fef12SXin Ji case 192000: 1538566fef12SXin Ji rate = AUDIO_FS_192K; 1539566fef12SXin Ji break; 1540566fef12SXin Ji default: 1541566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 1542566fef12SXin Ji params->sample_rate); 1543566fef12SXin Ji return -EINVAL; 1544566fef12SXin Ji } 1545566fef12SXin Ji ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 1546566fef12SXin Ji AUDIO_CHANNEL_STATUS_4, 1547566fef12SXin Ji 0xf0, rate); 1548566fef12SXin Ji ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1549566fef12SXin Ji AP_AV_STATUS, AP_AUDIO_CHG); 1550566fef12SXin Ji if (ret < 0) { 1551566fef12SXin Ji DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 1552566fef12SXin Ji return -EIO; 1553566fef12SXin Ji } 1554566fef12SXin Ji 1555566fef12SXin Ji return 0; 1556566fef12SXin Ji } 1557566fef12SXin Ji 1558566fef12SXin Ji static void anx7625_audio_shutdown(struct device *dev, void *data) 1559566fef12SXin Ji { 1560566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 1561566fef12SXin Ji } 1562566fef12SXin Ji 1563566fef12SXin Ji static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 1564566fef12SXin Ji struct device_node *endpoint) 1565566fef12SXin Ji { 1566566fef12SXin Ji struct of_endpoint of_ep; 1567566fef12SXin Ji int ret; 1568566fef12SXin Ji 1569566fef12SXin Ji ret = of_graph_parse_endpoint(endpoint, &of_ep); 1570566fef12SXin Ji if (ret < 0) 1571566fef12SXin Ji return ret; 1572566fef12SXin Ji 1573566fef12SXin Ji /* 1574566fef12SXin Ji * HDMI sound should be located at external DPI port 1575566fef12SXin Ji * Didn't have good way to check where is internal(DSI) 1576566fef12SXin Ji * or external(DPI) bridge 1577566fef12SXin Ji */ 1578566fef12SXin Ji return 0; 1579566fef12SXin Ji } 1580566fef12SXin Ji 1581566fef12SXin Ji static void 1582566fef12SXin Ji anx7625_audio_update_connector_status(struct anx7625_data *ctx, 1583566fef12SXin Ji enum drm_connector_status status) 1584566fef12SXin Ji { 1585566fef12SXin Ji if (ctx->plugged_cb && ctx->codec_dev) { 1586566fef12SXin Ji ctx->plugged_cb(ctx->codec_dev, 1587566fef12SXin Ji status == connector_status_connected); 1588566fef12SXin Ji } 1589566fef12SXin Ji } 1590566fef12SXin Ji 1591566fef12SXin Ji static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 1592566fef12SXin Ji hdmi_codec_plugged_cb fn, 1593566fef12SXin Ji struct device *codec_dev) 1594566fef12SXin Ji { 1595566fef12SXin Ji struct anx7625_data *ctx = data; 1596566fef12SXin Ji 1597566fef12SXin Ji ctx->plugged_cb = fn; 1598566fef12SXin Ji ctx->codec_dev = codec_dev; 1599566fef12SXin Ji anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 1600566fef12SXin Ji 1601566fef12SXin Ji return 0; 1602566fef12SXin Ji } 1603566fef12SXin Ji 1604566fef12SXin Ji static const struct hdmi_codec_ops anx7625_codec_ops = { 1605566fef12SXin Ji .hw_params = anx7625_audio_hw_params, 1606566fef12SXin Ji .audio_shutdown = anx7625_audio_shutdown, 1607566fef12SXin Ji .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 1608566fef12SXin Ji .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 1609566fef12SXin Ji }; 1610566fef12SXin Ji 1611566fef12SXin Ji static void anx7625_unregister_audio(struct anx7625_data *ctx) 1612566fef12SXin Ji { 1613566fef12SXin Ji struct device *dev = &ctx->client->dev; 1614566fef12SXin Ji 1615566fef12SXin Ji if (ctx->audio_pdev) { 1616566fef12SXin Ji platform_device_unregister(ctx->audio_pdev); 1617566fef12SXin Ji ctx->audio_pdev = NULL; 1618566fef12SXin Ji } 1619566fef12SXin Ji 1620566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 1621566fef12SXin Ji } 1622566fef12SXin Ji 1623566fef12SXin Ji static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 1624566fef12SXin Ji { 1625566fef12SXin Ji struct hdmi_codec_pdata codec_data = { 1626566fef12SXin Ji .ops = &anx7625_codec_ops, 1627566fef12SXin Ji .max_i2s_channels = 8, 1628566fef12SXin Ji .i2s = 1, 1629566fef12SXin Ji .data = ctx, 1630566fef12SXin Ji }; 1631566fef12SXin Ji 1632566fef12SXin Ji ctx->audio_pdev = platform_device_register_data(dev, 1633566fef12SXin Ji HDMI_CODEC_DRV_NAME, 1634566fef12SXin Ji PLATFORM_DEVID_AUTO, 1635566fef12SXin Ji &codec_data, 1636566fef12SXin Ji sizeof(codec_data)); 1637566fef12SXin Ji 1638566fef12SXin Ji if (IS_ERR(ctx->audio_pdev)) 1639566fef12SXin Ji return IS_ERR(ctx->audio_pdev); 1640566fef12SXin Ji 1641566fef12SXin Ji DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 1642566fef12SXin Ji 1643566fef12SXin Ji return 0; 1644566fef12SXin Ji } 1645566fef12SXin Ji 16468bdfc5daSXin Ji static int anx7625_attach_dsi(struct anx7625_data *ctx) 16478bdfc5daSXin Ji { 16488bdfc5daSXin Ji struct mipi_dsi_device *dsi; 16498bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 16508bdfc5daSXin Ji struct mipi_dsi_host *host; 16518bdfc5daSXin Ji const struct mipi_dsi_device_info info = { 16528bdfc5daSXin Ji .type = "anx7625", 16538bdfc5daSXin Ji .channel = 0, 16548bdfc5daSXin Ji .node = NULL, 16558bdfc5daSXin Ji }; 165625a390a9SMaxime Ripard int ret; 16578bdfc5daSXin Ji 16588bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 16598bdfc5daSXin Ji 16608bdfc5daSXin Ji host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 16618bdfc5daSXin Ji if (!host) { 16628bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to find dsi host.\n"); 16638bdfc5daSXin Ji return -EINVAL; 16648bdfc5daSXin Ji } 16658bdfc5daSXin Ji 166625a390a9SMaxime Ripard dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 16678bdfc5daSXin Ji if (IS_ERR(dsi)) { 16688bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 16698bdfc5daSXin Ji return -EINVAL; 16708bdfc5daSXin Ji } 16718bdfc5daSXin Ji 1672fd0310b6SXin Ji dsi->lanes = ctx->pdata.mipi_lanes; 16738bdfc5daSXin Ji dsi->format = MIPI_DSI_FMT_RGB888; 16748bdfc5daSXin Ji dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 16758bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 16768bdfc5daSXin Ji MIPI_DSI_MODE_VIDEO_HSE; 16778bdfc5daSXin Ji 167825a390a9SMaxime Ripard ret = devm_mipi_dsi_attach(dev, dsi); 167925a390a9SMaxime Ripard if (ret) { 16808bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 168125a390a9SMaxime Ripard return ret; 16828bdfc5daSXin Ji } 16838bdfc5daSXin Ji 16848bdfc5daSXin Ji ctx->dsi = dsi; 16858bdfc5daSXin Ji 16868bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 16878bdfc5daSXin Ji 16888bdfc5daSXin Ji return 0; 16898bdfc5daSXin Ji } 16908bdfc5daSXin Ji 16918bdfc5daSXin Ji static int anx7625_bridge_attach(struct drm_bridge *bridge, 16928bdfc5daSXin Ji enum drm_bridge_attach_flags flags) 16938bdfc5daSXin Ji { 16948bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 16958bdfc5daSXin Ji int err; 16968bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 16978bdfc5daSXin Ji 16988bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 16998bdfc5daSXin Ji if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 17008bdfc5daSXin Ji return -EINVAL; 17018bdfc5daSXin Ji 17028bdfc5daSXin Ji if (!bridge->encoder) { 17038bdfc5daSXin Ji DRM_DEV_ERROR(dev, "Parent encoder object not found"); 17048bdfc5daSXin Ji return -ENODEV; 17058bdfc5daSXin Ji } 17068bdfc5daSXin Ji 17078bdfc5daSXin Ji if (ctx->pdata.panel_bridge) { 17088bdfc5daSXin Ji err = drm_bridge_attach(bridge->encoder, 17098bdfc5daSXin Ji ctx->pdata.panel_bridge, 17108bdfc5daSXin Ji &ctx->bridge, flags); 1711fb8d617fSLaurent Pinchart if (err) 17128bdfc5daSXin Ji return err; 17138bdfc5daSXin Ji } 17148bdfc5daSXin Ji 17158bdfc5daSXin Ji ctx->bridge_attached = 1; 17168bdfc5daSXin Ji 17178bdfc5daSXin Ji return 0; 17188bdfc5daSXin Ji } 17198bdfc5daSXin Ji 17208bdfc5daSXin Ji static enum drm_mode_status 17218bdfc5daSXin Ji anx7625_bridge_mode_valid(struct drm_bridge *bridge, 17228bdfc5daSXin Ji const struct drm_display_info *info, 17238bdfc5daSXin Ji const struct drm_display_mode *mode) 17248bdfc5daSXin Ji { 17258bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 17268bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17278bdfc5daSXin Ji 17288bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 17298bdfc5daSXin Ji 17308bdfc5daSXin Ji /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 17318bdfc5daSXin Ji if (mode->clock > SUPPORT_PIXEL_CLOCK) { 17328bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, 17338bdfc5daSXin Ji "drm mode invalid, pixelclock too high.\n"); 17348bdfc5daSXin Ji return MODE_CLOCK_HIGH; 17358bdfc5daSXin Ji } 17368bdfc5daSXin Ji 17378bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 17388bdfc5daSXin Ji 17398bdfc5daSXin Ji return MODE_OK; 17408bdfc5daSXin Ji } 17418bdfc5daSXin Ji 17428bdfc5daSXin Ji static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 17438bdfc5daSXin Ji const struct drm_display_mode *old_mode, 17448bdfc5daSXin Ji const struct drm_display_mode *mode) 17458bdfc5daSXin Ji { 17468bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 17478bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17488bdfc5daSXin Ji 17498bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 17508bdfc5daSXin Ji 17518bdfc5daSXin Ji ctx->dt.pixelclock.min = mode->clock; 17528bdfc5daSXin Ji ctx->dt.hactive.min = mode->hdisplay; 17538bdfc5daSXin Ji ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 17548bdfc5daSXin Ji ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 17558bdfc5daSXin Ji ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 17568bdfc5daSXin Ji ctx->dt.vactive.min = mode->vdisplay; 17578bdfc5daSXin Ji ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 17588bdfc5daSXin Ji ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 17598bdfc5daSXin Ji ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 17608bdfc5daSXin Ji 17618bdfc5daSXin Ji ctx->display_timing_valid = 1; 17628bdfc5daSXin Ji 17638bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 17648bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 17658bdfc5daSXin Ji ctx->dt.hactive.min, 17668bdfc5daSXin Ji ctx->dt.hsync_len.min, 17678bdfc5daSXin Ji ctx->dt.hfront_porch.min, 17688bdfc5daSXin Ji ctx->dt.hback_porch.min); 17698bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 17708bdfc5daSXin Ji ctx->dt.vactive.min, 17718bdfc5daSXin Ji ctx->dt.vsync_len.min, 17728bdfc5daSXin Ji ctx->dt.vfront_porch.min, 17738bdfc5daSXin Ji ctx->dt.vback_porch.min); 17748bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 17758bdfc5daSXin Ji mode->hdisplay, 17768bdfc5daSXin Ji mode->hsync_start); 17778bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 17788bdfc5daSXin Ji mode->hsync_end, 17798bdfc5daSXin Ji mode->htotal); 17808bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 17818bdfc5daSXin Ji mode->vdisplay, 17828bdfc5daSXin Ji mode->vsync_start); 17838bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 17848bdfc5daSXin Ji mode->vsync_end, 17858bdfc5daSXin Ji mode->vtotal); 17868bdfc5daSXin Ji } 17878bdfc5daSXin Ji 17888bdfc5daSXin Ji static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 17898bdfc5daSXin Ji const struct drm_display_mode *mode, 17908bdfc5daSXin Ji struct drm_display_mode *adj) 17918bdfc5daSXin Ji { 17928bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 17938bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 17948bdfc5daSXin Ji u32 hsync, hfp, hbp, hblanking; 17958bdfc5daSXin Ji u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 17968bdfc5daSXin Ji u32 vref, adj_clock; 17978bdfc5daSXin Ji 17988bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 17998bdfc5daSXin Ji 1800fd0310b6SXin Ji /* No need fixup for external monitor */ 1801fd0310b6SXin Ji if (!ctx->pdata.panel_bridge) 1802fd0310b6SXin Ji return true; 1803fd0310b6SXin Ji 18048bdfc5daSXin Ji hsync = mode->hsync_end - mode->hsync_start; 18058bdfc5daSXin Ji hfp = mode->hsync_start - mode->hdisplay; 18068bdfc5daSXin Ji hbp = mode->htotal - mode->hsync_end; 18078bdfc5daSXin Ji hblanking = mode->htotal - mode->hdisplay; 18088bdfc5daSXin Ji 18098bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 18108bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 18118bdfc5daSXin Ji hsync, hfp, hbp, adj->clock); 18128bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 18138bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 18148bdfc5daSXin Ji 18158bdfc5daSXin Ji adj_hfp = hfp; 18168bdfc5daSXin Ji adj_hsync = hsync; 18178bdfc5daSXin Ji adj_hbp = hbp; 18188bdfc5daSXin Ji adj_hblanking = hblanking; 18198bdfc5daSXin Ji 18208bdfc5daSXin Ji /* HFP needs to be even */ 18218bdfc5daSXin Ji if (hfp & 0x1) { 18228bdfc5daSXin Ji adj_hfp += 1; 18238bdfc5daSXin Ji adj_hblanking += 1; 18248bdfc5daSXin Ji } 18258bdfc5daSXin Ji 18268bdfc5daSXin Ji /* HBP needs to be even */ 18278bdfc5daSXin Ji if (hbp & 0x1) { 18288bdfc5daSXin Ji adj_hbp -= 1; 18298bdfc5daSXin Ji adj_hblanking -= 1; 18308bdfc5daSXin Ji } 18318bdfc5daSXin Ji 18328bdfc5daSXin Ji /* HSYNC needs to be even */ 18338bdfc5daSXin Ji if (hsync & 0x1) { 18348bdfc5daSXin Ji if (adj_hblanking < hblanking) 18358bdfc5daSXin Ji adj_hsync += 1; 18368bdfc5daSXin Ji else 18378bdfc5daSXin Ji adj_hsync -= 1; 18388bdfc5daSXin Ji } 18398bdfc5daSXin Ji 18408bdfc5daSXin Ji /* 18418bdfc5daSXin Ji * Once illegal timing detected, use default HFP, HSYNC, HBP 18428bdfc5daSXin Ji * This adjusting made for built-in eDP panel, for the externel 18438bdfc5daSXin Ji * DP monitor, may need return false. 18448bdfc5daSXin Ji */ 18458bdfc5daSXin Ji if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 18468bdfc5daSXin Ji adj_hsync = SYNC_LEN_DEF; 18478bdfc5daSXin Ji adj_hfp = HFP_HBP_DEF; 18488bdfc5daSXin Ji adj_hbp = HFP_HBP_DEF; 18498bdfc5daSXin Ji vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 18508bdfc5daSXin Ji if (hblanking < HBLANKING_MIN) { 18518bdfc5daSXin Ji delta_adj = HBLANKING_MIN - hblanking; 18528bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 18538bdfc5daSXin Ji adj->clock += DIV_ROUND_UP(adj_clock, 1000); 18548bdfc5daSXin Ji } else { 18558bdfc5daSXin Ji delta_adj = hblanking - HBLANKING_MIN; 18568bdfc5daSXin Ji adj_clock = vref * delta_adj * adj->vtotal; 18578bdfc5daSXin Ji adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 18588bdfc5daSXin Ji } 18598bdfc5daSXin Ji 18608bdfc5daSXin Ji DRM_WARN("illegal hblanking timing, use default.\n"); 18618bdfc5daSXin Ji DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 18628bdfc5daSXin Ji } else if (adj_hfp < HP_MIN) { 18638bdfc5daSXin Ji /* Adjust hfp if hfp less than HP_MIN */ 18648bdfc5daSXin Ji delta_adj = HP_MIN - adj_hfp; 18658bdfc5daSXin Ji adj_hfp = HP_MIN; 18668bdfc5daSXin Ji 18678bdfc5daSXin Ji /* 18688bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP does not have enough 18698bdfc5daSXin Ji * space, adjust HSYNC length, otherwise adjust HBP 18708bdfc5daSXin Ji */ 18718bdfc5daSXin Ji if ((adj_hbp - delta_adj) < HP_MIN) 18728bdfc5daSXin Ji /* HBP not enough space */ 18738bdfc5daSXin Ji adj_hsync -= delta_adj; 18748bdfc5daSXin Ji else 18758bdfc5daSXin Ji adj_hbp -= delta_adj; 18768bdfc5daSXin Ji } else if (adj_hbp < HP_MIN) { 18778bdfc5daSXin Ji delta_adj = HP_MIN - adj_hbp; 18788bdfc5daSXin Ji adj_hbp = HP_MIN; 18798bdfc5daSXin Ji 18808bdfc5daSXin Ji /* 18818bdfc5daSXin Ji * Balance total HBlanking pixel, if HBP hasn't enough space, 18828bdfc5daSXin Ji * adjust HSYNC length, otherwize adjust HBP 18838bdfc5daSXin Ji */ 18848bdfc5daSXin Ji if ((adj_hfp - delta_adj) < HP_MIN) 18858bdfc5daSXin Ji /* HFP not enough space */ 18868bdfc5daSXin Ji adj_hsync -= delta_adj; 18878bdfc5daSXin Ji else 18888bdfc5daSXin Ji adj_hfp -= delta_adj; 18898bdfc5daSXin Ji } 18908bdfc5daSXin Ji 18918bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 18928bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 18938bdfc5daSXin Ji adj_hsync, adj_hfp, adj_hbp, adj->clock); 18948bdfc5daSXin Ji 18958bdfc5daSXin Ji /* Reconstruct timing */ 18968bdfc5daSXin Ji adj->hsync_start = adj->hdisplay + adj_hfp; 18978bdfc5daSXin Ji adj->hsync_end = adj->hsync_start + adj_hsync; 18988bdfc5daSXin Ji adj->htotal = adj->hsync_end + adj_hbp; 18998bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 19008bdfc5daSXin Ji adj->hsync_start, adj->hsync_end, adj->htotal); 19018bdfc5daSXin Ji 19028bdfc5daSXin Ji return true; 19038bdfc5daSXin Ji } 19048bdfc5daSXin Ji 19058bdfc5daSXin Ji static void anx7625_bridge_enable(struct drm_bridge *bridge) 19068bdfc5daSXin Ji { 19078bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 19088bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 19098bdfc5daSXin Ji 19108bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n"); 19118bdfc5daSXin Ji 191260487584SPi-Hsun Shih pm_runtime_get_sync(dev); 19138bdfc5daSXin Ji 19148bdfc5daSXin Ji anx7625_dp_start(ctx); 19158bdfc5daSXin Ji } 19168bdfc5daSXin Ji 19178bdfc5daSXin Ji static void anx7625_bridge_disable(struct drm_bridge *bridge) 19188bdfc5daSXin Ji { 19198bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 19208bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 19218bdfc5daSXin Ji 19228bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n"); 19238bdfc5daSXin Ji 19248bdfc5daSXin Ji anx7625_dp_stop(ctx); 19258bdfc5daSXin Ji 19263203e497SPi-Hsun Shih pm_runtime_put_sync(dev); 19278bdfc5daSXin Ji } 19288bdfc5daSXin Ji 19298bdfc5daSXin Ji static enum drm_connector_status 19308bdfc5daSXin Ji anx7625_bridge_detect(struct drm_bridge *bridge) 19318bdfc5daSXin Ji { 19328bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 19338bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 19348bdfc5daSXin Ji 19358bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 19368bdfc5daSXin Ji 19378bdfc5daSXin Ji return anx7625_sink_detect(ctx); 19388bdfc5daSXin Ji } 19398bdfc5daSXin Ji 19408bdfc5daSXin Ji static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge, 19418bdfc5daSXin Ji struct drm_connector *connector) 19428bdfc5daSXin Ji { 19438bdfc5daSXin Ji struct anx7625_data *ctx = bridge_to_anx7625(bridge); 19448bdfc5daSXin Ji struct device *dev = &ctx->client->dev; 19458bdfc5daSXin Ji 19468bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 19478bdfc5daSXin Ji 19488bdfc5daSXin Ji return anx7625_get_edid(ctx); 19498bdfc5daSXin Ji } 19508bdfc5daSXin Ji 19518bdfc5daSXin Ji static const struct drm_bridge_funcs anx7625_bridge_funcs = { 19528bdfc5daSXin Ji .attach = anx7625_bridge_attach, 19538bdfc5daSXin Ji .disable = anx7625_bridge_disable, 19548bdfc5daSXin Ji .mode_valid = anx7625_bridge_mode_valid, 19558bdfc5daSXin Ji .mode_set = anx7625_bridge_mode_set, 19568bdfc5daSXin Ji .mode_fixup = anx7625_bridge_mode_fixup, 19578bdfc5daSXin Ji .enable = anx7625_bridge_enable, 19588bdfc5daSXin Ji .detect = anx7625_bridge_detect, 19598bdfc5daSXin Ji .get_edid = anx7625_bridge_get_edid, 19608bdfc5daSXin Ji }; 19618bdfc5daSXin Ji 19628bdfc5daSXin Ji static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 19638bdfc5daSXin Ji struct i2c_client *client) 19648bdfc5daSXin Ji { 19658bdfc5daSXin Ji ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, 19668bdfc5daSXin Ji TX_P0_ADDR >> 1); 19678bdfc5daSXin Ji if (!ctx->i2c.tx_p0_client) 19688bdfc5daSXin Ji return -ENOMEM; 19698bdfc5daSXin Ji 19708bdfc5daSXin Ji ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, 19718bdfc5daSXin Ji TX_P1_ADDR >> 1); 19728bdfc5daSXin Ji if (!ctx->i2c.tx_p1_client) 19738bdfc5daSXin Ji goto free_tx_p0; 19748bdfc5daSXin Ji 19758bdfc5daSXin Ji ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, 19768bdfc5daSXin Ji TX_P2_ADDR >> 1); 19778bdfc5daSXin Ji if (!ctx->i2c.tx_p2_client) 19788bdfc5daSXin Ji goto free_tx_p1; 19798bdfc5daSXin Ji 19808bdfc5daSXin Ji ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, 19818bdfc5daSXin Ji RX_P0_ADDR >> 1); 19828bdfc5daSXin Ji if (!ctx->i2c.rx_p0_client) 19838bdfc5daSXin Ji goto free_tx_p2; 19848bdfc5daSXin Ji 19858bdfc5daSXin Ji ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, 19868bdfc5daSXin Ji RX_P1_ADDR >> 1); 19878bdfc5daSXin Ji if (!ctx->i2c.rx_p1_client) 19888bdfc5daSXin Ji goto free_rx_p0; 19898bdfc5daSXin Ji 19908bdfc5daSXin Ji ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, 19918bdfc5daSXin Ji RX_P2_ADDR >> 1); 19928bdfc5daSXin Ji if (!ctx->i2c.rx_p2_client) 19938bdfc5daSXin Ji goto free_rx_p1; 19948bdfc5daSXin Ji 19958bdfc5daSXin Ji ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, 19968bdfc5daSXin Ji TCPC_INTERFACE_ADDR >> 1); 19978bdfc5daSXin Ji if (!ctx->i2c.tcpc_client) 19988bdfc5daSXin Ji goto free_rx_p2; 19998bdfc5daSXin Ji 20008bdfc5daSXin Ji return 0; 20018bdfc5daSXin Ji 20028bdfc5daSXin Ji free_rx_p2: 20038bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 20048bdfc5daSXin Ji free_rx_p1: 20058bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 20068bdfc5daSXin Ji free_rx_p0: 20078bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 20088bdfc5daSXin Ji free_tx_p2: 20098bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 20108bdfc5daSXin Ji free_tx_p1: 20118bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 20128bdfc5daSXin Ji free_tx_p0: 20138bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 20148bdfc5daSXin Ji 20158bdfc5daSXin Ji return -ENOMEM; 20168bdfc5daSXin Ji } 20178bdfc5daSXin Ji 20188bdfc5daSXin Ji static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) 20198bdfc5daSXin Ji { 20208bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p0_client); 20218bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p1_client); 20228bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tx_p2_client); 20238bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p0_client); 20248bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p1_client); 20258bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.rx_p2_client); 20268bdfc5daSXin Ji i2c_unregister_device(ctx->i2c.tcpc_client); 20278bdfc5daSXin Ji } 20288bdfc5daSXin Ji 202960487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 203060487584SPi-Hsun Shih { 203160487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 203260487584SPi-Hsun Shih 203360487584SPi-Hsun Shih mutex_lock(&ctx->lock); 203460487584SPi-Hsun Shih 203560487584SPi-Hsun Shih anx7625_stop_dp_work(ctx); 203660487584SPi-Hsun Shih anx7625_power_standby(ctx); 203760487584SPi-Hsun Shih 203860487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 203960487584SPi-Hsun Shih 204060487584SPi-Hsun Shih return 0; 204160487584SPi-Hsun Shih } 204260487584SPi-Hsun Shih 204360487584SPi-Hsun Shih static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 204460487584SPi-Hsun Shih { 204560487584SPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 204660487584SPi-Hsun Shih 204760487584SPi-Hsun Shih mutex_lock(&ctx->lock); 204860487584SPi-Hsun Shih 204960487584SPi-Hsun Shih anx7625_power_on_init(ctx); 205060487584SPi-Hsun Shih anx7625_hpd_polling(ctx); 205160487584SPi-Hsun Shih 205260487584SPi-Hsun Shih mutex_unlock(&ctx->lock); 205360487584SPi-Hsun Shih 205460487584SPi-Hsun Shih return 0; 205560487584SPi-Hsun Shih } 205660487584SPi-Hsun Shih 2057409776faSPi-Hsun Shih static int __maybe_unused anx7625_resume(struct device *dev) 2058409776faSPi-Hsun Shih { 2059409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 2060409776faSPi-Hsun Shih 2061409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 2062409776faSPi-Hsun Shih return 0; 2063409776faSPi-Hsun Shih 2064409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2065409776faSPi-Hsun Shih enable_irq(ctx->pdata.intp_irq); 2066409776faSPi-Hsun Shih anx7625_runtime_pm_resume(dev); 2067409776faSPi-Hsun Shih } 2068409776faSPi-Hsun Shih 2069409776faSPi-Hsun Shih return 0; 2070409776faSPi-Hsun Shih } 2071409776faSPi-Hsun Shih 2072409776faSPi-Hsun Shih static int __maybe_unused anx7625_suspend(struct device *dev) 2073409776faSPi-Hsun Shih { 2074409776faSPi-Hsun Shih struct anx7625_data *ctx = dev_get_drvdata(dev); 2075409776faSPi-Hsun Shih 2076409776faSPi-Hsun Shih if (!ctx->pdata.intp_irq) 2077409776faSPi-Hsun Shih return 0; 2078409776faSPi-Hsun Shih 2079409776faSPi-Hsun Shih if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 2080409776faSPi-Hsun Shih anx7625_runtime_pm_suspend(dev); 2081409776faSPi-Hsun Shih disable_irq(ctx->pdata.intp_irq); 2082409776faSPi-Hsun Shih } 2083409776faSPi-Hsun Shih 2084409776faSPi-Hsun Shih return 0; 2085409776faSPi-Hsun Shih } 2086409776faSPi-Hsun Shih 208760487584SPi-Hsun Shih static const struct dev_pm_ops anx7625_pm_ops = { 2088409776faSPi-Hsun Shih SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume) 208960487584SPi-Hsun Shih SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 209060487584SPi-Hsun Shih anx7625_runtime_pm_resume, NULL) 209160487584SPi-Hsun Shih }; 209260487584SPi-Hsun Shih 20938bdfc5daSXin Ji static int anx7625_i2c_probe(struct i2c_client *client, 20948bdfc5daSXin Ji const struct i2c_device_id *id) 20958bdfc5daSXin Ji { 20968bdfc5daSXin Ji struct anx7625_data *platform; 20978bdfc5daSXin Ji struct anx7625_platform_data *pdata; 20988bdfc5daSXin Ji int ret = 0; 20998bdfc5daSXin Ji struct device *dev = &client->dev; 21008bdfc5daSXin Ji 21018bdfc5daSXin Ji if (!i2c_check_functionality(client->adapter, 21028bdfc5daSXin Ji I2C_FUNC_SMBUS_I2C_BLOCK)) { 21038bdfc5daSXin Ji DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 21048bdfc5daSXin Ji return -ENODEV; 21058bdfc5daSXin Ji } 21068bdfc5daSXin Ji 21078bdfc5daSXin Ji platform = kzalloc(sizeof(*platform), GFP_KERNEL); 21088bdfc5daSXin Ji if (!platform) { 21098bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 21108bdfc5daSXin Ji return -ENOMEM; 21118bdfc5daSXin Ji } 21128bdfc5daSXin Ji 21138bdfc5daSXin Ji pdata = &platform->pdata; 21148bdfc5daSXin Ji 21158bdfc5daSXin Ji ret = anx7625_parse_dt(dev, pdata); 21168bdfc5daSXin Ji if (ret) { 21178bdfc5daSXin Ji if (ret != -EPROBE_DEFER) 21188bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 21198bdfc5daSXin Ji goto free_platform; 21208bdfc5daSXin Ji } 21218bdfc5daSXin Ji 21228bdfc5daSXin Ji platform->client = client; 21238bdfc5daSXin Ji i2c_set_clientdata(client, platform); 21248bdfc5daSXin Ji 21256c744983SHsin-Yi Wang pdata->supplies[0].supply = "vdd10"; 21266c744983SHsin-Yi Wang pdata->supplies[1].supply = "vdd18"; 21276c744983SHsin-Yi Wang pdata->supplies[2].supply = "vdd33"; 21286c744983SHsin-Yi Wang ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 21296c744983SHsin-Yi Wang pdata->supplies); 21306c744983SHsin-Yi Wang if (ret) { 21316c744983SHsin-Yi Wang DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 21326c744983SHsin-Yi Wang return ret; 21336c744983SHsin-Yi Wang } 21348bdfc5daSXin Ji anx7625_init_gpio(platform); 21358bdfc5daSXin Ji 21368bdfc5daSXin Ji mutex_init(&platform->lock); 21378bdfc5daSXin Ji 21388bdfc5daSXin Ji platform->pdata.intp_irq = client->irq; 21398bdfc5daSXin Ji if (platform->pdata.intp_irq) { 21408bdfc5daSXin Ji INIT_WORK(&platform->work, anx7625_work_func); 2141f03ab662SPi-Hsun Shih platform->workqueue = alloc_workqueue("anx7625_work", 2142f03ab662SPi-Hsun Shih WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 21438bdfc5daSXin Ji if (!platform->workqueue) { 21448bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to create work queue\n"); 21458bdfc5daSXin Ji ret = -ENOMEM; 21468bdfc5daSXin Ji goto free_platform; 21478bdfc5daSXin Ji } 21488bdfc5daSXin Ji 21498bdfc5daSXin Ji ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 21508bdfc5daSXin Ji NULL, anx7625_intr_hpd_isr, 21518bdfc5daSXin Ji IRQF_TRIGGER_FALLING | 21528bdfc5daSXin Ji IRQF_ONESHOT, 21538bdfc5daSXin Ji "anx7625-intp", platform); 21548bdfc5daSXin Ji if (ret) { 21558bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to request irq\n"); 21568bdfc5daSXin Ji goto free_wq; 21578bdfc5daSXin Ji } 21588bdfc5daSXin Ji } 21598bdfc5daSXin Ji 21608bdfc5daSXin Ji if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 21618bdfc5daSXin Ji ret = -ENOMEM; 21628bdfc5daSXin Ji DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 21638bdfc5daSXin Ji goto free_wq; 21648bdfc5daSXin Ji } 21658bdfc5daSXin Ji 216660487584SPi-Hsun Shih pm_runtime_enable(dev); 216760487584SPi-Hsun Shih 216860487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) { 21698bdfc5daSXin Ji anx7625_disable_pd_protocol(platform); 217060487584SPi-Hsun Shih pm_runtime_get_sync(dev); 21718bdfc5daSXin Ji } 21728bdfc5daSXin Ji 21738bdfc5daSXin Ji /* Add work function */ 21748bdfc5daSXin Ji if (platform->pdata.intp_irq) 21758bdfc5daSXin Ji queue_work(platform->workqueue, &platform->work); 21768bdfc5daSXin Ji 21778bdfc5daSXin Ji platform->bridge.funcs = &anx7625_bridge_funcs; 21788bdfc5daSXin Ji platform->bridge.of_node = client->dev.of_node; 2179fd0310b6SXin Ji platform->bridge.ops = DRM_BRIDGE_OP_EDID; 2180fd0310b6SXin Ji if (!platform->pdata.panel_bridge) 2181fd0310b6SXin Ji platform->bridge.ops |= DRM_BRIDGE_OP_HPD | 2182fd0310b6SXin Ji DRM_BRIDGE_OP_DETECT; 2183fd0310b6SXin Ji platform->bridge.type = platform->pdata.panel_bridge ? 2184fd0310b6SXin Ji DRM_MODE_CONNECTOR_eDP : 2185fd0310b6SXin Ji DRM_MODE_CONNECTOR_DisplayPort; 2186fd0310b6SXin Ji 21878bdfc5daSXin Ji drm_bridge_add(&platform->bridge); 21888bdfc5daSXin Ji 2189fd0310b6SXin Ji if (!platform->pdata.is_dpi) { 219049e61beeSMaxime Ripard ret = anx7625_attach_dsi(platform); 219149e61beeSMaxime Ripard if (ret) { 219249e61beeSMaxime Ripard DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret); 219349e61beeSMaxime Ripard goto unregister_bridge; 219449e61beeSMaxime Ripard } 2195fd0310b6SXin Ji } 219649e61beeSMaxime Ripard 2197566fef12SXin Ji if (platform->pdata.audio_en) 2198566fef12SXin Ji anx7625_register_audio(dev, platform); 2199566fef12SXin Ji 22008bdfc5daSXin Ji DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 22018bdfc5daSXin Ji 22028bdfc5daSXin Ji return 0; 22038bdfc5daSXin Ji 220449e61beeSMaxime Ripard unregister_bridge: 220549e61beeSMaxime Ripard drm_bridge_remove(&platform->bridge); 220649e61beeSMaxime Ripard 220749e61beeSMaxime Ripard if (!platform->pdata.low_power_mode) 220849e61beeSMaxime Ripard pm_runtime_put_sync_suspend(&client->dev); 220949e61beeSMaxime Ripard 221049e61beeSMaxime Ripard anx7625_unregister_i2c_dummy_clients(platform); 221149e61beeSMaxime Ripard 22128bdfc5daSXin Ji free_wq: 22138bdfc5daSXin Ji if (platform->workqueue) 22148bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 22158bdfc5daSXin Ji 22168bdfc5daSXin Ji free_platform: 22178bdfc5daSXin Ji kfree(platform); 22188bdfc5daSXin Ji 22198bdfc5daSXin Ji return ret; 22208bdfc5daSXin Ji } 22218bdfc5daSXin Ji 22228bdfc5daSXin Ji static int anx7625_i2c_remove(struct i2c_client *client) 22238bdfc5daSXin Ji { 22248bdfc5daSXin Ji struct anx7625_data *platform = i2c_get_clientdata(client); 22258bdfc5daSXin Ji 22268bdfc5daSXin Ji drm_bridge_remove(&platform->bridge); 22278bdfc5daSXin Ji 22288bdfc5daSXin Ji if (platform->pdata.intp_irq) 22298bdfc5daSXin Ji destroy_workqueue(platform->workqueue); 22308bdfc5daSXin Ji 223160487584SPi-Hsun Shih if (!platform->pdata.low_power_mode) 223260487584SPi-Hsun Shih pm_runtime_put_sync_suspend(&client->dev); 223360487584SPi-Hsun Shih 22348bdfc5daSXin Ji anx7625_unregister_i2c_dummy_clients(platform); 22358bdfc5daSXin Ji 2236566fef12SXin Ji if (platform->pdata.audio_en) 2237566fef12SXin Ji anx7625_unregister_audio(platform); 2238566fef12SXin Ji 22398bdfc5daSXin Ji kfree(platform); 22408bdfc5daSXin Ji return 0; 22418bdfc5daSXin Ji } 22428bdfc5daSXin Ji 22438bdfc5daSXin Ji static const struct i2c_device_id anx7625_id[] = { 22448bdfc5daSXin Ji {"anx7625", 0}, 22458bdfc5daSXin Ji {} 22468bdfc5daSXin Ji }; 22478bdfc5daSXin Ji 22488bdfc5daSXin Ji MODULE_DEVICE_TABLE(i2c, anx7625_id); 22498bdfc5daSXin Ji 22508bdfc5daSXin Ji static const struct of_device_id anx_match_table[] = { 22518bdfc5daSXin Ji {.compatible = "analogix,anx7625",}, 22528bdfc5daSXin Ji {}, 22538bdfc5daSXin Ji }; 2254ad5fd900SYu Jiahua MODULE_DEVICE_TABLE(of, anx_match_table); 22558bdfc5daSXin Ji 22568bdfc5daSXin Ji static struct i2c_driver anx7625_driver = { 22578bdfc5daSXin Ji .driver = { 22588bdfc5daSXin Ji .name = "anx7625", 22598bdfc5daSXin Ji .of_match_table = anx_match_table, 226060487584SPi-Hsun Shih .pm = &anx7625_pm_ops, 22618bdfc5daSXin Ji }, 22628bdfc5daSXin Ji .probe = anx7625_i2c_probe, 22638bdfc5daSXin Ji .remove = anx7625_i2c_remove, 22648bdfc5daSXin Ji 22658bdfc5daSXin Ji .id_table = anx7625_id, 22668bdfc5daSXin Ji }; 22678bdfc5daSXin Ji 22688bdfc5daSXin Ji module_i2c_driver(anx7625_driver); 22698bdfc5daSXin Ji 22708bdfc5daSXin Ji MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 22718bdfc5daSXin Ji MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 22728bdfc5daSXin Ji MODULE_LICENSE("GPL v2"); 22738bdfc5daSXin Ji MODULE_VERSION(ANX7625_DRV_VERSION); 2274