1 /* 2 * Register definition file for Analogix DP core driver 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef _ANALOGIX_DP_REG_H 13 #define _ANALOGIX_DP_REG_H 14 15 #define ANALOGIX_DP_TX_SW_RESET 0x14 16 #define ANALOGIX_DP_FUNC_EN_1 0x18 17 #define ANALOGIX_DP_FUNC_EN_2 0x1C 18 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 19 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 20 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 21 22 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 23 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 24 25 #define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8 26 27 #define ANALOGIX_DP_PLL_REG_1 0xfc 28 #define ANALOGIX_DP_PLL_REG_2 0x9e4 29 #define ANALOGIX_DP_PLL_REG_3 0x9e8 30 #define ANALOGIX_DP_PLL_REG_4 0x9ec 31 #define ANALOGIX_DP_PLL_REG_5 0xa00 32 33 #define ANALOGIX_DP_PD 0x12c 34 35 #define ANALOGIX_DP_IF_TYPE 0x244 36 #define ANALOGIX_DP_IF_PKT_DB1 0x254 37 #define ANALOGIX_DP_IF_PKT_DB2 0x258 38 #define ANALOGIX_DP_SPD_HB0 0x2F8 39 #define ANALOGIX_DP_SPD_HB1 0x2FC 40 #define ANALOGIX_DP_SPD_HB2 0x300 41 #define ANALOGIX_DP_SPD_HB3 0x304 42 #define ANALOGIX_DP_SPD_PB0 0x308 43 #define ANALOGIX_DP_SPD_PB1 0x30C 44 #define ANALOGIX_DP_SPD_PB2 0x310 45 #define ANALOGIX_DP_SPD_PB3 0x314 46 #define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL 0x318 47 #define ANALOGIX_DP_VSC_SHADOW_DB0 0x31C 48 #define ANALOGIX_DP_VSC_SHADOW_DB1 0x320 49 50 #define ANALOGIX_DP_LANE_MAP 0x35C 51 52 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 53 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 54 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 55 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 56 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 57 58 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 59 60 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 61 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 62 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 63 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 64 #define ANALOGIX_DP_INT_STA 0x3DC 65 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 66 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 67 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 68 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 69 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 70 #define ANALOGIX_DP_INT_CTL 0x3FC 71 72 #define ANALOGIX_DP_SYS_CTL_1 0x600 73 #define ANALOGIX_DP_SYS_CTL_2 0x604 74 #define ANALOGIX_DP_SYS_CTL_3 0x608 75 #define ANALOGIX_DP_SYS_CTL_4 0x60C 76 77 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 78 #define ANALOGIX_DP_HDCP_CTL 0x648 79 80 #define ANALOGIX_DP_LINK_BW_SET 0x680 81 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 82 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 83 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 84 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 85 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 86 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 87 88 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 89 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 90 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 91 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 92 93 #define ANALOGIX_DP_M_VID_0 0x700 94 #define ANALOGIX_DP_M_VID_1 0x704 95 #define ANALOGIX_DP_M_VID_2 0x708 96 #define ANALOGIX_DP_N_VID_0 0x70C 97 #define ANALOGIX_DP_N_VID_1 0x710 98 #define ANALOGIX_DP_N_VID_2 0x714 99 100 #define ANALOGIX_DP_PLL_CTL 0x71C 101 #define ANALOGIX_DP_PHY_PD 0x720 102 #define ANALOGIX_DP_PHY_TEST 0x724 103 104 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 105 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 106 107 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 108 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 109 #define ANALOGIX_DP_AUX_CH_STA 0x780 110 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 111 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 112 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 113 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 114 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 115 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 116 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 117 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 118 119 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 120 121 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 122 123 #define ANALOGIX_DP_CRC_CON 0x890 124 125 /* ANALOGIX_DP_TX_SW_RESET */ 126 #define RESET_DP_TX (0x1 << 0) 127 128 /* ANALOGIX_DP_FUNC_EN_1 */ 129 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 130 #define RK_VID_CAP_FUNC_EN_N (0x1 << 6) 131 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 132 #define RK_VID_FIFO_FUNC_EN_N (0x1 << 5) 133 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 134 #define AUD_FUNC_EN_N (0x1 << 3) 135 #define HDCP_FUNC_EN_N (0x1 << 2) 136 #define CRC_FUNC_EN_N (0x1 << 1) 137 #define SW_FUNC_EN_N (0x1 << 0) 138 139 /* ANALOGIX_DP_FUNC_EN_2 */ 140 #define SSC_FUNC_EN_N (0x1 << 7) 141 #define AUX_FUNC_EN_N (0x1 << 2) 142 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 143 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 144 145 /* ANALOGIX_DP_VIDEO_CTL_1 */ 146 #define VIDEO_EN (0x1 << 7) 147 #define HDCP_VIDEO_MUTE (0x1 << 6) 148 149 /* ANALOGIX_DP_VIDEO_CTL_1 */ 150 #define IN_D_RANGE_MASK (0x1 << 7) 151 #define IN_D_RANGE_SHIFT (7) 152 #define IN_D_RANGE_CEA (0x1 << 7) 153 #define IN_D_RANGE_VESA (0x0 << 7) 154 #define IN_BPC_MASK (0x7 << 4) 155 #define IN_BPC_SHIFT (4) 156 #define IN_BPC_12_BITS (0x3 << 4) 157 #define IN_BPC_10_BITS (0x2 << 4) 158 #define IN_BPC_8_BITS (0x1 << 4) 159 #define IN_BPC_6_BITS (0x0 << 4) 160 #define IN_COLOR_F_MASK (0x3 << 0) 161 #define IN_COLOR_F_SHIFT (0) 162 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 163 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 164 #define IN_COLOR_F_RGB (0x0 << 0) 165 166 /* ANALOGIX_DP_VIDEO_CTL_3 */ 167 #define IN_YC_COEFFI_MASK (0x1 << 7) 168 #define IN_YC_COEFFI_SHIFT (7) 169 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 170 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 171 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 172 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 173 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 174 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 175 #define REUSE_SPD_EN (0x1 << 3) 176 177 /* ANALOGIX_DP_VIDEO_CTL_8 */ 178 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 179 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 180 181 /* ANALOGIX_DP_VIDEO_CTL_10 */ 182 #define FORMAT_SEL (0x1 << 4) 183 #define INTERACE_SCAN_CFG (0x1 << 2) 184 #define VSYNC_POLARITY_CFG (0x1 << 1) 185 #define HSYNC_POLARITY_CFG (0x1 << 0) 186 187 /* ANALOGIX_DP_PLL_REG_1 */ 188 #define REF_CLK_24M (0x1 << 0) 189 #define REF_CLK_27M (0x0 << 0) 190 #define REF_CLK_MASK (0x1 << 0) 191 192 /* ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL */ 193 #define PSR_FRAME_UP_TYPE_BURST (0x1 << 0) 194 #define PSR_FRAME_UP_TYPE_SINGLE (0x0 << 0) 195 #define PSR_CRC_SEL_HARDWARE (0x1 << 1) 196 #define PSR_CRC_SEL_MANUALLY (0x0 << 1) 197 198 /* ANALOGIX_DP_LANE_MAP */ 199 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 200 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 201 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 202 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 203 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 204 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 205 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 206 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 207 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 208 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 209 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 210 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 211 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 212 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 213 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 214 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 215 216 /* ANALOGIX_DP_ANALOG_CTL_1 */ 217 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 218 219 /* ANALOGIX_DP_ANALOG_CTL_2 */ 220 #define SEL_24M (0x1 << 3) 221 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 222 223 /* ANALOGIX_DP_ANALOG_CTL_3 */ 224 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 225 #define VCO_BIT_600_MICRO (0x5 << 0) 226 227 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 228 #define PD_RING_OSC (0x1 << 6) 229 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 230 #define TX_CUR1_2X (0x1 << 2) 231 #define TX_CUR_16_MA (0x3 << 0) 232 233 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 234 #define CH3_AMP_400_MV (0x0 << 24) 235 #define CH2_AMP_400_MV (0x0 << 16) 236 #define CH1_AMP_400_MV (0x0 << 8) 237 #define CH0_AMP_400_MV (0x0 << 0) 238 239 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 240 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 241 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 242 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 243 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 244 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 245 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 246 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 247 248 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 249 #define VSYNC_DET (0x1 << 7) 250 #define PLL_LOCK_CHG (0x1 << 6) 251 #define SPDIF_ERR (0x1 << 5) 252 #define SPDIF_UNSTBL (0x1 << 4) 253 #define VID_FORMAT_CHG (0x1 << 3) 254 #define AUD_CLK_CHG (0x1 << 2) 255 #define VID_CLK_CHG (0x1 << 1) 256 #define SW_INT (0x1 << 0) 257 258 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 259 #define ENC_EN_CHG (0x1 << 6) 260 #define HW_BKSV_RDY (0x1 << 3) 261 #define HW_SHA_DONE (0x1 << 2) 262 #define HW_AUTH_STATE_CHG (0x1 << 1) 263 #define HW_AUTH_DONE (0x1 << 0) 264 265 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 266 #define AFIFO_UNDER (0x1 << 7) 267 #define AFIFO_OVER (0x1 << 6) 268 #define R0_CHK_FLAG (0x1 << 5) 269 270 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 271 #define PSR_ACTIVE (0x1 << 7) 272 #define PSR_INACTIVE (0x1 << 6) 273 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 274 #define HOTPLUG_CHG (0x1 << 2) 275 #define HPD_LOST (0x1 << 1) 276 #define PLUG (0x1 << 0) 277 278 /* ANALOGIX_DP_INT_STA */ 279 #define INT_HPD (0x1 << 6) 280 #define HW_TRAINING_FINISH (0x1 << 5) 281 #define RPLY_RECEIV (0x1 << 1) 282 #define AUX_ERR (0x1 << 0) 283 284 /* ANALOGIX_DP_INT_CTL */ 285 #define SOFT_INT_CTRL (0x1 << 2) 286 #define INT_POL1 (0x1 << 1) 287 #define INT_POL0 (0x1 << 0) 288 289 /* ANALOGIX_DP_SYS_CTL_1 */ 290 #define DET_STA (0x1 << 2) 291 #define FORCE_DET (0x1 << 1) 292 #define DET_CTRL (0x1 << 0) 293 294 /* ANALOGIX_DP_SYS_CTL_2 */ 295 #define CHA_CRI(x) (((x) & 0xf) << 4) 296 #define CHA_STA (0x1 << 2) 297 #define FORCE_CHA (0x1 << 1) 298 #define CHA_CTRL (0x1 << 0) 299 300 /* ANALOGIX_DP_SYS_CTL_3 */ 301 #define HPD_STATUS (0x1 << 6) 302 #define F_HPD (0x1 << 5) 303 #define HPD_CTRL (0x1 << 4) 304 #define HDCP_RDY (0x1 << 3) 305 #define STRM_VALID (0x1 << 2) 306 #define F_VALID (0x1 << 1) 307 #define VALID_CTRL (0x1 << 0) 308 309 /* ANALOGIX_DP_SYS_CTL_4 */ 310 #define FIX_M_AUD (0x1 << 4) 311 #define ENHANCED (0x1 << 3) 312 #define FIX_M_VID (0x1 << 2) 313 #define M_VID_UPDATE_CTRL (0x3 << 0) 314 315 /* ANALOGIX_DP_TRAINING_PTN_SET */ 316 #define SCRAMBLER_TYPE (0x1 << 9) 317 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 318 #define SCRAMBLING_DISABLE (0x1 << 5) 319 #define SCRAMBLING_ENABLE (0x0 << 5) 320 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 321 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 322 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 323 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 324 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 325 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 326 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 327 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 328 329 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 330 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 331 #define PRE_EMPHASIS_SET_SHIFT (3) 332 333 /* ANALOGIX_DP_DEBUG_CTL */ 334 #define PLL_LOCK (0x1 << 4) 335 #define F_PLL_LOCK (0x1 << 3) 336 #define PLL_LOCK_CTRL (0x1 << 2) 337 #define PN_INV (0x1 << 0) 338 339 /* ANALOGIX_DP_PLL_CTL */ 340 #define DP_PLL_PD (0x1 << 7) 341 #define DP_PLL_RESET (0x1 << 6) 342 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 343 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 344 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 345 346 /* ANALOGIX_DP_PHY_PD */ 347 #define DP_INC_BG (0x1 << 7) 348 #define DP_EXP_BG (0x1 << 6) 349 #define DP_PHY_PD (0x1 << 5) 350 #define RK_AUX_PD (0x1 << 5) 351 #define AUX_PD (0x1 << 4) 352 #define RK_PLL_PD (0x1 << 4) 353 #define CH3_PD (0x1 << 3) 354 #define CH2_PD (0x1 << 2) 355 #define CH1_PD (0x1 << 1) 356 #define CH0_PD (0x1 << 0) 357 #define DP_ALL_PD (0xff) 358 359 /* ANALOGIX_DP_PHY_TEST */ 360 #define MACRO_RST (0x1 << 5) 361 #define CH1_TEST (0x1 << 1) 362 #define CH0_TEST (0x1 << 0) 363 364 /* ANALOGIX_DP_AUX_CH_STA */ 365 #define AUX_BUSY (0x1 << 4) 366 #define AUX_STATUS_MASK (0xf << 0) 367 368 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 369 #define DEFER_CTRL_EN (0x1 << 7) 370 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 371 372 /* ANALOGIX_DP_AUX_RX_COMM */ 373 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 374 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 375 376 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 377 #define BUF_CLR (0x1 << 7) 378 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 379 380 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 381 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 382 #define AUX_TX_COMM_MASK (0xf << 0) 383 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 384 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 385 #define AUX_TX_COMM_MOT (0x1 << 2) 386 #define AUX_TX_COMM_WRITE (0x0 << 0) 387 #define AUX_TX_COMM_READ (0x1 << 0) 388 389 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 390 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 391 392 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 393 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 394 395 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 396 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 397 398 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 399 #define ADDR_ONLY (0x1 << 1) 400 #define AUX_EN (0x1 << 0) 401 402 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 403 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 404 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 405 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 406 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 407 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 408 #define VIDEO_MODE_MASK (0x1 << 0) 409 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 410 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 411 412 /* ANALOGIX_DP_PKT_SEND_CTL */ 413 #define IF_UP (0x1 << 4) 414 #define IF_EN (0x1 << 0) 415 416 /* ANALOGIX_DP_CRC_CON */ 417 #define PSR_VID_CRC_FLUSH (0x1 << 2) 418 #define PSR_VID_CRC_ENABLE (0x1 << 0) 419 420 #endif /* _ANALOGIX_DP_REG_H */ 421