1 /* 2 * Analogix DP (Display Port) core interface driver. 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/interrupt.h> 20 #include <linux/of.h> 21 #include <linux/of_gpio.h> 22 #include <linux/gpio.h> 23 #include <linux/component.h> 24 #include <linux/phy/phy.h> 25 26 #include <drm/drmP.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_crtc.h> 29 #include <drm/drm_crtc_helper.h> 30 #include <drm/drm_panel.h> 31 32 #include <drm/bridge/analogix_dp.h> 33 34 #include "analogix_dp_core.h" 35 #include "analogix_dp_reg.h" 36 37 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm) 38 39 static const bool verify_fast_training; 40 41 struct bridge_init { 42 struct i2c_client *client; 43 struct device_node *node; 44 }; 45 46 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 47 { 48 analogix_dp_reset(dp); 49 50 analogix_dp_swreset(dp); 51 52 analogix_dp_init_analog_param(dp); 53 analogix_dp_init_interrupt(dp); 54 55 /* SW defined function Normal operation */ 56 analogix_dp_enable_sw_function(dp); 57 58 analogix_dp_config_interrupt(dp); 59 analogix_dp_init_analog_func(dp); 60 61 analogix_dp_init_hpd(dp); 62 analogix_dp_init_aux(dp); 63 } 64 65 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp) 66 { 67 int timeout_loop = 0; 68 69 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) { 70 if (analogix_dp_get_plug_in_status(dp) == 0) 71 return 0; 72 73 timeout_loop++; 74 usleep_range(10, 11); 75 } 76 77 /* 78 * Some edp screen do not have hpd signal, so we can't just 79 * return failed when hpd plug in detect failed, DT property 80 * "force-hpd" would indicate whether driver need this. 81 */ 82 if (!dp->force_hpd) 83 return -ETIMEDOUT; 84 85 /* 86 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH 87 * will not work, so we need to give a force hpd action to 88 * set HPD_STATUS manually. 89 */ 90 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); 91 92 analogix_dp_force_hpd(dp); 93 94 if (analogix_dp_get_plug_in_status(dp) != 0) { 95 dev_err(dp->dev, "failed to get hpd plug in status\n"); 96 return -EINVAL; 97 } 98 99 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); 100 101 return 0; 102 } 103 104 int analogix_dp_psr_enabled(struct analogix_dp_device *dp) 105 { 106 107 return dp->psr_enable; 108 } 109 EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled); 110 111 int analogix_dp_enable_psr(struct analogix_dp_device *dp) 112 { 113 struct edp_vsc_psr psr_vsc; 114 115 if (!dp->psr_enable) 116 return 0; 117 118 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ 119 memset(&psr_vsc, 0, sizeof(psr_vsc)); 120 psr_vsc.sdp_header.HB0 = 0; 121 psr_vsc.sdp_header.HB1 = 0x7; 122 psr_vsc.sdp_header.HB2 = 0x2; 123 psr_vsc.sdp_header.HB3 = 0x8; 124 125 psr_vsc.DB0 = 0; 126 psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID; 127 128 return analogix_dp_send_psr_spd(dp, &psr_vsc, true); 129 } 130 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr); 131 132 int analogix_dp_disable_psr(struct analogix_dp_device *dp) 133 { 134 struct edp_vsc_psr psr_vsc; 135 int ret; 136 137 if (!dp->psr_enable) 138 return 0; 139 140 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ 141 memset(&psr_vsc, 0, sizeof(psr_vsc)); 142 psr_vsc.sdp_header.HB0 = 0; 143 psr_vsc.sdp_header.HB1 = 0x7; 144 psr_vsc.sdp_header.HB2 = 0x2; 145 psr_vsc.sdp_header.HB3 = 0x8; 146 147 psr_vsc.DB0 = 0; 148 psr_vsc.DB1 = 0; 149 150 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 151 if (ret != 1) 152 dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret); 153 154 return analogix_dp_send_psr_spd(dp, &psr_vsc, false); 155 } 156 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); 157 158 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) 159 { 160 unsigned char psr_version; 161 162 drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); 163 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); 164 165 return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; 166 } 167 168 static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) 169 { 170 unsigned char psr_en; 171 172 /* Disable psr function */ 173 drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en); 174 psr_en &= ~DP_PSR_ENABLE; 175 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 176 177 /* Main-Link transmitter remains active during PSR active states */ 178 psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; 179 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 180 181 /* Enable psr function */ 182 psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | 183 DP_PSR_CRC_VERIFICATION; 184 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 185 186 analogix_dp_enable_psr_crc(dp); 187 } 188 189 static void 190 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 191 bool enable) 192 { 193 u8 data; 194 195 drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 196 197 if (enable) 198 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 199 DP_LANE_COUNT_ENHANCED_FRAME_EN | 200 DPCD_LANE_COUNT_SET(data)); 201 else 202 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 203 DPCD_LANE_COUNT_SET(data)); 204 } 205 206 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 207 { 208 u8 data; 209 int retval; 210 211 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 212 retval = DPCD_ENHANCED_FRAME_CAP(data); 213 214 return retval; 215 } 216 217 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 218 { 219 u8 data; 220 221 data = analogix_dp_is_enhanced_mode_available(dp); 222 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 223 analogix_dp_enable_enhanced_mode(dp, data); 224 } 225 226 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 227 { 228 analogix_dp_set_training_pattern(dp, DP_NONE); 229 230 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 231 DP_TRAINING_PATTERN_DISABLE); 232 } 233 234 static void 235 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp, 236 int pre_emphasis, int lane) 237 { 238 switch (lane) { 239 case 0: 240 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis); 241 break; 242 case 1: 243 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis); 244 break; 245 246 case 2: 247 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis); 248 break; 249 250 case 3: 251 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis); 252 break; 253 } 254 } 255 256 static int analogix_dp_link_start(struct analogix_dp_device *dp) 257 { 258 u8 buf[4]; 259 int lane, lane_count, pll_tries, retval; 260 261 lane_count = dp->link_train.lane_count; 262 263 dp->link_train.lt_state = CLOCK_RECOVERY; 264 dp->link_train.eq_loop = 0; 265 266 for (lane = 0; lane < lane_count; lane++) 267 dp->link_train.cr_loop[lane] = 0; 268 269 /* Set link rate and count as you want to establish*/ 270 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 271 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 272 273 /* Setup RX configuration */ 274 buf[0] = dp->link_train.link_rate; 275 buf[1] = dp->link_train.lane_count; 276 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 277 if (retval < 0) 278 return retval; 279 280 /* Set TX pre-emphasis to minimum */ 281 for (lane = 0; lane < lane_count; lane++) 282 analogix_dp_set_lane_lane_pre_emphasis(dp, 283 PRE_EMPHASIS_LEVEL_0, lane); 284 285 /* Wait for PLL lock */ 286 pll_tries = 0; 287 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 288 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { 289 dev_err(dp->dev, "Wait for PLL lock timed out\n"); 290 return -ETIMEDOUT; 291 } 292 293 pll_tries++; 294 usleep_range(90, 120); 295 } 296 297 /* Set training pattern 1 */ 298 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 299 300 /* Set RX training pattern */ 301 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 302 DP_LINK_SCRAMBLING_DISABLE | 303 DP_TRAINING_PATTERN_1); 304 if (retval < 0) 305 return retval; 306 307 for (lane = 0; lane < lane_count; lane++) 308 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 309 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 310 311 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 312 lane_count); 313 if (retval < 0) 314 return retval; 315 316 return 0; 317 } 318 319 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 320 { 321 int shift = (lane & 1) * 4; 322 u8 link_value = link_status[lane >> 1]; 323 324 return (link_value >> shift) & 0xf; 325 } 326 327 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 328 { 329 int lane; 330 u8 lane_status; 331 332 for (lane = 0; lane < lane_count; lane++) { 333 lane_status = analogix_dp_get_lane_status(link_status, lane); 334 if ((lane_status & DP_LANE_CR_DONE) == 0) 335 return -EINVAL; 336 } 337 return 0; 338 } 339 340 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 341 int lane_count) 342 { 343 int lane; 344 u8 lane_status; 345 346 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 347 return -EINVAL; 348 349 for (lane = 0; lane < lane_count; lane++) { 350 lane_status = analogix_dp_get_lane_status(link_status, lane); 351 lane_status &= DP_CHANNEL_EQ_BITS; 352 if (lane_status != DP_CHANNEL_EQ_BITS) 353 return -EINVAL; 354 } 355 356 return 0; 357 } 358 359 static unsigned char 360 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 361 { 362 int shift = (lane & 1) * 4; 363 u8 link_value = adjust_request[lane >> 1]; 364 365 return (link_value >> shift) & 0x3; 366 } 367 368 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 369 u8 adjust_request[2], 370 int lane) 371 { 372 int shift = (lane & 1) * 4; 373 u8 link_value = adjust_request[lane >> 1]; 374 375 return ((link_value >> shift) & 0xc) >> 2; 376 } 377 378 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp, 379 u8 training_lane_set, int lane) 380 { 381 switch (lane) { 382 case 0: 383 analogix_dp_set_lane0_link_training(dp, training_lane_set); 384 break; 385 case 1: 386 analogix_dp_set_lane1_link_training(dp, training_lane_set); 387 break; 388 389 case 2: 390 analogix_dp_set_lane2_link_training(dp, training_lane_set); 391 break; 392 393 case 3: 394 analogix_dp_set_lane3_link_training(dp, training_lane_set); 395 break; 396 } 397 } 398 399 static unsigned int 400 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, 401 int lane) 402 { 403 u32 reg; 404 405 switch (lane) { 406 case 0: 407 reg = analogix_dp_get_lane0_link_training(dp); 408 break; 409 case 1: 410 reg = analogix_dp_get_lane1_link_training(dp); 411 break; 412 case 2: 413 reg = analogix_dp_get_lane2_link_training(dp); 414 break; 415 case 3: 416 reg = analogix_dp_get_lane3_link_training(dp); 417 break; 418 default: 419 WARN_ON(1); 420 return 0; 421 } 422 423 return reg; 424 } 425 426 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 427 { 428 analogix_dp_training_pattern_dis(dp); 429 analogix_dp_set_enhanced_mode(dp); 430 431 dp->link_train.lt_state = FAILED; 432 } 433 434 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 435 u8 adjust_request[2]) 436 { 437 int lane, lane_count; 438 u8 voltage_swing, pre_emphasis, training_lane; 439 440 lane_count = dp->link_train.lane_count; 441 for (lane = 0; lane < lane_count; lane++) { 442 voltage_swing = analogix_dp_get_adjust_request_voltage( 443 adjust_request, lane); 444 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 445 adjust_request, lane); 446 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 447 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 448 449 if (voltage_swing == VOLTAGE_LEVEL_3) 450 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 451 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 452 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 453 454 dp->link_train.training_lane[lane] = training_lane; 455 } 456 } 457 458 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 459 { 460 int lane, lane_count, retval; 461 u8 voltage_swing, pre_emphasis, training_lane; 462 u8 link_status[2], adjust_request[2]; 463 464 usleep_range(100, 101); 465 466 lane_count = dp->link_train.lane_count; 467 468 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 469 if (retval < 0) 470 return retval; 471 472 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 473 adjust_request, 2); 474 if (retval < 0) 475 return retval; 476 477 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 478 /* set training pattern 2 for EQ */ 479 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 480 481 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 482 DP_LINK_SCRAMBLING_DISABLE | 483 DP_TRAINING_PATTERN_2); 484 if (retval < 0) 485 return retval; 486 487 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 488 dp->link_train.lt_state = EQUALIZER_TRAINING; 489 } else { 490 for (lane = 0; lane < lane_count; lane++) { 491 training_lane = analogix_dp_get_lane_link_training( 492 dp, lane); 493 voltage_swing = analogix_dp_get_adjust_request_voltage( 494 adjust_request, lane); 495 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 496 adjust_request, lane); 497 498 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 499 voltage_swing && 500 DPCD_PRE_EMPHASIS_GET(training_lane) == 501 pre_emphasis) 502 dp->link_train.cr_loop[lane]++; 503 504 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 505 voltage_swing == VOLTAGE_LEVEL_3 || 506 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 507 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 508 dp->link_train.cr_loop[lane], 509 voltage_swing, pre_emphasis); 510 analogix_dp_reduce_link_rate(dp); 511 return -EIO; 512 } 513 } 514 } 515 516 analogix_dp_get_adjust_training_lane(dp, adjust_request); 517 518 for (lane = 0; lane < lane_count; lane++) 519 analogix_dp_set_lane_link_training(dp, 520 dp->link_train.training_lane[lane], lane); 521 522 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 523 dp->link_train.training_lane, lane_count); 524 if (retval < 0) 525 return retval; 526 527 return 0; 528 } 529 530 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 531 { 532 int lane, lane_count, retval; 533 u32 reg; 534 u8 link_align, link_status[2], adjust_request[2], spread; 535 536 usleep_range(400, 401); 537 538 lane_count = dp->link_train.lane_count; 539 540 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 541 if (retval < 0) 542 return retval; 543 544 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 545 analogix_dp_reduce_link_rate(dp); 546 return -EIO; 547 } 548 549 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 550 adjust_request, 2); 551 if (retval < 0) 552 return retval; 553 554 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, 555 &link_align); 556 if (retval < 0) 557 return retval; 558 559 analogix_dp_get_adjust_training_lane(dp, adjust_request); 560 561 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 562 /* traing pattern Set to Normal */ 563 analogix_dp_training_pattern_dis(dp); 564 565 dev_info(dp->dev, "Link Training success!\n"); 566 567 analogix_dp_get_link_bandwidth(dp, ®); 568 dp->link_train.link_rate = reg; 569 dev_dbg(dp->dev, "final bandwidth = %.2x\n", 570 dp->link_train.link_rate); 571 572 analogix_dp_get_lane_count(dp, ®); 573 dp->link_train.lane_count = reg; 574 dev_dbg(dp->dev, "final lane count = %.2x\n", 575 dp->link_train.lane_count); 576 577 retval = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, 578 &spread); 579 if (retval != 1) { 580 dev_err(dp->dev, "failed to read downspread %d\n", 581 retval); 582 dp->fast_train_support = false; 583 } else { 584 dp->fast_train_support = 585 (spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ? 586 true : false; 587 } 588 dev_dbg(dp->dev, "fast link training %s\n", 589 dp->fast_train_support ? "supported" : "unsupported"); 590 591 /* set enhanced mode if available */ 592 analogix_dp_set_enhanced_mode(dp); 593 dp->link_train.lt_state = FINISHED; 594 595 return 0; 596 } 597 598 /* not all locked */ 599 dp->link_train.eq_loop++; 600 601 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 602 dev_err(dp->dev, "EQ Max loop\n"); 603 analogix_dp_reduce_link_rate(dp); 604 return -EIO; 605 } 606 607 for (lane = 0; lane < lane_count; lane++) 608 analogix_dp_set_lane_link_training(dp, 609 dp->link_train.training_lane[lane], lane); 610 611 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 612 dp->link_train.training_lane, lane_count); 613 if (retval < 0) 614 return retval; 615 616 return 0; 617 } 618 619 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 620 u8 *bandwidth) 621 { 622 u8 data; 623 624 /* 625 * For DP rev.1.1, Maximum link rate of Main Link lanes 626 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 627 * For DP rev.1.2, Maximum link rate of Main Link lanes 628 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 629 */ 630 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 631 *bandwidth = data; 632 } 633 634 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 635 u8 *lane_count) 636 { 637 u8 data; 638 639 /* 640 * For DP rev.1.1, Maximum number of Main Link lanes 641 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 642 */ 643 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 644 *lane_count = DPCD_MAX_LANE_COUNT(data); 645 } 646 647 static int analogix_dp_full_link_train(struct analogix_dp_device *dp, 648 u32 max_lanes, u32 max_rate) 649 { 650 int retval = 0; 651 bool training_finished = false; 652 653 /* 654 * MACRO_RST must be applied after the PLL_LOCK to avoid 655 * the DP inter pair skew issue for at least 10 us 656 */ 657 analogix_dp_reset_macro(dp); 658 659 /* Initialize by reading RX's DPCD */ 660 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 661 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 662 663 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 664 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 665 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 666 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", 667 dp->link_train.link_rate); 668 dp->link_train.link_rate = DP_LINK_BW_1_62; 669 } 670 671 if (dp->link_train.lane_count == 0) { 672 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", 673 dp->link_train.lane_count); 674 dp->link_train.lane_count = (u8)LANE_COUNT1; 675 } 676 677 /* Setup TX lane count & rate */ 678 if (dp->link_train.lane_count > max_lanes) 679 dp->link_train.lane_count = max_lanes; 680 if (dp->link_train.link_rate > max_rate) 681 dp->link_train.link_rate = max_rate; 682 683 /* All DP analog module power up */ 684 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 685 686 dp->link_train.lt_state = START; 687 688 /* Process here */ 689 while (!retval && !training_finished) { 690 switch (dp->link_train.lt_state) { 691 case START: 692 retval = analogix_dp_link_start(dp); 693 if (retval) 694 dev_err(dp->dev, "LT link start failed!\n"); 695 break; 696 case CLOCK_RECOVERY: 697 retval = analogix_dp_process_clock_recovery(dp); 698 if (retval) 699 dev_err(dp->dev, "LT CR failed!\n"); 700 break; 701 case EQUALIZER_TRAINING: 702 retval = analogix_dp_process_equalizer_training(dp); 703 if (retval) 704 dev_err(dp->dev, "LT EQ failed!\n"); 705 break; 706 case FINISHED: 707 training_finished = 1; 708 break; 709 case FAILED: 710 return -EREMOTEIO; 711 } 712 } 713 if (retval) 714 dev_err(dp->dev, "eDP link training failed (%d)\n", retval); 715 716 return retval; 717 } 718 719 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp) 720 { 721 int i, ret; 722 u8 link_align, link_status[2]; 723 enum pll_status status; 724 725 analogix_dp_reset_macro(dp); 726 727 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 728 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 729 730 for (i = 0; i < dp->link_train.lane_count; i++) { 731 analogix_dp_set_lane_link_training(dp, 732 dp->link_train.training_lane[i], i); 733 } 734 735 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status, 736 status != PLL_UNLOCKED, 120, 737 120 * DP_TIMEOUT_LOOP_COUNT); 738 if (ret) { 739 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret); 740 return ret; 741 } 742 743 /* source Set training pattern 1 */ 744 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 745 /* From DP spec, pattern must be on-screen for a minimum 500us */ 746 usleep_range(500, 600); 747 748 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 749 /* From DP spec, pattern must be on-screen for a minimum 500us */ 750 usleep_range(500, 600); 751 752 /* TODO: enhanced_mode?*/ 753 analogix_dp_set_training_pattern(dp, DP_NONE); 754 755 /* 756 * Useful for debugging issues with fast link training, disable for more 757 * speed 758 */ 759 if (verify_fast_training) { 760 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, 761 &link_align); 762 if (ret < 0) { 763 DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n", 764 ret); 765 return ret; 766 } 767 768 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 769 2); 770 if (ret < 0) { 771 DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n", 772 ret); 773 return ret; 774 } 775 776 if (analogix_dp_clock_recovery_ok(link_status, 777 dp->link_train.lane_count)) { 778 DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n"); 779 analogix_dp_reduce_link_rate(dp); 780 return -EIO; 781 } 782 783 if (analogix_dp_channel_eq_ok(link_status, link_align, 784 dp->link_train.lane_count)) { 785 DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n"); 786 analogix_dp_reduce_link_rate(dp); 787 return -EIO; 788 } 789 } 790 791 return 0; 792 } 793 794 static int analogix_dp_train_link(struct analogix_dp_device *dp) 795 { 796 if (dp->fast_train_support) 797 return analogix_dp_fast_link_train(dp); 798 799 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count, 800 dp->video_info.max_link_rate); 801 } 802 803 static int analogix_dp_config_video(struct analogix_dp_device *dp) 804 { 805 int timeout_loop = 0; 806 int done_count = 0; 807 808 analogix_dp_config_video_slave_mode(dp); 809 810 analogix_dp_set_video_color_format(dp); 811 812 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 813 dev_err(dp->dev, "PLL is not locked yet.\n"); 814 return -EINVAL; 815 } 816 817 for (;;) { 818 timeout_loop++; 819 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 820 break; 821 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 822 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 823 return -ETIMEDOUT; 824 } 825 826 usleep_range(1, 2); 827 } 828 829 /* Set to use the register calculated M/N video */ 830 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 831 832 /* For video bist, Video timing must be generated by register */ 833 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 834 835 /* Disable video mute */ 836 analogix_dp_enable_video_mute(dp, 0); 837 838 /* Configure video slave mode */ 839 analogix_dp_enable_video_master(dp, 0); 840 841 timeout_loop = 0; 842 843 for (;;) { 844 timeout_loop++; 845 if (analogix_dp_is_video_stream_on(dp) == 0) { 846 done_count++; 847 if (done_count > 10) 848 break; 849 } else if (done_count) { 850 done_count = 0; 851 } 852 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 853 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 854 return -ETIMEDOUT; 855 } 856 857 usleep_range(1000, 1001); 858 } 859 860 return 0; 861 } 862 863 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 864 bool enable) 865 { 866 u8 data; 867 868 if (enable) { 869 analogix_dp_enable_scrambling(dp); 870 871 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); 872 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 873 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 874 } else { 875 analogix_dp_disable_scrambling(dp); 876 877 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); 878 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 879 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 880 } 881 } 882 883 static irqreturn_t analogix_dp_hardirq(int irq, void *arg) 884 { 885 struct analogix_dp_device *dp = arg; 886 irqreturn_t ret = IRQ_NONE; 887 enum dp_irq_type irq_type; 888 889 irq_type = analogix_dp_get_irq_type(dp); 890 if (irq_type != DP_IRQ_TYPE_UNKNOWN) { 891 analogix_dp_mute_hpd_interrupt(dp); 892 ret = IRQ_WAKE_THREAD; 893 } 894 895 return ret; 896 } 897 898 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg) 899 { 900 struct analogix_dp_device *dp = arg; 901 enum dp_irq_type irq_type; 902 903 irq_type = analogix_dp_get_irq_type(dp); 904 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN || 905 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) { 906 dev_dbg(dp->dev, "Detected cable status changed!\n"); 907 if (dp->drm_dev) 908 drm_helper_hpd_irq_event(dp->drm_dev); 909 } 910 911 if (irq_type != DP_IRQ_TYPE_UNKNOWN) { 912 analogix_dp_clear_hotplug_interrupts(dp); 913 analogix_dp_unmute_hpd_interrupt(dp); 914 } 915 916 return IRQ_HANDLED; 917 } 918 919 static void analogix_dp_commit(struct analogix_dp_device *dp) 920 { 921 int ret; 922 923 /* Keep the panel disabled while we configure video */ 924 if (dp->plat_data->panel) { 925 if (drm_panel_disable(dp->plat_data->panel)) 926 DRM_ERROR("failed to disable the panel\n"); 927 } 928 929 ret = readx_poll_timeout(analogix_dp_train_link, dp, ret, !ret, 100, 930 DP_TIMEOUT_TRAINING_US * 5); 931 if (ret) { 932 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret); 933 return; 934 } 935 936 analogix_dp_enable_scramble(dp, 1); 937 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 938 analogix_dp_enable_enhanced_mode(dp, 1); 939 940 analogix_dp_init_video(dp); 941 ret = analogix_dp_config_video(dp); 942 if (ret) 943 dev_err(dp->dev, "unable to config video\n"); 944 945 /* Safe to enable the panel now */ 946 if (dp->plat_data->panel) { 947 if (drm_panel_enable(dp->plat_data->panel)) 948 DRM_ERROR("failed to enable the panel\n"); 949 } 950 951 /* Enable video */ 952 analogix_dp_start_video(dp); 953 954 dp->psr_enable = analogix_dp_detect_sink_psr(dp); 955 if (dp->psr_enable) 956 analogix_dp_enable_sink_psr(dp); 957 } 958 959 /* 960 * This function is a bit of a catch-all for panel preparation, hopefully 961 * simplifying the logic of functions that need to prepare/unprepare the panel 962 * below. 963 * 964 * If @prepare is true, this function will prepare the panel. Conversely, if it 965 * is false, the panel will be unprepared. 966 * 967 * If @is_modeset_prepare is true, the function will disregard the current state 968 * of the panel and either prepare/unprepare the panel based on @prepare. Once 969 * it finishes, it will update dp->panel_is_modeset to reflect the current state 970 * of the panel. 971 */ 972 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp, 973 bool prepare, bool is_modeset_prepare) 974 { 975 int ret = 0; 976 977 if (!dp->plat_data->panel) 978 return 0; 979 980 mutex_lock(&dp->panel_lock); 981 982 /* 983 * Exit early if this is a temporary prepare/unprepare and we're already 984 * modeset (since we neither want to prepare twice or unprepare early). 985 */ 986 if (dp->panel_is_modeset && !is_modeset_prepare) 987 goto out; 988 989 if (prepare) 990 ret = drm_panel_prepare(dp->plat_data->panel); 991 else 992 ret = drm_panel_unprepare(dp->plat_data->panel); 993 994 if (ret) 995 goto out; 996 997 if (is_modeset_prepare) 998 dp->panel_is_modeset = prepare; 999 1000 out: 1001 mutex_unlock(&dp->panel_lock); 1002 return ret; 1003 } 1004 1005 static int analogix_dp_get_modes(struct drm_connector *connector) 1006 { 1007 struct analogix_dp_device *dp = to_dp(connector); 1008 struct edid *edid; 1009 int ret, num_modes = 0; 1010 1011 if (dp->plat_data->panel) { 1012 num_modes += drm_panel_get_modes(dp->plat_data->panel); 1013 } else { 1014 ret = analogix_dp_prepare_panel(dp, true, false); 1015 if (ret) { 1016 DRM_ERROR("Failed to prepare panel (%d)\n", ret); 1017 return 0; 1018 } 1019 1020 pm_runtime_get_sync(dp->dev); 1021 edid = drm_get_edid(connector, &dp->aux.ddc); 1022 pm_runtime_put(dp->dev); 1023 if (edid) { 1024 drm_mode_connector_update_edid_property(&dp->connector, 1025 edid); 1026 num_modes += drm_add_edid_modes(&dp->connector, edid); 1027 kfree(edid); 1028 } 1029 1030 ret = analogix_dp_prepare_panel(dp, false, false); 1031 if (ret) 1032 DRM_ERROR("Failed to unprepare panel (%d)\n", ret); 1033 } 1034 1035 if (dp->plat_data->get_modes) 1036 num_modes += dp->plat_data->get_modes(dp->plat_data, connector); 1037 1038 return num_modes; 1039 } 1040 1041 static struct drm_encoder * 1042 analogix_dp_best_encoder(struct drm_connector *connector) 1043 { 1044 struct analogix_dp_device *dp = to_dp(connector); 1045 1046 return dp->encoder; 1047 } 1048 1049 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = { 1050 .get_modes = analogix_dp_get_modes, 1051 .best_encoder = analogix_dp_best_encoder, 1052 }; 1053 1054 static enum drm_connector_status 1055 analogix_dp_detect(struct drm_connector *connector, bool force) 1056 { 1057 struct analogix_dp_device *dp = to_dp(connector); 1058 enum drm_connector_status status = connector_status_disconnected; 1059 int ret; 1060 1061 if (dp->plat_data->panel) 1062 return connector_status_connected; 1063 1064 ret = analogix_dp_prepare_panel(dp, true, false); 1065 if (ret) { 1066 DRM_ERROR("Failed to prepare panel (%d)\n", ret); 1067 return connector_status_disconnected; 1068 } 1069 1070 if (!analogix_dp_detect_hpd(dp)) 1071 status = connector_status_connected; 1072 1073 ret = analogix_dp_prepare_panel(dp, false, false); 1074 if (ret) 1075 DRM_ERROR("Failed to unprepare panel (%d)\n", ret); 1076 1077 return status; 1078 } 1079 1080 static const struct drm_connector_funcs analogix_dp_connector_funcs = { 1081 .fill_modes = drm_helper_probe_single_connector_modes, 1082 .detect = analogix_dp_detect, 1083 .destroy = drm_connector_cleanup, 1084 .reset = drm_atomic_helper_connector_reset, 1085 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1086 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1087 }; 1088 1089 static int analogix_dp_bridge_attach(struct drm_bridge *bridge) 1090 { 1091 struct analogix_dp_device *dp = bridge->driver_private; 1092 struct drm_encoder *encoder = dp->encoder; 1093 struct drm_connector *connector = NULL; 1094 int ret = 0; 1095 1096 if (!bridge->encoder) { 1097 DRM_ERROR("Parent encoder object not found"); 1098 return -ENODEV; 1099 } 1100 1101 if (!dp->plat_data->skip_connector) { 1102 connector = &dp->connector; 1103 connector->polled = DRM_CONNECTOR_POLL_HPD; 1104 1105 ret = drm_connector_init(dp->drm_dev, connector, 1106 &analogix_dp_connector_funcs, 1107 DRM_MODE_CONNECTOR_eDP); 1108 if (ret) { 1109 DRM_ERROR("Failed to initialize connector with drm\n"); 1110 return ret; 1111 } 1112 1113 drm_connector_helper_add(connector, 1114 &analogix_dp_connector_helper_funcs); 1115 drm_mode_connector_attach_encoder(connector, encoder); 1116 } 1117 1118 /* 1119 * NOTE: the connector registration is implemented in analogix 1120 * platform driver, that to say connector would be exist after 1121 * plat_data->attch return, that's why we record the connector 1122 * point after plat attached. 1123 */ 1124 if (dp->plat_data->attach) { 1125 ret = dp->plat_data->attach(dp->plat_data, bridge, connector); 1126 if (ret) { 1127 DRM_ERROR("Failed at platform attch func\n"); 1128 return ret; 1129 } 1130 } 1131 1132 if (dp->plat_data->panel) { 1133 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector); 1134 if (ret) { 1135 DRM_ERROR("Failed to attach panel\n"); 1136 return ret; 1137 } 1138 } 1139 1140 return 0; 1141 } 1142 1143 static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge) 1144 { 1145 struct analogix_dp_device *dp = bridge->driver_private; 1146 int ret; 1147 1148 ret = analogix_dp_prepare_panel(dp, true, true); 1149 if (ret) 1150 DRM_ERROR("failed to setup the panel ret = %d\n", ret); 1151 } 1152 1153 static void analogix_dp_bridge_enable(struct drm_bridge *bridge) 1154 { 1155 struct analogix_dp_device *dp = bridge->driver_private; 1156 1157 if (dp->dpms_mode == DRM_MODE_DPMS_ON) 1158 return; 1159 1160 pm_runtime_get_sync(dp->dev); 1161 1162 if (dp->plat_data->power_on) 1163 dp->plat_data->power_on(dp->plat_data); 1164 1165 phy_power_on(dp->phy); 1166 analogix_dp_init_dp(dp); 1167 enable_irq(dp->irq); 1168 analogix_dp_commit(dp); 1169 1170 dp->dpms_mode = DRM_MODE_DPMS_ON; 1171 } 1172 1173 static void analogix_dp_bridge_disable(struct drm_bridge *bridge) 1174 { 1175 struct analogix_dp_device *dp = bridge->driver_private; 1176 int ret; 1177 1178 if (dp->dpms_mode != DRM_MODE_DPMS_ON) 1179 return; 1180 1181 if (dp->plat_data->panel) { 1182 if (drm_panel_disable(dp->plat_data->panel)) { 1183 DRM_ERROR("failed to disable the panel\n"); 1184 return; 1185 } 1186 } 1187 1188 disable_irq(dp->irq); 1189 phy_power_off(dp->phy); 1190 1191 if (dp->plat_data->power_off) 1192 dp->plat_data->power_off(dp->plat_data); 1193 1194 pm_runtime_put_sync(dp->dev); 1195 1196 ret = analogix_dp_prepare_panel(dp, false, true); 1197 if (ret) 1198 DRM_ERROR("failed to setup the panel ret = %d\n", ret); 1199 1200 dp->psr_enable = false; 1201 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1202 } 1203 1204 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, 1205 struct drm_display_mode *orig_mode, 1206 struct drm_display_mode *mode) 1207 { 1208 struct analogix_dp_device *dp = bridge->driver_private; 1209 struct drm_display_info *display_info = &dp->connector.display_info; 1210 struct video_info *video = &dp->video_info; 1211 struct device_node *dp_node = dp->dev->of_node; 1212 int vic; 1213 1214 /* Input video interlaces & hsync pol & vsync pol */ 1215 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 1216 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); 1217 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); 1218 1219 /* Input video dynamic_range & colorimetry */ 1220 vic = drm_match_cea_mode(mode); 1221 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || 1222 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) { 1223 video->dynamic_range = CEA; 1224 video->ycbcr_coeff = COLOR_YCBCR601; 1225 } else if (vic) { 1226 video->dynamic_range = CEA; 1227 video->ycbcr_coeff = COLOR_YCBCR709; 1228 } else { 1229 video->dynamic_range = VESA; 1230 video->ycbcr_coeff = COLOR_YCBCR709; 1231 } 1232 1233 /* Input vide bpc and color_formats */ 1234 switch (display_info->bpc) { 1235 case 12: 1236 video->color_depth = COLOR_12; 1237 break; 1238 case 10: 1239 video->color_depth = COLOR_10; 1240 break; 1241 case 8: 1242 video->color_depth = COLOR_8; 1243 break; 1244 case 6: 1245 video->color_depth = COLOR_6; 1246 break; 1247 default: 1248 video->color_depth = COLOR_8; 1249 break; 1250 } 1251 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 1252 video->color_space = COLOR_YCBCR444; 1253 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1254 video->color_space = COLOR_YCBCR422; 1255 else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444) 1256 video->color_space = COLOR_RGB; 1257 else 1258 video->color_space = COLOR_RGB; 1259 1260 /* 1261 * NOTE: those property parsing code is used for providing backward 1262 * compatibility for samsung platform. 1263 * Due to we used the "of_property_read_u32" interfaces, when this 1264 * property isn't present, the "video_info" can keep the original 1265 * values and wouldn't be modified. 1266 */ 1267 of_property_read_u32(dp_node, "samsung,color-space", 1268 &video->color_space); 1269 of_property_read_u32(dp_node, "samsung,dynamic-range", 1270 &video->dynamic_range); 1271 of_property_read_u32(dp_node, "samsung,ycbcr-coeff", 1272 &video->ycbcr_coeff); 1273 of_property_read_u32(dp_node, "samsung,color-depth", 1274 &video->color_depth); 1275 if (of_property_read_bool(dp_node, "hsync-active-high")) 1276 video->h_sync_polarity = true; 1277 if (of_property_read_bool(dp_node, "vsync-active-high")) 1278 video->v_sync_polarity = true; 1279 if (of_property_read_bool(dp_node, "interlaced")) 1280 video->interlaced = true; 1281 } 1282 1283 static void analogix_dp_bridge_nop(struct drm_bridge *bridge) 1284 { 1285 /* do nothing */ 1286 } 1287 1288 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = { 1289 .pre_enable = analogix_dp_bridge_pre_enable, 1290 .enable = analogix_dp_bridge_enable, 1291 .disable = analogix_dp_bridge_disable, 1292 .post_disable = analogix_dp_bridge_nop, 1293 .mode_set = analogix_dp_bridge_mode_set, 1294 .attach = analogix_dp_bridge_attach, 1295 }; 1296 1297 static int analogix_dp_create_bridge(struct drm_device *drm_dev, 1298 struct analogix_dp_device *dp) 1299 { 1300 struct drm_bridge *bridge; 1301 int ret; 1302 1303 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL); 1304 if (!bridge) { 1305 DRM_ERROR("failed to allocate for drm bridge\n"); 1306 return -ENOMEM; 1307 } 1308 1309 dp->bridge = bridge; 1310 1311 bridge->driver_private = dp; 1312 bridge->funcs = &analogix_dp_bridge_funcs; 1313 1314 ret = drm_bridge_attach(dp->encoder, bridge, NULL); 1315 if (ret) { 1316 DRM_ERROR("failed to attach drm bridge\n"); 1317 return -EINVAL; 1318 } 1319 1320 return 0; 1321 } 1322 1323 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) 1324 { 1325 struct device_node *dp_node = dp->dev->of_node; 1326 struct video_info *video_info = &dp->video_info; 1327 1328 switch (dp->plat_data->dev_type) { 1329 case RK3288_DP: 1330 case RK3399_EDP: 1331 /* 1332 * Like Rk3288 DisplayPort TRM indicate that "Main link 1333 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 1334 */ 1335 video_info->max_link_rate = 0x0A; 1336 video_info->max_lane_count = 0x04; 1337 break; 1338 case EXYNOS_DP: 1339 /* 1340 * NOTE: those property parseing code is used for 1341 * providing backward compatibility for samsung platform. 1342 */ 1343 of_property_read_u32(dp_node, "samsung,link-rate", 1344 &video_info->max_link_rate); 1345 of_property_read_u32(dp_node, "samsung,lane-count", 1346 &video_info->max_lane_count); 1347 break; 1348 } 1349 1350 return 0; 1351 } 1352 1353 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux, 1354 struct drm_dp_aux_msg *msg) 1355 { 1356 struct analogix_dp_device *dp = to_dp(aux); 1357 1358 return analogix_dp_transfer(dp, msg); 1359 } 1360 1361 struct analogix_dp_device * 1362 analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, 1363 struct analogix_dp_plat_data *plat_data) 1364 { 1365 struct platform_device *pdev = to_platform_device(dev); 1366 struct analogix_dp_device *dp; 1367 struct resource *res; 1368 unsigned int irq_flags; 1369 int ret; 1370 1371 if (!plat_data) { 1372 dev_err(dev, "Invalided input plat_data\n"); 1373 return ERR_PTR(-EINVAL); 1374 } 1375 1376 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL); 1377 if (!dp) 1378 return ERR_PTR(-ENOMEM); 1379 1380 dp->dev = &pdev->dev; 1381 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1382 1383 mutex_init(&dp->panel_lock); 1384 dp->panel_is_modeset = false; 1385 1386 /* 1387 * platform dp driver need containor_of the plat_data to get 1388 * the driver private data, so we need to store the point of 1389 * plat_data, not the context of plat_data. 1390 */ 1391 dp->plat_data = plat_data; 1392 1393 ret = analogix_dp_dt_parse_pdata(dp); 1394 if (ret) 1395 return ERR_PTR(ret); 1396 1397 dp->phy = devm_phy_get(dp->dev, "dp"); 1398 if (IS_ERR(dp->phy)) { 1399 dev_err(dp->dev, "no DP phy configured\n"); 1400 ret = PTR_ERR(dp->phy); 1401 if (ret) { 1402 /* 1403 * phy itself is not enabled, so we can move forward 1404 * assigning NULL to phy pointer. 1405 */ 1406 if (ret == -ENOSYS || ret == -ENODEV) 1407 dp->phy = NULL; 1408 else 1409 return ERR_PTR(ret); 1410 } 1411 } 1412 1413 dp->clock = devm_clk_get(&pdev->dev, "dp"); 1414 if (IS_ERR(dp->clock)) { 1415 dev_err(&pdev->dev, "failed to get clock\n"); 1416 return ERR_CAST(dp->clock); 1417 } 1418 1419 clk_prepare_enable(dp->clock); 1420 1421 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1422 1423 dp->reg_base = devm_ioremap_resource(&pdev->dev, res); 1424 if (IS_ERR(dp->reg_base)) 1425 return ERR_CAST(dp->reg_base); 1426 1427 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd"); 1428 1429 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0); 1430 if (!gpio_is_valid(dp->hpd_gpio)) 1431 dp->hpd_gpio = of_get_named_gpio(dev->of_node, 1432 "samsung,hpd-gpio", 0); 1433 1434 if (gpio_is_valid(dp->hpd_gpio)) { 1435 /* 1436 * Set up the hotplug GPIO from the device tree as an interrupt. 1437 * Simply specifying a different interrupt in the device tree 1438 * doesn't work since we handle hotplug rather differently when 1439 * using a GPIO. We also need the actual GPIO specifier so 1440 * that we can get the current state of the GPIO. 1441 */ 1442 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN, 1443 "hpd_gpio"); 1444 if (ret) { 1445 dev_err(&pdev->dev, "failed to get hpd gpio\n"); 1446 return ERR_PTR(ret); 1447 } 1448 dp->irq = gpio_to_irq(dp->hpd_gpio); 1449 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; 1450 } else { 1451 dp->hpd_gpio = -ENODEV; 1452 dp->irq = platform_get_irq(pdev, 0); 1453 irq_flags = 0; 1454 } 1455 1456 if (dp->irq == -ENXIO) { 1457 dev_err(&pdev->dev, "failed to get irq\n"); 1458 return ERR_PTR(-ENODEV); 1459 } 1460 1461 ret = devm_request_threaded_irq(&pdev->dev, dp->irq, 1462 analogix_dp_hardirq, 1463 analogix_dp_irq_thread, 1464 irq_flags, "analogix-dp", dp); 1465 if (ret) { 1466 dev_err(&pdev->dev, "failed to request irq\n"); 1467 goto err_disable_pm_runtime; 1468 } 1469 disable_irq(dp->irq); 1470 1471 dp->drm_dev = drm_dev; 1472 dp->encoder = dp->plat_data->encoder; 1473 1474 dp->aux.name = "DP-AUX"; 1475 dp->aux.transfer = analogix_dpaux_transfer; 1476 dp->aux.dev = &pdev->dev; 1477 1478 ret = drm_dp_aux_register(&dp->aux); 1479 if (ret) 1480 return ERR_PTR(ret); 1481 1482 pm_runtime_enable(dev); 1483 1484 ret = analogix_dp_create_bridge(drm_dev, dp); 1485 if (ret) { 1486 DRM_ERROR("failed to create bridge (%d)\n", ret); 1487 goto err_disable_pm_runtime; 1488 } 1489 1490 return dp; 1491 1492 err_disable_pm_runtime: 1493 1494 pm_runtime_disable(dev); 1495 1496 return ERR_PTR(ret); 1497 } 1498 EXPORT_SYMBOL_GPL(analogix_dp_bind); 1499 1500 void analogix_dp_unbind(struct analogix_dp_device *dp) 1501 { 1502 analogix_dp_bridge_disable(dp->bridge); 1503 dp->connector.funcs->destroy(&dp->connector); 1504 1505 if (dp->plat_data->panel) { 1506 if (drm_panel_unprepare(dp->plat_data->panel)) 1507 DRM_ERROR("failed to turnoff the panel\n"); 1508 if (drm_panel_detach(dp->plat_data->panel)) 1509 DRM_ERROR("failed to detach the panel\n"); 1510 } 1511 1512 drm_dp_aux_unregister(&dp->aux); 1513 pm_runtime_disable(dp->dev); 1514 clk_disable_unprepare(dp->clock); 1515 } 1516 EXPORT_SYMBOL_GPL(analogix_dp_unbind); 1517 1518 #ifdef CONFIG_PM 1519 int analogix_dp_suspend(struct analogix_dp_device *dp) 1520 { 1521 clk_disable_unprepare(dp->clock); 1522 1523 if (dp->plat_data->panel) { 1524 if (drm_panel_unprepare(dp->plat_data->panel)) 1525 DRM_ERROR("failed to turnoff the panel\n"); 1526 } 1527 1528 return 0; 1529 } 1530 EXPORT_SYMBOL_GPL(analogix_dp_suspend); 1531 1532 int analogix_dp_resume(struct analogix_dp_device *dp) 1533 { 1534 int ret; 1535 1536 ret = clk_prepare_enable(dp->clock); 1537 if (ret < 0) { 1538 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret); 1539 return ret; 1540 } 1541 1542 if (dp->plat_data->panel) { 1543 if (drm_panel_prepare(dp->plat_data->panel)) { 1544 DRM_ERROR("failed to setup the panel\n"); 1545 return -EBUSY; 1546 } 1547 } 1548 1549 return 0; 1550 } 1551 EXPORT_SYMBOL_GPL(analogix_dp_resume); 1552 #endif 1553 1554 int analogix_dp_start_crc(struct drm_connector *connector) 1555 { 1556 struct analogix_dp_device *dp = to_dp(connector); 1557 1558 if (!connector->state->crtc) { 1559 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n", 1560 connector->name); 1561 return -EINVAL; 1562 } 1563 1564 return drm_dp_start_crc(&dp->aux, connector->state->crtc); 1565 } 1566 EXPORT_SYMBOL_GPL(analogix_dp_start_crc); 1567 1568 int analogix_dp_stop_crc(struct drm_connector *connector) 1569 { 1570 struct analogix_dp_device *dp = to_dp(connector); 1571 1572 return drm_dp_stop_crc(&dp->aux); 1573 } 1574 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc); 1575 1576 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); 1577 MODULE_DESCRIPTION("Analogix DP Core Driver"); 1578 MODULE_LICENSE("GPL v2"); 1579