1 /* 2 * Analogix DP (Display Port) core interface driver. 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/interrupt.h> 20 #include <linux/of.h> 21 #include <linux/of_gpio.h> 22 #include <linux/gpio.h> 23 #include <linux/component.h> 24 #include <linux/phy/phy.h> 25 26 #include <drm/drmP.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_crtc.h> 29 #include <drm/drm_crtc_helper.h> 30 #include <drm/drm_panel.h> 31 32 #include <drm/bridge/analogix_dp.h> 33 34 #include "analogix_dp_core.h" 35 #include "analogix_dp_reg.h" 36 37 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm) 38 39 static const bool verify_fast_training; 40 41 struct bridge_init { 42 struct i2c_client *client; 43 struct device_node *node; 44 }; 45 46 static int analogix_dp_init_dp(struct analogix_dp_device *dp) 47 { 48 int ret; 49 50 analogix_dp_reset(dp); 51 52 analogix_dp_swreset(dp); 53 54 analogix_dp_init_analog_param(dp); 55 analogix_dp_init_interrupt(dp); 56 57 /* SW defined function Normal operation */ 58 analogix_dp_enable_sw_function(dp); 59 60 analogix_dp_config_interrupt(dp); 61 ret = analogix_dp_init_analog_func(dp); 62 if (ret) 63 return ret; 64 65 analogix_dp_init_hpd(dp); 66 analogix_dp_init_aux(dp); 67 return 0; 68 } 69 70 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp) 71 { 72 int timeout_loop = 0; 73 74 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) { 75 if (analogix_dp_get_plug_in_status(dp) == 0) 76 return 0; 77 78 timeout_loop++; 79 usleep_range(10, 11); 80 } 81 82 /* 83 * Some edp screen do not have hpd signal, so we can't just 84 * return failed when hpd plug in detect failed, DT property 85 * "force-hpd" would indicate whether driver need this. 86 */ 87 if (!dp->force_hpd) 88 return -ETIMEDOUT; 89 90 /* 91 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH 92 * will not work, so we need to give a force hpd action to 93 * set HPD_STATUS manually. 94 */ 95 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); 96 97 analogix_dp_force_hpd(dp); 98 99 if (analogix_dp_get_plug_in_status(dp) != 0) { 100 dev_err(dp->dev, "failed to get hpd plug in status\n"); 101 return -EINVAL; 102 } 103 104 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); 105 106 return 0; 107 } 108 109 int analogix_dp_psr_enabled(struct analogix_dp_device *dp) 110 { 111 112 return dp->psr_enable; 113 } 114 EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled); 115 116 int analogix_dp_enable_psr(struct analogix_dp_device *dp) 117 { 118 struct edp_vsc_psr psr_vsc; 119 120 if (!dp->psr_enable) 121 return 0; 122 123 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ 124 memset(&psr_vsc, 0, sizeof(psr_vsc)); 125 psr_vsc.sdp_header.HB0 = 0; 126 psr_vsc.sdp_header.HB1 = 0x7; 127 psr_vsc.sdp_header.HB2 = 0x2; 128 psr_vsc.sdp_header.HB3 = 0x8; 129 130 psr_vsc.DB0 = 0; 131 psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID; 132 133 return analogix_dp_send_psr_spd(dp, &psr_vsc, true); 134 } 135 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr); 136 137 int analogix_dp_disable_psr(struct analogix_dp_device *dp) 138 { 139 struct edp_vsc_psr psr_vsc; 140 int ret; 141 142 if (!dp->psr_enable) 143 return 0; 144 145 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ 146 memset(&psr_vsc, 0, sizeof(psr_vsc)); 147 psr_vsc.sdp_header.HB0 = 0; 148 psr_vsc.sdp_header.HB1 = 0x7; 149 psr_vsc.sdp_header.HB2 = 0x2; 150 psr_vsc.sdp_header.HB3 = 0x8; 151 152 psr_vsc.DB0 = 0; 153 psr_vsc.DB1 = 0; 154 155 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 156 if (ret != 1) 157 dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret); 158 159 return analogix_dp_send_psr_spd(dp, &psr_vsc, false); 160 } 161 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); 162 163 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) 164 { 165 unsigned char psr_version; 166 167 drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); 168 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); 169 170 return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; 171 } 172 173 static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) 174 { 175 unsigned char psr_en; 176 177 /* Disable psr function */ 178 drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en); 179 psr_en &= ~DP_PSR_ENABLE; 180 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 181 182 /* Main-Link transmitter remains active during PSR active states */ 183 psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; 184 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 185 186 /* Enable psr function */ 187 psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | 188 DP_PSR_CRC_VERIFICATION; 189 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 190 191 analogix_dp_enable_psr_crc(dp); 192 } 193 194 static void 195 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 196 bool enable) 197 { 198 u8 data; 199 200 drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 201 202 if (enable) 203 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 204 DP_LANE_COUNT_ENHANCED_FRAME_EN | 205 DPCD_LANE_COUNT_SET(data)); 206 else 207 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 208 DPCD_LANE_COUNT_SET(data)); 209 } 210 211 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 212 { 213 u8 data; 214 int retval; 215 216 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 217 retval = DPCD_ENHANCED_FRAME_CAP(data); 218 219 return retval; 220 } 221 222 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 223 { 224 u8 data; 225 226 data = analogix_dp_is_enhanced_mode_available(dp); 227 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 228 analogix_dp_enable_enhanced_mode(dp, data); 229 } 230 231 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 232 { 233 analogix_dp_set_training_pattern(dp, DP_NONE); 234 235 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 236 DP_TRAINING_PATTERN_DISABLE); 237 } 238 239 static void 240 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp, 241 int pre_emphasis, int lane) 242 { 243 switch (lane) { 244 case 0: 245 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis); 246 break; 247 case 1: 248 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis); 249 break; 250 251 case 2: 252 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis); 253 break; 254 255 case 3: 256 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis); 257 break; 258 } 259 } 260 261 static int analogix_dp_link_start(struct analogix_dp_device *dp) 262 { 263 u8 buf[4]; 264 int lane, lane_count, pll_tries, retval; 265 266 lane_count = dp->link_train.lane_count; 267 268 dp->link_train.lt_state = CLOCK_RECOVERY; 269 dp->link_train.eq_loop = 0; 270 271 for (lane = 0; lane < lane_count; lane++) 272 dp->link_train.cr_loop[lane] = 0; 273 274 /* Set link rate and count as you want to establish*/ 275 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 276 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 277 278 /* Setup RX configuration */ 279 buf[0] = dp->link_train.link_rate; 280 buf[1] = dp->link_train.lane_count; 281 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 282 if (retval < 0) 283 return retval; 284 285 /* Set TX pre-emphasis to minimum */ 286 for (lane = 0; lane < lane_count; lane++) 287 analogix_dp_set_lane_lane_pre_emphasis(dp, 288 PRE_EMPHASIS_LEVEL_0, lane); 289 290 /* Wait for PLL lock */ 291 pll_tries = 0; 292 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 293 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { 294 dev_err(dp->dev, "Wait for PLL lock timed out\n"); 295 return -ETIMEDOUT; 296 } 297 298 pll_tries++; 299 usleep_range(90, 120); 300 } 301 302 /* Set training pattern 1 */ 303 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 304 305 /* Set RX training pattern */ 306 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 307 DP_LINK_SCRAMBLING_DISABLE | 308 DP_TRAINING_PATTERN_1); 309 if (retval < 0) 310 return retval; 311 312 for (lane = 0; lane < lane_count; lane++) 313 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 314 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 315 316 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 317 lane_count); 318 if (retval < 0) 319 return retval; 320 321 return 0; 322 } 323 324 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 325 { 326 int shift = (lane & 1) * 4; 327 u8 link_value = link_status[lane >> 1]; 328 329 return (link_value >> shift) & 0xf; 330 } 331 332 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 333 { 334 int lane; 335 u8 lane_status; 336 337 for (lane = 0; lane < lane_count; lane++) { 338 lane_status = analogix_dp_get_lane_status(link_status, lane); 339 if ((lane_status & DP_LANE_CR_DONE) == 0) 340 return -EINVAL; 341 } 342 return 0; 343 } 344 345 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 346 int lane_count) 347 { 348 int lane; 349 u8 lane_status; 350 351 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 352 return -EINVAL; 353 354 for (lane = 0; lane < lane_count; lane++) { 355 lane_status = analogix_dp_get_lane_status(link_status, lane); 356 lane_status &= DP_CHANNEL_EQ_BITS; 357 if (lane_status != DP_CHANNEL_EQ_BITS) 358 return -EINVAL; 359 } 360 361 return 0; 362 } 363 364 static unsigned char 365 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 366 { 367 int shift = (lane & 1) * 4; 368 u8 link_value = adjust_request[lane >> 1]; 369 370 return (link_value >> shift) & 0x3; 371 } 372 373 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 374 u8 adjust_request[2], 375 int lane) 376 { 377 int shift = (lane & 1) * 4; 378 u8 link_value = adjust_request[lane >> 1]; 379 380 return ((link_value >> shift) & 0xc) >> 2; 381 } 382 383 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp, 384 u8 training_lane_set, int lane) 385 { 386 switch (lane) { 387 case 0: 388 analogix_dp_set_lane0_link_training(dp, training_lane_set); 389 break; 390 case 1: 391 analogix_dp_set_lane1_link_training(dp, training_lane_set); 392 break; 393 394 case 2: 395 analogix_dp_set_lane2_link_training(dp, training_lane_set); 396 break; 397 398 case 3: 399 analogix_dp_set_lane3_link_training(dp, training_lane_set); 400 break; 401 } 402 } 403 404 static unsigned int 405 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, 406 int lane) 407 { 408 u32 reg; 409 410 switch (lane) { 411 case 0: 412 reg = analogix_dp_get_lane0_link_training(dp); 413 break; 414 case 1: 415 reg = analogix_dp_get_lane1_link_training(dp); 416 break; 417 case 2: 418 reg = analogix_dp_get_lane2_link_training(dp); 419 break; 420 case 3: 421 reg = analogix_dp_get_lane3_link_training(dp); 422 break; 423 default: 424 WARN_ON(1); 425 return 0; 426 } 427 428 return reg; 429 } 430 431 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 432 { 433 analogix_dp_training_pattern_dis(dp); 434 analogix_dp_set_enhanced_mode(dp); 435 436 dp->link_train.lt_state = FAILED; 437 } 438 439 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 440 u8 adjust_request[2]) 441 { 442 int lane, lane_count; 443 u8 voltage_swing, pre_emphasis, training_lane; 444 445 lane_count = dp->link_train.lane_count; 446 for (lane = 0; lane < lane_count; lane++) { 447 voltage_swing = analogix_dp_get_adjust_request_voltage( 448 adjust_request, lane); 449 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 450 adjust_request, lane); 451 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 452 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 453 454 if (voltage_swing == VOLTAGE_LEVEL_3) 455 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 456 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 457 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 458 459 dp->link_train.training_lane[lane] = training_lane; 460 } 461 } 462 463 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 464 { 465 int lane, lane_count, retval; 466 u8 voltage_swing, pre_emphasis, training_lane; 467 u8 link_status[2], adjust_request[2]; 468 469 usleep_range(100, 101); 470 471 lane_count = dp->link_train.lane_count; 472 473 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 474 if (retval < 0) 475 return retval; 476 477 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 478 adjust_request, 2); 479 if (retval < 0) 480 return retval; 481 482 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 483 /* set training pattern 2 for EQ */ 484 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 485 486 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 487 DP_LINK_SCRAMBLING_DISABLE | 488 DP_TRAINING_PATTERN_2); 489 if (retval < 0) 490 return retval; 491 492 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 493 dp->link_train.lt_state = EQUALIZER_TRAINING; 494 } else { 495 for (lane = 0; lane < lane_count; lane++) { 496 training_lane = analogix_dp_get_lane_link_training( 497 dp, lane); 498 voltage_swing = analogix_dp_get_adjust_request_voltage( 499 adjust_request, lane); 500 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 501 adjust_request, lane); 502 503 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 504 voltage_swing && 505 DPCD_PRE_EMPHASIS_GET(training_lane) == 506 pre_emphasis) 507 dp->link_train.cr_loop[lane]++; 508 509 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 510 voltage_swing == VOLTAGE_LEVEL_3 || 511 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 512 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 513 dp->link_train.cr_loop[lane], 514 voltage_swing, pre_emphasis); 515 analogix_dp_reduce_link_rate(dp); 516 return -EIO; 517 } 518 } 519 } 520 521 analogix_dp_get_adjust_training_lane(dp, adjust_request); 522 523 for (lane = 0; lane < lane_count; lane++) 524 analogix_dp_set_lane_link_training(dp, 525 dp->link_train.training_lane[lane], lane); 526 527 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 528 dp->link_train.training_lane, lane_count); 529 if (retval < 0) 530 return retval; 531 532 return 0; 533 } 534 535 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 536 { 537 int lane, lane_count, retval; 538 u32 reg; 539 u8 link_align, link_status[2], adjust_request[2], spread; 540 541 usleep_range(400, 401); 542 543 lane_count = dp->link_train.lane_count; 544 545 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 546 if (retval < 0) 547 return retval; 548 549 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 550 analogix_dp_reduce_link_rate(dp); 551 return -EIO; 552 } 553 554 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 555 adjust_request, 2); 556 if (retval < 0) 557 return retval; 558 559 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, 560 &link_align); 561 if (retval < 0) 562 return retval; 563 564 analogix_dp_get_adjust_training_lane(dp, adjust_request); 565 566 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 567 /* traing pattern Set to Normal */ 568 analogix_dp_training_pattern_dis(dp); 569 570 dev_info(dp->dev, "Link Training success!\n"); 571 572 analogix_dp_get_link_bandwidth(dp, ®); 573 dp->link_train.link_rate = reg; 574 dev_dbg(dp->dev, "final bandwidth = %.2x\n", 575 dp->link_train.link_rate); 576 577 analogix_dp_get_lane_count(dp, ®); 578 dp->link_train.lane_count = reg; 579 dev_dbg(dp->dev, "final lane count = %.2x\n", 580 dp->link_train.lane_count); 581 582 retval = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, 583 &spread); 584 if (retval != 1) { 585 dev_err(dp->dev, "failed to read downspread %d\n", 586 retval); 587 dp->fast_train_enable = false; 588 } else { 589 dp->fast_train_enable = 590 (spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ? 591 true : false; 592 } 593 dev_dbg(dp->dev, "fast link training %s\n", 594 dp->fast_train_enable ? "supported" : "unsupported"); 595 596 /* set enhanced mode if available */ 597 analogix_dp_set_enhanced_mode(dp); 598 dp->link_train.lt_state = FINISHED; 599 600 return 0; 601 } 602 603 /* not all locked */ 604 dp->link_train.eq_loop++; 605 606 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 607 dev_err(dp->dev, "EQ Max loop\n"); 608 analogix_dp_reduce_link_rate(dp); 609 return -EIO; 610 } 611 612 for (lane = 0; lane < lane_count; lane++) 613 analogix_dp_set_lane_link_training(dp, 614 dp->link_train.training_lane[lane], lane); 615 616 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 617 dp->link_train.training_lane, lane_count); 618 if (retval < 0) 619 return retval; 620 621 return 0; 622 } 623 624 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 625 u8 *bandwidth) 626 { 627 u8 data; 628 629 /* 630 * For DP rev.1.1, Maximum link rate of Main Link lanes 631 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 632 * For DP rev.1.2, Maximum link rate of Main Link lanes 633 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 634 */ 635 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 636 *bandwidth = data; 637 } 638 639 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 640 u8 *lane_count) 641 { 642 u8 data; 643 644 /* 645 * For DP rev.1.1, Maximum number of Main Link lanes 646 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 647 */ 648 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 649 *lane_count = DPCD_MAX_LANE_COUNT(data); 650 } 651 652 static int analogix_dp_full_link_train(struct analogix_dp_device *dp, 653 u32 max_lanes, u32 max_rate) 654 { 655 int retval = 0; 656 bool training_finished = false; 657 658 /* 659 * MACRO_RST must be applied after the PLL_LOCK to avoid 660 * the DP inter pair skew issue for at least 10 us 661 */ 662 analogix_dp_reset_macro(dp); 663 664 /* Initialize by reading RX's DPCD */ 665 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 666 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 667 668 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 669 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 670 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 671 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", 672 dp->link_train.link_rate); 673 dp->link_train.link_rate = DP_LINK_BW_1_62; 674 } 675 676 if (dp->link_train.lane_count == 0) { 677 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", 678 dp->link_train.lane_count); 679 dp->link_train.lane_count = (u8)LANE_COUNT1; 680 } 681 682 /* Setup TX lane count & rate */ 683 if (dp->link_train.lane_count > max_lanes) 684 dp->link_train.lane_count = max_lanes; 685 if (dp->link_train.link_rate > max_rate) 686 dp->link_train.link_rate = max_rate; 687 688 /* All DP analog module power up */ 689 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 690 691 dp->link_train.lt_state = START; 692 693 /* Process here */ 694 while (!retval && !training_finished) { 695 switch (dp->link_train.lt_state) { 696 case START: 697 retval = analogix_dp_link_start(dp); 698 if (retval) 699 dev_err(dp->dev, "LT link start failed!\n"); 700 break; 701 case CLOCK_RECOVERY: 702 retval = analogix_dp_process_clock_recovery(dp); 703 if (retval) 704 dev_err(dp->dev, "LT CR failed!\n"); 705 break; 706 case EQUALIZER_TRAINING: 707 retval = analogix_dp_process_equalizer_training(dp); 708 if (retval) 709 dev_err(dp->dev, "LT EQ failed!\n"); 710 break; 711 case FINISHED: 712 training_finished = 1; 713 break; 714 case FAILED: 715 return -EREMOTEIO; 716 } 717 } 718 if (retval) 719 dev_err(dp->dev, "eDP link training failed (%d)\n", retval); 720 721 return retval; 722 } 723 724 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp) 725 { 726 int i, ret; 727 u8 link_align, link_status[2]; 728 enum pll_status status; 729 730 analogix_dp_reset_macro(dp); 731 732 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 733 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 734 735 for (i = 0; i < dp->link_train.lane_count; i++) { 736 analogix_dp_set_lane_link_training(dp, 737 dp->link_train.training_lane[i], i); 738 } 739 740 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status, 741 status != PLL_UNLOCKED, 120, 742 120 * DP_TIMEOUT_LOOP_COUNT); 743 if (ret) { 744 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret); 745 return ret; 746 } 747 748 /* source Set training pattern 1 */ 749 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 750 /* From DP spec, pattern must be on-screen for a minimum 500us */ 751 usleep_range(500, 600); 752 753 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 754 /* From DP spec, pattern must be on-screen for a minimum 500us */ 755 usleep_range(500, 600); 756 757 /* TODO: enhanced_mode?*/ 758 analogix_dp_set_training_pattern(dp, DP_NONE); 759 760 /* 761 * Useful for debugging issues with fast link training, disable for more 762 * speed 763 */ 764 if (verify_fast_training) { 765 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, 766 &link_align); 767 if (ret < 0) { 768 DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n", 769 ret); 770 return ret; 771 } 772 773 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 774 2); 775 if (ret < 0) { 776 DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n", 777 ret); 778 return ret; 779 } 780 781 if (analogix_dp_clock_recovery_ok(link_status, 782 dp->link_train.lane_count)) { 783 DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n"); 784 analogix_dp_reduce_link_rate(dp); 785 return -EIO; 786 } 787 788 if (analogix_dp_channel_eq_ok(link_status, link_align, 789 dp->link_train.lane_count)) { 790 DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n"); 791 analogix_dp_reduce_link_rate(dp); 792 return -EIO; 793 } 794 } 795 796 return 0; 797 } 798 799 static int analogix_dp_train_link(struct analogix_dp_device *dp) 800 { 801 if (dp->fast_train_enable) 802 return analogix_dp_fast_link_train(dp); 803 804 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count, 805 dp->video_info.max_link_rate); 806 } 807 808 static int analogix_dp_config_video(struct analogix_dp_device *dp) 809 { 810 int timeout_loop = 0; 811 int done_count = 0; 812 813 analogix_dp_config_video_slave_mode(dp); 814 815 analogix_dp_set_video_color_format(dp); 816 817 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 818 dev_err(dp->dev, "PLL is not locked yet.\n"); 819 return -EINVAL; 820 } 821 822 for (;;) { 823 timeout_loop++; 824 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 825 break; 826 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 827 dev_err(dp->dev, "Timeout of slave video streamclk ok\n"); 828 return -ETIMEDOUT; 829 } 830 usleep_range(1000, 1001); 831 } 832 833 /* Set to use the register calculated M/N video */ 834 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 835 836 /* For video bist, Video timing must be generated by register */ 837 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 838 839 /* Disable video mute */ 840 analogix_dp_enable_video_mute(dp, 0); 841 842 /* Configure video slave mode */ 843 analogix_dp_enable_video_master(dp, 0); 844 845 /* Enable video */ 846 analogix_dp_start_video(dp); 847 848 timeout_loop = 0; 849 850 for (;;) { 851 timeout_loop++; 852 if (analogix_dp_is_video_stream_on(dp) == 0) { 853 done_count++; 854 if (done_count > 10) 855 break; 856 } else if (done_count) { 857 done_count = 0; 858 } 859 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 860 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 861 return -ETIMEDOUT; 862 } 863 864 usleep_range(1000, 1001); 865 } 866 867 return 0; 868 } 869 870 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 871 bool enable) 872 { 873 u8 data; 874 875 if (enable) { 876 analogix_dp_enable_scrambling(dp); 877 878 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); 879 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 880 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 881 } else { 882 analogix_dp_disable_scrambling(dp); 883 884 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); 885 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 886 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 887 } 888 } 889 890 static irqreturn_t analogix_dp_hardirq(int irq, void *arg) 891 { 892 struct analogix_dp_device *dp = arg; 893 irqreturn_t ret = IRQ_NONE; 894 enum dp_irq_type irq_type; 895 896 irq_type = analogix_dp_get_irq_type(dp); 897 if (irq_type != DP_IRQ_TYPE_UNKNOWN) { 898 analogix_dp_mute_hpd_interrupt(dp); 899 ret = IRQ_WAKE_THREAD; 900 } 901 902 return ret; 903 } 904 905 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg) 906 { 907 struct analogix_dp_device *dp = arg; 908 enum dp_irq_type irq_type; 909 910 irq_type = analogix_dp_get_irq_type(dp); 911 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN || 912 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) { 913 dev_dbg(dp->dev, "Detected cable status changed!\n"); 914 if (dp->drm_dev) 915 drm_helper_hpd_irq_event(dp->drm_dev); 916 } 917 918 if (irq_type != DP_IRQ_TYPE_UNKNOWN) { 919 analogix_dp_clear_hotplug_interrupts(dp); 920 analogix_dp_unmute_hpd_interrupt(dp); 921 } 922 923 return IRQ_HANDLED; 924 } 925 926 static int analogix_dp_commit(struct analogix_dp_device *dp) 927 { 928 int ret; 929 930 /* Keep the panel disabled while we configure video */ 931 if (dp->plat_data->panel) { 932 if (drm_panel_disable(dp->plat_data->panel)) 933 DRM_ERROR("failed to disable the panel\n"); 934 } 935 936 ret = analogix_dp_train_link(dp); 937 if (ret) { 938 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret); 939 return ret; 940 } 941 942 analogix_dp_enable_scramble(dp, 1); 943 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 944 analogix_dp_enable_enhanced_mode(dp, 1); 945 946 analogix_dp_init_video(dp); 947 ret = analogix_dp_config_video(dp); 948 if (ret) 949 dev_err(dp->dev, "unable to config video\n"); 950 951 /* Safe to enable the panel now */ 952 if (dp->plat_data->panel) { 953 if (drm_panel_enable(dp->plat_data->panel)) 954 DRM_ERROR("failed to enable the panel\n"); 955 } 956 957 dp->psr_enable = analogix_dp_detect_sink_psr(dp); 958 if (dp->psr_enable) 959 analogix_dp_enable_sink_psr(dp); 960 return 0; 961 } 962 963 /* 964 * This function is a bit of a catch-all for panel preparation, hopefully 965 * simplifying the logic of functions that need to prepare/unprepare the panel 966 * below. 967 * 968 * If @prepare is true, this function will prepare the panel. Conversely, if it 969 * is false, the panel will be unprepared. 970 * 971 * If @is_modeset_prepare is true, the function will disregard the current state 972 * of the panel and either prepare/unprepare the panel based on @prepare. Once 973 * it finishes, it will update dp->panel_is_modeset to reflect the current state 974 * of the panel. 975 */ 976 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp, 977 bool prepare, bool is_modeset_prepare) 978 { 979 int ret = 0; 980 981 if (!dp->plat_data->panel) 982 return 0; 983 984 mutex_lock(&dp->panel_lock); 985 986 /* 987 * Exit early if this is a temporary prepare/unprepare and we're already 988 * modeset (since we neither want to prepare twice or unprepare early). 989 */ 990 if (dp->panel_is_modeset && !is_modeset_prepare) 991 goto out; 992 993 if (prepare) 994 ret = drm_panel_prepare(dp->plat_data->panel); 995 else 996 ret = drm_panel_unprepare(dp->plat_data->panel); 997 998 if (ret) 999 goto out; 1000 1001 if (is_modeset_prepare) 1002 dp->panel_is_modeset = prepare; 1003 1004 out: 1005 mutex_unlock(&dp->panel_lock); 1006 return ret; 1007 } 1008 1009 static int analogix_dp_get_modes(struct drm_connector *connector) 1010 { 1011 struct analogix_dp_device *dp = to_dp(connector); 1012 struct edid *edid; 1013 int ret, num_modes = 0; 1014 1015 if (dp->plat_data->panel) { 1016 num_modes += drm_panel_get_modes(dp->plat_data->panel); 1017 } else { 1018 ret = analogix_dp_prepare_panel(dp, true, false); 1019 if (ret) { 1020 DRM_ERROR("Failed to prepare panel (%d)\n", ret); 1021 return 0; 1022 } 1023 1024 pm_runtime_get_sync(dp->dev); 1025 edid = drm_get_edid(connector, &dp->aux.ddc); 1026 pm_runtime_put(dp->dev); 1027 if (edid) { 1028 drm_mode_connector_update_edid_property(&dp->connector, 1029 edid); 1030 num_modes += drm_add_edid_modes(&dp->connector, edid); 1031 kfree(edid); 1032 } 1033 1034 ret = analogix_dp_prepare_panel(dp, false, false); 1035 if (ret) 1036 DRM_ERROR("Failed to unprepare panel (%d)\n", ret); 1037 } 1038 1039 if (dp->plat_data->get_modes) 1040 num_modes += dp->plat_data->get_modes(dp->plat_data, connector); 1041 1042 return num_modes; 1043 } 1044 1045 static struct drm_encoder * 1046 analogix_dp_best_encoder(struct drm_connector *connector) 1047 { 1048 struct analogix_dp_device *dp = to_dp(connector); 1049 1050 return dp->encoder; 1051 } 1052 1053 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = { 1054 .get_modes = analogix_dp_get_modes, 1055 .best_encoder = analogix_dp_best_encoder, 1056 }; 1057 1058 static enum drm_connector_status 1059 analogix_dp_detect(struct drm_connector *connector, bool force) 1060 { 1061 struct analogix_dp_device *dp = to_dp(connector); 1062 enum drm_connector_status status = connector_status_disconnected; 1063 int ret; 1064 1065 if (dp->plat_data->panel) 1066 return connector_status_connected; 1067 1068 ret = analogix_dp_prepare_panel(dp, true, false); 1069 if (ret) { 1070 DRM_ERROR("Failed to prepare panel (%d)\n", ret); 1071 return connector_status_disconnected; 1072 } 1073 1074 if (!analogix_dp_detect_hpd(dp)) 1075 status = connector_status_connected; 1076 1077 ret = analogix_dp_prepare_panel(dp, false, false); 1078 if (ret) 1079 DRM_ERROR("Failed to unprepare panel (%d)\n", ret); 1080 1081 return status; 1082 } 1083 1084 static const struct drm_connector_funcs analogix_dp_connector_funcs = { 1085 .fill_modes = drm_helper_probe_single_connector_modes, 1086 .detect = analogix_dp_detect, 1087 .destroy = drm_connector_cleanup, 1088 .reset = drm_atomic_helper_connector_reset, 1089 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1090 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1091 }; 1092 1093 static int analogix_dp_bridge_attach(struct drm_bridge *bridge) 1094 { 1095 struct analogix_dp_device *dp = bridge->driver_private; 1096 struct drm_encoder *encoder = dp->encoder; 1097 struct drm_connector *connector = NULL; 1098 int ret = 0; 1099 1100 if (!bridge->encoder) { 1101 DRM_ERROR("Parent encoder object not found"); 1102 return -ENODEV; 1103 } 1104 1105 if (!dp->plat_data->skip_connector) { 1106 connector = &dp->connector; 1107 connector->polled = DRM_CONNECTOR_POLL_HPD; 1108 1109 ret = drm_connector_init(dp->drm_dev, connector, 1110 &analogix_dp_connector_funcs, 1111 DRM_MODE_CONNECTOR_eDP); 1112 if (ret) { 1113 DRM_ERROR("Failed to initialize connector with drm\n"); 1114 return ret; 1115 } 1116 1117 drm_connector_helper_add(connector, 1118 &analogix_dp_connector_helper_funcs); 1119 drm_mode_connector_attach_encoder(connector, encoder); 1120 } 1121 1122 /* 1123 * NOTE: the connector registration is implemented in analogix 1124 * platform driver, that to say connector would be exist after 1125 * plat_data->attch return, that's why we record the connector 1126 * point after plat attached. 1127 */ 1128 if (dp->plat_data->attach) { 1129 ret = dp->plat_data->attach(dp->plat_data, bridge, connector); 1130 if (ret) { 1131 DRM_ERROR("Failed at platform attch func\n"); 1132 return ret; 1133 } 1134 } 1135 1136 if (dp->plat_data->panel) { 1137 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector); 1138 if (ret) { 1139 DRM_ERROR("Failed to attach panel\n"); 1140 return ret; 1141 } 1142 } 1143 1144 return 0; 1145 } 1146 1147 static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge) 1148 { 1149 struct analogix_dp_device *dp = bridge->driver_private; 1150 int ret; 1151 1152 ret = analogix_dp_prepare_panel(dp, true, true); 1153 if (ret) 1154 DRM_ERROR("failed to setup the panel ret = %d\n", ret); 1155 } 1156 1157 static int analogix_dp_set_bridge(struct analogix_dp_device *dp) 1158 { 1159 int ret; 1160 1161 pm_runtime_get_sync(dp->dev); 1162 1163 if (dp->plat_data->power_on) 1164 dp->plat_data->power_on(dp->plat_data); 1165 1166 phy_power_on(dp->phy); 1167 1168 ret = analogix_dp_init_dp(dp); 1169 if (ret) 1170 goto out_dp_init; 1171 1172 ret = analogix_dp_commit(dp); 1173 if (ret) 1174 goto out_dp_init; 1175 1176 enable_irq(dp->irq); 1177 return 0; 1178 1179 out_dp_init: 1180 phy_power_off(dp->phy); 1181 if (dp->plat_data->power_off) 1182 dp->plat_data->power_off(dp->plat_data); 1183 pm_runtime_put_sync(dp->dev); 1184 1185 return ret; 1186 } 1187 1188 static void analogix_dp_bridge_enable(struct drm_bridge *bridge) 1189 { 1190 struct analogix_dp_device *dp = bridge->driver_private; 1191 int timeout_loop = 0; 1192 1193 if (dp->dpms_mode == DRM_MODE_DPMS_ON) 1194 return; 1195 1196 while (timeout_loop < MAX_PLL_LOCK_LOOP) { 1197 if (analogix_dp_set_bridge(dp) == 0) { 1198 dp->dpms_mode = DRM_MODE_DPMS_ON; 1199 return; 1200 } 1201 dev_err(dp->dev, "failed to set bridge, retry: %d\n", 1202 timeout_loop); 1203 timeout_loop++; 1204 usleep_range(10, 11); 1205 } 1206 dev_err(dp->dev, "too many times retry set bridge, give it up\n"); 1207 } 1208 1209 static void analogix_dp_bridge_disable(struct drm_bridge *bridge) 1210 { 1211 struct analogix_dp_device *dp = bridge->driver_private; 1212 int ret; 1213 1214 if (dp->dpms_mode != DRM_MODE_DPMS_ON) 1215 return; 1216 1217 if (dp->plat_data->panel) { 1218 if (drm_panel_disable(dp->plat_data->panel)) { 1219 DRM_ERROR("failed to disable the panel\n"); 1220 return; 1221 } 1222 } 1223 1224 disable_irq(dp->irq); 1225 phy_power_off(dp->phy); 1226 1227 if (dp->plat_data->power_off) 1228 dp->plat_data->power_off(dp->plat_data); 1229 1230 pm_runtime_put_sync(dp->dev); 1231 1232 ret = analogix_dp_prepare_panel(dp, false, true); 1233 if (ret) 1234 DRM_ERROR("failed to setup the panel ret = %d\n", ret); 1235 1236 dp->psr_enable = false; 1237 dp->fast_train_enable = false; 1238 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1239 } 1240 1241 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, 1242 struct drm_display_mode *orig_mode, 1243 struct drm_display_mode *mode) 1244 { 1245 struct analogix_dp_device *dp = bridge->driver_private; 1246 struct drm_display_info *display_info = &dp->connector.display_info; 1247 struct video_info *video = &dp->video_info; 1248 struct device_node *dp_node = dp->dev->of_node; 1249 int vic; 1250 1251 /* Input video interlaces & hsync pol & vsync pol */ 1252 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 1253 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); 1254 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); 1255 1256 /* Input video dynamic_range & colorimetry */ 1257 vic = drm_match_cea_mode(mode); 1258 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || 1259 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) { 1260 video->dynamic_range = CEA; 1261 video->ycbcr_coeff = COLOR_YCBCR601; 1262 } else if (vic) { 1263 video->dynamic_range = CEA; 1264 video->ycbcr_coeff = COLOR_YCBCR709; 1265 } else { 1266 video->dynamic_range = VESA; 1267 video->ycbcr_coeff = COLOR_YCBCR709; 1268 } 1269 1270 /* Input vide bpc and color_formats */ 1271 switch (display_info->bpc) { 1272 case 12: 1273 video->color_depth = COLOR_12; 1274 break; 1275 case 10: 1276 video->color_depth = COLOR_10; 1277 break; 1278 case 8: 1279 video->color_depth = COLOR_8; 1280 break; 1281 case 6: 1282 video->color_depth = COLOR_6; 1283 break; 1284 default: 1285 video->color_depth = COLOR_8; 1286 break; 1287 } 1288 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 1289 video->color_space = COLOR_YCBCR444; 1290 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1291 video->color_space = COLOR_YCBCR422; 1292 else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444) 1293 video->color_space = COLOR_RGB; 1294 else 1295 video->color_space = COLOR_RGB; 1296 1297 /* 1298 * NOTE: those property parsing code is used for providing backward 1299 * compatibility for samsung platform. 1300 * Due to we used the "of_property_read_u32" interfaces, when this 1301 * property isn't present, the "video_info" can keep the original 1302 * values and wouldn't be modified. 1303 */ 1304 of_property_read_u32(dp_node, "samsung,color-space", 1305 &video->color_space); 1306 of_property_read_u32(dp_node, "samsung,dynamic-range", 1307 &video->dynamic_range); 1308 of_property_read_u32(dp_node, "samsung,ycbcr-coeff", 1309 &video->ycbcr_coeff); 1310 of_property_read_u32(dp_node, "samsung,color-depth", 1311 &video->color_depth); 1312 if (of_property_read_bool(dp_node, "hsync-active-high")) 1313 video->h_sync_polarity = true; 1314 if (of_property_read_bool(dp_node, "vsync-active-high")) 1315 video->v_sync_polarity = true; 1316 if (of_property_read_bool(dp_node, "interlaced")) 1317 video->interlaced = true; 1318 } 1319 1320 static void analogix_dp_bridge_nop(struct drm_bridge *bridge) 1321 { 1322 /* do nothing */ 1323 } 1324 1325 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = { 1326 .pre_enable = analogix_dp_bridge_pre_enable, 1327 .enable = analogix_dp_bridge_enable, 1328 .disable = analogix_dp_bridge_disable, 1329 .post_disable = analogix_dp_bridge_nop, 1330 .mode_set = analogix_dp_bridge_mode_set, 1331 .attach = analogix_dp_bridge_attach, 1332 }; 1333 1334 static int analogix_dp_create_bridge(struct drm_device *drm_dev, 1335 struct analogix_dp_device *dp) 1336 { 1337 struct drm_bridge *bridge; 1338 int ret; 1339 1340 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL); 1341 if (!bridge) { 1342 DRM_ERROR("failed to allocate for drm bridge\n"); 1343 return -ENOMEM; 1344 } 1345 1346 dp->bridge = bridge; 1347 1348 bridge->driver_private = dp; 1349 bridge->funcs = &analogix_dp_bridge_funcs; 1350 1351 ret = drm_bridge_attach(dp->encoder, bridge, NULL); 1352 if (ret) { 1353 DRM_ERROR("failed to attach drm bridge\n"); 1354 return -EINVAL; 1355 } 1356 1357 return 0; 1358 } 1359 1360 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) 1361 { 1362 struct device_node *dp_node = dp->dev->of_node; 1363 struct video_info *video_info = &dp->video_info; 1364 1365 switch (dp->plat_data->dev_type) { 1366 case RK3288_DP: 1367 case RK3399_EDP: 1368 /* 1369 * Like Rk3288 DisplayPort TRM indicate that "Main link 1370 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 1371 */ 1372 video_info->max_link_rate = 0x0A; 1373 video_info->max_lane_count = 0x04; 1374 break; 1375 case EXYNOS_DP: 1376 /* 1377 * NOTE: those property parseing code is used for 1378 * providing backward compatibility for samsung platform. 1379 */ 1380 of_property_read_u32(dp_node, "samsung,link-rate", 1381 &video_info->max_link_rate); 1382 of_property_read_u32(dp_node, "samsung,lane-count", 1383 &video_info->max_lane_count); 1384 break; 1385 } 1386 1387 return 0; 1388 } 1389 1390 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux, 1391 struct drm_dp_aux_msg *msg) 1392 { 1393 struct analogix_dp_device *dp = to_dp(aux); 1394 1395 return analogix_dp_transfer(dp, msg); 1396 } 1397 1398 struct analogix_dp_device * 1399 analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, 1400 struct analogix_dp_plat_data *plat_data) 1401 { 1402 struct platform_device *pdev = to_platform_device(dev); 1403 struct analogix_dp_device *dp; 1404 struct resource *res; 1405 unsigned int irq_flags; 1406 int ret; 1407 1408 if (!plat_data) { 1409 dev_err(dev, "Invalided input plat_data\n"); 1410 return ERR_PTR(-EINVAL); 1411 } 1412 1413 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL); 1414 if (!dp) 1415 return ERR_PTR(-ENOMEM); 1416 1417 dp->dev = &pdev->dev; 1418 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1419 1420 mutex_init(&dp->panel_lock); 1421 dp->panel_is_modeset = false; 1422 1423 /* 1424 * platform dp driver need containor_of the plat_data to get 1425 * the driver private data, so we need to store the point of 1426 * plat_data, not the context of plat_data. 1427 */ 1428 dp->plat_data = plat_data; 1429 1430 ret = analogix_dp_dt_parse_pdata(dp); 1431 if (ret) 1432 return ERR_PTR(ret); 1433 1434 dp->phy = devm_phy_get(dp->dev, "dp"); 1435 if (IS_ERR(dp->phy)) { 1436 dev_err(dp->dev, "no DP phy configured\n"); 1437 ret = PTR_ERR(dp->phy); 1438 if (ret) { 1439 /* 1440 * phy itself is not enabled, so we can move forward 1441 * assigning NULL to phy pointer. 1442 */ 1443 if (ret == -ENOSYS || ret == -ENODEV) 1444 dp->phy = NULL; 1445 else 1446 return ERR_PTR(ret); 1447 } 1448 } 1449 1450 dp->clock = devm_clk_get(&pdev->dev, "dp"); 1451 if (IS_ERR(dp->clock)) { 1452 dev_err(&pdev->dev, "failed to get clock\n"); 1453 return ERR_CAST(dp->clock); 1454 } 1455 1456 clk_prepare_enable(dp->clock); 1457 1458 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1459 1460 dp->reg_base = devm_ioremap_resource(&pdev->dev, res); 1461 if (IS_ERR(dp->reg_base)) 1462 return ERR_CAST(dp->reg_base); 1463 1464 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd"); 1465 1466 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0); 1467 if (!gpio_is_valid(dp->hpd_gpio)) 1468 dp->hpd_gpio = of_get_named_gpio(dev->of_node, 1469 "samsung,hpd-gpio", 0); 1470 1471 if (gpio_is_valid(dp->hpd_gpio)) { 1472 /* 1473 * Set up the hotplug GPIO from the device tree as an interrupt. 1474 * Simply specifying a different interrupt in the device tree 1475 * doesn't work since we handle hotplug rather differently when 1476 * using a GPIO. We also need the actual GPIO specifier so 1477 * that we can get the current state of the GPIO. 1478 */ 1479 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN, 1480 "hpd_gpio"); 1481 if (ret) { 1482 dev_err(&pdev->dev, "failed to get hpd gpio\n"); 1483 return ERR_PTR(ret); 1484 } 1485 dp->irq = gpio_to_irq(dp->hpd_gpio); 1486 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; 1487 } else { 1488 dp->hpd_gpio = -ENODEV; 1489 dp->irq = platform_get_irq(pdev, 0); 1490 irq_flags = 0; 1491 } 1492 1493 if (dp->irq == -ENXIO) { 1494 dev_err(&pdev->dev, "failed to get irq\n"); 1495 return ERR_PTR(-ENODEV); 1496 } 1497 1498 ret = devm_request_threaded_irq(&pdev->dev, dp->irq, 1499 analogix_dp_hardirq, 1500 analogix_dp_irq_thread, 1501 irq_flags, "analogix-dp", dp); 1502 if (ret) { 1503 dev_err(&pdev->dev, "failed to request irq\n"); 1504 goto err_disable_pm_runtime; 1505 } 1506 disable_irq(dp->irq); 1507 1508 dp->drm_dev = drm_dev; 1509 dp->encoder = dp->plat_data->encoder; 1510 1511 dp->aux.name = "DP-AUX"; 1512 dp->aux.transfer = analogix_dpaux_transfer; 1513 dp->aux.dev = &pdev->dev; 1514 1515 ret = drm_dp_aux_register(&dp->aux); 1516 if (ret) 1517 return ERR_PTR(ret); 1518 1519 pm_runtime_enable(dev); 1520 1521 ret = analogix_dp_create_bridge(drm_dev, dp); 1522 if (ret) { 1523 DRM_ERROR("failed to create bridge (%d)\n", ret); 1524 goto err_disable_pm_runtime; 1525 } 1526 1527 return dp; 1528 1529 err_disable_pm_runtime: 1530 1531 pm_runtime_disable(dev); 1532 1533 return ERR_PTR(ret); 1534 } 1535 EXPORT_SYMBOL_GPL(analogix_dp_bind); 1536 1537 void analogix_dp_unbind(struct analogix_dp_device *dp) 1538 { 1539 analogix_dp_bridge_disable(dp->bridge); 1540 dp->connector.funcs->destroy(&dp->connector); 1541 1542 if (dp->plat_data->panel) { 1543 if (drm_panel_unprepare(dp->plat_data->panel)) 1544 DRM_ERROR("failed to turnoff the panel\n"); 1545 if (drm_panel_detach(dp->plat_data->panel)) 1546 DRM_ERROR("failed to detach the panel\n"); 1547 } 1548 1549 drm_dp_aux_unregister(&dp->aux); 1550 pm_runtime_disable(dp->dev); 1551 clk_disable_unprepare(dp->clock); 1552 } 1553 EXPORT_SYMBOL_GPL(analogix_dp_unbind); 1554 1555 #ifdef CONFIG_PM 1556 int analogix_dp_suspend(struct analogix_dp_device *dp) 1557 { 1558 clk_disable_unprepare(dp->clock); 1559 1560 if (dp->plat_data->panel) { 1561 if (drm_panel_unprepare(dp->plat_data->panel)) 1562 DRM_ERROR("failed to turnoff the panel\n"); 1563 } 1564 1565 return 0; 1566 } 1567 EXPORT_SYMBOL_GPL(analogix_dp_suspend); 1568 1569 int analogix_dp_resume(struct analogix_dp_device *dp) 1570 { 1571 int ret; 1572 1573 ret = clk_prepare_enable(dp->clock); 1574 if (ret < 0) { 1575 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret); 1576 return ret; 1577 } 1578 1579 if (dp->plat_data->panel) { 1580 if (drm_panel_prepare(dp->plat_data->panel)) { 1581 DRM_ERROR("failed to setup the panel\n"); 1582 return -EBUSY; 1583 } 1584 } 1585 1586 return 0; 1587 } 1588 EXPORT_SYMBOL_GPL(analogix_dp_resume); 1589 #endif 1590 1591 int analogix_dp_start_crc(struct drm_connector *connector) 1592 { 1593 struct analogix_dp_device *dp = to_dp(connector); 1594 1595 if (!connector->state->crtc) { 1596 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n", 1597 connector->name); 1598 return -EINVAL; 1599 } 1600 1601 return drm_dp_start_crc(&dp->aux, connector->state->crtc); 1602 } 1603 EXPORT_SYMBOL_GPL(analogix_dp_start_crc); 1604 1605 int analogix_dp_stop_crc(struct drm_connector *connector) 1606 { 1607 struct analogix_dp_device *dp = to_dp(connector); 1608 1609 return drm_dp_stop_crc(&dp->aux); 1610 } 1611 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc); 1612 1613 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); 1614 MODULE_DESCRIPTION("Analogix DP Core Driver"); 1615 MODULE_LICENSE("GPL v2"); 1616