1 /* 2 * Analogix DP (Display Port) core interface driver. 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/of.h> 20 #include <linux/of_gpio.h> 21 #include <linux/gpio.h> 22 #include <linux/component.h> 23 #include <linux/phy/phy.h> 24 25 #include <drm/drmP.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_crtc.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_panel.h> 30 31 #include <drm/bridge/analogix_dp.h> 32 33 #include "analogix_dp_core.h" 34 #include "analogix_dp_reg.h" 35 36 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm) 37 38 struct bridge_init { 39 struct i2c_client *client; 40 struct device_node *node; 41 }; 42 43 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 44 { 45 analogix_dp_reset(dp); 46 47 analogix_dp_swreset(dp); 48 49 analogix_dp_init_analog_param(dp); 50 analogix_dp_init_interrupt(dp); 51 52 /* SW defined function Normal operation */ 53 analogix_dp_enable_sw_function(dp); 54 55 analogix_dp_config_interrupt(dp); 56 analogix_dp_init_analog_func(dp); 57 58 analogix_dp_init_hpd(dp); 59 analogix_dp_init_aux(dp); 60 } 61 62 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp) 63 { 64 int timeout_loop = 0; 65 66 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) { 67 if (analogix_dp_get_plug_in_status(dp) == 0) 68 return 0; 69 70 timeout_loop++; 71 usleep_range(10, 11); 72 } 73 74 /* 75 * Some edp screen do not have hpd signal, so we can't just 76 * return failed when hpd plug in detect failed, DT property 77 * "force-hpd" would indicate whether driver need this. 78 */ 79 if (!dp->force_hpd) 80 return -ETIMEDOUT; 81 82 /* 83 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH 84 * will not work, so we need to give a force hpd action to 85 * set HPD_STATUS manually. 86 */ 87 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); 88 89 analogix_dp_force_hpd(dp); 90 91 if (analogix_dp_get_plug_in_status(dp) != 0) { 92 dev_err(dp->dev, "failed to get hpd plug in status\n"); 93 return -EINVAL; 94 } 95 96 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); 97 98 return 0; 99 } 100 101 int analogix_dp_psr_supported(struct analogix_dp_device *dp) 102 { 103 104 return dp->psr_support; 105 } 106 EXPORT_SYMBOL_GPL(analogix_dp_psr_supported); 107 108 int analogix_dp_enable_psr(struct analogix_dp_device *dp) 109 { 110 struct edp_vsc_psr psr_vsc; 111 112 if (!dp->psr_support) 113 return 0; 114 115 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ 116 memset(&psr_vsc, 0, sizeof(psr_vsc)); 117 psr_vsc.sdp_header.HB0 = 0; 118 psr_vsc.sdp_header.HB1 = 0x7; 119 psr_vsc.sdp_header.HB2 = 0x2; 120 psr_vsc.sdp_header.HB3 = 0x8; 121 122 psr_vsc.DB0 = 0; 123 psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID; 124 125 analogix_dp_send_psr_spd(dp, &psr_vsc); 126 return 0; 127 } 128 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr); 129 130 int analogix_dp_disable_psr(struct analogix_dp_device *dp) 131 { 132 struct edp_vsc_psr psr_vsc; 133 int ret; 134 135 if (!dp->psr_support) 136 return 0; 137 138 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ 139 memset(&psr_vsc, 0, sizeof(psr_vsc)); 140 psr_vsc.sdp_header.HB0 = 0; 141 psr_vsc.sdp_header.HB1 = 0x7; 142 psr_vsc.sdp_header.HB2 = 0x2; 143 psr_vsc.sdp_header.HB3 = 0x8; 144 145 psr_vsc.DB0 = 0; 146 psr_vsc.DB1 = 0; 147 148 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 149 if (ret != 1) 150 dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret); 151 152 analogix_dp_send_psr_spd(dp, &psr_vsc); 153 return 0; 154 } 155 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); 156 157 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) 158 { 159 unsigned char psr_version; 160 161 drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); 162 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); 163 164 return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; 165 } 166 167 static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) 168 { 169 unsigned char psr_en; 170 171 /* Disable psr function */ 172 drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en); 173 psr_en &= ~DP_PSR_ENABLE; 174 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 175 176 /* Main-Link transmitter remains active during PSR active states */ 177 psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; 178 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 179 180 /* Enable psr function */ 181 psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | 182 DP_PSR_CRC_VERIFICATION; 183 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 184 185 analogix_dp_enable_psr_crc(dp); 186 } 187 188 static void 189 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 190 bool enable) 191 { 192 u8 data; 193 194 drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 195 196 if (enable) 197 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 198 DP_LANE_COUNT_ENHANCED_FRAME_EN | 199 DPCD_LANE_COUNT_SET(data)); 200 else 201 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 202 DPCD_LANE_COUNT_SET(data)); 203 } 204 205 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 206 { 207 u8 data; 208 int retval; 209 210 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 211 retval = DPCD_ENHANCED_FRAME_CAP(data); 212 213 return retval; 214 } 215 216 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 217 { 218 u8 data; 219 220 data = analogix_dp_is_enhanced_mode_available(dp); 221 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 222 analogix_dp_enable_enhanced_mode(dp, data); 223 } 224 225 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 226 { 227 analogix_dp_set_training_pattern(dp, DP_NONE); 228 229 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 230 DP_TRAINING_PATTERN_DISABLE); 231 } 232 233 static void 234 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp, 235 int pre_emphasis, int lane) 236 { 237 switch (lane) { 238 case 0: 239 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis); 240 break; 241 case 1: 242 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis); 243 break; 244 245 case 2: 246 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis); 247 break; 248 249 case 3: 250 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis); 251 break; 252 } 253 } 254 255 static int analogix_dp_link_start(struct analogix_dp_device *dp) 256 { 257 u8 buf[4]; 258 int lane, lane_count, pll_tries, retval; 259 260 lane_count = dp->link_train.lane_count; 261 262 dp->link_train.lt_state = CLOCK_RECOVERY; 263 dp->link_train.eq_loop = 0; 264 265 for (lane = 0; lane < lane_count; lane++) 266 dp->link_train.cr_loop[lane] = 0; 267 268 /* Set link rate and count as you want to establish*/ 269 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 270 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 271 272 /* Setup RX configuration */ 273 buf[0] = dp->link_train.link_rate; 274 buf[1] = dp->link_train.lane_count; 275 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 276 if (retval < 0) 277 return retval; 278 279 /* Set TX pre-emphasis to minimum */ 280 for (lane = 0; lane < lane_count; lane++) 281 analogix_dp_set_lane_lane_pre_emphasis(dp, 282 PRE_EMPHASIS_LEVEL_0, lane); 283 284 /* Wait for PLL lock */ 285 pll_tries = 0; 286 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 287 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { 288 dev_err(dp->dev, "Wait for PLL lock timed out\n"); 289 return -ETIMEDOUT; 290 } 291 292 pll_tries++; 293 usleep_range(90, 120); 294 } 295 296 /* Set training pattern 1 */ 297 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 298 299 /* Set RX training pattern */ 300 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 301 DP_LINK_SCRAMBLING_DISABLE | 302 DP_TRAINING_PATTERN_1); 303 if (retval < 0) 304 return retval; 305 306 for (lane = 0; lane < lane_count; lane++) 307 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 308 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 309 310 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 311 lane_count); 312 if (retval < 0) 313 return retval; 314 315 return 0; 316 } 317 318 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 319 { 320 int shift = (lane & 1) * 4; 321 u8 link_value = link_status[lane >> 1]; 322 323 return (link_value >> shift) & 0xf; 324 } 325 326 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 327 { 328 int lane; 329 u8 lane_status; 330 331 for (lane = 0; lane < lane_count; lane++) { 332 lane_status = analogix_dp_get_lane_status(link_status, lane); 333 if ((lane_status & DP_LANE_CR_DONE) == 0) 334 return -EINVAL; 335 } 336 return 0; 337 } 338 339 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 340 int lane_count) 341 { 342 int lane; 343 u8 lane_status; 344 345 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 346 return -EINVAL; 347 348 for (lane = 0; lane < lane_count; lane++) { 349 lane_status = analogix_dp_get_lane_status(link_status, lane); 350 lane_status &= DP_CHANNEL_EQ_BITS; 351 if (lane_status != DP_CHANNEL_EQ_BITS) 352 return -EINVAL; 353 } 354 355 return 0; 356 } 357 358 static unsigned char 359 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 360 { 361 int shift = (lane & 1) * 4; 362 u8 link_value = adjust_request[lane >> 1]; 363 364 return (link_value >> shift) & 0x3; 365 } 366 367 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 368 u8 adjust_request[2], 369 int lane) 370 { 371 int shift = (lane & 1) * 4; 372 u8 link_value = adjust_request[lane >> 1]; 373 374 return ((link_value >> shift) & 0xc) >> 2; 375 } 376 377 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp, 378 u8 training_lane_set, int lane) 379 { 380 switch (lane) { 381 case 0: 382 analogix_dp_set_lane0_link_training(dp, training_lane_set); 383 break; 384 case 1: 385 analogix_dp_set_lane1_link_training(dp, training_lane_set); 386 break; 387 388 case 2: 389 analogix_dp_set_lane2_link_training(dp, training_lane_set); 390 break; 391 392 case 3: 393 analogix_dp_set_lane3_link_training(dp, training_lane_set); 394 break; 395 } 396 } 397 398 static unsigned int 399 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, 400 int lane) 401 { 402 u32 reg; 403 404 switch (lane) { 405 case 0: 406 reg = analogix_dp_get_lane0_link_training(dp); 407 break; 408 case 1: 409 reg = analogix_dp_get_lane1_link_training(dp); 410 break; 411 case 2: 412 reg = analogix_dp_get_lane2_link_training(dp); 413 break; 414 case 3: 415 reg = analogix_dp_get_lane3_link_training(dp); 416 break; 417 default: 418 WARN_ON(1); 419 return 0; 420 } 421 422 return reg; 423 } 424 425 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 426 { 427 analogix_dp_training_pattern_dis(dp); 428 analogix_dp_set_enhanced_mode(dp); 429 430 dp->link_train.lt_state = FAILED; 431 } 432 433 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 434 u8 adjust_request[2]) 435 { 436 int lane, lane_count; 437 u8 voltage_swing, pre_emphasis, training_lane; 438 439 lane_count = dp->link_train.lane_count; 440 for (lane = 0; lane < lane_count; lane++) { 441 voltage_swing = analogix_dp_get_adjust_request_voltage( 442 adjust_request, lane); 443 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 444 adjust_request, lane); 445 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 446 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 447 448 if (voltage_swing == VOLTAGE_LEVEL_3) 449 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 450 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 451 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 452 453 dp->link_train.training_lane[lane] = training_lane; 454 } 455 } 456 457 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 458 { 459 int lane, lane_count, retval; 460 u8 voltage_swing, pre_emphasis, training_lane; 461 u8 link_status[2], adjust_request[2]; 462 463 usleep_range(100, 101); 464 465 lane_count = dp->link_train.lane_count; 466 467 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 468 if (retval < 0) 469 return retval; 470 471 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 472 adjust_request, 2); 473 if (retval < 0) 474 return retval; 475 476 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 477 /* set training pattern 2 for EQ */ 478 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 479 480 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 481 DP_LINK_SCRAMBLING_DISABLE | 482 DP_TRAINING_PATTERN_2); 483 if (retval < 0) 484 return retval; 485 486 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 487 dp->link_train.lt_state = EQUALIZER_TRAINING; 488 } else { 489 for (lane = 0; lane < lane_count; lane++) { 490 training_lane = analogix_dp_get_lane_link_training( 491 dp, lane); 492 voltage_swing = analogix_dp_get_adjust_request_voltage( 493 adjust_request, lane); 494 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 495 adjust_request, lane); 496 497 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 498 voltage_swing && 499 DPCD_PRE_EMPHASIS_GET(training_lane) == 500 pre_emphasis) 501 dp->link_train.cr_loop[lane]++; 502 503 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 504 voltage_swing == VOLTAGE_LEVEL_3 || 505 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 506 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 507 dp->link_train.cr_loop[lane], 508 voltage_swing, pre_emphasis); 509 analogix_dp_reduce_link_rate(dp); 510 return -EIO; 511 } 512 } 513 } 514 515 analogix_dp_get_adjust_training_lane(dp, adjust_request); 516 517 for (lane = 0; lane < lane_count; lane++) 518 analogix_dp_set_lane_link_training(dp, 519 dp->link_train.training_lane[lane], lane); 520 521 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 522 dp->link_train.training_lane, lane_count); 523 if (retval < 0) 524 return retval; 525 526 return 0; 527 } 528 529 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 530 { 531 int lane, lane_count, retval; 532 u32 reg; 533 u8 link_align, link_status[2], adjust_request[2]; 534 535 usleep_range(400, 401); 536 537 lane_count = dp->link_train.lane_count; 538 539 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 540 if (retval < 0) 541 return retval; 542 543 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 544 analogix_dp_reduce_link_rate(dp); 545 return -EIO; 546 } 547 548 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 549 adjust_request, 2); 550 if (retval < 0) 551 return retval; 552 553 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, 554 &link_align); 555 if (retval < 0) 556 return retval; 557 558 analogix_dp_get_adjust_training_lane(dp, adjust_request); 559 560 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 561 /* traing pattern Set to Normal */ 562 analogix_dp_training_pattern_dis(dp); 563 564 dev_info(dp->dev, "Link Training success!\n"); 565 566 analogix_dp_get_link_bandwidth(dp, ®); 567 dp->link_train.link_rate = reg; 568 dev_dbg(dp->dev, "final bandwidth = %.2x\n", 569 dp->link_train.link_rate); 570 571 analogix_dp_get_lane_count(dp, ®); 572 dp->link_train.lane_count = reg; 573 dev_dbg(dp->dev, "final lane count = %.2x\n", 574 dp->link_train.lane_count); 575 576 /* set enhanced mode if available */ 577 analogix_dp_set_enhanced_mode(dp); 578 dp->link_train.lt_state = FINISHED; 579 580 return 0; 581 } 582 583 /* not all locked */ 584 dp->link_train.eq_loop++; 585 586 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 587 dev_err(dp->dev, "EQ Max loop\n"); 588 analogix_dp_reduce_link_rate(dp); 589 return -EIO; 590 } 591 592 for (lane = 0; lane < lane_count; lane++) 593 analogix_dp_set_lane_link_training(dp, 594 dp->link_train.training_lane[lane], lane); 595 596 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 597 dp->link_train.training_lane, lane_count); 598 if (retval < 0) 599 return retval; 600 601 return 0; 602 } 603 604 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 605 u8 *bandwidth) 606 { 607 u8 data; 608 609 /* 610 * For DP rev.1.1, Maximum link rate of Main Link lanes 611 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 612 * For DP rev.1.2, Maximum link rate of Main Link lanes 613 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 614 */ 615 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 616 *bandwidth = data; 617 } 618 619 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 620 u8 *lane_count) 621 { 622 u8 data; 623 624 /* 625 * For DP rev.1.1, Maximum number of Main Link lanes 626 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 627 */ 628 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 629 *lane_count = DPCD_MAX_LANE_COUNT(data); 630 } 631 632 static void analogix_dp_init_training(struct analogix_dp_device *dp, 633 enum link_lane_count_type max_lane, 634 int max_rate) 635 { 636 /* 637 * MACRO_RST must be applied after the PLL_LOCK to avoid 638 * the DP inter pair skew issue for at least 10 us 639 */ 640 analogix_dp_reset_macro(dp); 641 642 /* Initialize by reading RX's DPCD */ 643 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 644 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 645 646 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 647 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 648 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 649 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", 650 dp->link_train.link_rate); 651 dp->link_train.link_rate = DP_LINK_BW_1_62; 652 } 653 654 if (dp->link_train.lane_count == 0) { 655 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", 656 dp->link_train.lane_count); 657 dp->link_train.lane_count = (u8)LANE_COUNT1; 658 } 659 660 /* Setup TX lane count & rate */ 661 if (dp->link_train.lane_count > max_lane) 662 dp->link_train.lane_count = max_lane; 663 if (dp->link_train.link_rate > max_rate) 664 dp->link_train.link_rate = max_rate; 665 666 /* All DP analog module power up */ 667 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 668 } 669 670 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 671 { 672 int retval = 0, training_finished = 0; 673 674 dp->link_train.lt_state = START; 675 676 /* Process here */ 677 while (!retval && !training_finished) { 678 switch (dp->link_train.lt_state) { 679 case START: 680 retval = analogix_dp_link_start(dp); 681 if (retval) 682 dev_err(dp->dev, "LT link start failed!\n"); 683 break; 684 case CLOCK_RECOVERY: 685 retval = analogix_dp_process_clock_recovery(dp); 686 if (retval) 687 dev_err(dp->dev, "LT CR failed!\n"); 688 break; 689 case EQUALIZER_TRAINING: 690 retval = analogix_dp_process_equalizer_training(dp); 691 if (retval) 692 dev_err(dp->dev, "LT EQ failed!\n"); 693 break; 694 case FINISHED: 695 training_finished = 1; 696 break; 697 case FAILED: 698 return -EREMOTEIO; 699 } 700 } 701 if (retval) 702 dev_err(dp->dev, "eDP link training failed (%d)\n", retval); 703 704 return retval; 705 } 706 707 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 708 u32 count, u32 bwtype) 709 { 710 int i; 711 int retval; 712 713 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { 714 analogix_dp_init_training(dp, count, bwtype); 715 retval = analogix_dp_sw_link_training(dp); 716 if (retval == 0) 717 break; 718 719 usleep_range(100, 110); 720 } 721 722 return retval; 723 } 724 725 static int analogix_dp_config_video(struct analogix_dp_device *dp) 726 { 727 int timeout_loop = 0; 728 int done_count = 0; 729 730 analogix_dp_config_video_slave_mode(dp); 731 732 analogix_dp_set_video_color_format(dp); 733 734 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 735 dev_err(dp->dev, "PLL is not locked yet.\n"); 736 return -EINVAL; 737 } 738 739 for (;;) { 740 timeout_loop++; 741 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 742 break; 743 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 744 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 745 return -ETIMEDOUT; 746 } 747 748 usleep_range(1, 2); 749 } 750 751 /* Set to use the register calculated M/N video */ 752 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 753 754 /* For video bist, Video timing must be generated by register */ 755 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 756 757 /* Disable video mute */ 758 analogix_dp_enable_video_mute(dp, 0); 759 760 /* Configure video slave mode */ 761 analogix_dp_enable_video_master(dp, 0); 762 763 timeout_loop = 0; 764 765 for (;;) { 766 timeout_loop++; 767 if (analogix_dp_is_video_stream_on(dp) == 0) { 768 done_count++; 769 if (done_count > 10) 770 break; 771 } else if (done_count) { 772 done_count = 0; 773 } 774 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 775 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 776 return -ETIMEDOUT; 777 } 778 779 usleep_range(1000, 1001); 780 } 781 782 return 0; 783 } 784 785 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 786 bool enable) 787 { 788 u8 data; 789 790 if (enable) { 791 analogix_dp_enable_scrambling(dp); 792 793 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); 794 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 795 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 796 } else { 797 analogix_dp_disable_scrambling(dp); 798 799 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); 800 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 801 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 802 } 803 } 804 805 static irqreturn_t analogix_dp_hardirq(int irq, void *arg) 806 { 807 struct analogix_dp_device *dp = arg; 808 irqreturn_t ret = IRQ_NONE; 809 enum dp_irq_type irq_type; 810 811 irq_type = analogix_dp_get_irq_type(dp); 812 if (irq_type != DP_IRQ_TYPE_UNKNOWN) { 813 analogix_dp_mute_hpd_interrupt(dp); 814 ret = IRQ_WAKE_THREAD; 815 } 816 817 return ret; 818 } 819 820 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg) 821 { 822 struct analogix_dp_device *dp = arg; 823 enum dp_irq_type irq_type; 824 825 irq_type = analogix_dp_get_irq_type(dp); 826 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN || 827 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) { 828 dev_dbg(dp->dev, "Detected cable status changed!\n"); 829 if (dp->drm_dev) 830 drm_helper_hpd_irq_event(dp->drm_dev); 831 } 832 833 if (irq_type != DP_IRQ_TYPE_UNKNOWN) { 834 analogix_dp_clear_hotplug_interrupts(dp); 835 analogix_dp_unmute_hpd_interrupt(dp); 836 } 837 838 return IRQ_HANDLED; 839 } 840 841 static void analogix_dp_commit(struct analogix_dp_device *dp) 842 { 843 int ret; 844 845 /* Keep the panel disabled while we configure video */ 846 if (dp->plat_data->panel) { 847 if (drm_panel_disable(dp->plat_data->panel)) 848 DRM_ERROR("failed to disable the panel\n"); 849 } 850 851 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 852 dp->video_info.max_link_rate); 853 if (ret) { 854 dev_err(dp->dev, "unable to do link train\n"); 855 return; 856 } 857 858 analogix_dp_enable_scramble(dp, 1); 859 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 860 analogix_dp_enable_enhanced_mode(dp, 1); 861 862 analogix_dp_init_video(dp); 863 ret = analogix_dp_config_video(dp); 864 if (ret) 865 dev_err(dp->dev, "unable to config video\n"); 866 867 /* Safe to enable the panel now */ 868 if (dp->plat_data->panel) { 869 if (drm_panel_enable(dp->plat_data->panel)) 870 DRM_ERROR("failed to enable the panel\n"); 871 } 872 873 /* Enable video */ 874 analogix_dp_start_video(dp); 875 876 dp->psr_support = analogix_dp_detect_sink_psr(dp); 877 if (dp->psr_support) 878 analogix_dp_enable_sink_psr(dp); 879 } 880 881 /* 882 * This function is a bit of a catch-all for panel preparation, hopefully 883 * simplifying the logic of functions that need to prepare/unprepare the panel 884 * below. 885 * 886 * If @prepare is true, this function will prepare the panel. Conversely, if it 887 * is false, the panel will be unprepared. 888 * 889 * If @is_modeset_prepare is true, the function will disregard the current state 890 * of the panel and either prepare/unprepare the panel based on @prepare. Once 891 * it finishes, it will update dp->panel_is_modeset to reflect the current state 892 * of the panel. 893 */ 894 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp, 895 bool prepare, bool is_modeset_prepare) 896 { 897 int ret = 0; 898 899 if (!dp->plat_data->panel) 900 return 0; 901 902 mutex_lock(&dp->panel_lock); 903 904 /* 905 * Exit early if this is a temporary prepare/unprepare and we're already 906 * modeset (since we neither want to prepare twice or unprepare early). 907 */ 908 if (dp->panel_is_modeset && !is_modeset_prepare) 909 goto out; 910 911 if (prepare) 912 ret = drm_panel_prepare(dp->plat_data->panel); 913 else 914 ret = drm_panel_unprepare(dp->plat_data->panel); 915 916 if (ret) 917 goto out; 918 919 if (is_modeset_prepare) 920 dp->panel_is_modeset = prepare; 921 922 out: 923 mutex_unlock(&dp->panel_lock); 924 return ret; 925 } 926 927 static int analogix_dp_get_modes(struct drm_connector *connector) 928 { 929 struct analogix_dp_device *dp = to_dp(connector); 930 struct edid *edid; 931 int ret, num_modes = 0; 932 933 if (dp->plat_data->panel) { 934 num_modes += drm_panel_get_modes(dp->plat_data->panel); 935 } else { 936 ret = analogix_dp_prepare_panel(dp, true, false); 937 if (ret) { 938 DRM_ERROR("Failed to prepare panel (%d)\n", ret); 939 return 0; 940 } 941 942 pm_runtime_get_sync(dp->dev); 943 edid = drm_get_edid(connector, &dp->aux.ddc); 944 pm_runtime_put(dp->dev); 945 if (edid) { 946 drm_mode_connector_update_edid_property(&dp->connector, 947 edid); 948 num_modes += drm_add_edid_modes(&dp->connector, edid); 949 kfree(edid); 950 } 951 952 ret = analogix_dp_prepare_panel(dp, false, false); 953 if (ret) 954 DRM_ERROR("Failed to unprepare panel (%d)\n", ret); 955 } 956 957 if (dp->plat_data->get_modes) 958 num_modes += dp->plat_data->get_modes(dp->plat_data, connector); 959 960 return num_modes; 961 } 962 963 static struct drm_encoder * 964 analogix_dp_best_encoder(struct drm_connector *connector) 965 { 966 struct analogix_dp_device *dp = to_dp(connector); 967 968 return dp->encoder; 969 } 970 971 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = { 972 .get_modes = analogix_dp_get_modes, 973 .best_encoder = analogix_dp_best_encoder, 974 }; 975 976 static enum drm_connector_status 977 analogix_dp_detect(struct drm_connector *connector, bool force) 978 { 979 struct analogix_dp_device *dp = to_dp(connector); 980 enum drm_connector_status status = connector_status_disconnected; 981 int ret; 982 983 if (dp->plat_data->panel) 984 return connector_status_connected; 985 986 ret = analogix_dp_prepare_panel(dp, true, false); 987 if (ret) { 988 DRM_ERROR("Failed to prepare panel (%d)\n", ret); 989 return connector_status_disconnected; 990 } 991 992 if (!analogix_dp_detect_hpd(dp)) 993 status = connector_status_connected; 994 995 ret = analogix_dp_prepare_panel(dp, false, false); 996 if (ret) 997 DRM_ERROR("Failed to unprepare panel (%d)\n", ret); 998 999 return status; 1000 } 1001 1002 static const struct drm_connector_funcs analogix_dp_connector_funcs = { 1003 .fill_modes = drm_helper_probe_single_connector_modes, 1004 .detect = analogix_dp_detect, 1005 .destroy = drm_connector_cleanup, 1006 .reset = drm_atomic_helper_connector_reset, 1007 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1008 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1009 }; 1010 1011 static int analogix_dp_bridge_attach(struct drm_bridge *bridge) 1012 { 1013 struct analogix_dp_device *dp = bridge->driver_private; 1014 struct drm_encoder *encoder = dp->encoder; 1015 struct drm_connector *connector = &dp->connector; 1016 int ret; 1017 1018 if (!bridge->encoder) { 1019 DRM_ERROR("Parent encoder object not found"); 1020 return -ENODEV; 1021 } 1022 1023 connector->polled = DRM_CONNECTOR_POLL_HPD; 1024 1025 ret = drm_connector_init(dp->drm_dev, connector, 1026 &analogix_dp_connector_funcs, 1027 DRM_MODE_CONNECTOR_eDP); 1028 if (ret) { 1029 DRM_ERROR("Failed to initialize connector with drm\n"); 1030 return ret; 1031 } 1032 1033 drm_connector_helper_add(connector, 1034 &analogix_dp_connector_helper_funcs); 1035 drm_mode_connector_attach_encoder(connector, encoder); 1036 1037 /* 1038 * NOTE: the connector registration is implemented in analogix 1039 * platform driver, that to say connector would be exist after 1040 * plat_data->attch return, that's why we record the connector 1041 * point after plat attached. 1042 */ 1043 if (dp->plat_data->attach) { 1044 ret = dp->plat_data->attach(dp->plat_data, bridge, connector); 1045 if (ret) { 1046 DRM_ERROR("Failed at platform attch func\n"); 1047 return ret; 1048 } 1049 } 1050 1051 if (dp->plat_data->panel) { 1052 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector); 1053 if (ret) { 1054 DRM_ERROR("Failed to attach panel\n"); 1055 return ret; 1056 } 1057 } 1058 1059 return 0; 1060 } 1061 1062 static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge) 1063 { 1064 struct analogix_dp_device *dp = bridge->driver_private; 1065 int ret; 1066 1067 ret = analogix_dp_prepare_panel(dp, true, true); 1068 if (ret) 1069 DRM_ERROR("failed to setup the panel ret = %d\n", ret); 1070 } 1071 1072 static void analogix_dp_bridge_enable(struct drm_bridge *bridge) 1073 { 1074 struct analogix_dp_device *dp = bridge->driver_private; 1075 1076 if (dp->dpms_mode == DRM_MODE_DPMS_ON) 1077 return; 1078 1079 pm_runtime_get_sync(dp->dev); 1080 1081 if (dp->plat_data->power_on) 1082 dp->plat_data->power_on(dp->plat_data); 1083 1084 phy_power_on(dp->phy); 1085 analogix_dp_init_dp(dp); 1086 enable_irq(dp->irq); 1087 analogix_dp_commit(dp); 1088 1089 dp->dpms_mode = DRM_MODE_DPMS_ON; 1090 } 1091 1092 static void analogix_dp_bridge_disable(struct drm_bridge *bridge) 1093 { 1094 struct analogix_dp_device *dp = bridge->driver_private; 1095 int ret; 1096 1097 if (dp->dpms_mode != DRM_MODE_DPMS_ON) 1098 return; 1099 1100 if (dp->plat_data->panel) { 1101 if (drm_panel_disable(dp->plat_data->panel)) { 1102 DRM_ERROR("failed to disable the panel\n"); 1103 return; 1104 } 1105 } 1106 1107 disable_irq(dp->irq); 1108 phy_power_off(dp->phy); 1109 1110 if (dp->plat_data->power_off) 1111 dp->plat_data->power_off(dp->plat_data); 1112 1113 pm_runtime_put_sync(dp->dev); 1114 1115 ret = analogix_dp_prepare_panel(dp, false, true); 1116 if (ret) 1117 DRM_ERROR("failed to setup the panel ret = %d\n", ret); 1118 1119 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1120 } 1121 1122 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, 1123 struct drm_display_mode *orig_mode, 1124 struct drm_display_mode *mode) 1125 { 1126 struct analogix_dp_device *dp = bridge->driver_private; 1127 struct drm_display_info *display_info = &dp->connector.display_info; 1128 struct video_info *video = &dp->video_info; 1129 struct device_node *dp_node = dp->dev->of_node; 1130 int vic; 1131 1132 /* Input video interlaces & hsync pol & vsync pol */ 1133 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 1134 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); 1135 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); 1136 1137 /* Input video dynamic_range & colorimetry */ 1138 vic = drm_match_cea_mode(mode); 1139 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || 1140 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) { 1141 video->dynamic_range = CEA; 1142 video->ycbcr_coeff = COLOR_YCBCR601; 1143 } else if (vic) { 1144 video->dynamic_range = CEA; 1145 video->ycbcr_coeff = COLOR_YCBCR709; 1146 } else { 1147 video->dynamic_range = VESA; 1148 video->ycbcr_coeff = COLOR_YCBCR709; 1149 } 1150 1151 /* Input vide bpc and color_formats */ 1152 switch (display_info->bpc) { 1153 case 12: 1154 video->color_depth = COLOR_12; 1155 break; 1156 case 10: 1157 video->color_depth = COLOR_10; 1158 break; 1159 case 8: 1160 video->color_depth = COLOR_8; 1161 break; 1162 case 6: 1163 video->color_depth = COLOR_6; 1164 break; 1165 default: 1166 video->color_depth = COLOR_8; 1167 break; 1168 } 1169 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 1170 video->color_space = COLOR_YCBCR444; 1171 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1172 video->color_space = COLOR_YCBCR422; 1173 else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444) 1174 video->color_space = COLOR_RGB; 1175 else 1176 video->color_space = COLOR_RGB; 1177 1178 /* 1179 * NOTE: those property parsing code is used for providing backward 1180 * compatibility for samsung platform. 1181 * Due to we used the "of_property_read_u32" interfaces, when this 1182 * property isn't present, the "video_info" can keep the original 1183 * values and wouldn't be modified. 1184 */ 1185 of_property_read_u32(dp_node, "samsung,color-space", 1186 &video->color_space); 1187 of_property_read_u32(dp_node, "samsung,dynamic-range", 1188 &video->dynamic_range); 1189 of_property_read_u32(dp_node, "samsung,ycbcr-coeff", 1190 &video->ycbcr_coeff); 1191 of_property_read_u32(dp_node, "samsung,color-depth", 1192 &video->color_depth); 1193 if (of_property_read_bool(dp_node, "hsync-active-high")) 1194 video->h_sync_polarity = true; 1195 if (of_property_read_bool(dp_node, "vsync-active-high")) 1196 video->v_sync_polarity = true; 1197 if (of_property_read_bool(dp_node, "interlaced")) 1198 video->interlaced = true; 1199 } 1200 1201 static void analogix_dp_bridge_nop(struct drm_bridge *bridge) 1202 { 1203 /* do nothing */ 1204 } 1205 1206 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = { 1207 .pre_enable = analogix_dp_bridge_pre_enable, 1208 .enable = analogix_dp_bridge_enable, 1209 .disable = analogix_dp_bridge_disable, 1210 .post_disable = analogix_dp_bridge_nop, 1211 .mode_set = analogix_dp_bridge_mode_set, 1212 .attach = analogix_dp_bridge_attach, 1213 }; 1214 1215 static int analogix_dp_create_bridge(struct drm_device *drm_dev, 1216 struct analogix_dp_device *dp) 1217 { 1218 struct drm_bridge *bridge; 1219 int ret; 1220 1221 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL); 1222 if (!bridge) { 1223 DRM_ERROR("failed to allocate for drm bridge\n"); 1224 return -ENOMEM; 1225 } 1226 1227 dp->bridge = bridge; 1228 1229 bridge->driver_private = dp; 1230 bridge->funcs = &analogix_dp_bridge_funcs; 1231 1232 ret = drm_bridge_attach(dp->encoder, bridge, NULL); 1233 if (ret) { 1234 DRM_ERROR("failed to attach drm bridge\n"); 1235 return -EINVAL; 1236 } 1237 1238 return 0; 1239 } 1240 1241 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) 1242 { 1243 struct device_node *dp_node = dp->dev->of_node; 1244 struct video_info *video_info = &dp->video_info; 1245 1246 switch (dp->plat_data->dev_type) { 1247 case RK3288_DP: 1248 case RK3399_EDP: 1249 /* 1250 * Like Rk3288 DisplayPort TRM indicate that "Main link 1251 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 1252 */ 1253 video_info->max_link_rate = 0x0A; 1254 video_info->max_lane_count = 0x04; 1255 break; 1256 case EXYNOS_DP: 1257 /* 1258 * NOTE: those property parseing code is used for 1259 * providing backward compatibility for samsung platform. 1260 */ 1261 of_property_read_u32(dp_node, "samsung,link-rate", 1262 &video_info->max_link_rate); 1263 of_property_read_u32(dp_node, "samsung,lane-count", 1264 &video_info->max_lane_count); 1265 break; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux, 1272 struct drm_dp_aux_msg *msg) 1273 { 1274 struct analogix_dp_device *dp = to_dp(aux); 1275 1276 return analogix_dp_transfer(dp, msg); 1277 } 1278 1279 struct analogix_dp_device * 1280 analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, 1281 struct analogix_dp_plat_data *plat_data) 1282 { 1283 struct platform_device *pdev = to_platform_device(dev); 1284 struct analogix_dp_device *dp; 1285 struct resource *res; 1286 unsigned int irq_flags; 1287 int ret; 1288 1289 if (!plat_data) { 1290 dev_err(dev, "Invalided input plat_data\n"); 1291 return ERR_PTR(-EINVAL); 1292 } 1293 1294 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL); 1295 if (!dp) 1296 return ERR_PTR(-ENOMEM); 1297 1298 dp->dev = &pdev->dev; 1299 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1300 1301 mutex_init(&dp->panel_lock); 1302 dp->panel_is_modeset = false; 1303 1304 /* 1305 * platform dp driver need containor_of the plat_data to get 1306 * the driver private data, so we need to store the point of 1307 * plat_data, not the context of plat_data. 1308 */ 1309 dp->plat_data = plat_data; 1310 1311 ret = analogix_dp_dt_parse_pdata(dp); 1312 if (ret) 1313 return ERR_PTR(ret); 1314 1315 dp->phy = devm_phy_get(dp->dev, "dp"); 1316 if (IS_ERR(dp->phy)) { 1317 dev_err(dp->dev, "no DP phy configured\n"); 1318 ret = PTR_ERR(dp->phy); 1319 if (ret) { 1320 /* 1321 * phy itself is not enabled, so we can move forward 1322 * assigning NULL to phy pointer. 1323 */ 1324 if (ret == -ENOSYS || ret == -ENODEV) 1325 dp->phy = NULL; 1326 else 1327 return ERR_PTR(ret); 1328 } 1329 } 1330 1331 dp->clock = devm_clk_get(&pdev->dev, "dp"); 1332 if (IS_ERR(dp->clock)) { 1333 dev_err(&pdev->dev, "failed to get clock\n"); 1334 return ERR_CAST(dp->clock); 1335 } 1336 1337 clk_prepare_enable(dp->clock); 1338 1339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1340 1341 dp->reg_base = devm_ioremap_resource(&pdev->dev, res); 1342 if (IS_ERR(dp->reg_base)) 1343 return ERR_CAST(dp->reg_base); 1344 1345 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd"); 1346 1347 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0); 1348 if (!gpio_is_valid(dp->hpd_gpio)) 1349 dp->hpd_gpio = of_get_named_gpio(dev->of_node, 1350 "samsung,hpd-gpio", 0); 1351 1352 if (gpio_is_valid(dp->hpd_gpio)) { 1353 /* 1354 * Set up the hotplug GPIO from the device tree as an interrupt. 1355 * Simply specifying a different interrupt in the device tree 1356 * doesn't work since we handle hotplug rather differently when 1357 * using a GPIO. We also need the actual GPIO specifier so 1358 * that we can get the current state of the GPIO. 1359 */ 1360 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN, 1361 "hpd_gpio"); 1362 if (ret) { 1363 dev_err(&pdev->dev, "failed to get hpd gpio\n"); 1364 return ERR_PTR(ret); 1365 } 1366 dp->irq = gpio_to_irq(dp->hpd_gpio); 1367 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; 1368 } else { 1369 dp->hpd_gpio = -ENODEV; 1370 dp->irq = platform_get_irq(pdev, 0); 1371 irq_flags = 0; 1372 } 1373 1374 if (dp->irq == -ENXIO) { 1375 dev_err(&pdev->dev, "failed to get irq\n"); 1376 return ERR_PTR(-ENODEV); 1377 } 1378 1379 pm_runtime_enable(dev); 1380 1381 pm_runtime_get_sync(dev); 1382 phy_power_on(dp->phy); 1383 1384 analogix_dp_init_dp(dp); 1385 1386 ret = devm_request_threaded_irq(&pdev->dev, dp->irq, 1387 analogix_dp_hardirq, 1388 analogix_dp_irq_thread, 1389 irq_flags, "analogix-dp", dp); 1390 if (ret) { 1391 dev_err(&pdev->dev, "failed to request irq\n"); 1392 goto err_disable_pm_runtime; 1393 } 1394 disable_irq(dp->irq); 1395 1396 dp->drm_dev = drm_dev; 1397 dp->encoder = dp->plat_data->encoder; 1398 1399 dp->aux.name = "DP-AUX"; 1400 dp->aux.transfer = analogix_dpaux_transfer; 1401 dp->aux.dev = &pdev->dev; 1402 1403 ret = drm_dp_aux_register(&dp->aux); 1404 if (ret) 1405 goto err_disable_pm_runtime; 1406 1407 ret = analogix_dp_create_bridge(drm_dev, dp); 1408 if (ret) { 1409 DRM_ERROR("failed to create bridge (%d)\n", ret); 1410 drm_encoder_cleanup(dp->encoder); 1411 goto err_disable_pm_runtime; 1412 } 1413 1414 phy_power_off(dp->phy); 1415 pm_runtime_put(dev); 1416 1417 return dp; 1418 1419 err_disable_pm_runtime: 1420 1421 phy_power_off(dp->phy); 1422 pm_runtime_put(dev); 1423 pm_runtime_disable(dev); 1424 1425 return ERR_PTR(ret); 1426 } 1427 EXPORT_SYMBOL_GPL(analogix_dp_bind); 1428 1429 void analogix_dp_unbind(struct analogix_dp_device *dp) 1430 { 1431 analogix_dp_bridge_disable(dp->bridge); 1432 dp->connector.funcs->destroy(&dp->connector); 1433 dp->encoder->funcs->destroy(dp->encoder); 1434 1435 if (dp->plat_data->panel) { 1436 if (drm_panel_unprepare(dp->plat_data->panel)) 1437 DRM_ERROR("failed to turnoff the panel\n"); 1438 if (drm_panel_detach(dp->plat_data->panel)) 1439 DRM_ERROR("failed to detach the panel\n"); 1440 } 1441 1442 drm_dp_aux_unregister(&dp->aux); 1443 pm_runtime_disable(dp->dev); 1444 clk_disable_unprepare(dp->clock); 1445 } 1446 EXPORT_SYMBOL_GPL(analogix_dp_unbind); 1447 1448 #ifdef CONFIG_PM 1449 int analogix_dp_suspend(struct analogix_dp_device *dp) 1450 { 1451 clk_disable_unprepare(dp->clock); 1452 1453 if (dp->plat_data->panel) { 1454 if (drm_panel_unprepare(dp->plat_data->panel)) 1455 DRM_ERROR("failed to turnoff the panel\n"); 1456 } 1457 1458 return 0; 1459 } 1460 EXPORT_SYMBOL_GPL(analogix_dp_suspend); 1461 1462 int analogix_dp_resume(struct analogix_dp_device *dp) 1463 { 1464 int ret; 1465 1466 ret = clk_prepare_enable(dp->clock); 1467 if (ret < 0) { 1468 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret); 1469 return ret; 1470 } 1471 1472 if (dp->plat_data->panel) { 1473 if (drm_panel_prepare(dp->plat_data->panel)) { 1474 DRM_ERROR("failed to setup the panel\n"); 1475 return -EBUSY; 1476 } 1477 } 1478 1479 return 0; 1480 } 1481 EXPORT_SYMBOL_GPL(analogix_dp_resume); 1482 #endif 1483 1484 int analogix_dp_start_crc(struct drm_connector *connector) 1485 { 1486 struct analogix_dp_device *dp = to_dp(connector); 1487 1488 if (!connector->state->crtc) { 1489 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n", 1490 connector->name); 1491 return -EINVAL; 1492 } 1493 1494 return drm_dp_start_crc(&dp->aux, connector->state->crtc); 1495 } 1496 EXPORT_SYMBOL_GPL(analogix_dp_start_crc); 1497 1498 int analogix_dp_stop_crc(struct drm_connector *connector) 1499 { 1500 struct analogix_dp_device *dp = to_dp(connector); 1501 1502 return drm_dp_stop_crc(&dp->aux); 1503 } 1504 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc); 1505 1506 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); 1507 MODULE_DESCRIPTION("Analogix DP Core Driver"); 1508 MODULE_LICENSE("GPL v2"); 1509