1 /* 2 * Analogix DP (Display Port) core interface driver. 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/of.h> 20 #include <linux/of_gpio.h> 21 #include <linux/gpio.h> 22 #include <linux/component.h> 23 #include <linux/phy/phy.h> 24 25 #include <drm/drmP.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_crtc.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_panel.h> 30 31 #include <drm/bridge/analogix_dp.h> 32 33 #include "analogix_dp_core.h" 34 #include "analogix_dp_reg.h" 35 36 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm) 37 38 struct bridge_init { 39 struct i2c_client *client; 40 struct device_node *node; 41 }; 42 43 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 44 { 45 analogix_dp_reset(dp); 46 47 analogix_dp_swreset(dp); 48 49 analogix_dp_init_analog_param(dp); 50 analogix_dp_init_interrupt(dp); 51 52 /* SW defined function Normal operation */ 53 analogix_dp_enable_sw_function(dp); 54 55 analogix_dp_config_interrupt(dp); 56 analogix_dp_init_analog_func(dp); 57 58 analogix_dp_init_hpd(dp); 59 analogix_dp_init_aux(dp); 60 } 61 62 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp) 63 { 64 int timeout_loop = 0; 65 66 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) { 67 if (analogix_dp_get_plug_in_status(dp) == 0) 68 return 0; 69 70 timeout_loop++; 71 usleep_range(10, 11); 72 } 73 74 /* 75 * Some edp screen do not have hpd signal, so we can't just 76 * return failed when hpd plug in detect failed, DT property 77 * "force-hpd" would indicate whether driver need this. 78 */ 79 if (!dp->force_hpd) 80 return -ETIMEDOUT; 81 82 /* 83 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH 84 * will not work, so we need to give a force hpd action to 85 * set HPD_STATUS manually. 86 */ 87 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); 88 89 analogix_dp_force_hpd(dp); 90 91 if (analogix_dp_get_plug_in_status(dp) != 0) { 92 dev_err(dp->dev, "failed to get hpd plug in status\n"); 93 return -EINVAL; 94 } 95 96 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); 97 98 return 0; 99 } 100 101 int analogix_dp_psr_supported(struct analogix_dp_device *dp) 102 { 103 104 return dp->psr_support; 105 } 106 EXPORT_SYMBOL_GPL(analogix_dp_psr_supported); 107 108 int analogix_dp_enable_psr(struct analogix_dp_device *dp) 109 { 110 struct edp_vsc_psr psr_vsc; 111 112 if (!dp->psr_support) 113 return 0; 114 115 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ 116 memset(&psr_vsc, 0, sizeof(psr_vsc)); 117 psr_vsc.sdp_header.HB0 = 0; 118 psr_vsc.sdp_header.HB1 = 0x7; 119 psr_vsc.sdp_header.HB2 = 0x2; 120 psr_vsc.sdp_header.HB3 = 0x8; 121 122 psr_vsc.DB0 = 0; 123 psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID; 124 125 return analogix_dp_send_psr_spd(dp, &psr_vsc); 126 } 127 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr); 128 129 int analogix_dp_disable_psr(struct analogix_dp_device *dp) 130 { 131 struct edp_vsc_psr psr_vsc; 132 int ret; 133 134 if (!dp->psr_support) 135 return 0; 136 137 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ 138 memset(&psr_vsc, 0, sizeof(psr_vsc)); 139 psr_vsc.sdp_header.HB0 = 0; 140 psr_vsc.sdp_header.HB1 = 0x7; 141 psr_vsc.sdp_header.HB2 = 0x2; 142 psr_vsc.sdp_header.HB3 = 0x8; 143 144 psr_vsc.DB0 = 0; 145 psr_vsc.DB1 = 0; 146 147 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 148 if (ret != 1) 149 dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret); 150 151 return analogix_dp_send_psr_spd(dp, &psr_vsc); 152 } 153 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); 154 155 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) 156 { 157 unsigned char psr_version; 158 159 drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); 160 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); 161 162 return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; 163 } 164 165 static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) 166 { 167 unsigned char psr_en; 168 169 /* Disable psr function */ 170 drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en); 171 psr_en &= ~DP_PSR_ENABLE; 172 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 173 174 /* Main-Link transmitter remains active during PSR active states */ 175 psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; 176 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 177 178 /* Enable psr function */ 179 psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | 180 DP_PSR_CRC_VERIFICATION; 181 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); 182 183 analogix_dp_enable_psr_crc(dp); 184 } 185 186 static void 187 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 188 bool enable) 189 { 190 u8 data; 191 192 drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 193 194 if (enable) 195 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 196 DP_LANE_COUNT_ENHANCED_FRAME_EN | 197 DPCD_LANE_COUNT_SET(data)); 198 else 199 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 200 DPCD_LANE_COUNT_SET(data)); 201 } 202 203 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 204 { 205 u8 data; 206 int retval; 207 208 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 209 retval = DPCD_ENHANCED_FRAME_CAP(data); 210 211 return retval; 212 } 213 214 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 215 { 216 u8 data; 217 218 data = analogix_dp_is_enhanced_mode_available(dp); 219 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 220 analogix_dp_enable_enhanced_mode(dp, data); 221 } 222 223 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 224 { 225 analogix_dp_set_training_pattern(dp, DP_NONE); 226 227 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 228 DP_TRAINING_PATTERN_DISABLE); 229 } 230 231 static void 232 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp, 233 int pre_emphasis, int lane) 234 { 235 switch (lane) { 236 case 0: 237 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis); 238 break; 239 case 1: 240 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis); 241 break; 242 243 case 2: 244 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis); 245 break; 246 247 case 3: 248 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis); 249 break; 250 } 251 } 252 253 static int analogix_dp_link_start(struct analogix_dp_device *dp) 254 { 255 u8 buf[4]; 256 int lane, lane_count, pll_tries, retval; 257 258 lane_count = dp->link_train.lane_count; 259 260 dp->link_train.lt_state = CLOCK_RECOVERY; 261 dp->link_train.eq_loop = 0; 262 263 for (lane = 0; lane < lane_count; lane++) 264 dp->link_train.cr_loop[lane] = 0; 265 266 /* Set link rate and count as you want to establish*/ 267 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 268 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 269 270 /* Setup RX configuration */ 271 buf[0] = dp->link_train.link_rate; 272 buf[1] = dp->link_train.lane_count; 273 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 274 if (retval < 0) 275 return retval; 276 277 /* Set TX pre-emphasis to minimum */ 278 for (lane = 0; lane < lane_count; lane++) 279 analogix_dp_set_lane_lane_pre_emphasis(dp, 280 PRE_EMPHASIS_LEVEL_0, lane); 281 282 /* Wait for PLL lock */ 283 pll_tries = 0; 284 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 285 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { 286 dev_err(dp->dev, "Wait for PLL lock timed out\n"); 287 return -ETIMEDOUT; 288 } 289 290 pll_tries++; 291 usleep_range(90, 120); 292 } 293 294 /* Set training pattern 1 */ 295 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 296 297 /* Set RX training pattern */ 298 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 299 DP_LINK_SCRAMBLING_DISABLE | 300 DP_TRAINING_PATTERN_1); 301 if (retval < 0) 302 return retval; 303 304 for (lane = 0; lane < lane_count; lane++) 305 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 306 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 307 308 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 309 lane_count); 310 if (retval < 0) 311 return retval; 312 313 return 0; 314 } 315 316 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 317 { 318 int shift = (lane & 1) * 4; 319 u8 link_value = link_status[lane >> 1]; 320 321 return (link_value >> shift) & 0xf; 322 } 323 324 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 325 { 326 int lane; 327 u8 lane_status; 328 329 for (lane = 0; lane < lane_count; lane++) { 330 lane_status = analogix_dp_get_lane_status(link_status, lane); 331 if ((lane_status & DP_LANE_CR_DONE) == 0) 332 return -EINVAL; 333 } 334 return 0; 335 } 336 337 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 338 int lane_count) 339 { 340 int lane; 341 u8 lane_status; 342 343 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 344 return -EINVAL; 345 346 for (lane = 0; lane < lane_count; lane++) { 347 lane_status = analogix_dp_get_lane_status(link_status, lane); 348 lane_status &= DP_CHANNEL_EQ_BITS; 349 if (lane_status != DP_CHANNEL_EQ_BITS) 350 return -EINVAL; 351 } 352 353 return 0; 354 } 355 356 static unsigned char 357 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 358 { 359 int shift = (lane & 1) * 4; 360 u8 link_value = adjust_request[lane >> 1]; 361 362 return (link_value >> shift) & 0x3; 363 } 364 365 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 366 u8 adjust_request[2], 367 int lane) 368 { 369 int shift = (lane & 1) * 4; 370 u8 link_value = adjust_request[lane >> 1]; 371 372 return ((link_value >> shift) & 0xc) >> 2; 373 } 374 375 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp, 376 u8 training_lane_set, int lane) 377 { 378 switch (lane) { 379 case 0: 380 analogix_dp_set_lane0_link_training(dp, training_lane_set); 381 break; 382 case 1: 383 analogix_dp_set_lane1_link_training(dp, training_lane_set); 384 break; 385 386 case 2: 387 analogix_dp_set_lane2_link_training(dp, training_lane_set); 388 break; 389 390 case 3: 391 analogix_dp_set_lane3_link_training(dp, training_lane_set); 392 break; 393 } 394 } 395 396 static unsigned int 397 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, 398 int lane) 399 { 400 u32 reg; 401 402 switch (lane) { 403 case 0: 404 reg = analogix_dp_get_lane0_link_training(dp); 405 break; 406 case 1: 407 reg = analogix_dp_get_lane1_link_training(dp); 408 break; 409 case 2: 410 reg = analogix_dp_get_lane2_link_training(dp); 411 break; 412 case 3: 413 reg = analogix_dp_get_lane3_link_training(dp); 414 break; 415 default: 416 WARN_ON(1); 417 return 0; 418 } 419 420 return reg; 421 } 422 423 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 424 { 425 analogix_dp_training_pattern_dis(dp); 426 analogix_dp_set_enhanced_mode(dp); 427 428 dp->link_train.lt_state = FAILED; 429 } 430 431 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 432 u8 adjust_request[2]) 433 { 434 int lane, lane_count; 435 u8 voltage_swing, pre_emphasis, training_lane; 436 437 lane_count = dp->link_train.lane_count; 438 for (lane = 0; lane < lane_count; lane++) { 439 voltage_swing = analogix_dp_get_adjust_request_voltage( 440 adjust_request, lane); 441 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 442 adjust_request, lane); 443 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 444 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 445 446 if (voltage_swing == VOLTAGE_LEVEL_3) 447 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 448 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 449 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 450 451 dp->link_train.training_lane[lane] = training_lane; 452 } 453 } 454 455 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 456 { 457 int lane, lane_count, retval; 458 u8 voltage_swing, pre_emphasis, training_lane; 459 u8 link_status[2], adjust_request[2]; 460 461 usleep_range(100, 101); 462 463 lane_count = dp->link_train.lane_count; 464 465 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 466 if (retval < 0) 467 return retval; 468 469 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 470 adjust_request, 2); 471 if (retval < 0) 472 return retval; 473 474 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 475 /* set training pattern 2 for EQ */ 476 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 477 478 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 479 DP_LINK_SCRAMBLING_DISABLE | 480 DP_TRAINING_PATTERN_2); 481 if (retval < 0) 482 return retval; 483 484 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 485 dp->link_train.lt_state = EQUALIZER_TRAINING; 486 } else { 487 for (lane = 0; lane < lane_count; lane++) { 488 training_lane = analogix_dp_get_lane_link_training( 489 dp, lane); 490 voltage_swing = analogix_dp_get_adjust_request_voltage( 491 adjust_request, lane); 492 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 493 adjust_request, lane); 494 495 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 496 voltage_swing && 497 DPCD_PRE_EMPHASIS_GET(training_lane) == 498 pre_emphasis) 499 dp->link_train.cr_loop[lane]++; 500 501 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 502 voltage_swing == VOLTAGE_LEVEL_3 || 503 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 504 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 505 dp->link_train.cr_loop[lane], 506 voltage_swing, pre_emphasis); 507 analogix_dp_reduce_link_rate(dp); 508 return -EIO; 509 } 510 } 511 } 512 513 analogix_dp_get_adjust_training_lane(dp, adjust_request); 514 515 for (lane = 0; lane < lane_count; lane++) 516 analogix_dp_set_lane_link_training(dp, 517 dp->link_train.training_lane[lane], lane); 518 519 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 520 dp->link_train.training_lane, lane_count); 521 if (retval < 0) 522 return retval; 523 524 return 0; 525 } 526 527 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 528 { 529 int lane, lane_count, retval; 530 u32 reg; 531 u8 link_align, link_status[2], adjust_request[2]; 532 533 usleep_range(400, 401); 534 535 lane_count = dp->link_train.lane_count; 536 537 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 538 if (retval < 0) 539 return retval; 540 541 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 542 analogix_dp_reduce_link_rate(dp); 543 return -EIO; 544 } 545 546 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 547 adjust_request, 2); 548 if (retval < 0) 549 return retval; 550 551 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, 552 &link_align); 553 if (retval < 0) 554 return retval; 555 556 analogix_dp_get_adjust_training_lane(dp, adjust_request); 557 558 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 559 /* traing pattern Set to Normal */ 560 analogix_dp_training_pattern_dis(dp); 561 562 dev_info(dp->dev, "Link Training success!\n"); 563 564 analogix_dp_get_link_bandwidth(dp, ®); 565 dp->link_train.link_rate = reg; 566 dev_dbg(dp->dev, "final bandwidth = %.2x\n", 567 dp->link_train.link_rate); 568 569 analogix_dp_get_lane_count(dp, ®); 570 dp->link_train.lane_count = reg; 571 dev_dbg(dp->dev, "final lane count = %.2x\n", 572 dp->link_train.lane_count); 573 574 /* set enhanced mode if available */ 575 analogix_dp_set_enhanced_mode(dp); 576 dp->link_train.lt_state = FINISHED; 577 578 return 0; 579 } 580 581 /* not all locked */ 582 dp->link_train.eq_loop++; 583 584 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 585 dev_err(dp->dev, "EQ Max loop\n"); 586 analogix_dp_reduce_link_rate(dp); 587 return -EIO; 588 } 589 590 for (lane = 0; lane < lane_count; lane++) 591 analogix_dp_set_lane_link_training(dp, 592 dp->link_train.training_lane[lane], lane); 593 594 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 595 dp->link_train.training_lane, lane_count); 596 if (retval < 0) 597 return retval; 598 599 return 0; 600 } 601 602 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 603 u8 *bandwidth) 604 { 605 u8 data; 606 607 /* 608 * For DP rev.1.1, Maximum link rate of Main Link lanes 609 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 610 * For DP rev.1.2, Maximum link rate of Main Link lanes 611 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 612 */ 613 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 614 *bandwidth = data; 615 } 616 617 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 618 u8 *lane_count) 619 { 620 u8 data; 621 622 /* 623 * For DP rev.1.1, Maximum number of Main Link lanes 624 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 625 */ 626 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 627 *lane_count = DPCD_MAX_LANE_COUNT(data); 628 } 629 630 static void analogix_dp_init_training(struct analogix_dp_device *dp, 631 enum link_lane_count_type max_lane, 632 int max_rate) 633 { 634 /* 635 * MACRO_RST must be applied after the PLL_LOCK to avoid 636 * the DP inter pair skew issue for at least 10 us 637 */ 638 analogix_dp_reset_macro(dp); 639 640 /* Initialize by reading RX's DPCD */ 641 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 642 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 643 644 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 645 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 646 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 647 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", 648 dp->link_train.link_rate); 649 dp->link_train.link_rate = DP_LINK_BW_1_62; 650 } 651 652 if (dp->link_train.lane_count == 0) { 653 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", 654 dp->link_train.lane_count); 655 dp->link_train.lane_count = (u8)LANE_COUNT1; 656 } 657 658 /* Setup TX lane count & rate */ 659 if (dp->link_train.lane_count > max_lane) 660 dp->link_train.lane_count = max_lane; 661 if (dp->link_train.link_rate > max_rate) 662 dp->link_train.link_rate = max_rate; 663 664 /* All DP analog module power up */ 665 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 666 } 667 668 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 669 { 670 int retval = 0, training_finished = 0; 671 672 dp->link_train.lt_state = START; 673 674 /* Process here */ 675 while (!retval && !training_finished) { 676 switch (dp->link_train.lt_state) { 677 case START: 678 retval = analogix_dp_link_start(dp); 679 if (retval) 680 dev_err(dp->dev, "LT link start failed!\n"); 681 break; 682 case CLOCK_RECOVERY: 683 retval = analogix_dp_process_clock_recovery(dp); 684 if (retval) 685 dev_err(dp->dev, "LT CR failed!\n"); 686 break; 687 case EQUALIZER_TRAINING: 688 retval = analogix_dp_process_equalizer_training(dp); 689 if (retval) 690 dev_err(dp->dev, "LT EQ failed!\n"); 691 break; 692 case FINISHED: 693 training_finished = 1; 694 break; 695 case FAILED: 696 return -EREMOTEIO; 697 } 698 } 699 if (retval) 700 dev_err(dp->dev, "eDP link training failed (%d)\n", retval); 701 702 return retval; 703 } 704 705 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 706 u32 count, u32 bwtype) 707 { 708 int i; 709 int retval; 710 711 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { 712 analogix_dp_init_training(dp, count, bwtype); 713 retval = analogix_dp_sw_link_training(dp); 714 if (retval == 0) 715 break; 716 717 usleep_range(100, 110); 718 } 719 720 return retval; 721 } 722 723 static int analogix_dp_config_video(struct analogix_dp_device *dp) 724 { 725 int timeout_loop = 0; 726 int done_count = 0; 727 728 analogix_dp_config_video_slave_mode(dp); 729 730 analogix_dp_set_video_color_format(dp); 731 732 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 733 dev_err(dp->dev, "PLL is not locked yet.\n"); 734 return -EINVAL; 735 } 736 737 for (;;) { 738 timeout_loop++; 739 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 740 break; 741 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 742 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 743 return -ETIMEDOUT; 744 } 745 746 usleep_range(1, 2); 747 } 748 749 /* Set to use the register calculated M/N video */ 750 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 751 752 /* For video bist, Video timing must be generated by register */ 753 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 754 755 /* Disable video mute */ 756 analogix_dp_enable_video_mute(dp, 0); 757 758 /* Configure video slave mode */ 759 analogix_dp_enable_video_master(dp, 0); 760 761 timeout_loop = 0; 762 763 for (;;) { 764 timeout_loop++; 765 if (analogix_dp_is_video_stream_on(dp) == 0) { 766 done_count++; 767 if (done_count > 10) 768 break; 769 } else if (done_count) { 770 done_count = 0; 771 } 772 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 773 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 774 return -ETIMEDOUT; 775 } 776 777 usleep_range(1000, 1001); 778 } 779 780 return 0; 781 } 782 783 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 784 bool enable) 785 { 786 u8 data; 787 788 if (enable) { 789 analogix_dp_enable_scrambling(dp); 790 791 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); 792 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 793 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 794 } else { 795 analogix_dp_disable_scrambling(dp); 796 797 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data); 798 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 799 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 800 } 801 } 802 803 static irqreturn_t analogix_dp_hardirq(int irq, void *arg) 804 { 805 struct analogix_dp_device *dp = arg; 806 irqreturn_t ret = IRQ_NONE; 807 enum dp_irq_type irq_type; 808 809 irq_type = analogix_dp_get_irq_type(dp); 810 if (irq_type != DP_IRQ_TYPE_UNKNOWN) { 811 analogix_dp_mute_hpd_interrupt(dp); 812 ret = IRQ_WAKE_THREAD; 813 } 814 815 return ret; 816 } 817 818 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg) 819 { 820 struct analogix_dp_device *dp = arg; 821 enum dp_irq_type irq_type; 822 823 irq_type = analogix_dp_get_irq_type(dp); 824 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN || 825 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) { 826 dev_dbg(dp->dev, "Detected cable status changed!\n"); 827 if (dp->drm_dev) 828 drm_helper_hpd_irq_event(dp->drm_dev); 829 } 830 831 if (irq_type != DP_IRQ_TYPE_UNKNOWN) { 832 analogix_dp_clear_hotplug_interrupts(dp); 833 analogix_dp_unmute_hpd_interrupt(dp); 834 } 835 836 return IRQ_HANDLED; 837 } 838 839 static void analogix_dp_commit(struct analogix_dp_device *dp) 840 { 841 int ret; 842 843 /* Keep the panel disabled while we configure video */ 844 if (dp->plat_data->panel) { 845 if (drm_panel_disable(dp->plat_data->panel)) 846 DRM_ERROR("failed to disable the panel\n"); 847 } 848 849 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 850 dp->video_info.max_link_rate); 851 if (ret) { 852 dev_err(dp->dev, "unable to do link train\n"); 853 return; 854 } 855 856 analogix_dp_enable_scramble(dp, 1); 857 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 858 analogix_dp_enable_enhanced_mode(dp, 1); 859 860 analogix_dp_init_video(dp); 861 ret = analogix_dp_config_video(dp); 862 if (ret) 863 dev_err(dp->dev, "unable to config video\n"); 864 865 /* Safe to enable the panel now */ 866 if (dp->plat_data->panel) { 867 if (drm_panel_enable(dp->plat_data->panel)) 868 DRM_ERROR("failed to enable the panel\n"); 869 } 870 871 /* Enable video */ 872 analogix_dp_start_video(dp); 873 874 dp->psr_support = analogix_dp_detect_sink_psr(dp); 875 if (dp->psr_support) 876 analogix_dp_enable_sink_psr(dp); 877 } 878 879 /* 880 * This function is a bit of a catch-all for panel preparation, hopefully 881 * simplifying the logic of functions that need to prepare/unprepare the panel 882 * below. 883 * 884 * If @prepare is true, this function will prepare the panel. Conversely, if it 885 * is false, the panel will be unprepared. 886 * 887 * If @is_modeset_prepare is true, the function will disregard the current state 888 * of the panel and either prepare/unprepare the panel based on @prepare. Once 889 * it finishes, it will update dp->panel_is_modeset to reflect the current state 890 * of the panel. 891 */ 892 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp, 893 bool prepare, bool is_modeset_prepare) 894 { 895 int ret = 0; 896 897 if (!dp->plat_data->panel) 898 return 0; 899 900 mutex_lock(&dp->panel_lock); 901 902 /* 903 * Exit early if this is a temporary prepare/unprepare and we're already 904 * modeset (since we neither want to prepare twice or unprepare early). 905 */ 906 if (dp->panel_is_modeset && !is_modeset_prepare) 907 goto out; 908 909 if (prepare) 910 ret = drm_panel_prepare(dp->plat_data->panel); 911 else 912 ret = drm_panel_unprepare(dp->plat_data->panel); 913 914 if (ret) 915 goto out; 916 917 if (is_modeset_prepare) 918 dp->panel_is_modeset = prepare; 919 920 out: 921 mutex_unlock(&dp->panel_lock); 922 return ret; 923 } 924 925 static int analogix_dp_get_modes(struct drm_connector *connector) 926 { 927 struct analogix_dp_device *dp = to_dp(connector); 928 struct edid *edid; 929 int ret, num_modes = 0; 930 931 if (dp->plat_data->panel) { 932 num_modes += drm_panel_get_modes(dp->plat_data->panel); 933 } else { 934 ret = analogix_dp_prepare_panel(dp, true, false); 935 if (ret) { 936 DRM_ERROR("Failed to prepare panel (%d)\n", ret); 937 return 0; 938 } 939 940 pm_runtime_get_sync(dp->dev); 941 edid = drm_get_edid(connector, &dp->aux.ddc); 942 pm_runtime_put(dp->dev); 943 if (edid) { 944 drm_mode_connector_update_edid_property(&dp->connector, 945 edid); 946 num_modes += drm_add_edid_modes(&dp->connector, edid); 947 kfree(edid); 948 } 949 950 ret = analogix_dp_prepare_panel(dp, false, false); 951 if (ret) 952 DRM_ERROR("Failed to unprepare panel (%d)\n", ret); 953 } 954 955 if (dp->plat_data->get_modes) 956 num_modes += dp->plat_data->get_modes(dp->plat_data, connector); 957 958 return num_modes; 959 } 960 961 static struct drm_encoder * 962 analogix_dp_best_encoder(struct drm_connector *connector) 963 { 964 struct analogix_dp_device *dp = to_dp(connector); 965 966 return dp->encoder; 967 } 968 969 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = { 970 .get_modes = analogix_dp_get_modes, 971 .best_encoder = analogix_dp_best_encoder, 972 }; 973 974 static enum drm_connector_status 975 analogix_dp_detect(struct drm_connector *connector, bool force) 976 { 977 struct analogix_dp_device *dp = to_dp(connector); 978 enum drm_connector_status status = connector_status_disconnected; 979 int ret; 980 981 if (dp->plat_data->panel) 982 return connector_status_connected; 983 984 ret = analogix_dp_prepare_panel(dp, true, false); 985 if (ret) { 986 DRM_ERROR("Failed to prepare panel (%d)\n", ret); 987 return connector_status_disconnected; 988 } 989 990 if (!analogix_dp_detect_hpd(dp)) 991 status = connector_status_connected; 992 993 ret = analogix_dp_prepare_panel(dp, false, false); 994 if (ret) 995 DRM_ERROR("Failed to unprepare panel (%d)\n", ret); 996 997 return status; 998 } 999 1000 static const struct drm_connector_funcs analogix_dp_connector_funcs = { 1001 .fill_modes = drm_helper_probe_single_connector_modes, 1002 .detect = analogix_dp_detect, 1003 .destroy = drm_connector_cleanup, 1004 .reset = drm_atomic_helper_connector_reset, 1005 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1006 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1007 }; 1008 1009 static int analogix_dp_bridge_attach(struct drm_bridge *bridge) 1010 { 1011 struct analogix_dp_device *dp = bridge->driver_private; 1012 struct drm_encoder *encoder = dp->encoder; 1013 struct drm_connector *connector = NULL; 1014 int ret = 0; 1015 1016 if (!bridge->encoder) { 1017 DRM_ERROR("Parent encoder object not found"); 1018 return -ENODEV; 1019 } 1020 1021 if (!dp->plat_data->skip_connector) { 1022 connector = &dp->connector; 1023 connector->polled = DRM_CONNECTOR_POLL_HPD; 1024 1025 ret = drm_connector_init(dp->drm_dev, connector, 1026 &analogix_dp_connector_funcs, 1027 DRM_MODE_CONNECTOR_eDP); 1028 if (ret) { 1029 DRM_ERROR("Failed to initialize connector with drm\n"); 1030 return ret; 1031 } 1032 1033 drm_connector_helper_add(connector, 1034 &analogix_dp_connector_helper_funcs); 1035 drm_mode_connector_attach_encoder(connector, encoder); 1036 } 1037 1038 /* 1039 * NOTE: the connector registration is implemented in analogix 1040 * platform driver, that to say connector would be exist after 1041 * plat_data->attch return, that's why we record the connector 1042 * point after plat attached. 1043 */ 1044 if (dp->plat_data->attach) { 1045 ret = dp->plat_data->attach(dp->plat_data, bridge, connector); 1046 if (ret) { 1047 DRM_ERROR("Failed at platform attch func\n"); 1048 return ret; 1049 } 1050 } 1051 1052 if (dp->plat_data->panel) { 1053 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector); 1054 if (ret) { 1055 DRM_ERROR("Failed to attach panel\n"); 1056 return ret; 1057 } 1058 } 1059 1060 return 0; 1061 } 1062 1063 static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge) 1064 { 1065 struct analogix_dp_device *dp = bridge->driver_private; 1066 int ret; 1067 1068 ret = analogix_dp_prepare_panel(dp, true, true); 1069 if (ret) 1070 DRM_ERROR("failed to setup the panel ret = %d\n", ret); 1071 } 1072 1073 static void analogix_dp_bridge_enable(struct drm_bridge *bridge) 1074 { 1075 struct analogix_dp_device *dp = bridge->driver_private; 1076 1077 if (dp->dpms_mode == DRM_MODE_DPMS_ON) 1078 return; 1079 1080 pm_runtime_get_sync(dp->dev); 1081 1082 if (dp->plat_data->power_on) 1083 dp->plat_data->power_on(dp->plat_data); 1084 1085 phy_power_on(dp->phy); 1086 analogix_dp_init_dp(dp); 1087 enable_irq(dp->irq); 1088 analogix_dp_commit(dp); 1089 1090 dp->dpms_mode = DRM_MODE_DPMS_ON; 1091 } 1092 1093 static void analogix_dp_bridge_disable(struct drm_bridge *bridge) 1094 { 1095 struct analogix_dp_device *dp = bridge->driver_private; 1096 int ret; 1097 1098 if (dp->dpms_mode != DRM_MODE_DPMS_ON) 1099 return; 1100 1101 if (dp->plat_data->panel) { 1102 if (drm_panel_disable(dp->plat_data->panel)) { 1103 DRM_ERROR("failed to disable the panel\n"); 1104 return; 1105 } 1106 } 1107 1108 disable_irq(dp->irq); 1109 phy_power_off(dp->phy); 1110 1111 if (dp->plat_data->power_off) 1112 dp->plat_data->power_off(dp->plat_data); 1113 1114 pm_runtime_put_sync(dp->dev); 1115 1116 ret = analogix_dp_prepare_panel(dp, false, true); 1117 if (ret) 1118 DRM_ERROR("failed to setup the panel ret = %d\n", ret); 1119 1120 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1121 } 1122 1123 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, 1124 struct drm_display_mode *orig_mode, 1125 struct drm_display_mode *mode) 1126 { 1127 struct analogix_dp_device *dp = bridge->driver_private; 1128 struct drm_display_info *display_info = &dp->connector.display_info; 1129 struct video_info *video = &dp->video_info; 1130 struct device_node *dp_node = dp->dev->of_node; 1131 int vic; 1132 1133 /* Input video interlaces & hsync pol & vsync pol */ 1134 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 1135 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); 1136 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); 1137 1138 /* Input video dynamic_range & colorimetry */ 1139 vic = drm_match_cea_mode(mode); 1140 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || 1141 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) { 1142 video->dynamic_range = CEA; 1143 video->ycbcr_coeff = COLOR_YCBCR601; 1144 } else if (vic) { 1145 video->dynamic_range = CEA; 1146 video->ycbcr_coeff = COLOR_YCBCR709; 1147 } else { 1148 video->dynamic_range = VESA; 1149 video->ycbcr_coeff = COLOR_YCBCR709; 1150 } 1151 1152 /* Input vide bpc and color_formats */ 1153 switch (display_info->bpc) { 1154 case 12: 1155 video->color_depth = COLOR_12; 1156 break; 1157 case 10: 1158 video->color_depth = COLOR_10; 1159 break; 1160 case 8: 1161 video->color_depth = COLOR_8; 1162 break; 1163 case 6: 1164 video->color_depth = COLOR_6; 1165 break; 1166 default: 1167 video->color_depth = COLOR_8; 1168 break; 1169 } 1170 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 1171 video->color_space = COLOR_YCBCR444; 1172 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1173 video->color_space = COLOR_YCBCR422; 1174 else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444) 1175 video->color_space = COLOR_RGB; 1176 else 1177 video->color_space = COLOR_RGB; 1178 1179 /* 1180 * NOTE: those property parsing code is used for providing backward 1181 * compatibility for samsung platform. 1182 * Due to we used the "of_property_read_u32" interfaces, when this 1183 * property isn't present, the "video_info" can keep the original 1184 * values and wouldn't be modified. 1185 */ 1186 of_property_read_u32(dp_node, "samsung,color-space", 1187 &video->color_space); 1188 of_property_read_u32(dp_node, "samsung,dynamic-range", 1189 &video->dynamic_range); 1190 of_property_read_u32(dp_node, "samsung,ycbcr-coeff", 1191 &video->ycbcr_coeff); 1192 of_property_read_u32(dp_node, "samsung,color-depth", 1193 &video->color_depth); 1194 if (of_property_read_bool(dp_node, "hsync-active-high")) 1195 video->h_sync_polarity = true; 1196 if (of_property_read_bool(dp_node, "vsync-active-high")) 1197 video->v_sync_polarity = true; 1198 if (of_property_read_bool(dp_node, "interlaced")) 1199 video->interlaced = true; 1200 } 1201 1202 static void analogix_dp_bridge_nop(struct drm_bridge *bridge) 1203 { 1204 /* do nothing */ 1205 } 1206 1207 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = { 1208 .pre_enable = analogix_dp_bridge_pre_enable, 1209 .enable = analogix_dp_bridge_enable, 1210 .disable = analogix_dp_bridge_disable, 1211 .post_disable = analogix_dp_bridge_nop, 1212 .mode_set = analogix_dp_bridge_mode_set, 1213 .attach = analogix_dp_bridge_attach, 1214 }; 1215 1216 static int analogix_dp_create_bridge(struct drm_device *drm_dev, 1217 struct analogix_dp_device *dp) 1218 { 1219 struct drm_bridge *bridge; 1220 int ret; 1221 1222 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL); 1223 if (!bridge) { 1224 DRM_ERROR("failed to allocate for drm bridge\n"); 1225 return -ENOMEM; 1226 } 1227 1228 dp->bridge = bridge; 1229 1230 bridge->driver_private = dp; 1231 bridge->funcs = &analogix_dp_bridge_funcs; 1232 1233 ret = drm_bridge_attach(dp->encoder, bridge, NULL); 1234 if (ret) { 1235 DRM_ERROR("failed to attach drm bridge\n"); 1236 return -EINVAL; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) 1243 { 1244 struct device_node *dp_node = dp->dev->of_node; 1245 struct video_info *video_info = &dp->video_info; 1246 1247 switch (dp->plat_data->dev_type) { 1248 case RK3288_DP: 1249 case RK3399_EDP: 1250 /* 1251 * Like Rk3288 DisplayPort TRM indicate that "Main link 1252 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 1253 */ 1254 video_info->max_link_rate = 0x0A; 1255 video_info->max_lane_count = 0x04; 1256 break; 1257 case EXYNOS_DP: 1258 /* 1259 * NOTE: those property parseing code is used for 1260 * providing backward compatibility for samsung platform. 1261 */ 1262 of_property_read_u32(dp_node, "samsung,link-rate", 1263 &video_info->max_link_rate); 1264 of_property_read_u32(dp_node, "samsung,lane-count", 1265 &video_info->max_lane_count); 1266 break; 1267 } 1268 1269 return 0; 1270 } 1271 1272 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux, 1273 struct drm_dp_aux_msg *msg) 1274 { 1275 struct analogix_dp_device *dp = to_dp(aux); 1276 1277 return analogix_dp_transfer(dp, msg); 1278 } 1279 1280 struct analogix_dp_device * 1281 analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, 1282 struct analogix_dp_plat_data *plat_data) 1283 { 1284 struct platform_device *pdev = to_platform_device(dev); 1285 struct analogix_dp_device *dp; 1286 struct resource *res; 1287 unsigned int irq_flags; 1288 int ret; 1289 1290 if (!plat_data) { 1291 dev_err(dev, "Invalided input plat_data\n"); 1292 return ERR_PTR(-EINVAL); 1293 } 1294 1295 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL); 1296 if (!dp) 1297 return ERR_PTR(-ENOMEM); 1298 1299 dp->dev = &pdev->dev; 1300 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1301 1302 mutex_init(&dp->panel_lock); 1303 dp->panel_is_modeset = false; 1304 1305 /* 1306 * platform dp driver need containor_of the plat_data to get 1307 * the driver private data, so we need to store the point of 1308 * plat_data, not the context of plat_data. 1309 */ 1310 dp->plat_data = plat_data; 1311 1312 ret = analogix_dp_dt_parse_pdata(dp); 1313 if (ret) 1314 return ERR_PTR(ret); 1315 1316 dp->phy = devm_phy_get(dp->dev, "dp"); 1317 if (IS_ERR(dp->phy)) { 1318 dev_err(dp->dev, "no DP phy configured\n"); 1319 ret = PTR_ERR(dp->phy); 1320 if (ret) { 1321 /* 1322 * phy itself is not enabled, so we can move forward 1323 * assigning NULL to phy pointer. 1324 */ 1325 if (ret == -ENOSYS || ret == -ENODEV) 1326 dp->phy = NULL; 1327 else 1328 return ERR_PTR(ret); 1329 } 1330 } 1331 1332 dp->clock = devm_clk_get(&pdev->dev, "dp"); 1333 if (IS_ERR(dp->clock)) { 1334 dev_err(&pdev->dev, "failed to get clock\n"); 1335 return ERR_CAST(dp->clock); 1336 } 1337 1338 clk_prepare_enable(dp->clock); 1339 1340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1341 1342 dp->reg_base = devm_ioremap_resource(&pdev->dev, res); 1343 if (IS_ERR(dp->reg_base)) 1344 return ERR_CAST(dp->reg_base); 1345 1346 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd"); 1347 1348 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0); 1349 if (!gpio_is_valid(dp->hpd_gpio)) 1350 dp->hpd_gpio = of_get_named_gpio(dev->of_node, 1351 "samsung,hpd-gpio", 0); 1352 1353 if (gpio_is_valid(dp->hpd_gpio)) { 1354 /* 1355 * Set up the hotplug GPIO from the device tree as an interrupt. 1356 * Simply specifying a different interrupt in the device tree 1357 * doesn't work since we handle hotplug rather differently when 1358 * using a GPIO. We also need the actual GPIO specifier so 1359 * that we can get the current state of the GPIO. 1360 */ 1361 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN, 1362 "hpd_gpio"); 1363 if (ret) { 1364 dev_err(&pdev->dev, "failed to get hpd gpio\n"); 1365 return ERR_PTR(ret); 1366 } 1367 dp->irq = gpio_to_irq(dp->hpd_gpio); 1368 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; 1369 } else { 1370 dp->hpd_gpio = -ENODEV; 1371 dp->irq = platform_get_irq(pdev, 0); 1372 irq_flags = 0; 1373 } 1374 1375 if (dp->irq == -ENXIO) { 1376 dev_err(&pdev->dev, "failed to get irq\n"); 1377 return ERR_PTR(-ENODEV); 1378 } 1379 1380 ret = devm_request_threaded_irq(&pdev->dev, dp->irq, 1381 analogix_dp_hardirq, 1382 analogix_dp_irq_thread, 1383 irq_flags, "analogix-dp", dp); 1384 if (ret) { 1385 dev_err(&pdev->dev, "failed to request irq\n"); 1386 goto err_disable_pm_runtime; 1387 } 1388 disable_irq(dp->irq); 1389 1390 dp->drm_dev = drm_dev; 1391 dp->encoder = dp->plat_data->encoder; 1392 1393 dp->aux.name = "DP-AUX"; 1394 dp->aux.transfer = analogix_dpaux_transfer; 1395 dp->aux.dev = &pdev->dev; 1396 1397 ret = drm_dp_aux_register(&dp->aux); 1398 if (ret) 1399 return ERR_PTR(ret); 1400 1401 pm_runtime_enable(dev); 1402 1403 ret = analogix_dp_create_bridge(drm_dev, dp); 1404 if (ret) { 1405 DRM_ERROR("failed to create bridge (%d)\n", ret); 1406 goto err_disable_pm_runtime; 1407 } 1408 1409 return dp; 1410 1411 err_disable_pm_runtime: 1412 1413 pm_runtime_disable(dev); 1414 1415 return ERR_PTR(ret); 1416 } 1417 EXPORT_SYMBOL_GPL(analogix_dp_bind); 1418 1419 void analogix_dp_unbind(struct analogix_dp_device *dp) 1420 { 1421 analogix_dp_bridge_disable(dp->bridge); 1422 dp->connector.funcs->destroy(&dp->connector); 1423 1424 if (dp->plat_data->panel) { 1425 if (drm_panel_unprepare(dp->plat_data->panel)) 1426 DRM_ERROR("failed to turnoff the panel\n"); 1427 if (drm_panel_detach(dp->plat_data->panel)) 1428 DRM_ERROR("failed to detach the panel\n"); 1429 } 1430 1431 drm_dp_aux_unregister(&dp->aux); 1432 pm_runtime_disable(dp->dev); 1433 clk_disable_unprepare(dp->clock); 1434 } 1435 EXPORT_SYMBOL_GPL(analogix_dp_unbind); 1436 1437 #ifdef CONFIG_PM 1438 int analogix_dp_suspend(struct analogix_dp_device *dp) 1439 { 1440 clk_disable_unprepare(dp->clock); 1441 1442 if (dp->plat_data->panel) { 1443 if (drm_panel_unprepare(dp->plat_data->panel)) 1444 DRM_ERROR("failed to turnoff the panel\n"); 1445 } 1446 1447 return 0; 1448 } 1449 EXPORT_SYMBOL_GPL(analogix_dp_suspend); 1450 1451 int analogix_dp_resume(struct analogix_dp_device *dp) 1452 { 1453 int ret; 1454 1455 ret = clk_prepare_enable(dp->clock); 1456 if (ret < 0) { 1457 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret); 1458 return ret; 1459 } 1460 1461 if (dp->plat_data->panel) { 1462 if (drm_panel_prepare(dp->plat_data->panel)) { 1463 DRM_ERROR("failed to setup the panel\n"); 1464 return -EBUSY; 1465 } 1466 } 1467 1468 return 0; 1469 } 1470 EXPORT_SYMBOL_GPL(analogix_dp_resume); 1471 #endif 1472 1473 int analogix_dp_start_crc(struct drm_connector *connector) 1474 { 1475 struct analogix_dp_device *dp = to_dp(connector); 1476 1477 if (!connector->state->crtc) { 1478 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n", 1479 connector->name); 1480 return -EINVAL; 1481 } 1482 1483 return drm_dp_start_crc(&dp->aux, connector->state->crtc); 1484 } 1485 EXPORT_SYMBOL_GPL(analogix_dp_start_crc); 1486 1487 int analogix_dp_stop_crc(struct drm_connector *connector) 1488 { 1489 struct analogix_dp_device *dp = to_dp(connector); 1490 1491 return drm_dp_stop_crc(&dp->aux); 1492 } 1493 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc); 1494 1495 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); 1496 MODULE_DESCRIPTION("Analogix DP Core Driver"); 1497 MODULE_LICENSE("GPL v2"); 1498