16aa19269SIcenowy Zheng /* SPDX-License-Identifier: GPL-2.0-only */ 26aa19269SIcenowy Zheng /* 36aa19269SIcenowy Zheng * Copyright(c) 2016, Analogix Semiconductor. 46aa19269SIcenowy Zheng * Copyright(c) 2017, Icenowy Zheng <icenowy@aosc.io> 56aa19269SIcenowy Zheng * 66aa19269SIcenowy Zheng * Based on anx7808 driver obtained from chromeos with copyright: 76aa19269SIcenowy Zheng * Copyright(c) 2013, Google Inc. 86aa19269SIcenowy Zheng */ 96aa19269SIcenowy Zheng #include <linux/delay.h> 106aa19269SIcenowy Zheng #include <linux/err.h> 116aa19269SIcenowy Zheng #include <linux/gpio/consumer.h> 126aa19269SIcenowy Zheng #include <linux/i2c.h> 136aa19269SIcenowy Zheng #include <linux/interrupt.h> 146aa19269SIcenowy Zheng #include <linux/kernel.h> 156aa19269SIcenowy Zheng #include <linux/module.h> 166aa19269SIcenowy Zheng #include <linux/of_platform.h> 176aa19269SIcenowy Zheng #include <linux/regmap.h> 186aa19269SIcenowy Zheng #include <linux/regulator/consumer.h> 196aa19269SIcenowy Zheng #include <linux/types.h> 206aa19269SIcenowy Zheng 21da68386dSThomas Zimmermann #include <drm/display/drm_dp_helper.h> 226aa19269SIcenowy Zheng #include <drm/drm_atomic_helper.h> 23e1cff82cSTorsten Duwe #include <drm/drm_bridge.h> 246aa19269SIcenowy Zheng #include <drm/drm_crtc.h> 256aa19269SIcenowy Zheng #include <drm/drm_edid.h> 266aa19269SIcenowy Zheng #include <drm/drm_of.h> 276aa19269SIcenowy Zheng #include <drm/drm_panel.h> 286aa19269SIcenowy Zheng #include <drm/drm_print.h> 296aa19269SIcenowy Zheng #include <drm/drm_probe_helper.h> 306aa19269SIcenowy Zheng 316aa19269SIcenowy Zheng #include "analogix-i2c-dptx.h" 326aa19269SIcenowy Zheng #include "analogix-i2c-txcommon.h" 336aa19269SIcenowy Zheng 346aa19269SIcenowy Zheng #define POLL_DELAY 50000 /* us */ 356aa19269SIcenowy Zheng #define POLL_TIMEOUT 5000000 /* us */ 366aa19269SIcenowy Zheng 376aa19269SIcenowy Zheng #define I2C_IDX_DPTX 0 386aa19269SIcenowy Zheng #define I2C_IDX_TXCOM 1 396aa19269SIcenowy Zheng 406aa19269SIcenowy Zheng static const u8 anx6345_i2c_addresses[] = { 416aa19269SIcenowy Zheng [I2C_IDX_DPTX] = 0x70, 426aa19269SIcenowy Zheng [I2C_IDX_TXCOM] = 0x72, 436aa19269SIcenowy Zheng }; 446aa19269SIcenowy Zheng #define I2C_NUM_ADDRESSES ARRAY_SIZE(anx6345_i2c_addresses) 456aa19269SIcenowy Zheng 466aa19269SIcenowy Zheng struct anx6345 { 476aa19269SIcenowy Zheng struct drm_dp_aux aux; 486aa19269SIcenowy Zheng struct drm_bridge bridge; 496aa19269SIcenowy Zheng struct i2c_client *client; 506aa19269SIcenowy Zheng struct edid *edid; 516aa19269SIcenowy Zheng struct drm_connector connector; 526aa19269SIcenowy Zheng struct drm_panel *panel; 536aa19269SIcenowy Zheng struct regulator *dvdd12; 546aa19269SIcenowy Zheng struct regulator *dvdd25; 556aa19269SIcenowy Zheng struct gpio_desc *gpiod_reset; 566aa19269SIcenowy Zheng struct mutex lock; /* protect EDID access */ 576aa19269SIcenowy Zheng 586aa19269SIcenowy Zheng /* I2C Slave addresses of ANX6345 are mapped as DPTX and SYS */ 596aa19269SIcenowy Zheng struct i2c_client *i2c_clients[I2C_NUM_ADDRESSES]; 606aa19269SIcenowy Zheng struct regmap *map[I2C_NUM_ADDRESSES]; 616aa19269SIcenowy Zheng 626aa19269SIcenowy Zheng u16 chipid; 636aa19269SIcenowy Zheng u8 dpcd[DP_RECEIVER_CAP_SIZE]; 646aa19269SIcenowy Zheng 656aa19269SIcenowy Zheng bool powered; 666aa19269SIcenowy Zheng }; 676aa19269SIcenowy Zheng 686aa19269SIcenowy Zheng static inline struct anx6345 *connector_to_anx6345(struct drm_connector *c) 696aa19269SIcenowy Zheng { 706aa19269SIcenowy Zheng return container_of(c, struct anx6345, connector); 716aa19269SIcenowy Zheng } 726aa19269SIcenowy Zheng 736aa19269SIcenowy Zheng static inline struct anx6345 *bridge_to_anx6345(struct drm_bridge *bridge) 746aa19269SIcenowy Zheng { 756aa19269SIcenowy Zheng return container_of(bridge, struct anx6345, bridge); 766aa19269SIcenowy Zheng } 776aa19269SIcenowy Zheng 786aa19269SIcenowy Zheng static int anx6345_set_bits(struct regmap *map, u8 reg, u8 mask) 796aa19269SIcenowy Zheng { 806aa19269SIcenowy Zheng return regmap_update_bits(map, reg, mask, mask); 816aa19269SIcenowy Zheng } 826aa19269SIcenowy Zheng 836aa19269SIcenowy Zheng static int anx6345_clear_bits(struct regmap *map, u8 reg, u8 mask) 846aa19269SIcenowy Zheng { 856aa19269SIcenowy Zheng return regmap_update_bits(map, reg, mask, 0); 866aa19269SIcenowy Zheng } 876aa19269SIcenowy Zheng 886aa19269SIcenowy Zheng static ssize_t anx6345_aux_transfer(struct drm_dp_aux *aux, 896aa19269SIcenowy Zheng struct drm_dp_aux_msg *msg) 906aa19269SIcenowy Zheng { 916aa19269SIcenowy Zheng struct anx6345 *anx6345 = container_of(aux, struct anx6345, aux); 926aa19269SIcenowy Zheng 936aa19269SIcenowy Zheng return anx_dp_aux_transfer(anx6345->map[I2C_IDX_DPTX], msg); 946aa19269SIcenowy Zheng } 956aa19269SIcenowy Zheng 966aa19269SIcenowy Zheng static int anx6345_dp_link_training(struct anx6345 *anx6345) 976aa19269SIcenowy Zheng { 986aa19269SIcenowy Zheng unsigned int value; 99e1cff82cSTorsten Duwe u8 dp_bw, dpcd[2]; 1006aa19269SIcenowy Zheng int err; 1016aa19269SIcenowy Zheng 1026aa19269SIcenowy Zheng err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], 1036aa19269SIcenowy Zheng SP_POWERDOWN_CTRL_REG, 1046aa19269SIcenowy Zheng SP_TOTAL_PD); 1056aa19269SIcenowy Zheng if (err) 1066aa19269SIcenowy Zheng return err; 1076aa19269SIcenowy Zheng 1086aa19269SIcenowy Zheng err = drm_dp_dpcd_readb(&anx6345->aux, DP_MAX_LINK_RATE, &dp_bw); 1096aa19269SIcenowy Zheng if (err < 0) 1106aa19269SIcenowy Zheng return err; 1116aa19269SIcenowy Zheng 1126aa19269SIcenowy Zheng switch (dp_bw) { 1136aa19269SIcenowy Zheng case DP_LINK_BW_1_62: 1146aa19269SIcenowy Zheng case DP_LINK_BW_2_7: 1156aa19269SIcenowy Zheng break; 1166aa19269SIcenowy Zheng 1176aa19269SIcenowy Zheng default: 1186aa19269SIcenowy Zheng DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw); 1196aa19269SIcenowy Zheng return -EINVAL; 1206aa19269SIcenowy Zheng } 1216aa19269SIcenowy Zheng 1226aa19269SIcenowy Zheng err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG, 1236aa19269SIcenowy Zheng SP_VIDEO_MUTE); 1246aa19269SIcenowy Zheng if (err) 1256aa19269SIcenowy Zheng return err; 1266aa19269SIcenowy Zheng 1276aa19269SIcenowy Zheng err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], 1286aa19269SIcenowy Zheng SP_VID_CTRL1_REG, SP_VIDEO_EN); 1296aa19269SIcenowy Zheng if (err) 1306aa19269SIcenowy Zheng return err; 1316aa19269SIcenowy Zheng 1326aa19269SIcenowy Zheng /* Get DPCD info */ 1336aa19269SIcenowy Zheng err = drm_dp_dpcd_read(&anx6345->aux, DP_DPCD_REV, 1346aa19269SIcenowy Zheng &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); 1356aa19269SIcenowy Zheng if (err < 0) { 1366aa19269SIcenowy Zheng DRM_ERROR("Failed to read DPCD: %d\n", err); 1376aa19269SIcenowy Zheng return err; 1386aa19269SIcenowy Zheng } 1396aa19269SIcenowy Zheng 1406aa19269SIcenowy Zheng /* Clear channel x SERDES power down */ 1416aa19269SIcenowy Zheng err = anx6345_clear_bits(anx6345->map[I2C_IDX_DPTX], 1426aa19269SIcenowy Zheng SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD); 1436aa19269SIcenowy Zheng if (err) 1446aa19269SIcenowy Zheng return err; 1456aa19269SIcenowy Zheng 146e1cff82cSTorsten Duwe /* 147e1cff82cSTorsten Duwe * Power up the sink (DP_SET_POWER register is only available on DPCD 148e1cff82cSTorsten Duwe * v1.1 and later). 149e1cff82cSTorsten Duwe */ 150e1cff82cSTorsten Duwe if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) { 151e1cff82cSTorsten Duwe err = drm_dp_dpcd_readb(&anx6345->aux, DP_SET_POWER, &dpcd[0]); 1526aa19269SIcenowy Zheng if (err < 0) { 153e1cff82cSTorsten Duwe DRM_ERROR("Failed to read DP_SET_POWER register: %d\n", 154e1cff82cSTorsten Duwe err); 1556aa19269SIcenowy Zheng return err; 1566aa19269SIcenowy Zheng } 1576aa19269SIcenowy Zheng 158e1cff82cSTorsten Duwe dpcd[0] &= ~DP_SET_POWER_MASK; 159e1cff82cSTorsten Duwe dpcd[0] |= DP_SET_POWER_D0; 160e1cff82cSTorsten Duwe 161e1cff82cSTorsten Duwe err = drm_dp_dpcd_writeb(&anx6345->aux, DP_SET_POWER, dpcd[0]); 1626aa19269SIcenowy Zheng if (err < 0) { 163e1cff82cSTorsten Duwe DRM_ERROR("Failed to power up DisplayPort link: %d\n", 164e1cff82cSTorsten Duwe err); 1656aa19269SIcenowy Zheng return err; 1666aa19269SIcenowy Zheng } 1676aa19269SIcenowy Zheng 168e1cff82cSTorsten Duwe /* 169e1cff82cSTorsten Duwe * According to the DP 1.1 specification, a "Sink Device must 170e1cff82cSTorsten Duwe * exit the power saving state within 1 ms" (Section 2.5.3.1, 171e1cff82cSTorsten Duwe * Table 5-52, "Sink Control Field" (register 0x600). 172e1cff82cSTorsten Duwe */ 173e1cff82cSTorsten Duwe usleep_range(1000, 2000); 174e1cff82cSTorsten Duwe } 175e1cff82cSTorsten Duwe 1766aa19269SIcenowy Zheng /* Possibly enable downspread on the sink */ 1776aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], 1786aa19269SIcenowy Zheng SP_DP_DOWNSPREAD_CTRL1_REG, 0); 1796aa19269SIcenowy Zheng if (err) 1806aa19269SIcenowy Zheng return err; 1816aa19269SIcenowy Zheng 1826aa19269SIcenowy Zheng if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { 1836aa19269SIcenowy Zheng DRM_DEBUG("Enable downspread on the sink\n"); 1846aa19269SIcenowy Zheng /* 4000PPM */ 1856aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], 1866aa19269SIcenowy Zheng SP_DP_DOWNSPREAD_CTRL1_REG, 8); 1876aa19269SIcenowy Zheng if (err) 1886aa19269SIcenowy Zheng return err; 1896aa19269SIcenowy Zheng 1906aa19269SIcenowy Zheng err = drm_dp_dpcd_writeb(&anx6345->aux, DP_DOWNSPREAD_CTRL, 1916aa19269SIcenowy Zheng DP_SPREAD_AMP_0_5); 1926aa19269SIcenowy Zheng if (err < 0) 1936aa19269SIcenowy Zheng return err; 1946aa19269SIcenowy Zheng } else { 1956aa19269SIcenowy Zheng err = drm_dp_dpcd_writeb(&anx6345->aux, DP_DOWNSPREAD_CTRL, 0); 1966aa19269SIcenowy Zheng if (err < 0) 1976aa19269SIcenowy Zheng return err; 1986aa19269SIcenowy Zheng } 1996aa19269SIcenowy Zheng 2006aa19269SIcenowy Zheng /* Set the lane count and the link rate on the sink */ 2016aa19269SIcenowy Zheng if (drm_dp_enhanced_frame_cap(anx6345->dpcd)) 2026aa19269SIcenowy Zheng err = anx6345_set_bits(anx6345->map[I2C_IDX_DPTX], 2036aa19269SIcenowy Zheng SP_DP_SYSTEM_CTRL_BASE + 4, 2046aa19269SIcenowy Zheng SP_ENHANCED_MODE); 2056aa19269SIcenowy Zheng else 2066aa19269SIcenowy Zheng err = anx6345_clear_bits(anx6345->map[I2C_IDX_DPTX], 2076aa19269SIcenowy Zheng SP_DP_SYSTEM_CTRL_BASE + 4, 2086aa19269SIcenowy Zheng SP_ENHANCED_MODE); 2096aa19269SIcenowy Zheng if (err) 2106aa19269SIcenowy Zheng return err; 2116aa19269SIcenowy Zheng 2122be30d34SIcenowy Zheng dpcd[0] = dp_bw; 2136aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], 214e1cff82cSTorsten Duwe SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]); 2156aa19269SIcenowy Zheng if (err) 2166aa19269SIcenowy Zheng return err; 2176aa19269SIcenowy Zheng 218e1cff82cSTorsten Duwe dpcd[1] = drm_dp_max_lane_count(anx6345->dpcd); 219e1cff82cSTorsten Duwe 2206aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], 221e1cff82cSTorsten Duwe SP_DP_LANE_COUNT_SET_REG, dpcd[1]); 2226aa19269SIcenowy Zheng if (err) 2236aa19269SIcenowy Zheng return err; 2246aa19269SIcenowy Zheng 225e1cff82cSTorsten Duwe if (drm_dp_enhanced_frame_cap(anx6345->dpcd)) 226e1cff82cSTorsten Duwe dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 227e1cff82cSTorsten Duwe 228e1cff82cSTorsten Duwe err = drm_dp_dpcd_write(&anx6345->aux, DP_LINK_BW_SET, dpcd, 229e1cff82cSTorsten Duwe sizeof(dpcd)); 230e1cff82cSTorsten Duwe 2316aa19269SIcenowy Zheng if (err < 0) { 232e1cff82cSTorsten Duwe DRM_ERROR("Failed to configure link: %d\n", err); 2336aa19269SIcenowy Zheng return err; 2346aa19269SIcenowy Zheng } 2356aa19269SIcenowy Zheng 2366aa19269SIcenowy Zheng /* Start training on the source */ 2376aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], SP_DP_LT_CTRL_REG, 2386aa19269SIcenowy Zheng SP_LT_EN); 2396aa19269SIcenowy Zheng if (err) 2406aa19269SIcenowy Zheng return err; 2416aa19269SIcenowy Zheng 2426aa19269SIcenowy Zheng return regmap_read_poll_timeout(anx6345->map[I2C_IDX_DPTX], 2436aa19269SIcenowy Zheng SP_DP_LT_CTRL_REG, 2446aa19269SIcenowy Zheng value, !(value & SP_DP_LT_INPROGRESS), 2456aa19269SIcenowy Zheng POLL_DELAY, POLL_TIMEOUT); 2466aa19269SIcenowy Zheng } 2476aa19269SIcenowy Zheng 2486aa19269SIcenowy Zheng static int anx6345_tx_initialization(struct anx6345 *anx6345) 2496aa19269SIcenowy Zheng { 2506aa19269SIcenowy Zheng int err, i; 2516aa19269SIcenowy Zheng 2526aa19269SIcenowy Zheng /* FIXME: colordepth is hardcoded for now */ 2536aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL2_REG, 2546aa19269SIcenowy Zheng SP_IN_BPC_6BIT << SP_IN_BPC_SHIFT); 2556aa19269SIcenowy Zheng if (err) 2566aa19269SIcenowy Zheng return err; 2576aa19269SIcenowy Zheng 2586aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], SP_DP_PLL_CTRL_REG, 0); 2596aa19269SIcenowy Zheng if (err) 2606aa19269SIcenowy Zheng return err; 2616aa19269SIcenowy Zheng 2626aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_TXCOM], 2636aa19269SIcenowy Zheng SP_ANALOG_DEBUG1_REG, 0); 2646aa19269SIcenowy Zheng if (err) 2656aa19269SIcenowy Zheng return err; 2666aa19269SIcenowy Zheng 2676aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], 2686aa19269SIcenowy Zheng SP_DP_LINK_DEBUG_CTRL_REG, 2696aa19269SIcenowy Zheng SP_NEW_PRBS7 | SP_M_VID_DEBUG); 2706aa19269SIcenowy Zheng if (err) 2716aa19269SIcenowy Zheng return err; 2726aa19269SIcenowy Zheng 2736aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], 2746aa19269SIcenowy Zheng SP_DP_ANALOG_POWER_DOWN_REG, 0); 2756aa19269SIcenowy Zheng if (err) 2766aa19269SIcenowy Zheng return err; 2776aa19269SIcenowy Zheng 2786aa19269SIcenowy Zheng /* Force HPD */ 2796aa19269SIcenowy Zheng err = anx6345_set_bits(anx6345->map[I2C_IDX_DPTX], 2806aa19269SIcenowy Zheng SP_DP_SYSTEM_CTRL_BASE + 3, 2816aa19269SIcenowy Zheng SP_HPD_FORCE | SP_HPD_CTRL); 2826aa19269SIcenowy Zheng if (err) 2836aa19269SIcenowy Zheng return err; 2846aa19269SIcenowy Zheng 2856aa19269SIcenowy Zheng for (i = 0; i < 4; i++) { 2866aa19269SIcenowy Zheng /* 4 lanes */ 2876aa19269SIcenowy Zheng err = regmap_write(anx6345->map[I2C_IDX_DPTX], 2886aa19269SIcenowy Zheng SP_DP_LANE0_LT_CTRL_REG + i, 0); 2896aa19269SIcenowy Zheng if (err) 2906aa19269SIcenowy Zheng return err; 2916aa19269SIcenowy Zheng } 2926aa19269SIcenowy Zheng 2936aa19269SIcenowy Zheng /* Reset AUX */ 2946aa19269SIcenowy Zheng err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], 2956aa19269SIcenowy Zheng SP_RESET_CTRL2_REG, SP_AUX_RST); 2966aa19269SIcenowy Zheng if (err) 2976aa19269SIcenowy Zheng return err; 2986aa19269SIcenowy Zheng 2996aa19269SIcenowy Zheng return anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], 3006aa19269SIcenowy Zheng SP_RESET_CTRL2_REG, SP_AUX_RST); 3016aa19269SIcenowy Zheng } 3026aa19269SIcenowy Zheng 3036aa19269SIcenowy Zheng static void anx6345_poweron(struct anx6345 *anx6345) 3046aa19269SIcenowy Zheng { 3056aa19269SIcenowy Zheng int err; 3066aa19269SIcenowy Zheng 3076aa19269SIcenowy Zheng /* Ensure reset is asserted before starting power on sequence */ 3086aa19269SIcenowy Zheng gpiod_set_value_cansleep(anx6345->gpiod_reset, 1); 3096aa19269SIcenowy Zheng usleep_range(1000, 2000); 3106aa19269SIcenowy Zheng 3116aa19269SIcenowy Zheng err = regulator_enable(anx6345->dvdd12); 3126aa19269SIcenowy Zheng if (err) { 3136aa19269SIcenowy Zheng DRM_ERROR("Failed to enable dvdd12 regulator: %d\n", 3146aa19269SIcenowy Zheng err); 3156aa19269SIcenowy Zheng return; 3166aa19269SIcenowy Zheng } 3176aa19269SIcenowy Zheng 3186aa19269SIcenowy Zheng /* T1 - delay between VDD12 and VDD25 should be 0-2ms */ 3196aa19269SIcenowy Zheng usleep_range(1000, 2000); 3206aa19269SIcenowy Zheng 3216aa19269SIcenowy Zheng err = regulator_enable(anx6345->dvdd25); 3226aa19269SIcenowy Zheng if (err) { 3236aa19269SIcenowy Zheng DRM_ERROR("Failed to enable dvdd25 regulator: %d\n", 3246aa19269SIcenowy Zheng err); 3256aa19269SIcenowy Zheng return; 3266aa19269SIcenowy Zheng } 3276aa19269SIcenowy Zheng 3286aa19269SIcenowy Zheng /* T2 - delay between RESETN and all power rail stable, 3296aa19269SIcenowy Zheng * should be 2-5ms 3306aa19269SIcenowy Zheng */ 3316aa19269SIcenowy Zheng usleep_range(2000, 5000); 3326aa19269SIcenowy Zheng 3336aa19269SIcenowy Zheng gpiod_set_value_cansleep(anx6345->gpiod_reset, 0); 3346aa19269SIcenowy Zheng 3356aa19269SIcenowy Zheng /* Power on registers module */ 3366aa19269SIcenowy Zheng anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG, 3376aa19269SIcenowy Zheng SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD); 3386aa19269SIcenowy Zheng anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG, 3396aa19269SIcenowy Zheng SP_REGISTER_PD | SP_TOTAL_PD); 3406aa19269SIcenowy Zheng 3416aa19269SIcenowy Zheng if (anx6345->panel) 3426aa19269SIcenowy Zheng drm_panel_prepare(anx6345->panel); 3436aa19269SIcenowy Zheng 3446aa19269SIcenowy Zheng anx6345->powered = true; 3456aa19269SIcenowy Zheng } 3466aa19269SIcenowy Zheng 3476aa19269SIcenowy Zheng static void anx6345_poweroff(struct anx6345 *anx6345) 3486aa19269SIcenowy Zheng { 3496aa19269SIcenowy Zheng int err; 3506aa19269SIcenowy Zheng 3516aa19269SIcenowy Zheng gpiod_set_value_cansleep(anx6345->gpiod_reset, 1); 3526aa19269SIcenowy Zheng usleep_range(1000, 2000); 3536aa19269SIcenowy Zheng 3546aa19269SIcenowy Zheng if (anx6345->panel) 3556aa19269SIcenowy Zheng drm_panel_unprepare(anx6345->panel); 3566aa19269SIcenowy Zheng 3576aa19269SIcenowy Zheng err = regulator_disable(anx6345->dvdd25); 3586aa19269SIcenowy Zheng if (err) { 3596aa19269SIcenowy Zheng DRM_ERROR("Failed to disable dvdd25 regulator: %d\n", 3606aa19269SIcenowy Zheng err); 3616aa19269SIcenowy Zheng return; 3626aa19269SIcenowy Zheng } 3636aa19269SIcenowy Zheng 3646aa19269SIcenowy Zheng usleep_range(5000, 10000); 3656aa19269SIcenowy Zheng 3666aa19269SIcenowy Zheng err = regulator_disable(anx6345->dvdd12); 3676aa19269SIcenowy Zheng if (err) { 3686aa19269SIcenowy Zheng DRM_ERROR("Failed to disable dvdd12 regulator: %d\n", 3696aa19269SIcenowy Zheng err); 3706aa19269SIcenowy Zheng return; 3716aa19269SIcenowy Zheng } 3726aa19269SIcenowy Zheng 3736aa19269SIcenowy Zheng usleep_range(1000, 2000); 3746aa19269SIcenowy Zheng 3756aa19269SIcenowy Zheng anx6345->powered = false; 3766aa19269SIcenowy Zheng } 3776aa19269SIcenowy Zheng 3786aa19269SIcenowy Zheng static int anx6345_start(struct anx6345 *anx6345) 3796aa19269SIcenowy Zheng { 3806aa19269SIcenowy Zheng int err; 3816aa19269SIcenowy Zheng 3826aa19269SIcenowy Zheng if (!anx6345->powered) 3836aa19269SIcenowy Zheng anx6345_poweron(anx6345); 3846aa19269SIcenowy Zheng 3856aa19269SIcenowy Zheng /* Power on needed modules */ 3866aa19269SIcenowy Zheng err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], 3876aa19269SIcenowy Zheng SP_POWERDOWN_CTRL_REG, 3886aa19269SIcenowy Zheng SP_VIDEO_PD | SP_LINK_PD); 3896aa19269SIcenowy Zheng 3906aa19269SIcenowy Zheng err = anx6345_tx_initialization(anx6345); 3916aa19269SIcenowy Zheng if (err) { 3926aa19269SIcenowy Zheng DRM_ERROR("Failed eDP transmitter initialization: %d\n", err); 3936aa19269SIcenowy Zheng anx6345_poweroff(anx6345); 3946aa19269SIcenowy Zheng return err; 3956aa19269SIcenowy Zheng } 3966aa19269SIcenowy Zheng 3976aa19269SIcenowy Zheng err = anx6345_dp_link_training(anx6345); 3986aa19269SIcenowy Zheng if (err) { 3996aa19269SIcenowy Zheng DRM_ERROR("Failed link training: %d\n", err); 4006aa19269SIcenowy Zheng anx6345_poweroff(anx6345); 4016aa19269SIcenowy Zheng return err; 4026aa19269SIcenowy Zheng } 4036aa19269SIcenowy Zheng 4046aa19269SIcenowy Zheng /* 4056aa19269SIcenowy Zheng * This delay seems to help keep the hardware in a good state. Without 4066aa19269SIcenowy Zheng * it, there are times where it fails silently. 4076aa19269SIcenowy Zheng */ 4086aa19269SIcenowy Zheng usleep_range(10000, 15000); 4096aa19269SIcenowy Zheng 4106aa19269SIcenowy Zheng return 0; 4116aa19269SIcenowy Zheng } 4126aa19269SIcenowy Zheng 4136aa19269SIcenowy Zheng static int anx6345_config_dp_output(struct anx6345 *anx6345) 4146aa19269SIcenowy Zheng { 4156aa19269SIcenowy Zheng int err; 4166aa19269SIcenowy Zheng 4176aa19269SIcenowy Zheng err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG, 4186aa19269SIcenowy Zheng SP_VIDEO_MUTE); 4196aa19269SIcenowy Zheng if (err) 4206aa19269SIcenowy Zheng return err; 4216aa19269SIcenowy Zheng 4226aa19269SIcenowy Zheng /* Enable DP output */ 4236aa19269SIcenowy Zheng err = anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_VID_CTRL1_REG, 4246aa19269SIcenowy Zheng SP_VIDEO_EN); 4256aa19269SIcenowy Zheng if (err) 4266aa19269SIcenowy Zheng return err; 4276aa19269SIcenowy Zheng 4286aa19269SIcenowy Zheng /* Force stream valid */ 4296aa19269SIcenowy Zheng return anx6345_set_bits(anx6345->map[I2C_IDX_DPTX], 4306aa19269SIcenowy Zheng SP_DP_SYSTEM_CTRL_BASE + 3, 4316aa19269SIcenowy Zheng SP_STRM_FORCE | SP_STRM_CTRL); 4326aa19269SIcenowy Zheng } 4336aa19269SIcenowy Zheng 4346aa19269SIcenowy Zheng static int anx6345_get_downstream_info(struct anx6345 *anx6345) 4356aa19269SIcenowy Zheng { 4366aa19269SIcenowy Zheng u8 value; 4376aa19269SIcenowy Zheng int err; 4386aa19269SIcenowy Zheng 4396aa19269SIcenowy Zheng err = drm_dp_dpcd_readb(&anx6345->aux, DP_SINK_COUNT, &value); 4406aa19269SIcenowy Zheng if (err < 0) { 4416aa19269SIcenowy Zheng DRM_ERROR("Get sink count failed %d\n", err); 4426aa19269SIcenowy Zheng return err; 4436aa19269SIcenowy Zheng } 4446aa19269SIcenowy Zheng 4456aa19269SIcenowy Zheng if (!DP_GET_SINK_COUNT(value)) { 4466aa19269SIcenowy Zheng DRM_ERROR("Downstream disconnected\n"); 4476aa19269SIcenowy Zheng return -EIO; 4486aa19269SIcenowy Zheng } 4496aa19269SIcenowy Zheng 4506aa19269SIcenowy Zheng return 0; 4516aa19269SIcenowy Zheng } 4526aa19269SIcenowy Zheng 4536aa19269SIcenowy Zheng static int anx6345_get_modes(struct drm_connector *connector) 4546aa19269SIcenowy Zheng { 4556aa19269SIcenowy Zheng struct anx6345 *anx6345 = connector_to_anx6345(connector); 4566aa19269SIcenowy Zheng int err, num_modes = 0; 4576aa19269SIcenowy Zheng bool power_off = false; 4586aa19269SIcenowy Zheng 4596aa19269SIcenowy Zheng mutex_lock(&anx6345->lock); 4606aa19269SIcenowy Zheng 4616aa19269SIcenowy Zheng if (!anx6345->edid) { 4626aa19269SIcenowy Zheng if (!anx6345->powered) { 4636aa19269SIcenowy Zheng anx6345_poweron(anx6345); 4646aa19269SIcenowy Zheng power_off = true; 4656aa19269SIcenowy Zheng } 4666aa19269SIcenowy Zheng 4676aa19269SIcenowy Zheng err = anx6345_get_downstream_info(anx6345); 4686aa19269SIcenowy Zheng if (err) { 4696aa19269SIcenowy Zheng DRM_ERROR("Failed to get downstream info: %d\n", err); 4706aa19269SIcenowy Zheng goto unlock; 4716aa19269SIcenowy Zheng } 4726aa19269SIcenowy Zheng 4736aa19269SIcenowy Zheng anx6345->edid = drm_get_edid(connector, &anx6345->aux.ddc); 4746aa19269SIcenowy Zheng if (!anx6345->edid) 4756aa19269SIcenowy Zheng DRM_ERROR("Failed to read EDID from panel\n"); 4766aa19269SIcenowy Zheng 4776aa19269SIcenowy Zheng err = drm_connector_update_edid_property(connector, 4786aa19269SIcenowy Zheng anx6345->edid); 4796aa19269SIcenowy Zheng if (err) { 4806aa19269SIcenowy Zheng DRM_ERROR("Failed to update EDID property: %d\n", err); 4816aa19269SIcenowy Zheng goto unlock; 4826aa19269SIcenowy Zheng } 4836aa19269SIcenowy Zheng } 4846aa19269SIcenowy Zheng 4856aa19269SIcenowy Zheng num_modes += drm_add_edid_modes(connector, anx6345->edid); 4866aa19269SIcenowy Zheng 4871e8a6ce9SVasily Khoruzhick /* Driver currently supports only 6bpc */ 4881e8a6ce9SVasily Khoruzhick connector->display_info.bpc = 6; 4891e8a6ce9SVasily Khoruzhick 4906aa19269SIcenowy Zheng unlock: 4916aa19269SIcenowy Zheng if (power_off) 4926aa19269SIcenowy Zheng anx6345_poweroff(anx6345); 4936aa19269SIcenowy Zheng 4946aa19269SIcenowy Zheng mutex_unlock(&anx6345->lock); 4956aa19269SIcenowy Zheng 4966aa19269SIcenowy Zheng if (!num_modes && anx6345->panel) 49706c4a9c2SSam Ravnborg num_modes += drm_panel_get_modes(anx6345->panel, connector); 4986aa19269SIcenowy Zheng 4996aa19269SIcenowy Zheng return num_modes; 5006aa19269SIcenowy Zheng } 5016aa19269SIcenowy Zheng 5026aa19269SIcenowy Zheng static const struct drm_connector_helper_funcs anx6345_connector_helper_funcs = { 5036aa19269SIcenowy Zheng .get_modes = anx6345_get_modes, 5046aa19269SIcenowy Zheng }; 5056aa19269SIcenowy Zheng 5066aa19269SIcenowy Zheng static void 5076aa19269SIcenowy Zheng anx6345_connector_destroy(struct drm_connector *connector) 5086aa19269SIcenowy Zheng { 5096aa19269SIcenowy Zheng drm_connector_cleanup(connector); 5106aa19269SIcenowy Zheng } 5116aa19269SIcenowy Zheng 5126aa19269SIcenowy Zheng static const struct drm_connector_funcs anx6345_connector_funcs = { 5136aa19269SIcenowy Zheng .fill_modes = drm_helper_probe_single_connector_modes, 5146aa19269SIcenowy Zheng .destroy = anx6345_connector_destroy, 5156aa19269SIcenowy Zheng .reset = drm_atomic_helper_connector_reset, 5166aa19269SIcenowy Zheng .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 5176aa19269SIcenowy Zheng .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 5186aa19269SIcenowy Zheng }; 5196aa19269SIcenowy Zheng 520a25b988fSLaurent Pinchart static int anx6345_bridge_attach(struct drm_bridge *bridge, 521a25b988fSLaurent Pinchart enum drm_bridge_attach_flags flags) 5226aa19269SIcenowy Zheng { 5236aa19269SIcenowy Zheng struct anx6345 *anx6345 = bridge_to_anx6345(bridge); 5246aa19269SIcenowy Zheng int err; 5256aa19269SIcenowy Zheng 526a25b988fSLaurent Pinchart if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 527a25b988fSLaurent Pinchart DRM_ERROR("Fix bridge driver to make connector optional!"); 528a25b988fSLaurent Pinchart return -EINVAL; 529a25b988fSLaurent Pinchart } 530a25b988fSLaurent Pinchart 5316aa19269SIcenowy Zheng if (!bridge->encoder) { 5326aa19269SIcenowy Zheng DRM_ERROR("Parent encoder object not found"); 5336aa19269SIcenowy Zheng return -ENODEV; 5346aa19269SIcenowy Zheng } 5356aa19269SIcenowy Zheng 5366aa19269SIcenowy Zheng /* Register aux channel */ 5376aa19269SIcenowy Zheng anx6345->aux.name = "DP-AUX"; 5386aa19269SIcenowy Zheng anx6345->aux.dev = &anx6345->client->dev; 5396cba3fe4SLyude Paul anx6345->aux.drm_dev = bridge->dev; 5406aa19269SIcenowy Zheng anx6345->aux.transfer = anx6345_aux_transfer; 5416aa19269SIcenowy Zheng 5426aa19269SIcenowy Zheng err = drm_dp_aux_register(&anx6345->aux); 5436aa19269SIcenowy Zheng if (err < 0) { 5446aa19269SIcenowy Zheng DRM_ERROR("Failed to register aux channel: %d\n", err); 5456aa19269SIcenowy Zheng return err; 5466aa19269SIcenowy Zheng } 5476aa19269SIcenowy Zheng 5486aa19269SIcenowy Zheng err = drm_connector_init(bridge->dev, &anx6345->connector, 5496aa19269SIcenowy Zheng &anx6345_connector_funcs, 5506aa19269SIcenowy Zheng DRM_MODE_CONNECTOR_eDP); 5516aa19269SIcenowy Zheng if (err) { 5526aa19269SIcenowy Zheng DRM_ERROR("Failed to initialize connector: %d\n", err); 553c42712c6SLyude Paul goto aux_unregister; 5546aa19269SIcenowy Zheng } 5556aa19269SIcenowy Zheng 5566aa19269SIcenowy Zheng drm_connector_helper_add(&anx6345->connector, 5576aa19269SIcenowy Zheng &anx6345_connector_helper_funcs); 5586aa19269SIcenowy Zheng 5596aa19269SIcenowy Zheng anx6345->connector.polled = DRM_CONNECTOR_POLL_HPD; 5606aa19269SIcenowy Zheng 5616aa19269SIcenowy Zheng err = drm_connector_attach_encoder(&anx6345->connector, 5626aa19269SIcenowy Zheng bridge->encoder); 5636aa19269SIcenowy Zheng if (err) { 5646aa19269SIcenowy Zheng DRM_ERROR("Failed to link up connector to encoder: %d\n", err); 565c42712c6SLyude Paul goto connector_cleanup; 5666aa19269SIcenowy Zheng } 5676aa19269SIcenowy Zheng 568acf5ff29SLyude Paul err = drm_connector_register(&anx6345->connector); 569acf5ff29SLyude Paul if (err) { 570acf5ff29SLyude Paul DRM_ERROR("Failed to register connector: %d\n", err); 571c42712c6SLyude Paul goto connector_cleanup; 572acf5ff29SLyude Paul } 573acf5ff29SLyude Paul 5746aa19269SIcenowy Zheng return 0; 575c42712c6SLyude Paul connector_cleanup: 576c42712c6SLyude Paul drm_connector_cleanup(&anx6345->connector); 577c42712c6SLyude Paul aux_unregister: 578c42712c6SLyude Paul drm_dp_aux_unregister(&anx6345->aux); 579c42712c6SLyude Paul return err; 5806aa19269SIcenowy Zheng } 5816aa19269SIcenowy Zheng 582ba5070ecSLyude Paul static void anx6345_bridge_detach(struct drm_bridge *bridge) 583ba5070ecSLyude Paul { 584ba5070ecSLyude Paul drm_dp_aux_unregister(&bridge_to_anx6345(bridge)->aux); 585ba5070ecSLyude Paul } 586ba5070ecSLyude Paul 5876aa19269SIcenowy Zheng static enum drm_mode_status 5886aa19269SIcenowy Zheng anx6345_bridge_mode_valid(struct drm_bridge *bridge, 58912c683e1SLaurent Pinchart const struct drm_display_info *info, 5906aa19269SIcenowy Zheng const struct drm_display_mode *mode) 5916aa19269SIcenowy Zheng { 5926aa19269SIcenowy Zheng if (mode->flags & DRM_MODE_FLAG_INTERLACE) 5936aa19269SIcenowy Zheng return MODE_NO_INTERLACE; 5946aa19269SIcenowy Zheng 5956aa19269SIcenowy Zheng /* Max 1200p at 5.4 Ghz, one lane */ 5966aa19269SIcenowy Zheng if (mode->clock > 154000) 5976aa19269SIcenowy Zheng return MODE_CLOCK_HIGH; 5986aa19269SIcenowy Zheng 5996aa19269SIcenowy Zheng return MODE_OK; 6006aa19269SIcenowy Zheng } 6016aa19269SIcenowy Zheng 6026aa19269SIcenowy Zheng static void anx6345_bridge_disable(struct drm_bridge *bridge) 6036aa19269SIcenowy Zheng { 6046aa19269SIcenowy Zheng struct anx6345 *anx6345 = bridge_to_anx6345(bridge); 6056aa19269SIcenowy Zheng 6066aa19269SIcenowy Zheng /* Power off all modules except configuration registers access */ 6076aa19269SIcenowy Zheng anx6345_set_bits(anx6345->map[I2C_IDX_TXCOM], SP_POWERDOWN_CTRL_REG, 6086aa19269SIcenowy Zheng SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD); 6096aa19269SIcenowy Zheng if (anx6345->panel) 6106aa19269SIcenowy Zheng drm_panel_disable(anx6345->panel); 6116aa19269SIcenowy Zheng 6126aa19269SIcenowy Zheng if (anx6345->powered) 6136aa19269SIcenowy Zheng anx6345_poweroff(anx6345); 6146aa19269SIcenowy Zheng } 6156aa19269SIcenowy Zheng 6166aa19269SIcenowy Zheng static void anx6345_bridge_enable(struct drm_bridge *bridge) 6176aa19269SIcenowy Zheng { 6186aa19269SIcenowy Zheng struct anx6345 *anx6345 = bridge_to_anx6345(bridge); 6196aa19269SIcenowy Zheng int err; 6206aa19269SIcenowy Zheng 6216aa19269SIcenowy Zheng if (anx6345->panel) 6226aa19269SIcenowy Zheng drm_panel_enable(anx6345->panel); 6236aa19269SIcenowy Zheng 6246aa19269SIcenowy Zheng err = anx6345_start(anx6345); 6256aa19269SIcenowy Zheng if (err) { 6266aa19269SIcenowy Zheng DRM_ERROR("Failed to initialize: %d\n", err); 6276aa19269SIcenowy Zheng return; 6286aa19269SIcenowy Zheng } 6296aa19269SIcenowy Zheng 6306aa19269SIcenowy Zheng err = anx6345_config_dp_output(anx6345); 6316aa19269SIcenowy Zheng if (err) 6326aa19269SIcenowy Zheng DRM_ERROR("Failed to enable DP output: %d\n", err); 6336aa19269SIcenowy Zheng } 6346aa19269SIcenowy Zheng 6356aa19269SIcenowy Zheng static const struct drm_bridge_funcs anx6345_bridge_funcs = { 6366aa19269SIcenowy Zheng .attach = anx6345_bridge_attach, 637ba5070ecSLyude Paul .detach = anx6345_bridge_detach, 6386aa19269SIcenowy Zheng .mode_valid = anx6345_bridge_mode_valid, 6396aa19269SIcenowy Zheng .disable = anx6345_bridge_disable, 6406aa19269SIcenowy Zheng .enable = anx6345_bridge_enable, 6416aa19269SIcenowy Zheng }; 6426aa19269SIcenowy Zheng 6436aa19269SIcenowy Zheng static void unregister_i2c_dummy_clients(struct anx6345 *anx6345) 6446aa19269SIcenowy Zheng { 6456aa19269SIcenowy Zheng unsigned int i; 6466aa19269SIcenowy Zheng 6476aa19269SIcenowy Zheng for (i = 1; i < ARRAY_SIZE(anx6345->i2c_clients); i++) 6486aa19269SIcenowy Zheng if (anx6345->i2c_clients[i] && 6496aa19269SIcenowy Zheng anx6345->i2c_clients[i]->addr != anx6345->client->addr) 6506aa19269SIcenowy Zheng i2c_unregister_device(anx6345->i2c_clients[i]); 6516aa19269SIcenowy Zheng } 6526aa19269SIcenowy Zheng 6536aa19269SIcenowy Zheng static const struct regmap_config anx6345_regmap_config = { 6546aa19269SIcenowy Zheng .reg_bits = 8, 6556aa19269SIcenowy Zheng .val_bits = 8, 6566aa19269SIcenowy Zheng .max_register = 0xff, 6576aa19269SIcenowy Zheng .cache_type = REGCACHE_NONE, 6586aa19269SIcenowy Zheng }; 6596aa19269SIcenowy Zheng 6606aa19269SIcenowy Zheng static const u16 anx6345_chipid_list[] = { 6616aa19269SIcenowy Zheng 0x6345, 6626aa19269SIcenowy Zheng }; 6636aa19269SIcenowy Zheng 6646aa19269SIcenowy Zheng static bool anx6345_get_chip_id(struct anx6345 *anx6345) 6656aa19269SIcenowy Zheng { 6666aa19269SIcenowy Zheng unsigned int i, idl, idh, version; 6676aa19269SIcenowy Zheng 6686aa19269SIcenowy Zheng if (regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_IDL_REG, &idl)) 6696aa19269SIcenowy Zheng return false; 6706aa19269SIcenowy Zheng 6716aa19269SIcenowy Zheng if (regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_IDH_REG, &idh)) 6726aa19269SIcenowy Zheng return false; 6736aa19269SIcenowy Zheng 6746aa19269SIcenowy Zheng anx6345->chipid = (u8)idl | ((u8)idh << 8); 6756aa19269SIcenowy Zheng 6766aa19269SIcenowy Zheng if (regmap_read(anx6345->map[I2C_IDX_TXCOM], SP_DEVICE_VERSION_REG, 6776aa19269SIcenowy Zheng &version)) 6786aa19269SIcenowy Zheng return false; 6796aa19269SIcenowy Zheng 6806aa19269SIcenowy Zheng for (i = 0; i < ARRAY_SIZE(anx6345_chipid_list); i++) { 6816aa19269SIcenowy Zheng if (anx6345->chipid == anx6345_chipid_list[i]) { 6826aa19269SIcenowy Zheng DRM_INFO("Found ANX%x (ver. %d) eDP Transmitter\n", 6836aa19269SIcenowy Zheng anx6345->chipid, version); 6846aa19269SIcenowy Zheng return true; 6856aa19269SIcenowy Zheng } 6866aa19269SIcenowy Zheng } 6876aa19269SIcenowy Zheng 6886aa19269SIcenowy Zheng DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n", 6896aa19269SIcenowy Zheng anx6345->chipid, version); 6906aa19269SIcenowy Zheng 6916aa19269SIcenowy Zheng return false; 6926aa19269SIcenowy Zheng } 6936aa19269SIcenowy Zheng 694a36f4334SUwe Kleine-König static int anx6345_i2c_probe(struct i2c_client *client) 6956aa19269SIcenowy Zheng { 6966aa19269SIcenowy Zheng struct anx6345 *anx6345; 6976aa19269SIcenowy Zheng struct device *dev; 6986aa19269SIcenowy Zheng int i, err; 6996aa19269SIcenowy Zheng 7006aa19269SIcenowy Zheng anx6345 = devm_kzalloc(&client->dev, sizeof(*anx6345), GFP_KERNEL); 7016aa19269SIcenowy Zheng if (!anx6345) 7026aa19269SIcenowy Zheng return -ENOMEM; 7036aa19269SIcenowy Zheng 7046aa19269SIcenowy Zheng mutex_init(&anx6345->lock); 7056aa19269SIcenowy Zheng 7066aa19269SIcenowy Zheng anx6345->bridge.of_node = client->dev.of_node; 7076aa19269SIcenowy Zheng 7086aa19269SIcenowy Zheng anx6345->client = client; 7096aa19269SIcenowy Zheng i2c_set_clientdata(client, anx6345); 7106aa19269SIcenowy Zheng 7116aa19269SIcenowy Zheng dev = &anx6345->client->dev; 7126aa19269SIcenowy Zheng 7136aa19269SIcenowy Zheng err = drm_of_find_panel_or_bridge(client->dev.of_node, 1, 0, 7146aa19269SIcenowy Zheng &anx6345->panel, NULL); 7156aa19269SIcenowy Zheng if (err == -EPROBE_DEFER) 7166aa19269SIcenowy Zheng return err; 7176aa19269SIcenowy Zheng 7186aa19269SIcenowy Zheng if (err) 7196aa19269SIcenowy Zheng DRM_DEBUG("No panel found\n"); 7206aa19269SIcenowy Zheng 7216aa19269SIcenowy Zheng /* 1.2V digital core power regulator */ 7226726ca1aSTorsten Duwe anx6345->dvdd12 = devm_regulator_get(dev, "dvdd12"); 7236aa19269SIcenowy Zheng if (IS_ERR(anx6345->dvdd12)) { 7246f13d2ceSVasily Khoruzhick if (PTR_ERR(anx6345->dvdd12) != -EPROBE_DEFER) 7256f13d2ceSVasily Khoruzhick DRM_ERROR("Failed to get dvdd12 supply (%ld)\n", 7266f13d2ceSVasily Khoruzhick PTR_ERR(anx6345->dvdd12)); 7276aa19269SIcenowy Zheng return PTR_ERR(anx6345->dvdd12); 7286aa19269SIcenowy Zheng } 7296aa19269SIcenowy Zheng 7306aa19269SIcenowy Zheng /* 2.5V digital core power regulator */ 7316726ca1aSTorsten Duwe anx6345->dvdd25 = devm_regulator_get(dev, "dvdd25"); 7326aa19269SIcenowy Zheng if (IS_ERR(anx6345->dvdd25)) { 7336f13d2ceSVasily Khoruzhick if (PTR_ERR(anx6345->dvdd25) != -EPROBE_DEFER) 7346f13d2ceSVasily Khoruzhick DRM_ERROR("Failed to get dvdd25 supply (%ld)\n", 7356f13d2ceSVasily Khoruzhick PTR_ERR(anx6345->dvdd25)); 7366aa19269SIcenowy Zheng return PTR_ERR(anx6345->dvdd25); 7376aa19269SIcenowy Zheng } 7386aa19269SIcenowy Zheng 7396aa19269SIcenowy Zheng /* GPIO for chip reset */ 7406aa19269SIcenowy Zheng anx6345->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 7416aa19269SIcenowy Zheng if (IS_ERR(anx6345->gpiod_reset)) { 7426aa19269SIcenowy Zheng DRM_ERROR("Reset gpio not found\n"); 7436aa19269SIcenowy Zheng return PTR_ERR(anx6345->gpiod_reset); 7446aa19269SIcenowy Zheng } 7456aa19269SIcenowy Zheng 7466aa19269SIcenowy Zheng /* Map slave addresses of ANX6345 */ 7476aa19269SIcenowy Zheng for (i = 0; i < I2C_NUM_ADDRESSES; i++) { 7486aa19269SIcenowy Zheng if (anx6345_i2c_addresses[i] >> 1 != client->addr) 749ed08ddd9SStephen Rothwell anx6345->i2c_clients[i] = i2c_new_dummy_device(client->adapter, 7506aa19269SIcenowy Zheng anx6345_i2c_addresses[i] >> 1); 7516aa19269SIcenowy Zheng else 7526aa19269SIcenowy Zheng anx6345->i2c_clients[i] = client; 7536aa19269SIcenowy Zheng 754ed08ddd9SStephen Rothwell if (IS_ERR(anx6345->i2c_clients[i])) { 755ed08ddd9SStephen Rothwell err = PTR_ERR(anx6345->i2c_clients[i]); 7566aa19269SIcenowy Zheng DRM_ERROR("Failed to reserve I2C bus %02x\n", 7576aa19269SIcenowy Zheng anx6345_i2c_addresses[i]); 7586aa19269SIcenowy Zheng goto err_unregister_i2c; 7596aa19269SIcenowy Zheng } 7606aa19269SIcenowy Zheng 7616aa19269SIcenowy Zheng anx6345->map[i] = devm_regmap_init_i2c(anx6345->i2c_clients[i], 7626aa19269SIcenowy Zheng &anx6345_regmap_config); 7636aa19269SIcenowy Zheng if (IS_ERR(anx6345->map[i])) { 7646aa19269SIcenowy Zheng err = PTR_ERR(anx6345->map[i]); 7656aa19269SIcenowy Zheng DRM_ERROR("Failed regmap initialization %02x\n", 7666aa19269SIcenowy Zheng anx6345_i2c_addresses[i]); 7676aa19269SIcenowy Zheng goto err_unregister_i2c; 7686aa19269SIcenowy Zheng } 7696aa19269SIcenowy Zheng } 7706aa19269SIcenowy Zheng 7716aa19269SIcenowy Zheng /* Look for supported chip ID */ 7726aa19269SIcenowy Zheng anx6345_poweron(anx6345); 7736aa19269SIcenowy Zheng if (anx6345_get_chip_id(anx6345)) { 7746aa19269SIcenowy Zheng anx6345->bridge.funcs = &anx6345_bridge_funcs; 7756aa19269SIcenowy Zheng drm_bridge_add(&anx6345->bridge); 7766aa19269SIcenowy Zheng 7776aa19269SIcenowy Zheng return 0; 7786aa19269SIcenowy Zheng } else { 7796aa19269SIcenowy Zheng anx6345_poweroff(anx6345); 7806aa19269SIcenowy Zheng err = -ENODEV; 7816aa19269SIcenowy Zheng } 7826aa19269SIcenowy Zheng 7836aa19269SIcenowy Zheng err_unregister_i2c: 7846aa19269SIcenowy Zheng unregister_i2c_dummy_clients(anx6345); 7856aa19269SIcenowy Zheng return err; 7866aa19269SIcenowy Zheng } 7876aa19269SIcenowy Zheng 788ed5c2f5fSUwe Kleine-König static void anx6345_i2c_remove(struct i2c_client *client) 7896aa19269SIcenowy Zheng { 7906aa19269SIcenowy Zheng struct anx6345 *anx6345 = i2c_get_clientdata(client); 7916aa19269SIcenowy Zheng 7926aa19269SIcenowy Zheng drm_bridge_remove(&anx6345->bridge); 7936aa19269SIcenowy Zheng 7946aa19269SIcenowy Zheng unregister_i2c_dummy_clients(anx6345); 7956aa19269SIcenowy Zheng 7966aa19269SIcenowy Zheng kfree(anx6345->edid); 7976aa19269SIcenowy Zheng 7986aa19269SIcenowy Zheng mutex_destroy(&anx6345->lock); 7996aa19269SIcenowy Zheng } 8006aa19269SIcenowy Zheng 8016aa19269SIcenowy Zheng static const struct i2c_device_id anx6345_id[] = { 8026aa19269SIcenowy Zheng { "anx6345", 0 }, 8036aa19269SIcenowy Zheng { /* sentinel */ } 8046aa19269SIcenowy Zheng }; 8056aa19269SIcenowy Zheng MODULE_DEVICE_TABLE(i2c, anx6345_id); 8066aa19269SIcenowy Zheng 8076aa19269SIcenowy Zheng static const struct of_device_id anx6345_match_table[] = { 8086aa19269SIcenowy Zheng { .compatible = "analogix,anx6345", }, 8096aa19269SIcenowy Zheng { /* sentinel */ }, 8106aa19269SIcenowy Zheng }; 8116aa19269SIcenowy Zheng MODULE_DEVICE_TABLE(of, anx6345_match_table); 8126aa19269SIcenowy Zheng 8136aa19269SIcenowy Zheng static struct i2c_driver anx6345_driver = { 8146aa19269SIcenowy Zheng .driver = { 8156aa19269SIcenowy Zheng .name = "anx6345", 8166aa19269SIcenowy Zheng .of_match_table = of_match_ptr(anx6345_match_table), 8176aa19269SIcenowy Zheng }, 818*332af828SUwe Kleine-König .probe = anx6345_i2c_probe, 8196aa19269SIcenowy Zheng .remove = anx6345_i2c_remove, 8206aa19269SIcenowy Zheng .id_table = anx6345_id, 8216aa19269SIcenowy Zheng }; 8226aa19269SIcenowy Zheng module_i2c_driver(anx6345_driver); 8236aa19269SIcenowy Zheng 8246aa19269SIcenowy Zheng MODULE_DESCRIPTION("ANX6345 eDP Transmitter driver"); 8256aa19269SIcenowy Zheng MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>"); 8266aa19269SIcenowy Zheng MODULE_LICENSE("GPL v2"); 827