1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/of_graph.h> 7 8 #include "adv7511.h" 9 10 static const struct reg_sequence adv7533_fixed_registers[] = { 11 { 0x16, 0x20 }, 12 { 0x9a, 0xe0 }, 13 { 0xba, 0x70 }, 14 { 0xde, 0x82 }, 15 { 0xe4, 0x40 }, 16 { 0xe5, 0x80 }, 17 }; 18 19 static const struct reg_sequence adv7533_cec_fixed_registers[] = { 20 { 0x15, 0xd0 }, 21 { 0x17, 0xd0 }, 22 { 0x24, 0x20 }, 23 { 0x57, 0x11 }, 24 { 0x05, 0xc8 }, 25 }; 26 27 static void adv7511_dsi_config_timing_gen(struct adv7511 *adv) 28 { 29 struct mipi_dsi_device *dsi = adv->dsi; 30 struct drm_display_mode *mode = &adv->curr_mode; 31 unsigned int hsw, hfp, hbp, vsw, vfp, vbp; 32 static const u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ 33 34 hsw = mode->hsync_end - mode->hsync_start; 35 hfp = mode->hsync_start - mode->hdisplay; 36 hbp = mode->htotal - mode->hsync_end; 37 vsw = mode->vsync_end - mode->vsync_start; 38 vfp = mode->vsync_start - mode->vdisplay; 39 vbp = mode->vtotal - mode->vsync_end; 40 41 /* set pixel clock divider mode */ 42 regmap_write(adv->regmap_cec, 0x16, 43 clock_div_by_lanes[dsi->lanes - 2] << 3); 44 45 /* horizontal porch params */ 46 regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4); 47 regmap_write(adv->regmap_cec, 0x29, (mode->htotal << 4) & 0xff); 48 regmap_write(adv->regmap_cec, 0x2a, hsw >> 4); 49 regmap_write(adv->regmap_cec, 0x2b, (hsw << 4) & 0xff); 50 regmap_write(adv->regmap_cec, 0x2c, hfp >> 4); 51 regmap_write(adv->regmap_cec, 0x2d, (hfp << 4) & 0xff); 52 regmap_write(adv->regmap_cec, 0x2e, hbp >> 4); 53 regmap_write(adv->regmap_cec, 0x2f, (hbp << 4) & 0xff); 54 55 /* vertical porch params */ 56 regmap_write(adv->regmap_cec, 0x30, mode->vtotal >> 4); 57 regmap_write(adv->regmap_cec, 0x31, (mode->vtotal << 4) & 0xff); 58 regmap_write(adv->regmap_cec, 0x32, vsw >> 4); 59 regmap_write(adv->regmap_cec, 0x33, (vsw << 4) & 0xff); 60 regmap_write(adv->regmap_cec, 0x34, vfp >> 4); 61 regmap_write(adv->regmap_cec, 0x35, (vfp << 4) & 0xff); 62 regmap_write(adv->regmap_cec, 0x36, vbp >> 4); 63 regmap_write(adv->regmap_cec, 0x37, (vbp << 4) & 0xff); 64 } 65 66 void adv7533_dsi_power_on(struct adv7511 *adv) 67 { 68 struct mipi_dsi_device *dsi = adv->dsi; 69 70 if (adv->use_timing_gen) 71 adv7511_dsi_config_timing_gen(adv); 72 73 /* set number of dsi lanes */ 74 regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4); 75 76 if (adv->use_timing_gen) { 77 /* reset internal timing generator */ 78 regmap_write(adv->regmap_cec, 0x27, 0xcb); 79 regmap_write(adv->regmap_cec, 0x27, 0x8b); 80 regmap_write(adv->regmap_cec, 0x27, 0xcb); 81 } else { 82 /* disable internal timing generator */ 83 regmap_write(adv->regmap_cec, 0x27, 0x0b); 84 } 85 86 /* enable hdmi */ 87 regmap_write(adv->regmap_cec, 0x03, 0x89); 88 /* disable test mode */ 89 regmap_write(adv->regmap_cec, 0x55, 0x00); 90 91 regmap_register_patch(adv->regmap_cec, adv7533_cec_fixed_registers, 92 ARRAY_SIZE(adv7533_cec_fixed_registers)); 93 } 94 95 void adv7533_dsi_power_off(struct adv7511 *adv) 96 { 97 /* disable hdmi */ 98 regmap_write(adv->regmap_cec, 0x03, 0x0b); 99 /* disable internal timing generator */ 100 regmap_write(adv->regmap_cec, 0x27, 0x0b); 101 } 102 103 enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv, 104 const struct drm_display_mode *mode) 105 { 106 unsigned long max_lane_freq; 107 struct mipi_dsi_device *dsi = adv->dsi; 108 u8 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 109 110 /* Check max clock for either 7533 or 7535 */ 111 if (mode->clock > (adv->type == ADV7533 ? 80000 : 148500)) 112 return MODE_CLOCK_HIGH; 113 114 /* Check max clock for each lane */ 115 max_lane_freq = (adv->type == ADV7533 ? 800000 : 891000); 116 117 if (mode->clock * bpp > max_lane_freq * adv->num_dsi_lanes) 118 return MODE_CLOCK_HIGH; 119 120 return MODE_OK; 121 } 122 123 int adv7533_patch_registers(struct adv7511 *adv) 124 { 125 return regmap_register_patch(adv->regmap, 126 adv7533_fixed_registers, 127 ARRAY_SIZE(adv7533_fixed_registers)); 128 } 129 130 int adv7533_patch_cec_registers(struct adv7511 *adv) 131 { 132 return regmap_register_patch(adv->regmap_cec, 133 adv7533_cec_fixed_registers, 134 ARRAY_SIZE(adv7533_cec_fixed_registers)); 135 } 136 137 int adv7533_attach_dsi(struct adv7511 *adv) 138 { 139 struct device *dev = &adv->i2c_main->dev; 140 struct mipi_dsi_host *host; 141 struct mipi_dsi_device *dsi; 142 int ret = 0; 143 const struct mipi_dsi_device_info info = { .type = "adv7533", 144 .channel = 0, 145 .node = NULL, 146 }; 147 148 host = of_find_mipi_dsi_host_by_node(adv->host_node); 149 if (!host) 150 return dev_err_probe(dev, -EPROBE_DEFER, 151 "failed to find dsi host\n"); 152 153 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 154 if (IS_ERR(dsi)) 155 return dev_err_probe(dev, PTR_ERR(dsi), 156 "failed to create dsi device\n"); 157 158 adv->dsi = dsi; 159 160 dsi->lanes = adv->num_dsi_lanes; 161 dsi->format = MIPI_DSI_FMT_RGB888; 162 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 163 MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE; 164 165 ret = devm_mipi_dsi_attach(dev, dsi); 166 if (ret < 0) 167 return dev_err_probe(dev, ret, "failed to attach dsi to host\n"); 168 169 return 0; 170 } 171 172 int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv) 173 { 174 u32 num_lanes; 175 176 of_property_read_u32(np, "adi,dsi-lanes", &num_lanes); 177 178 if (num_lanes < 1 || num_lanes > 4) 179 return -EINVAL; 180 181 adv->num_dsi_lanes = num_lanes; 182 183 adv->host_node = of_graph_get_remote_node(np, 0, 0); 184 if (!adv->host_node) 185 return -ENODEV; 186 187 of_node_put(adv->host_node); 188 189 adv->use_timing_gen = !of_property_read_bool(np, 190 "adi,disable-timing-generator"); 191 192 /* TODO: Check if these need to be parsed by DT or not */ 193 adv->rgb = true; 194 adv->embedded_sync = false; 195 196 return 0; 197 } 198