1 /*
2  * Copyright (C) 2014 Traphandler
3  * Copyright (C) 2014 Free Electrons
4  * Copyright (C) 2014 Atmel
5  *
6  * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms of the GNU General Public License version 2 as published by
11  * the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program.  If not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #ifndef DRM_ATMEL_HLCDC_H
23 #define DRM_ATMEL_HLCDC_H
24 
25 #include <linux/clk.h>
26 #include <linux/irqdomain.h>
27 #include <linux/pwm.h>
28 
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_atomic_helper.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_cma_helper.h>
34 #include <drm/drm_gem_cma_helper.h>
35 #include <drm/drm_panel.h>
36 #include <drm/drm_plane_helper.h>
37 #include <drm/drmP.h>
38 
39 #include "atmel_hlcdc_layer.h"
40 
41 #define ATMEL_HLCDC_MAX_LAYERS		5
42 
43 /**
44  * Atmel HLCDC Display Controller description structure.
45  *
46  * This structure describe the HLCDC IP capabilities and depends on the
47  * HLCDC IP version (or Atmel SoC family).
48  *
49  * @min_width: minimum width supported by the Display Controller
50  * @min_height: minimum height supported by the Display Controller
51  * @max_width: maximum width supported by the Display Controller
52  * @max_height: maximum height supported by the Display Controller
53  * @max_spw: maximum vertical/horizontal pulse width
54  * @max_vpw: maximum vertical back/front porch width
55  * @max_hpw: maximum horizontal back/front porch width
56  * @conflicting_output_formats: true if RGBXXX output formats conflict with
57  *				each other.
58  * @layers: a layer description table describing available layers
59  * @nlayers: layer description table size
60  */
61 struct atmel_hlcdc_dc_desc {
62 	int min_width;
63 	int min_height;
64 	int max_width;
65 	int max_height;
66 	int max_spw;
67 	int max_vpw;
68 	int max_hpw;
69 	bool conflicting_output_formats;
70 	const struct atmel_hlcdc_layer_desc *layers;
71 	int nlayers;
72 };
73 
74 /**
75  * Atmel HLCDC Plane properties.
76  *
77  * This structure stores plane property definitions.
78  *
79  * @alpha: alpha blending (or transparency) property
80  * @rotation: rotation property
81  */
82 struct atmel_hlcdc_plane_properties {
83 	struct drm_property *alpha;
84 };
85 
86 /**
87  * Atmel HLCDC Plane.
88  *
89  * @base: base DRM plane structure
90  * @layer: HLCDC layer structure
91  * @properties: pointer to the property definitions structure
92  * @rotation: current rotation status
93  */
94 struct atmel_hlcdc_plane {
95 	struct drm_plane base;
96 	struct atmel_hlcdc_layer layer;
97 	struct atmel_hlcdc_plane_properties *properties;
98 };
99 
100 static inline struct atmel_hlcdc_plane *
101 drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p)
102 {
103 	return container_of(p, struct atmel_hlcdc_plane, base);
104 }
105 
106 static inline struct atmel_hlcdc_plane *
107 atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *l)
108 {
109 	return container_of(l, struct atmel_hlcdc_plane, layer);
110 }
111 
112 /**
113  * Atmel HLCDC Planes.
114  *
115  * This structure stores the instantiated HLCDC Planes and can be accessed by
116  * the HLCDC Display Controller or the HLCDC CRTC.
117  *
118  * @primary: primary plane
119  * @cursor: hardware cursor plane
120  * @overlays: overlay plane table
121  * @noverlays: number of overlay planes
122  */
123 struct atmel_hlcdc_planes {
124 	struct atmel_hlcdc_plane *primary;
125 	struct atmel_hlcdc_plane *cursor;
126 	struct atmel_hlcdc_plane **overlays;
127 	int noverlays;
128 };
129 
130 /**
131  * Atmel HLCDC Display Controller.
132  *
133  * @desc: HLCDC Display Controller description
134  * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
135  * @fbdev: framebuffer device attached to the Display Controller
136  * @crtc: CRTC provided by the display controller
137  * @planes: instantiated planes
138  * @layers: active HLCDC layer
139  * @wq: display controller workqueue
140  * @commit: used for async commit handling
141  */
142 struct atmel_hlcdc_dc {
143 	const struct atmel_hlcdc_dc_desc *desc;
144 	struct atmel_hlcdc *hlcdc;
145 	struct drm_fbdev_cma *fbdev;
146 	struct drm_crtc *crtc;
147 	struct atmel_hlcdc_planes *planes;
148 	struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
149 	struct workqueue_struct *wq;
150 	struct {
151 		wait_queue_head_t wait;
152 		bool pending;
153 	} commit;
154 };
155 
156 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
157 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;
158 
159 int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
160 			      struct drm_display_mode *mode);
161 
162 struct atmel_hlcdc_planes *
163 atmel_hlcdc_create_planes(struct drm_device *dev);
164 
165 int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
166 int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);
167 
168 void atmel_hlcdc_crtc_irq(struct drm_crtc *c);
169 
170 void atmel_hlcdc_crtc_suspend(struct drm_crtc *crtc);
171 void atmel_hlcdc_crtc_resume(struct drm_crtc *crtc);
172 
173 int atmel_hlcdc_crtc_create(struct drm_device *dev);
174 
175 int atmel_hlcdc_create_outputs(struct drm_device *dev);
176 
177 #endif /* DRM_ATMEL_HLCDC_H */
178